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rt2x00: Use separate mac80211_ops for rt2800pci and rt2800usb
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
4 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
5
6 Based on the original rt2800pci.c and rt2800usb.c.
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31 /*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/slab.h>
39
40 #include "rt2x00.h"
41 #include "rt2800lib.h"
42 #include "rt2800.h"
43
44 /*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60 #define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64 #define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
68 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69 {
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
81 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
82 return false;
83 }
84
85 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
87 {
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108 }
109
110 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
112 {
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, &reg);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140 }
141
142 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
144 {
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
154 reg = 0;
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164 }
165
166 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
168 {
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
182 reg = 0;
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, &reg);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195 }
196
197 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
199 {
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
209 reg = 0;
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220 }
221
222 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
223 const u8 command, const u8 token,
224 const u8 arg0, const u8 arg1)
225 {
226 u32 reg;
227
228 /*
229 * SOC devices don't support MCU requests.
230 */
231 if (rt2x00_is_soc(rt2x00dev))
232 return;
233
234 mutex_lock(&rt2x00dev->csr_mutex);
235
236 /*
237 * Wait until the MCU becomes available, afterwards we
238 * can safely write the new data into the register.
239 */
240 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
241 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
242 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
245 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
246
247 reg = 0;
248 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
249 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
250 }
251
252 mutex_unlock(&rt2x00dev->csr_mutex);
253 }
254 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
255
256 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
257 {
258 unsigned int i;
259 u32 reg;
260
261 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
262 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
263 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
264 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
265 return 0;
266
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
271 return -EACCES;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
274
275 void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
276 {
277 u32 word;
278
279 /*
280 * Initialize TX Info descriptor
281 */
282 rt2x00_desc_read(txwi, 0, &word);
283 rt2x00_set_field32(&word, TXWI_W0_FRAG,
284 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
285 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
286 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
287 rt2x00_set_field32(&word, TXWI_W0_TS,
288 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
289 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
290 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
291 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
292 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
293 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
294 rt2x00_set_field32(&word, TXWI_W0_BW,
295 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
296 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
297 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
298 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
299 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
300 rt2x00_desc_write(txwi, 0, word);
301
302 rt2x00_desc_read(txwi, 1, &word);
303 rt2x00_set_field32(&word, TXWI_W1_ACK,
304 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
305 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
306 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
307 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
308 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
309 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
310 txdesc->key_idx : 0xff);
311 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
312 txdesc->length);
313 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
314 rt2x00_desc_write(txwi, 1, word);
315
316 /*
317 * Always write 0 to IV/EIV fields, hardware will insert the IV
318 * from the IVEIV register when TXD_W3_WIV is set to 0.
319 * When TXD_W3_WIV is set to 1 it will use the IV data
320 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
321 * crypto entry in the registers should be used to encrypt the frame.
322 */
323 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
324 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
325 }
326 EXPORT_SYMBOL_GPL(rt2800_write_txwi);
327
328 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
329 {
330 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
331 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
332 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
333 u16 eeprom;
334 u8 offset0;
335 u8 offset1;
336 u8 offset2;
337
338 if (rt2x00dev->rx_status.band == IEEE80211_BAND_2GHZ) {
339 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
340 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
341 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
342 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
343 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
344 } else {
345 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
346 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
347 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
348 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
349 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
350 }
351
352 /*
353 * Convert the value from the descriptor into the RSSI value
354 * If the value in the descriptor is 0, it is considered invalid
355 * and the default (extremely low) rssi value is assumed
356 */
357 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
358 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
359 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
360
361 /*
362 * mac80211 only accepts a single RSSI value. Calculating the
363 * average doesn't deliver a fair answer either since -60:-60 would
364 * be considered equally good as -50:-70 while the second is the one
365 * which gives less energy...
366 */
367 rssi0 = max(rssi0, rssi1);
368 return max(rssi0, rssi2);
369 }
370
371 void rt2800_process_rxwi(struct queue_entry *entry,
372 struct rxdone_entry_desc *rxdesc)
373 {
374 __le32 *rxwi = (__le32 *) entry->skb->data;
375 u32 word;
376
377 rt2x00_desc_read(rxwi, 0, &word);
378
379 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
380 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
381
382 rt2x00_desc_read(rxwi, 1, &word);
383
384 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
385 rxdesc->flags |= RX_FLAG_SHORT_GI;
386
387 if (rt2x00_get_field32(word, RXWI_W1_BW))
388 rxdesc->flags |= RX_FLAG_40MHZ;
389
390 /*
391 * Detect RX rate, always use MCS as signal type.
392 */
393 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
394 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
395 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
396
397 /*
398 * Mask of 0x8 bit to remove the short preamble flag.
399 */
400 if (rxdesc->rate_mode == RATE_MODE_CCK)
401 rxdesc->signal &= ~0x8;
402
403 rt2x00_desc_read(rxwi, 2, &word);
404
405 /*
406 * Convert descriptor AGC value to RSSI value.
407 */
408 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
409
410 /*
411 * Remove RXWI descriptor from start of buffer.
412 */
413 skb_pull(entry->skb, RXWI_DESC_SIZE);
414 }
415 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
416
417 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
418 {
419 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
420 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
421 unsigned int beacon_base;
422 u32 reg;
423
424 /*
425 * Disable beaconing while we are reloading the beacon data,
426 * otherwise we might be sending out invalid data.
427 */
428 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
429 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
430 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
431
432 /*
433 * Add space for the TXWI in front of the skb.
434 */
435 skb_push(entry->skb, TXWI_DESC_SIZE);
436 memset(entry->skb, 0, TXWI_DESC_SIZE);
437
438 /*
439 * Register descriptor details in skb frame descriptor.
440 */
441 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
442 skbdesc->desc = entry->skb->data;
443 skbdesc->desc_len = TXWI_DESC_SIZE;
444
445 /*
446 * Add the TXWI for the beacon to the skb.
447 */
448 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
449
450 /*
451 * Dump beacon to userspace through debugfs.
452 */
453 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
454
455 /*
456 * Write entire beacon with TXWI to register.
457 */
458 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
459 rt2800_register_multiwrite(rt2x00dev, beacon_base,
460 entry->skb->data, entry->skb->len);
461
462 /*
463 * Enable beaconing again.
464 */
465 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
466 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
467 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
468 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
469
470 /*
471 * Clean up beacon skb.
472 */
473 dev_kfree_skb_any(entry->skb);
474 entry->skb = NULL;
475 }
476 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
477
478 static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
479 unsigned int beacon_base)
480 {
481 int i;
482
483 /*
484 * For the Beacon base registers we only need to clear
485 * the whole TXWI which (when set to 0) will invalidate
486 * the entire beacon.
487 */
488 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
489 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
490 }
491
492 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
493 const struct rt2x00debug rt2800_rt2x00debug = {
494 .owner = THIS_MODULE,
495 .csr = {
496 .read = rt2800_register_read,
497 .write = rt2800_register_write,
498 .flags = RT2X00DEBUGFS_OFFSET,
499 .word_base = CSR_REG_BASE,
500 .word_size = sizeof(u32),
501 .word_count = CSR_REG_SIZE / sizeof(u32),
502 },
503 .eeprom = {
504 .read = rt2x00_eeprom_read,
505 .write = rt2x00_eeprom_write,
506 .word_base = EEPROM_BASE,
507 .word_size = sizeof(u16),
508 .word_count = EEPROM_SIZE / sizeof(u16),
509 },
510 .bbp = {
511 .read = rt2800_bbp_read,
512 .write = rt2800_bbp_write,
513 .word_base = BBP_BASE,
514 .word_size = sizeof(u8),
515 .word_count = BBP_SIZE / sizeof(u8),
516 },
517 .rf = {
518 .read = rt2x00_rf_read,
519 .write = rt2800_rf_write,
520 .word_base = RF_BASE,
521 .word_size = sizeof(u32),
522 .word_count = RF_SIZE / sizeof(u32),
523 },
524 };
525 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
526 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
527
528 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
529 {
530 u32 reg;
531
532 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
533 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
534 }
535 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
536
537 #ifdef CONFIG_RT2X00_LIB_LEDS
538 static void rt2800_brightness_set(struct led_classdev *led_cdev,
539 enum led_brightness brightness)
540 {
541 struct rt2x00_led *led =
542 container_of(led_cdev, struct rt2x00_led, led_dev);
543 unsigned int enabled = brightness != LED_OFF;
544 unsigned int bg_mode =
545 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
546 unsigned int polarity =
547 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
548 EEPROM_FREQ_LED_POLARITY);
549 unsigned int ledmode =
550 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
551 EEPROM_FREQ_LED_MODE);
552
553 if (led->type == LED_TYPE_RADIO) {
554 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
555 enabled ? 0x20 : 0);
556 } else if (led->type == LED_TYPE_ASSOC) {
557 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
558 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
559 } else if (led->type == LED_TYPE_QUALITY) {
560 /*
561 * The brightness is divided into 6 levels (0 - 5),
562 * The specs tell us the following levels:
563 * 0, 1 ,3, 7, 15, 31
564 * to determine the level in a simple way we can simply
565 * work with bitshifting:
566 * (1 << level) - 1
567 */
568 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
569 (1 << brightness / (LED_FULL / 6)) - 1,
570 polarity);
571 }
572 }
573
574 static int rt2800_blink_set(struct led_classdev *led_cdev,
575 unsigned long *delay_on, unsigned long *delay_off)
576 {
577 struct rt2x00_led *led =
578 container_of(led_cdev, struct rt2x00_led, led_dev);
579 u32 reg;
580
581 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
582 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
583 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
584 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
585
586 return 0;
587 }
588
589 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
590 struct rt2x00_led *led, enum led_type type)
591 {
592 led->rt2x00dev = rt2x00dev;
593 led->type = type;
594 led->led_dev.brightness_set = rt2800_brightness_set;
595 led->led_dev.blink_set = rt2800_blink_set;
596 led->flags = LED_INITIALIZED;
597 }
598 #endif /* CONFIG_RT2X00_LIB_LEDS */
599
600 /*
601 * Configuration handlers.
602 */
603 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
604 struct rt2x00lib_crypto *crypto,
605 struct ieee80211_key_conf *key)
606 {
607 struct mac_wcid_entry wcid_entry;
608 struct mac_iveiv_entry iveiv_entry;
609 u32 offset;
610 u32 reg;
611
612 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
613
614 if (crypto->cmd == SET_KEY) {
615 rt2800_register_read(rt2x00dev, offset, &reg);
616 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
617 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
618 /*
619 * Both the cipher as the BSS Idx numbers are split in a main
620 * value of 3 bits, and a extended field for adding one additional
621 * bit to the value.
622 */
623 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
624 (crypto->cipher & 0x7));
625 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
626 (crypto->cipher & 0x8) >> 3);
627 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
628 (crypto->bssidx & 0x7));
629 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
630 (crypto->bssidx & 0x8) >> 3);
631 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
632 rt2800_register_write(rt2x00dev, offset, reg);
633 } else {
634 rt2800_register_write(rt2x00dev, offset, 0);
635 }
636
637 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
638
639 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
640 if ((crypto->cipher == CIPHER_TKIP) ||
641 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
642 (crypto->cipher == CIPHER_AES))
643 iveiv_entry.iv[3] |= 0x20;
644 iveiv_entry.iv[3] |= key->keyidx << 6;
645 rt2800_register_multiwrite(rt2x00dev, offset,
646 &iveiv_entry, sizeof(iveiv_entry));
647
648 offset = MAC_WCID_ENTRY(key->hw_key_idx);
649
650 memset(&wcid_entry, 0, sizeof(wcid_entry));
651 if (crypto->cmd == SET_KEY)
652 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
653 rt2800_register_multiwrite(rt2x00dev, offset,
654 &wcid_entry, sizeof(wcid_entry));
655 }
656
657 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
658 struct rt2x00lib_crypto *crypto,
659 struct ieee80211_key_conf *key)
660 {
661 struct hw_key_entry key_entry;
662 struct rt2x00_field32 field;
663 u32 offset;
664 u32 reg;
665
666 if (crypto->cmd == SET_KEY) {
667 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
668
669 memcpy(key_entry.key, crypto->key,
670 sizeof(key_entry.key));
671 memcpy(key_entry.tx_mic, crypto->tx_mic,
672 sizeof(key_entry.tx_mic));
673 memcpy(key_entry.rx_mic, crypto->rx_mic,
674 sizeof(key_entry.rx_mic));
675
676 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
677 rt2800_register_multiwrite(rt2x00dev, offset,
678 &key_entry, sizeof(key_entry));
679 }
680
681 /*
682 * The cipher types are stored over multiple registers
683 * starting with SHARED_KEY_MODE_BASE each word will have
684 * 32 bits and contains the cipher types for 2 bssidx each.
685 * Using the correct defines correctly will cause overhead,
686 * so just calculate the correct offset.
687 */
688 field.bit_offset = 4 * (key->hw_key_idx % 8);
689 field.bit_mask = 0x7 << field.bit_offset;
690
691 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
692
693 rt2800_register_read(rt2x00dev, offset, &reg);
694 rt2x00_set_field32(&reg, field,
695 (crypto->cmd == SET_KEY) * crypto->cipher);
696 rt2800_register_write(rt2x00dev, offset, reg);
697
698 /*
699 * Update WCID information
700 */
701 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
702
703 return 0;
704 }
705 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
706
707 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
708 struct rt2x00lib_crypto *crypto,
709 struct ieee80211_key_conf *key)
710 {
711 struct hw_key_entry key_entry;
712 u32 offset;
713
714 if (crypto->cmd == SET_KEY) {
715 /*
716 * 1 pairwise key is possible per AID, this means that the AID
717 * equals our hw_key_idx. Make sure the WCID starts _after_ the
718 * last possible shared key entry.
719 */
720 if (crypto->aid > (256 - 32))
721 return -ENOSPC;
722
723 key->hw_key_idx = 32 + crypto->aid;
724
725 memcpy(key_entry.key, crypto->key,
726 sizeof(key_entry.key));
727 memcpy(key_entry.tx_mic, crypto->tx_mic,
728 sizeof(key_entry.tx_mic));
729 memcpy(key_entry.rx_mic, crypto->rx_mic,
730 sizeof(key_entry.rx_mic));
731
732 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
733 rt2800_register_multiwrite(rt2x00dev, offset,
734 &key_entry, sizeof(key_entry));
735 }
736
737 /*
738 * Update WCID information
739 */
740 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
741
742 return 0;
743 }
744 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
745
746 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
747 const unsigned int filter_flags)
748 {
749 u32 reg;
750
751 /*
752 * Start configuration steps.
753 * Note that the version error will always be dropped
754 * and broadcast frames will always be accepted since
755 * there is no filter for it at this time.
756 */
757 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
758 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
759 !(filter_flags & FIF_FCSFAIL));
760 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
761 !(filter_flags & FIF_PLCPFAIL));
762 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
763 !(filter_flags & FIF_PROMISC_IN_BSS));
764 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
765 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
766 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
767 !(filter_flags & FIF_ALLMULTI));
768 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
769 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
770 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
771 !(filter_flags & FIF_CONTROL));
772 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
773 !(filter_flags & FIF_CONTROL));
774 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
775 !(filter_flags & FIF_CONTROL));
776 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
777 !(filter_flags & FIF_CONTROL));
778 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
779 !(filter_flags & FIF_CONTROL));
780 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
781 !(filter_flags & FIF_PSPOLL));
782 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
783 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
784 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
785 !(filter_flags & FIF_CONTROL));
786 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
787 }
788 EXPORT_SYMBOL_GPL(rt2800_config_filter);
789
790 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
791 struct rt2x00intf_conf *conf, const unsigned int flags)
792 {
793 u32 reg;
794
795 if (flags & CONFIG_UPDATE_TYPE) {
796 /*
797 * Clear current synchronisation setup.
798 */
799 rt2800_clear_beacon(rt2x00dev,
800 HW_BEACON_OFFSET(intf->beacon->entry_idx));
801 /*
802 * Enable synchronisation.
803 */
804 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
805 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
806 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
807 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
808 (conf->sync == TSF_SYNC_BEACON));
809 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
810
811 /*
812 * Enable pre tbtt interrupt for beaconing modes
813 */
814 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
815 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
816 (conf->sync == TSF_SYNC_BEACON));
817 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
818
819 }
820
821 if (flags & CONFIG_UPDATE_MAC) {
822 reg = le32_to_cpu(conf->mac[1]);
823 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
824 conf->mac[1] = cpu_to_le32(reg);
825
826 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
827 conf->mac, sizeof(conf->mac));
828 }
829
830 if (flags & CONFIG_UPDATE_BSSID) {
831 reg = le32_to_cpu(conf->bssid[1]);
832 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
833 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
834 conf->bssid[1] = cpu_to_le32(reg);
835
836 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
837 conf->bssid, sizeof(conf->bssid));
838 }
839 }
840 EXPORT_SYMBOL_GPL(rt2800_config_intf);
841
842 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
843 {
844 u32 reg;
845
846 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
847 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
848 !!erp->short_preamble);
849 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
850 !!erp->short_preamble);
851 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
852
853 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
854 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
855 erp->cts_protection ? 2 : 0);
856 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
857
858 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
859 erp->basic_rates);
860 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
861
862 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
863 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
864 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
865
866 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
867 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
868 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
869
870 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
871 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
872 erp->beacon_int * 16);
873 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
874 }
875 EXPORT_SYMBOL_GPL(rt2800_config_erp);
876
877 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
878 {
879 u8 r1;
880 u8 r3;
881
882 rt2800_bbp_read(rt2x00dev, 1, &r1);
883 rt2800_bbp_read(rt2x00dev, 3, &r3);
884
885 /*
886 * Configure the TX antenna.
887 */
888 switch ((int)ant->tx) {
889 case 1:
890 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
891 break;
892 case 2:
893 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
894 break;
895 case 3:
896 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
897 break;
898 }
899
900 /*
901 * Configure the RX antenna.
902 */
903 switch ((int)ant->rx) {
904 case 1:
905 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
906 break;
907 case 2:
908 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
909 break;
910 case 3:
911 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
912 break;
913 }
914
915 rt2800_bbp_write(rt2x00dev, 3, r3);
916 rt2800_bbp_write(rt2x00dev, 1, r1);
917 }
918 EXPORT_SYMBOL_GPL(rt2800_config_ant);
919
920 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
921 struct rt2x00lib_conf *libconf)
922 {
923 u16 eeprom;
924 short lna_gain;
925
926 if (libconf->rf.channel <= 14) {
927 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
928 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
929 } else if (libconf->rf.channel <= 64) {
930 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
931 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
932 } else if (libconf->rf.channel <= 128) {
933 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
934 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
935 } else {
936 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
937 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
938 }
939
940 rt2x00dev->lna_gain = lna_gain;
941 }
942
943 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
944 struct ieee80211_conf *conf,
945 struct rf_channel *rf,
946 struct channel_info *info)
947 {
948 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
949
950 if (rt2x00dev->default_ant.tx == 1)
951 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
952
953 if (rt2x00dev->default_ant.rx == 1) {
954 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
955 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
956 } else if (rt2x00dev->default_ant.rx == 2)
957 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
958
959 if (rf->channel > 14) {
960 /*
961 * When TX power is below 0, we should increase it by 7 to
962 * make it a positive value (Minumum value is -7).
963 * However this means that values between 0 and 7 have
964 * double meaning, and we should set a 7DBm boost flag.
965 */
966 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
967 (info->tx_power1 >= 0));
968
969 if (info->tx_power1 < 0)
970 info->tx_power1 += 7;
971
972 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
973 TXPOWER_A_TO_DEV(info->tx_power1));
974
975 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
976 (info->tx_power2 >= 0));
977
978 if (info->tx_power2 < 0)
979 info->tx_power2 += 7;
980
981 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
982 TXPOWER_A_TO_DEV(info->tx_power2));
983 } else {
984 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
985 TXPOWER_G_TO_DEV(info->tx_power1));
986 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
987 TXPOWER_G_TO_DEV(info->tx_power2));
988 }
989
990 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
991
992 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
993 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
994 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
995 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
996
997 udelay(200);
998
999 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1000 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1001 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1002 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1003
1004 udelay(200);
1005
1006 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1007 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1008 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1009 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1010 }
1011
1012 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1013 struct ieee80211_conf *conf,
1014 struct rf_channel *rf,
1015 struct channel_info *info)
1016 {
1017 u8 rfcsr;
1018
1019 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1020 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1021
1022 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1023 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1024 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1025
1026 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1027 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1028 TXPOWER_G_TO_DEV(info->tx_power1));
1029 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1030
1031 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1032 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1033 TXPOWER_G_TO_DEV(info->tx_power2));
1034 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1035
1036 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1037 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1038 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1039
1040 rt2800_rfcsr_write(rt2x00dev, 24,
1041 rt2x00dev->calibration[conf_is_ht40(conf)]);
1042
1043 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1044 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1045 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1046 }
1047
1048 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1049 struct ieee80211_conf *conf,
1050 struct rf_channel *rf,
1051 struct channel_info *info)
1052 {
1053 u32 reg;
1054 unsigned int tx_pin;
1055 u8 bbp;
1056
1057 if (rt2x00_rf(rt2x00dev, RF2020) ||
1058 rt2x00_rf(rt2x00dev, RF3020) ||
1059 rt2x00_rf(rt2x00dev, RF3021) ||
1060 rt2x00_rf(rt2x00dev, RF3022))
1061 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1062 else
1063 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1064
1065 /*
1066 * Change BBP settings
1067 */
1068 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1069 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1070 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1071 rt2800_bbp_write(rt2x00dev, 86, 0);
1072
1073 if (rf->channel <= 14) {
1074 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1075 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1076 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1077 } else {
1078 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1079 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1080 }
1081 } else {
1082 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1083
1084 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1085 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1086 else
1087 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1088 }
1089
1090 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1091 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1092 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1093 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1094 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1095
1096 tx_pin = 0;
1097
1098 /* Turn on unused PA or LNA when not using 1T or 1R */
1099 if (rt2x00dev->default_ant.tx != 1) {
1100 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1101 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1102 }
1103
1104 /* Turn on unused PA or LNA when not using 1T or 1R */
1105 if (rt2x00dev->default_ant.rx != 1) {
1106 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1107 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1108 }
1109
1110 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1111 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1112 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1113 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1114 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1115 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1116
1117 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1118
1119 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1120 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1121 rt2800_bbp_write(rt2x00dev, 4, bbp);
1122
1123 rt2800_bbp_read(rt2x00dev, 3, &bbp);
1124 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1125 rt2800_bbp_write(rt2x00dev, 3, bbp);
1126
1127 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1128 if (conf_is_ht40(conf)) {
1129 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1130 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1131 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1132 } else {
1133 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1134 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1135 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1136 }
1137 }
1138
1139 msleep(1);
1140 }
1141
1142 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1143 const int max_txpower)
1144 {
1145 u8 txpower;
1146 u8 max_value = (u8)max_txpower;
1147 u16 eeprom;
1148 int i;
1149 u32 reg;
1150 u8 r1;
1151 u32 offset;
1152
1153 /*
1154 * set to normal tx power mode: +/- 0dBm
1155 */
1156 rt2800_bbp_read(rt2x00dev, 1, &r1);
1157 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1158 rt2800_bbp_write(rt2x00dev, 1, r1);
1159
1160 /*
1161 * The eeprom contains the tx power values for each rate. These
1162 * values map to 100% tx power. Each 16bit word contains four tx
1163 * power values and the order is the same as used in the TX_PWR_CFG
1164 * registers.
1165 */
1166 offset = TX_PWR_CFG_0;
1167
1168 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1169 /* just to be safe */
1170 if (offset > TX_PWR_CFG_4)
1171 break;
1172
1173 rt2800_register_read(rt2x00dev, offset, &reg);
1174
1175 /* read the next four txpower values */
1176 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1177 &eeprom);
1178
1179 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1180 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1181 * TX_PWR_CFG_4: unknown */
1182 txpower = rt2x00_get_field16(eeprom,
1183 EEPROM_TXPOWER_BYRATE_RATE0);
1184 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1185 min(txpower, max_value));
1186
1187 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1188 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1189 * TX_PWR_CFG_4: unknown */
1190 txpower = rt2x00_get_field16(eeprom,
1191 EEPROM_TXPOWER_BYRATE_RATE1);
1192 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1193 min(txpower, max_value));
1194
1195 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1196 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1197 * TX_PWR_CFG_4: unknown */
1198 txpower = rt2x00_get_field16(eeprom,
1199 EEPROM_TXPOWER_BYRATE_RATE2);
1200 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1201 min(txpower, max_value));
1202
1203 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1204 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1205 * TX_PWR_CFG_4: unknown */
1206 txpower = rt2x00_get_field16(eeprom,
1207 EEPROM_TXPOWER_BYRATE_RATE3);
1208 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1209 min(txpower, max_value));
1210
1211 /* read the next four txpower values */
1212 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1213 &eeprom);
1214
1215 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1216 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1217 * TX_PWR_CFG_4: unknown */
1218 txpower = rt2x00_get_field16(eeprom,
1219 EEPROM_TXPOWER_BYRATE_RATE0);
1220 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1221 min(txpower, max_value));
1222
1223 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1224 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1225 * TX_PWR_CFG_4: unknown */
1226 txpower = rt2x00_get_field16(eeprom,
1227 EEPROM_TXPOWER_BYRATE_RATE1);
1228 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1229 min(txpower, max_value));
1230
1231 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1232 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1233 * TX_PWR_CFG_4: unknown */
1234 txpower = rt2x00_get_field16(eeprom,
1235 EEPROM_TXPOWER_BYRATE_RATE2);
1236 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1237 min(txpower, max_value));
1238
1239 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1240 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1241 * TX_PWR_CFG_4: unknown */
1242 txpower = rt2x00_get_field16(eeprom,
1243 EEPROM_TXPOWER_BYRATE_RATE3);
1244 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1245 min(txpower, max_value));
1246
1247 rt2800_register_write(rt2x00dev, offset, reg);
1248
1249 /* next TX_PWR_CFG register */
1250 offset += 4;
1251 }
1252 }
1253
1254 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1255 struct rt2x00lib_conf *libconf)
1256 {
1257 u32 reg;
1258
1259 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1260 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1261 libconf->conf->short_frame_max_tx_count);
1262 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1263 libconf->conf->long_frame_max_tx_count);
1264 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1265 }
1266
1267 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1268 struct rt2x00lib_conf *libconf)
1269 {
1270 enum dev_state state =
1271 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1272 STATE_SLEEP : STATE_AWAKE;
1273 u32 reg;
1274
1275 if (state == STATE_SLEEP) {
1276 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1277
1278 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1279 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1280 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1281 libconf->conf->listen_interval - 1);
1282 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1283 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1284
1285 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1286 } else {
1287 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1288 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1289 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1290 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1291 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1292
1293 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1294 }
1295 }
1296
1297 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1298 struct rt2x00lib_conf *libconf,
1299 const unsigned int flags)
1300 {
1301 /* Always recalculate LNA gain before changing configuration */
1302 rt2800_config_lna_gain(rt2x00dev, libconf);
1303
1304 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1305 rt2800_config_channel(rt2x00dev, libconf->conf,
1306 &libconf->rf, &libconf->channel);
1307 if (flags & IEEE80211_CONF_CHANGE_POWER)
1308 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1309 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1310 rt2800_config_retry_limit(rt2x00dev, libconf);
1311 if (flags & IEEE80211_CONF_CHANGE_PS)
1312 rt2800_config_ps(rt2x00dev, libconf);
1313 }
1314 EXPORT_SYMBOL_GPL(rt2800_config);
1315
1316 /*
1317 * Link tuning
1318 */
1319 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1320 {
1321 u32 reg;
1322
1323 /*
1324 * Update FCS error count from register.
1325 */
1326 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1327 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1328 }
1329 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1330
1331 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1332 {
1333 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1334 if (rt2x00_rt(rt2x00dev, RT3070) ||
1335 rt2x00_rt(rt2x00dev, RT3071) ||
1336 rt2x00_rt(rt2x00dev, RT3090) ||
1337 rt2x00_rt(rt2x00dev, RT3390))
1338 return 0x1c + (2 * rt2x00dev->lna_gain);
1339 else
1340 return 0x2e + rt2x00dev->lna_gain;
1341 }
1342
1343 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1344 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1345 else
1346 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1347 }
1348
1349 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1350 struct link_qual *qual, u8 vgc_level)
1351 {
1352 if (qual->vgc_level != vgc_level) {
1353 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1354 qual->vgc_level = vgc_level;
1355 qual->vgc_level_reg = vgc_level;
1356 }
1357 }
1358
1359 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1360 {
1361 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1362 }
1363 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1364
1365 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1366 const u32 count)
1367 {
1368 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1369 return;
1370
1371 /*
1372 * When RSSI is better then -80 increase VGC level with 0x10
1373 */
1374 rt2800_set_vgc(rt2x00dev, qual,
1375 rt2800_get_default_vgc(rt2x00dev) +
1376 ((qual->rssi > -80) * 0x10));
1377 }
1378 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1379
1380 /*
1381 * Initialization functions.
1382 */
1383 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1384 {
1385 u32 reg;
1386 u16 eeprom;
1387 unsigned int i;
1388 int ret;
1389
1390 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1391 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1392 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1393 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1394 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1395 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1396 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1397
1398 ret = rt2800_drv_init_registers(rt2x00dev);
1399 if (ret)
1400 return ret;
1401
1402 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1403 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1404 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1405 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1406 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1407 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1408
1409 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1410 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1411 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1412 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1413 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1414 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1415
1416 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1417 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1418
1419 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1420
1421 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1422 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1423 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1424 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1425 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1426 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1427 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1428 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1429
1430 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1431
1432 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1433 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1434 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1435 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1436
1437 if (rt2x00_rt(rt2x00dev, RT3071) ||
1438 rt2x00_rt(rt2x00dev, RT3090) ||
1439 rt2x00_rt(rt2x00dev, RT3390)) {
1440 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1441 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1442 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1443 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1444 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1445 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1446 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1447 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1448 0x0000002c);
1449 else
1450 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1451 0x0000000f);
1452 } else {
1453 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1454 }
1455 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1456 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1457
1458 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1459 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1460 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1461 } else {
1462 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1463 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1464 }
1465 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1466 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1467 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1468 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1469 } else {
1470 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1471 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1472 }
1473
1474 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1475 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1476 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1477 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1478 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1479 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1480 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1481 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1482 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1483 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1484
1485 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1486 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1487 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1488 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1489 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1490
1491 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1492 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1493 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1494 rt2x00_rt(rt2x00dev, RT2883) ||
1495 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1496 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1497 else
1498 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1499 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1500 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1501 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1502
1503 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1504 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1505 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1506 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1507 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1508 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1509 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1510 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1511 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1512
1513 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1514
1515 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1516 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1517 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1518 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1519 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1520 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1521 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1522 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1523
1524 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1525 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1526 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1527 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1528 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1529 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1530 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1531 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1532 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1533
1534 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1535 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1536 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1537 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1538 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1539 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1540 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1541 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1542 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1543 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1544 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1545 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1546
1547 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1548 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1549 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1550 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1551 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1552 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1553 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1554 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1555 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1556 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1557 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1558 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1559
1560 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1561 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1562 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1563 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1564 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1565 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1566 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1567 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1568 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1569 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1570 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1571 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1572
1573 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1574 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1575 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1576 !rt2x00_is_usb(rt2x00dev));
1577 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1578 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1579 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1580 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1581 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1582 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1583 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1584 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1585 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1586
1587 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1588 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1589 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1590 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1591 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1592 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1593 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1594 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1595 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1596 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1597 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1598 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1599
1600 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1601 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1602 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1603 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1604 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1605 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1606 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1607 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1608 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1609 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1610 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1611 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1612
1613 if (rt2x00_is_usb(rt2x00dev)) {
1614 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1615
1616 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1617 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1618 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1619 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1620 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1621 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1622 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1623 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1624 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1625 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1626 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1627 }
1628
1629 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1630 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1631
1632 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1633 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1634 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1635 IEEE80211_MAX_RTS_THRESHOLD);
1636 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1637 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1638
1639 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1640
1641 /*
1642 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1643 * time should be set to 16. However, the original Ralink driver uses
1644 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1645 * connection problems with 11g + CTS protection. Hence, use the same
1646 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1647 */
1648 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1649 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1650 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
1651 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1652 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1653 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1654 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1655
1656 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1657
1658 /*
1659 * ASIC will keep garbage value after boot, clear encryption keys.
1660 */
1661 for (i = 0; i < 4; i++)
1662 rt2800_register_write(rt2x00dev,
1663 SHARED_KEY_MODE_ENTRY(i), 0);
1664
1665 for (i = 0; i < 256; i++) {
1666 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1667 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1668 wcid, sizeof(wcid));
1669
1670 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1671 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1672 }
1673
1674 /*
1675 * Clear all beacons
1676 */
1677 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1678 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1679 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1680 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1681 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1682 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1683 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1684 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
1685
1686 if (rt2x00_is_usb(rt2x00dev)) {
1687 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1688 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1689 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
1690 }
1691
1692 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1693 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1694 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1695 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1696 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1697 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1698 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1699 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1700 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1701 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1702
1703 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1704 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1705 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1706 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1707 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1708 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1709 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1710 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1711 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1712 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1713
1714 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1715 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1716 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1717 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1718 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1719 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1720 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1721 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1722 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1723 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1724
1725 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1726 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1727 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1728 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1729 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1730 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1731
1732 /*
1733 * We must clear the error counters.
1734 * These registers are cleared on read,
1735 * so we may pass a useless variable to store the value.
1736 */
1737 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1738 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1739 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1740 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1741 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1742 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1743
1744 /*
1745 * Setup leadtime for pre tbtt interrupt to 6ms
1746 */
1747 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
1748 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
1749 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
1750
1751 return 0;
1752 }
1753 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1754
1755 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1756 {
1757 unsigned int i;
1758 u32 reg;
1759
1760 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1761 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1762 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1763 return 0;
1764
1765 udelay(REGISTER_BUSY_DELAY);
1766 }
1767
1768 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1769 return -EACCES;
1770 }
1771
1772 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1773 {
1774 unsigned int i;
1775 u8 value;
1776
1777 /*
1778 * BBP was enabled after firmware was loaded,
1779 * but we need to reactivate it now.
1780 */
1781 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1782 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1783 msleep(1);
1784
1785 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1786 rt2800_bbp_read(rt2x00dev, 0, &value);
1787 if ((value != 0xff) && (value != 0x00))
1788 return 0;
1789 udelay(REGISTER_BUSY_DELAY);
1790 }
1791
1792 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1793 return -EACCES;
1794 }
1795
1796 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1797 {
1798 unsigned int i;
1799 u16 eeprom;
1800 u8 reg_id;
1801 u8 value;
1802
1803 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1804 rt2800_wait_bbp_ready(rt2x00dev)))
1805 return -EACCES;
1806
1807 if (rt2800_is_305x_soc(rt2x00dev))
1808 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1809
1810 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1811 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1812
1813 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1814 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1815 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1816 } else {
1817 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1818 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1819 }
1820
1821 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1822
1823 if (rt2x00_rt(rt2x00dev, RT3070) ||
1824 rt2x00_rt(rt2x00dev, RT3071) ||
1825 rt2x00_rt(rt2x00dev, RT3090) ||
1826 rt2x00_rt(rt2x00dev, RT3390)) {
1827 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1828 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1829 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1830 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1831 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1832 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1833 } else {
1834 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1835 }
1836
1837 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1838 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1839
1840 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
1841 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1842 else
1843 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1844
1845 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1846 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1847 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1848
1849 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1850 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1851 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1852 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1853 rt2800_is_305x_soc(rt2x00dev))
1854 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1855 else
1856 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1857
1858 if (rt2800_is_305x_soc(rt2x00dev))
1859 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1860 else
1861 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1862 rt2800_bbp_write(rt2x00dev, 106, 0x35);
1863
1864 if (rt2x00_rt(rt2x00dev, RT3071) ||
1865 rt2x00_rt(rt2x00dev, RT3090) ||
1866 rt2x00_rt(rt2x00dev, RT3390)) {
1867 rt2800_bbp_read(rt2x00dev, 138, &value);
1868
1869 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1870 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1871 value |= 0x20;
1872 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1873 value &= ~0x02;
1874
1875 rt2800_bbp_write(rt2x00dev, 138, value);
1876 }
1877
1878
1879 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1880 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1881
1882 if (eeprom != 0xffff && eeprom != 0x0000) {
1883 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1884 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1885 rt2800_bbp_write(rt2x00dev, reg_id, value);
1886 }
1887 }
1888
1889 return 0;
1890 }
1891 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1892
1893 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1894 bool bw40, u8 rfcsr24, u8 filter_target)
1895 {
1896 unsigned int i;
1897 u8 bbp;
1898 u8 rfcsr;
1899 u8 passband;
1900 u8 stopband;
1901 u8 overtuned = 0;
1902
1903 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1904
1905 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1906 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1907 rt2800_bbp_write(rt2x00dev, 4, bbp);
1908
1909 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1910 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1911 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1912
1913 /*
1914 * Set power & frequency of passband test tone
1915 */
1916 rt2800_bbp_write(rt2x00dev, 24, 0);
1917
1918 for (i = 0; i < 100; i++) {
1919 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1920 msleep(1);
1921
1922 rt2800_bbp_read(rt2x00dev, 55, &passband);
1923 if (passband)
1924 break;
1925 }
1926
1927 /*
1928 * Set power & frequency of stopband test tone
1929 */
1930 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1931
1932 for (i = 0; i < 100; i++) {
1933 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1934 msleep(1);
1935
1936 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1937
1938 if ((passband - stopband) <= filter_target) {
1939 rfcsr24++;
1940 overtuned += ((passband - stopband) == filter_target);
1941 } else
1942 break;
1943
1944 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1945 }
1946
1947 rfcsr24 -= !!overtuned;
1948
1949 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1950 return rfcsr24;
1951 }
1952
1953 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1954 {
1955 u8 rfcsr;
1956 u8 bbp;
1957 u32 reg;
1958 u16 eeprom;
1959
1960 if (!rt2x00_rt(rt2x00dev, RT3070) &&
1961 !rt2x00_rt(rt2x00dev, RT3071) &&
1962 !rt2x00_rt(rt2x00dev, RT3090) &&
1963 !rt2x00_rt(rt2x00dev, RT3390) &&
1964 !rt2800_is_305x_soc(rt2x00dev))
1965 return 0;
1966
1967 /*
1968 * Init RF calibration.
1969 */
1970 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1971 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1972 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1973 msleep(1);
1974 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1975 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1976
1977 if (rt2x00_rt(rt2x00dev, RT3070) ||
1978 rt2x00_rt(rt2x00dev, RT3071) ||
1979 rt2x00_rt(rt2x00dev, RT3090)) {
1980 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1981 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1982 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1983 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1984 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1985 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1986 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1987 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1988 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1989 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1990 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1991 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1992 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1993 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1994 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1995 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1996 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1997 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1998 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1999 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2000 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2001 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2002 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2003 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2004 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2005 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2006 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2007 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2008 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2009 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2010 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2011 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2012 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2013 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2014 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2015 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2016 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2017 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2018 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2019 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2020 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2021 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2022 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2023 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2024 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2025 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2026 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2027 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2028 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2029 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2030 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2031 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2032 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2033 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2034 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2035 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2036 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2037 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2038 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2039 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2040 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2041 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2042 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2043 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2044 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2045 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2046 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2047 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2048 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2049 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2050 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2051 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2052 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2053 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2054 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2055 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2056 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2057 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2058 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2059 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2060 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2061 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2062 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2063 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2064 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2065 return 0;
2066 }
2067
2068 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2069 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2070 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2071 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2072 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2073 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2074 rt2x00_rt(rt2x00dev, RT3090)) {
2075 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2076 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2077 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2078
2079 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2080
2081 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2082 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2083 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2084 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2085 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2086 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2087 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2088 else
2089 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2090 }
2091 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2092 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2093 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2094 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2095 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2096 }
2097
2098 /*
2099 * Set RX Filter calibration for 20MHz and 40MHz
2100 */
2101 if (rt2x00_rt(rt2x00dev, RT3070)) {
2102 rt2x00dev->calibration[0] =
2103 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2104 rt2x00dev->calibration[1] =
2105 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2106 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2107 rt2x00_rt(rt2x00dev, RT3090) ||
2108 rt2x00_rt(rt2x00dev, RT3390)) {
2109 rt2x00dev->calibration[0] =
2110 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2111 rt2x00dev->calibration[1] =
2112 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2113 }
2114
2115 /*
2116 * Set back to initial state
2117 */
2118 rt2800_bbp_write(rt2x00dev, 24, 0);
2119
2120 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2121 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2122 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2123
2124 /*
2125 * set BBP back to BW20
2126 */
2127 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2128 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2129 rt2800_bbp_write(rt2x00dev, 4, bbp);
2130
2131 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2132 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2133 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2134 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2135 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2136
2137 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2138 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2139 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2140
2141 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2142 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2143 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2144 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2145 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2146 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2147 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2148 }
2149 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2150 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2151 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2152 rt2x00_get_field16(eeprom,
2153 EEPROM_TXMIXER_GAIN_BG_VAL));
2154 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2155
2156 if (rt2x00_rt(rt2x00dev, RT3090)) {
2157 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2158
2159 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2160 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2161 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2162 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2163 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2164
2165 rt2800_bbp_write(rt2x00dev, 138, bbp);
2166 }
2167
2168 if (rt2x00_rt(rt2x00dev, RT3071) ||
2169 rt2x00_rt(rt2x00dev, RT3090) ||
2170 rt2x00_rt(rt2x00dev, RT3390)) {
2171 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2172 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2173 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2174 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2175 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2176 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2177 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2178
2179 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2180 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2181 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2182
2183 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2184 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2185 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2186
2187 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2188 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2189 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2190 }
2191
2192 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2193 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2194 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2195 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2196 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2197 else
2198 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2199 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2200 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2201 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2202 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2203 }
2204
2205 return 0;
2206 }
2207 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2208
2209 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2210 {
2211 u32 reg;
2212
2213 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2214
2215 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2216 }
2217 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2218
2219 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2220 {
2221 u32 reg;
2222
2223 mutex_lock(&rt2x00dev->csr_mutex);
2224
2225 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2226 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2227 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2228 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2229 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2230
2231 /* Wait until the EEPROM has been loaded */
2232 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2233
2234 /* Apparently the data is read from end to start */
2235 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2236 (u32 *)&rt2x00dev->eeprom[i]);
2237 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2238 (u32 *)&rt2x00dev->eeprom[i + 2]);
2239 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2240 (u32 *)&rt2x00dev->eeprom[i + 4]);
2241 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2242 (u32 *)&rt2x00dev->eeprom[i + 6]);
2243
2244 mutex_unlock(&rt2x00dev->csr_mutex);
2245 }
2246
2247 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2248 {
2249 unsigned int i;
2250
2251 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2252 rt2800_efuse_read(rt2x00dev, i);
2253 }
2254 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2255
2256 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2257 {
2258 u16 word;
2259 u8 *mac;
2260 u8 default_lna_gain;
2261
2262 /*
2263 * Start validation of the data that has been read.
2264 */
2265 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2266 if (!is_valid_ether_addr(mac)) {
2267 random_ether_addr(mac);
2268 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2269 }
2270
2271 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2272 if (word == 0xffff) {
2273 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2274 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2275 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2276 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2277 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2278 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2279 rt2x00_rt(rt2x00dev, RT2872)) {
2280 /*
2281 * There is a max of 2 RX streams for RT28x0 series
2282 */
2283 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2284 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2285 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2286 }
2287
2288 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2289 if (word == 0xffff) {
2290 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2291 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2292 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2293 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2294 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2295 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2296 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2297 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2298 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2299 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2300 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2301 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
2302 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2303 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2304 }
2305
2306 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2307 if ((word & 0x00ff) == 0x00ff) {
2308 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2309 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2310 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2311 }
2312 if ((word & 0xff00) == 0xff00) {
2313 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2314 LED_MODE_TXRX_ACTIVITY);
2315 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2316 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2317 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2318 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2319 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2320 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2321 }
2322
2323 /*
2324 * During the LNA validation we are going to use
2325 * lna0 as correct value. Note that EEPROM_LNA
2326 * is never validated.
2327 */
2328 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2329 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2330
2331 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2332 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2333 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2334 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2335 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2336 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2337
2338 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2339 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2340 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2341 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2342 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2343 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2344 default_lna_gain);
2345 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2346
2347 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2348 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2349 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2350 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2351 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2352 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2353
2354 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2355 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2356 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2357 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2358 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2359 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2360 default_lna_gain);
2361 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2362
2363 return 0;
2364 }
2365 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2366
2367 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2368 {
2369 u32 reg;
2370 u16 value;
2371 u16 eeprom;
2372
2373 /*
2374 * Read EEPROM word for configuration.
2375 */
2376 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2377
2378 /*
2379 * Identify RF chipset.
2380 */
2381 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2382 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2383
2384 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2385 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2386
2387 if (!rt2x00_rt(rt2x00dev, RT2860) &&
2388 !rt2x00_rt(rt2x00dev, RT2872) &&
2389 !rt2x00_rt(rt2x00dev, RT2883) &&
2390 !rt2x00_rt(rt2x00dev, RT3070) &&
2391 !rt2x00_rt(rt2x00dev, RT3071) &&
2392 !rt2x00_rt(rt2x00dev, RT3090) &&
2393 !rt2x00_rt(rt2x00dev, RT3390) &&
2394 !rt2x00_rt(rt2x00dev, RT3572)) {
2395 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2396 return -ENODEV;
2397 }
2398
2399 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2400 !rt2x00_rf(rt2x00dev, RF2850) &&
2401 !rt2x00_rf(rt2x00dev, RF2720) &&
2402 !rt2x00_rf(rt2x00dev, RF2750) &&
2403 !rt2x00_rf(rt2x00dev, RF3020) &&
2404 !rt2x00_rf(rt2x00dev, RF2020) &&
2405 !rt2x00_rf(rt2x00dev, RF3021) &&
2406 !rt2x00_rf(rt2x00dev, RF3022) &&
2407 !rt2x00_rf(rt2x00dev, RF3052)) {
2408 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2409 return -ENODEV;
2410 }
2411
2412 /*
2413 * Identify default antenna configuration.
2414 */
2415 rt2x00dev->default_ant.tx =
2416 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2417 rt2x00dev->default_ant.rx =
2418 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2419
2420 /*
2421 * Read frequency offset and RF programming sequence.
2422 */
2423 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2424 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2425
2426 /*
2427 * Read external LNA informations.
2428 */
2429 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2430
2431 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2432 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2433 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2434 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2435
2436 /*
2437 * Detect if this device has an hardware controlled radio.
2438 */
2439 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2440 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2441
2442 /*
2443 * Store led settings, for correct led behaviour.
2444 */
2445 #ifdef CONFIG_RT2X00_LIB_LEDS
2446 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2447 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2448 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2449
2450 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2451 #endif /* CONFIG_RT2X00_LIB_LEDS */
2452
2453 return 0;
2454 }
2455 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2456
2457 /*
2458 * RF value list for rt28xx
2459 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2460 */
2461 static const struct rf_channel rf_vals[] = {
2462 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2463 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2464 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2465 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2466 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2467 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2468 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2469 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2470 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2471 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2472 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2473 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2474 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2475 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2476
2477 /* 802.11 UNI / HyperLan 2 */
2478 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2479 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2480 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2481 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2482 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2483 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2484 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2485 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2486 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2487 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2488 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2489 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2490
2491 /* 802.11 HyperLan 2 */
2492 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2493 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2494 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2495 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2496 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2497 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2498 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2499 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2500 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2501 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2502 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2503 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2504 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2505 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2506 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2507 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2508
2509 /* 802.11 UNII */
2510 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2511 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2512 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2513 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2514 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2515 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2516 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2517 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2518 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2519 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2520 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2521
2522 /* 802.11 Japan */
2523 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2524 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2525 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2526 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2527 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2528 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2529 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2530 };
2531
2532 /*
2533 * RF value list for rt3xxx
2534 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2535 */
2536 static const struct rf_channel rf_vals_3x[] = {
2537 {1, 241, 2, 2 },
2538 {2, 241, 2, 7 },
2539 {3, 242, 2, 2 },
2540 {4, 242, 2, 7 },
2541 {5, 243, 2, 2 },
2542 {6, 243, 2, 7 },
2543 {7, 244, 2, 2 },
2544 {8, 244, 2, 7 },
2545 {9, 245, 2, 2 },
2546 {10, 245, 2, 7 },
2547 {11, 246, 2, 2 },
2548 {12, 246, 2, 7 },
2549 {13, 247, 2, 2 },
2550 {14, 248, 2, 4 },
2551
2552 /* 802.11 UNI / HyperLan 2 */
2553 {36, 0x56, 0, 4},
2554 {38, 0x56, 0, 6},
2555 {40, 0x56, 0, 8},
2556 {44, 0x57, 0, 0},
2557 {46, 0x57, 0, 2},
2558 {48, 0x57, 0, 4},
2559 {52, 0x57, 0, 8},
2560 {54, 0x57, 0, 10},
2561 {56, 0x58, 0, 0},
2562 {60, 0x58, 0, 4},
2563 {62, 0x58, 0, 6},
2564 {64, 0x58, 0, 8},
2565
2566 /* 802.11 HyperLan 2 */
2567 {100, 0x5b, 0, 8},
2568 {102, 0x5b, 0, 10},
2569 {104, 0x5c, 0, 0},
2570 {108, 0x5c, 0, 4},
2571 {110, 0x5c, 0, 6},
2572 {112, 0x5c, 0, 8},
2573 {116, 0x5d, 0, 0},
2574 {118, 0x5d, 0, 2},
2575 {120, 0x5d, 0, 4},
2576 {124, 0x5d, 0, 8},
2577 {126, 0x5d, 0, 10},
2578 {128, 0x5e, 0, 0},
2579 {132, 0x5e, 0, 4},
2580 {134, 0x5e, 0, 6},
2581 {136, 0x5e, 0, 8},
2582 {140, 0x5f, 0, 0},
2583
2584 /* 802.11 UNII */
2585 {149, 0x5f, 0, 9},
2586 {151, 0x5f, 0, 11},
2587 {153, 0x60, 0, 1},
2588 {157, 0x60, 0, 5},
2589 {159, 0x60, 0, 7},
2590 {161, 0x60, 0, 9},
2591 {165, 0x61, 0, 1},
2592 {167, 0x61, 0, 3},
2593 {169, 0x61, 0, 5},
2594 {171, 0x61, 0, 7},
2595 {173, 0x61, 0, 9},
2596 };
2597
2598 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2599 {
2600 struct hw_mode_spec *spec = &rt2x00dev->spec;
2601 struct channel_info *info;
2602 char *tx_power1;
2603 char *tx_power2;
2604 unsigned int i;
2605 u16 eeprom;
2606
2607 /*
2608 * Disable powersaving as default on PCI devices.
2609 */
2610 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2611 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2612
2613 /*
2614 * Initialize all hw fields.
2615 */
2616 rt2x00dev->hw->flags =
2617 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2618 IEEE80211_HW_SIGNAL_DBM |
2619 IEEE80211_HW_SUPPORTS_PS |
2620 IEEE80211_HW_PS_NULLFUNC_STACK |
2621 IEEE80211_HW_AMPDU_AGGREGATION;
2622
2623 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2624 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2625 rt2x00_eeprom_addr(rt2x00dev,
2626 EEPROM_MAC_ADDR_0));
2627
2628 /*
2629 * As rt2800 has a global fallback table we cannot specify
2630 * more then one tx rate per frame but since the hw will
2631 * try several rates (based on the fallback table) we should
2632 * still initialize max_rates to the maximum number of rates
2633 * we are going to try. Otherwise mac80211 will truncate our
2634 * reported tx rates and the rc algortihm will end up with
2635 * incorrect data.
2636 */
2637 rt2x00dev->hw->max_rates = 7;
2638 rt2x00dev->hw->max_rate_tries = 1;
2639
2640 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2641
2642 /*
2643 * Initialize hw_mode information.
2644 */
2645 spec->supported_bands = SUPPORT_BAND_2GHZ;
2646 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2647
2648 if (rt2x00_rf(rt2x00dev, RF2820) ||
2649 rt2x00_rf(rt2x00dev, RF2720)) {
2650 spec->num_channels = 14;
2651 spec->channels = rf_vals;
2652 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2653 rt2x00_rf(rt2x00dev, RF2750)) {
2654 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2655 spec->num_channels = ARRAY_SIZE(rf_vals);
2656 spec->channels = rf_vals;
2657 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2658 rt2x00_rf(rt2x00dev, RF2020) ||
2659 rt2x00_rf(rt2x00dev, RF3021) ||
2660 rt2x00_rf(rt2x00dev, RF3022)) {
2661 spec->num_channels = 14;
2662 spec->channels = rf_vals_3x;
2663 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2664 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2665 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2666 spec->channels = rf_vals_3x;
2667 }
2668
2669 /*
2670 * Initialize HT information.
2671 */
2672 if (!rt2x00_rf(rt2x00dev, RF2020))
2673 spec->ht.ht_supported = true;
2674 else
2675 spec->ht.ht_supported = false;
2676
2677 spec->ht.cap =
2678 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2679 IEEE80211_HT_CAP_GRN_FLD |
2680 IEEE80211_HT_CAP_SGI_20 |
2681 IEEE80211_HT_CAP_SGI_40;
2682
2683 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
2684 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2685
2686 spec->ht.cap |=
2687 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
2688 IEEE80211_HT_CAP_RX_STBC_SHIFT;
2689
2690 spec->ht.ampdu_factor = 3;
2691 spec->ht.ampdu_density = 4;
2692 spec->ht.mcs.tx_params =
2693 IEEE80211_HT_MCS_TX_DEFINED |
2694 IEEE80211_HT_MCS_TX_RX_DIFF |
2695 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2696 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2697
2698 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2699 case 3:
2700 spec->ht.mcs.rx_mask[2] = 0xff;
2701 case 2:
2702 spec->ht.mcs.rx_mask[1] = 0xff;
2703 case 1:
2704 spec->ht.mcs.rx_mask[0] = 0xff;
2705 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2706 break;
2707 }
2708
2709 /*
2710 * Create channel information array
2711 */
2712 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2713 if (!info)
2714 return -ENOMEM;
2715
2716 spec->channels_info = info;
2717
2718 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2719 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2720
2721 for (i = 0; i < 14; i++) {
2722 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2723 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2724 }
2725
2726 if (spec->num_channels > 14) {
2727 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2728 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2729
2730 for (i = 14; i < spec->num_channels; i++) {
2731 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2732 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2733 }
2734 }
2735
2736 return 0;
2737 }
2738 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2739
2740 /*
2741 * IEEE80211 stack callback functions.
2742 */
2743 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
2744 u16 *iv16)
2745 {
2746 struct rt2x00_dev *rt2x00dev = hw->priv;
2747 struct mac_iveiv_entry iveiv_entry;
2748 u32 offset;
2749
2750 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2751 rt2800_register_multiread(rt2x00dev, offset,
2752 &iveiv_entry, sizeof(iveiv_entry));
2753
2754 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2755 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2756 }
2757 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2758
2759 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2760 {
2761 struct rt2x00_dev *rt2x00dev = hw->priv;
2762 u32 reg;
2763 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2764
2765 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2766 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2767 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2768
2769 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2770 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2771 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2772
2773 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2774 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2775 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2776
2777 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2778 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2779 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2780
2781 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2782 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2783 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2784
2785 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2786 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2787 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2788
2789 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2790 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2791 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2792
2793 return 0;
2794 }
2795 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2796
2797 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2798 const struct ieee80211_tx_queue_params *params)
2799 {
2800 struct rt2x00_dev *rt2x00dev = hw->priv;
2801 struct data_queue *queue;
2802 struct rt2x00_field32 field;
2803 int retval;
2804 u32 reg;
2805 u32 offset;
2806
2807 /*
2808 * First pass the configuration through rt2x00lib, that will
2809 * update the queue settings and validate the input. After that
2810 * we are free to update the registers based on the value
2811 * in the queue parameter.
2812 */
2813 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2814 if (retval)
2815 return retval;
2816
2817 /*
2818 * We only need to perform additional register initialization
2819 * for WMM queues/
2820 */
2821 if (queue_idx >= 4)
2822 return 0;
2823
2824 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2825
2826 /* Update WMM TXOP register */
2827 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2828 field.bit_offset = (queue_idx & 1) * 16;
2829 field.bit_mask = 0xffff << field.bit_offset;
2830
2831 rt2800_register_read(rt2x00dev, offset, &reg);
2832 rt2x00_set_field32(&reg, field, queue->txop);
2833 rt2800_register_write(rt2x00dev, offset, reg);
2834
2835 /* Update WMM registers */
2836 field.bit_offset = queue_idx * 4;
2837 field.bit_mask = 0xf << field.bit_offset;
2838
2839 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2840 rt2x00_set_field32(&reg, field, queue->aifs);
2841 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2842
2843 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2844 rt2x00_set_field32(&reg, field, queue->cw_min);
2845 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2846
2847 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2848 rt2x00_set_field32(&reg, field, queue->cw_max);
2849 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2850
2851 /* Update EDCA registers */
2852 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2853
2854 rt2800_register_read(rt2x00dev, offset, &reg);
2855 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2856 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2857 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2858 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2859 rt2800_register_write(rt2x00dev, offset, reg);
2860
2861 return 0;
2862 }
2863 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2864
2865 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2866 {
2867 struct rt2x00_dev *rt2x00dev = hw->priv;
2868 u64 tsf;
2869 u32 reg;
2870
2871 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2872 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2873 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2874 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2875
2876 return tsf;
2877 }
2878 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2879
2880 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2881 enum ieee80211_ampdu_mlme_action action,
2882 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
2883 {
2884 int ret = 0;
2885
2886 switch (action) {
2887 case IEEE80211_AMPDU_RX_START:
2888 case IEEE80211_AMPDU_RX_STOP:
2889 /* we don't support RX aggregation yet */
2890 ret = -ENOTSUPP;
2891 break;
2892 case IEEE80211_AMPDU_TX_START:
2893 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2894 break;
2895 case IEEE80211_AMPDU_TX_STOP:
2896 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2897 break;
2898 case IEEE80211_AMPDU_TX_OPERATIONAL:
2899 break;
2900 default:
2901 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
2902 }
2903
2904 return ret;
2905 }
2906 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
2907
2908 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
2909 MODULE_VERSION(DRV_VERSION);
2910 MODULE_DESCRIPTION("Ralink RT2800 library");
2911 MODULE_LICENSE("GPL");
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