2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev
*rt2x00dev
)
229 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
230 if (rt2x00_get_field32(reg
, WLAN_EN
))
233 rt2x00_set_field32(®
, WLAN_GPIO_OUT_OE_BIT_ALL
, 0xff);
234 rt2x00_set_field32(®
, FRC_WL_ANT_SET
, 1);
235 rt2x00_set_field32(®
, WLAN_CLK_EN
, 0);
236 rt2x00_set_field32(®
, WLAN_EN
, 1);
237 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
239 udelay(REGISTER_BUSY_DELAY
);
244 * Check PLL_LD & XTAL_RDY.
246 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
247 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
248 if (rt2x00_get_field32(reg
, PLL_LD
) &&
249 rt2x00_get_field32(reg
, XTAL_RDY
))
251 udelay(REGISTER_BUSY_DELAY
);
254 if (i
>= REGISTER_BUSY_COUNT
) {
259 rt2800_register_write(rt2x00dev
, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY
);
261 rt2800_register_write(rt2x00dev
, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY
);
263 rt2800_register_write(rt2x00dev
, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY
);
270 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
271 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 0);
272 rt2x00_set_field32(®
, WLAN_CLK_EN
, 1);
273 rt2x00_set_field32(®
, WLAN_RESET
, 1);
274 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
276 rt2x00_set_field32(®
, WLAN_RESET
, 0);
277 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
279 rt2800_register_write(rt2x00dev
, INT_SOURCE_CSR
, 0x7fffffff);
280 } while (count
!= 0);
285 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
286 const u8 command
, const u8 token
,
287 const u8 arg0
, const u8 arg1
)
292 * SOC devices don't support MCU requests.
294 if (rt2x00_is_soc(rt2x00dev
))
297 mutex_lock(&rt2x00dev
->csr_mutex
);
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
303 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
304 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
305 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
306 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
307 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
308 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
311 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
312 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
315 mutex_unlock(&rt2x00dev
->csr_mutex
);
317 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
319 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
324 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
325 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
326 if (reg
&& reg
!= ~0)
331 ERROR(rt2x00dev
, "Unstable hardware.\n");
334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
336 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
342 * Some devices are really slow to respond here. Wait a whole second
345 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
346 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
347 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
348 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
354 ERROR(rt2x00dev
, "WPDMA TX/RX busy [0x%08x].\n", reg
);
357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
359 void rt2800_disable_wpdma(struct rt2x00_dev
*rt2x00dev
)
363 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
364 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
365 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
366 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
367 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
368 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
369 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma
);
373 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
383 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
392 crc
= crc_ccitt(~0, data
, len
- 2);
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
402 return fw_crc
== crc
;
405 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
406 const u8
*data
, const size_t len
)
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
421 if (rt2x00_is_usb(rt2x00dev
) || rt2x00_rt(rt2x00dev
, RT3290
))
428 * Validate the firmware length
430 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
431 return FW_BAD_LENGTH
;
434 * Check if the chipset requires one of the upper parts
437 if (rt2x00_is_usb(rt2x00dev
) &&
438 !rt2x00_rt(rt2x00dev
, RT2860
) &&
439 !rt2x00_rt(rt2x00dev
, RT2872
) &&
440 !rt2x00_rt(rt2x00dev
, RT3070
) &&
441 ((len
/ fw_len
) == 1))
442 return FW_BAD_VERSION
;
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
448 while (offset
< len
) {
449 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
457 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
459 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
460 const u8
*data
, const size_t len
)
466 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
467 retval
= rt2800_enable_wlan_rt3290(rt2x00dev
);
473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
476 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
479 * Wait for stable hardware.
481 if (rt2800_wait_csr_ready(rt2x00dev
))
484 if (rt2x00_is_pci(rt2x00dev
)) {
485 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
486 rt2x00_rt(rt2x00dev
, RT3572
) ||
487 rt2x00_rt(rt2x00dev
, RT5390
) ||
488 rt2x00_rt(rt2x00dev
, RT5392
)) {
489 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
490 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
491 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
492 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
494 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
497 rt2800_disable_wpdma(rt2x00dev
);
500 * Write firmware to the device.
502 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
505 * Wait for device to stabilize.
507 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
508 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
509 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
514 if (i
== REGISTER_BUSY_COUNT
) {
515 ERROR(rt2x00dev
, "PBF system register not ready.\n");
520 * Disable DMA, will be reenabled later when enabling
523 rt2800_disable_wpdma(rt2x00dev
);
526 * Initialize firmware.
528 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
529 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
530 if (rt2x00_is_usb(rt2x00dev
))
531 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
536 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
538 void rt2800_write_tx_data(struct queue_entry
*entry
,
539 struct txentry_desc
*txdesc
)
541 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
545 * Initialize TX Info descriptor
547 rt2x00_desc_read(txwi
, 0, &word
);
548 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
549 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
550 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
551 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
552 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
553 rt2x00_set_field32(&word
, TXWI_W0_TS
,
554 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
555 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
556 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
557 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
558 txdesc
->u
.ht
.mpdu_density
);
559 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
560 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
561 rt2x00_set_field32(&word
, TXWI_W0_BW
,
562 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
563 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
564 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
565 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
566 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
567 rt2x00_desc_write(txwi
, 0, word
);
569 rt2x00_desc_read(txwi
, 1, &word
);
570 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
571 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
572 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
573 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
574 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
575 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
576 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
577 txdesc
->key_idx
: txdesc
->u
.ht
.wcid
);
578 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
580 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
581 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
582 rt2x00_desc_write(txwi
, 1, word
);
585 * Always write 0 to IV/EIV fields, hardware will insert the IV
586 * from the IVEIV register when TXD_W3_WIV is set to 0.
587 * When TXD_W3_WIV is set to 1 it will use the IV data
588 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
589 * crypto entry in the registers should be used to encrypt the frame.
591 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
592 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
594 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
596 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
598 s8 rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
599 s8 rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
600 s8 rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
606 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
607 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
608 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
609 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
610 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
611 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
613 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
614 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
615 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
616 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
617 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
621 * Convert the value from the descriptor into the RSSI value
622 * If the value in the descriptor is 0, it is considered invalid
623 * and the default (extremely low) rssi value is assumed
625 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
626 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
627 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
630 * mac80211 only accepts a single RSSI value. Calculating the
631 * average doesn't deliver a fair answer either since -60:-60 would
632 * be considered equally good as -50:-70 while the second is the one
633 * which gives less energy...
635 rssi0
= max(rssi0
, rssi1
);
636 return (int)max(rssi0
, rssi2
);
639 void rt2800_process_rxwi(struct queue_entry
*entry
,
640 struct rxdone_entry_desc
*rxdesc
)
642 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
645 rt2x00_desc_read(rxwi
, 0, &word
);
647 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
648 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
650 rt2x00_desc_read(rxwi
, 1, &word
);
652 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
653 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
655 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
656 rxdesc
->flags
|= RX_FLAG_40MHZ
;
659 * Detect RX rate, always use MCS as signal type.
661 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
662 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
663 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
666 * Mask of 0x8 bit to remove the short preamble flag.
668 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
669 rxdesc
->signal
&= ~0x8;
671 rt2x00_desc_read(rxwi
, 2, &word
);
674 * Convert descriptor AGC value to RSSI value.
676 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
679 * Remove RXWI descriptor from start of buffer.
681 skb_pull(entry
->skb
, RXWI_DESC_SIZE
);
683 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
685 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
687 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
688 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
689 struct txdone_entry_desc txdesc
;
695 * Obtain the status about this packet.
698 rt2x00_desc_read(txwi
, 0, &word
);
700 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
701 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
703 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
704 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
707 * If a frame was meant to be sent as a single non-aggregated MPDU
708 * but ended up in an aggregate the used tx rate doesn't correlate
709 * with the one specified in the TXWI as the whole aggregate is sent
710 * with the same rate.
712 * For example: two frames are sent to rt2x00, the first one sets
713 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
714 * and requests MCS15. If the hw aggregates both frames into one
715 * AMDPU the tx status for both frames will contain MCS7 although
716 * the frame was sent successfully.
718 * Hence, replace the requested rate with the real tx rate to not
719 * confuse the rate control algortihm by providing clearly wrong
722 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
723 skbdesc
->tx_rate_idx
= real_mcs
;
727 if (aggr
== 1 || ampdu
== 1)
728 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
731 * Ralink has a retry mechanism using a global fallback
732 * table. We setup this fallback table to try the immediate
733 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
734 * always contains the MCS used for the last transmission, be
735 * it successful or not.
737 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
739 * Transmission succeeded. The number of retries is
742 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
743 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
746 * Transmission failed. The number of retries is
747 * always 7 in this case (for a total number of 8
750 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
751 txdesc
.retry
= rt2x00dev
->long_retry
;
755 * the frame was retried at least once
756 * -> hw used fallback rates
759 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
761 rt2x00lib_txdone(entry
, &txdesc
);
763 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
765 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
767 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
768 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
769 unsigned int beacon_base
;
770 unsigned int padding_len
;
774 * Disable beaconing while we are reloading the beacon data,
775 * otherwise we might be sending out invalid data.
777 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
779 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
780 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
783 * Add space for the TXWI in front of the skb.
785 memset(skb_push(entry
->skb
, TXWI_DESC_SIZE
), 0, TXWI_DESC_SIZE
);
788 * Register descriptor details in skb frame descriptor.
790 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
791 skbdesc
->desc
= entry
->skb
->data
;
792 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
795 * Add the TXWI for the beacon to the skb.
797 rt2800_write_tx_data(entry
, txdesc
);
800 * Dump beacon to userspace through debugfs.
802 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
805 * Write entire beacon with TXWI and padding to register.
807 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
808 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
809 ERROR(rt2x00dev
, "Failure padding beacon, aborting\n");
810 /* skb freed by skb_pad() on failure */
812 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
816 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
817 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
818 entry
->skb
->len
+ padding_len
);
821 * Enable beaconing again.
823 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
824 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
827 * Clean up beacon skb.
829 dev_kfree_skb_any(entry
->skb
);
832 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
834 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
835 unsigned int beacon_base
)
840 * For the Beacon base registers we only need to clear
841 * the whole TXWI which (when set to 0) will invalidate
844 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
845 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
848 void rt2800_clear_beacon(struct queue_entry
*entry
)
850 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
854 * Disable beaconing while we are reloading the beacon data,
855 * otherwise we might be sending out invalid data.
857 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
858 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
859 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
864 rt2800_clear_beacon_register(rt2x00dev
,
865 HW_BEACON_OFFSET(entry
->entry_idx
));
868 * Enabled beaconing again.
870 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
871 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
873 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
875 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
876 const struct rt2x00debug rt2800_rt2x00debug
= {
877 .owner
= THIS_MODULE
,
879 .read
= rt2800_register_read
,
880 .write
= rt2800_register_write
,
881 .flags
= RT2X00DEBUGFS_OFFSET
,
882 .word_base
= CSR_REG_BASE
,
883 .word_size
= sizeof(u32
),
884 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
887 .read
= rt2x00_eeprom_read
,
888 .write
= rt2x00_eeprom_write
,
889 .word_base
= EEPROM_BASE
,
890 .word_size
= sizeof(u16
),
891 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
894 .read
= rt2800_bbp_read
,
895 .write
= rt2800_bbp_write
,
896 .word_base
= BBP_BASE
,
897 .word_size
= sizeof(u8
),
898 .word_count
= BBP_SIZE
/ sizeof(u8
),
901 .read
= rt2x00_rf_read
,
902 .write
= rt2800_rf_write
,
903 .word_base
= RF_BASE
,
904 .word_size
= sizeof(u32
),
905 .word_count
= RF_SIZE
/ sizeof(u32
),
908 .read
= rt2800_rfcsr_read
,
909 .write
= rt2800_rfcsr_write
,
910 .word_base
= RFCSR_BASE
,
911 .word_size
= sizeof(u8
),
912 .word_count
= RFCSR_SIZE
/ sizeof(u8
),
915 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
916 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
918 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
922 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
923 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
924 return rt2x00_get_field32(reg
, WLAN_GPIO_IN_BIT0
);
926 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
927 return rt2x00_get_field32(reg
, GPIO_CTRL_VAL2
);
930 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
932 #ifdef CONFIG_RT2X00_LIB_LEDS
933 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
934 enum led_brightness brightness
)
936 struct rt2x00_led
*led
=
937 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
938 unsigned int enabled
= brightness
!= LED_OFF
;
939 unsigned int bg_mode
=
940 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
941 unsigned int polarity
=
942 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
943 EEPROM_FREQ_LED_POLARITY
);
944 unsigned int ledmode
=
945 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
946 EEPROM_FREQ_LED_MODE
);
949 /* Check for SoC (SOC devices don't support MCU requests) */
950 if (rt2x00_is_soc(led
->rt2x00dev
)) {
951 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
953 /* Set LED Polarity */
954 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
957 if (led
->type
== LED_TYPE_RADIO
) {
958 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
960 } else if (led
->type
== LED_TYPE_ASSOC
) {
961 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
963 } else if (led
->type
== LED_TYPE_QUALITY
) {
964 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
968 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
971 if (led
->type
== LED_TYPE_RADIO
) {
972 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
974 } else if (led
->type
== LED_TYPE_ASSOC
) {
975 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
976 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
977 } else if (led
->type
== LED_TYPE_QUALITY
) {
979 * The brightness is divided into 6 levels (0 - 5),
980 * The specs tell us the following levels:
982 * to determine the level in a simple way we can simply
983 * work with bitshifting:
986 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
987 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
993 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
994 struct rt2x00_led
*led
, enum led_type type
)
996 led
->rt2x00dev
= rt2x00dev
;
998 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
999 led
->flags
= LED_INITIALIZED
;
1001 #endif /* CONFIG_RT2X00_LIB_LEDS */
1004 * Configuration handlers.
1006 static void rt2800_config_wcid(struct rt2x00_dev
*rt2x00dev
,
1010 struct mac_wcid_entry wcid_entry
;
1013 offset
= MAC_WCID_ENTRY(wcid
);
1015 memset(&wcid_entry
, 0xff, sizeof(wcid_entry
));
1017 memcpy(wcid_entry
.mac
, address
, ETH_ALEN
);
1019 rt2800_register_multiwrite(rt2x00dev
, offset
,
1020 &wcid_entry
, sizeof(wcid_entry
));
1023 static void rt2800_delete_wcid_attr(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1026 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1027 rt2800_register_write(rt2x00dev
, offset
, 0);
1030 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev
*rt2x00dev
,
1031 int wcid
, u32 bssidx
)
1033 u32 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1037 * The BSS Idx numbers is split in a main value of 3 bits,
1038 * and a extended field for adding one additional bit to the value.
1040 rt2800_register_read(rt2x00dev
, offset
, ®
);
1041 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
, (bssidx
& 0x7));
1042 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
1043 (bssidx
& 0x8) >> 3);
1044 rt2800_register_write(rt2x00dev
, offset
, reg
);
1047 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev
*rt2x00dev
,
1048 struct rt2x00lib_crypto
*crypto
,
1049 struct ieee80211_key_conf
*key
)
1051 struct mac_iveiv_entry iveiv_entry
;
1055 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
1057 if (crypto
->cmd
== SET_KEY
) {
1058 rt2800_register_read(rt2x00dev
, offset
, ®
);
1059 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
1060 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
1062 * Both the cipher as the BSS Idx numbers are split in a main
1063 * value of 3 bits, and a extended field for adding one additional
1066 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
1067 (crypto
->cipher
& 0x7));
1068 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
1069 (crypto
->cipher
& 0x8) >> 3);
1070 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
1071 rt2800_register_write(rt2x00dev
, offset
, reg
);
1073 /* Delete the cipher without touching the bssidx */
1074 rt2800_register_read(rt2x00dev
, offset
, ®
);
1075 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
, 0);
1076 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
, 0);
1077 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
, 0);
1078 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, 0);
1079 rt2800_register_write(rt2x00dev
, offset
, reg
);
1082 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
1084 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
1085 if ((crypto
->cipher
== CIPHER_TKIP
) ||
1086 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
1087 (crypto
->cipher
== CIPHER_AES
))
1088 iveiv_entry
.iv
[3] |= 0x20;
1089 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
1090 rt2800_register_multiwrite(rt2x00dev
, offset
,
1091 &iveiv_entry
, sizeof(iveiv_entry
));
1094 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1095 struct rt2x00lib_crypto
*crypto
,
1096 struct ieee80211_key_conf
*key
)
1098 struct hw_key_entry key_entry
;
1099 struct rt2x00_field32 field
;
1103 if (crypto
->cmd
== SET_KEY
) {
1104 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1106 memcpy(key_entry
.key
, crypto
->key
,
1107 sizeof(key_entry
.key
));
1108 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1109 sizeof(key_entry
.tx_mic
));
1110 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1111 sizeof(key_entry
.rx_mic
));
1113 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1114 rt2800_register_multiwrite(rt2x00dev
, offset
,
1115 &key_entry
, sizeof(key_entry
));
1119 * The cipher types are stored over multiple registers
1120 * starting with SHARED_KEY_MODE_BASE each word will have
1121 * 32 bits and contains the cipher types for 2 bssidx each.
1122 * Using the correct defines correctly will cause overhead,
1123 * so just calculate the correct offset.
1125 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1126 field
.bit_mask
= 0x7 << field
.bit_offset
;
1128 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1130 rt2800_register_read(rt2x00dev
, offset
, ®
);
1131 rt2x00_set_field32(®
, field
,
1132 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1133 rt2800_register_write(rt2x00dev
, offset
, reg
);
1136 * Update WCID information
1138 rt2800_config_wcid(rt2x00dev
, crypto
->address
, key
->hw_key_idx
);
1139 rt2800_config_wcid_attr_bssidx(rt2x00dev
, key
->hw_key_idx
,
1141 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1145 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1147 static inline int rt2800_find_wcid(struct rt2x00_dev
*rt2x00dev
)
1149 struct mac_wcid_entry wcid_entry
;
1154 * Search for the first free WCID entry and return the corresponding
1157 * Make sure the WCID starts _after_ the last possible shared key
1160 * Since parts of the pairwise key table might be shared with
1161 * the beacon frame buffers 6 & 7 we should only write into the
1162 * first 222 entries.
1164 for (idx
= 33; idx
<= 222; idx
++) {
1165 offset
= MAC_WCID_ENTRY(idx
);
1166 rt2800_register_multiread(rt2x00dev
, offset
, &wcid_entry
,
1167 sizeof(wcid_entry
));
1168 if (is_broadcast_ether_addr(wcid_entry
.mac
))
1173 * Use -1 to indicate that we don't have any more space in the WCID
1179 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1180 struct rt2x00lib_crypto
*crypto
,
1181 struct ieee80211_key_conf
*key
)
1183 struct hw_key_entry key_entry
;
1186 if (crypto
->cmd
== SET_KEY
) {
1188 * Allow key configuration only for STAs that are
1191 if (crypto
->wcid
< 0)
1193 key
->hw_key_idx
= crypto
->wcid
;
1195 memcpy(key_entry
.key
, crypto
->key
,
1196 sizeof(key_entry
.key
));
1197 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1198 sizeof(key_entry
.tx_mic
));
1199 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1200 sizeof(key_entry
.rx_mic
));
1202 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1203 rt2800_register_multiwrite(rt2x00dev
, offset
,
1204 &key_entry
, sizeof(key_entry
));
1208 * Update WCID information
1210 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1214 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1216 int rt2800_sta_add(struct rt2x00_dev
*rt2x00dev
, struct ieee80211_vif
*vif
,
1217 struct ieee80211_sta
*sta
)
1220 struct rt2x00_sta
*sta_priv
= sta_to_rt2x00_sta(sta
);
1223 * Find next free WCID.
1225 wcid
= rt2800_find_wcid(rt2x00dev
);
1228 * Store selected wcid even if it is invalid so that we can
1229 * later decide if the STA is uploaded into the hw.
1231 sta_priv
->wcid
= wcid
;
1234 * No space left in the device, however, we can still communicate
1235 * with the STA -> No error.
1241 * Clean up WCID attributes and write STA address to the device.
1243 rt2800_delete_wcid_attr(rt2x00dev
, wcid
);
1244 rt2800_config_wcid(rt2x00dev
, sta
->addr
, wcid
);
1245 rt2800_config_wcid_attr_bssidx(rt2x00dev
, wcid
,
1246 rt2x00lib_get_bssidx(rt2x00dev
, vif
));
1249 EXPORT_SYMBOL_GPL(rt2800_sta_add
);
1251 int rt2800_sta_remove(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1254 * Remove WCID entry, no need to clean the attributes as they will
1255 * get renewed when the WCID is reused.
1257 rt2800_config_wcid(rt2x00dev
, NULL
, wcid
);
1261 EXPORT_SYMBOL_GPL(rt2800_sta_remove
);
1263 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1264 const unsigned int filter_flags
)
1269 * Start configuration steps.
1270 * Note that the version error will always be dropped
1271 * and broadcast frames will always be accepted since
1272 * there is no filter for it at this time.
1274 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1275 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1276 !(filter_flags
& FIF_FCSFAIL
));
1277 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1278 !(filter_flags
& FIF_PLCPFAIL
));
1279 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1280 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1281 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1282 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1283 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1284 !(filter_flags
& FIF_ALLMULTI
));
1285 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1286 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1287 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1288 !(filter_flags
& FIF_CONTROL
));
1289 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1290 !(filter_flags
& FIF_CONTROL
));
1291 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1292 !(filter_flags
& FIF_CONTROL
));
1293 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1294 !(filter_flags
& FIF_CONTROL
));
1295 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1296 !(filter_flags
& FIF_CONTROL
));
1297 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1298 !(filter_flags
& FIF_PSPOLL
));
1299 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
,
1300 !(filter_flags
& FIF_CONTROL
));
1301 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
,
1302 !(filter_flags
& FIF_CONTROL
));
1303 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1304 !(filter_flags
& FIF_CONTROL
));
1305 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1307 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1309 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1310 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1313 bool update_bssid
= false;
1315 if (flags
& CONFIG_UPDATE_TYPE
) {
1317 * Enable synchronisation.
1319 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1320 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1321 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1323 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1325 * Tune beacon queue transmit parameters for AP mode
1327 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1328 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1329 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1330 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1331 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1332 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1334 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1335 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1336 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1337 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1338 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1339 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1343 if (flags
& CONFIG_UPDATE_MAC
) {
1344 if (flags
& CONFIG_UPDATE_TYPE
&&
1345 conf
->sync
== TSF_SYNC_AP_NONE
) {
1347 * The BSSID register has to be set to our own mac
1348 * address in AP mode.
1350 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1351 update_bssid
= true;
1354 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1355 reg
= le32_to_cpu(conf
->mac
[1]);
1356 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1357 conf
->mac
[1] = cpu_to_le32(reg
);
1360 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1361 conf
->mac
, sizeof(conf
->mac
));
1364 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1365 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1366 reg
= le32_to_cpu(conf
->bssid
[1]);
1367 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1368 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1369 conf
->bssid
[1] = cpu_to_le32(reg
);
1372 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1373 conf
->bssid
, sizeof(conf
->bssid
));
1376 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1378 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1379 struct rt2x00lib_erp
*erp
)
1381 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1382 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1383 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1384 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1385 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1388 /* default protection rate for HT20: OFDM 24M */
1389 mm20_rate
= gf20_rate
= 0x4004;
1391 /* default protection rate for HT40: duplicate OFDM 24M */
1392 mm40_rate
= gf40_rate
= 0x4084;
1394 switch (protection
) {
1395 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1397 * All STAs in this BSS are HT20/40 but there might be
1398 * STAs not supporting greenfield mode.
1399 * => Disable protection for HT transmissions.
1401 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1404 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1406 * All STAs in this BSS are HT20 or HT20/40 but there
1407 * might be STAs not supporting greenfield mode.
1408 * => Protect all HT40 transmissions.
1410 mm20_mode
= gf20_mode
= 0;
1411 mm40_mode
= gf40_mode
= 2;
1414 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1416 * Nonmember protection:
1417 * According to 802.11n we _should_ protect all
1418 * HT transmissions (but we don't have to).
1420 * But if cts_protection is enabled we _shall_ protect
1421 * all HT transmissions using a CCK rate.
1423 * And if any station is non GF we _shall_ protect
1426 * We decide to protect everything
1427 * -> fall through to mixed mode.
1429 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1431 * Legacy STAs are present
1432 * => Protect all HT transmissions.
1434 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1437 * If erp protection is needed we have to protect HT
1438 * transmissions with CCK 11M long preamble.
1440 if (erp
->cts_protection
) {
1441 /* don't duplicate RTS/CTS in CCK mode */
1442 mm20_rate
= mm40_rate
= 0x0003;
1443 gf20_rate
= gf40_rate
= 0x0003;
1448 /* check for STAs not supporting greenfield mode */
1450 gf20_mode
= gf40_mode
= 2;
1452 /* Update HT protection config */
1453 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1454 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1455 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1456 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1458 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1459 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1460 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1461 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1463 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1464 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1465 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1466 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1468 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1469 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1470 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1471 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1474 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1479 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1480 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1481 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1482 !!erp
->short_preamble
);
1483 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1484 !!erp
->short_preamble
);
1485 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1488 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1489 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1490 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1491 erp
->cts_protection
? 2 : 0);
1492 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1495 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1496 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1498 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1501 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1502 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1503 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1505 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1507 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1508 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1509 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1512 if (changed
& BSS_CHANGED_BEACON_INT
) {
1513 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1514 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1515 erp
->beacon_int
* 16);
1516 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1519 if (changed
& BSS_CHANGED_HT
)
1520 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1522 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1524 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1528 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1530 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1531 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1532 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1533 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1535 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1536 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1538 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1540 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1541 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1542 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1543 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1544 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1545 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1546 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1547 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1548 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1549 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1550 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1552 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1553 (led_g_mode
<< 2) | led_r_mode
, 1);
1558 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1562 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1563 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1565 if (rt2x00_is_pci(rt2x00dev
)) {
1566 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1567 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1568 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1569 } else if (rt2x00_is_usb(rt2x00dev
))
1570 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1573 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1574 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
1575 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, gpio_bit3
);
1576 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
1579 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1585 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1586 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1588 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1589 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1590 rt2800_config_3572bt_ant(rt2x00dev
);
1593 * Configure the TX antenna.
1595 switch (ant
->tx_chain_num
) {
1597 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1600 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1601 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1602 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1604 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1607 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1612 * Configure the RX antenna.
1614 switch (ant
->rx_chain_num
) {
1616 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1617 rt2x00_rt(rt2x00dev
, RT3090
) ||
1618 rt2x00_rt(rt2x00dev
, RT3352
) ||
1619 rt2x00_rt(rt2x00dev
, RT3390
)) {
1620 rt2x00_eeprom_read(rt2x00dev
,
1621 EEPROM_NIC_CONF1
, &eeprom
);
1622 if (rt2x00_get_field16(eeprom
,
1623 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1624 rt2800_set_ant_diversity(rt2x00dev
,
1625 rt2x00dev
->default_ant
.rx
);
1627 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1630 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1631 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1632 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1633 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1634 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1635 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1637 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1641 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1645 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1646 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1648 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1650 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1651 struct rt2x00lib_conf
*libconf
)
1656 if (libconf
->rf
.channel
<= 14) {
1657 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1658 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1659 } else if (libconf
->rf
.channel
<= 64) {
1660 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1661 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1662 } else if (libconf
->rf
.channel
<= 128) {
1663 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1664 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1666 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1667 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1670 rt2x00dev
->lna_gain
= lna_gain
;
1673 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1674 struct ieee80211_conf
*conf
,
1675 struct rf_channel
*rf
,
1676 struct channel_info
*info
)
1678 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1680 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1681 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1683 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1684 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1685 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1686 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1687 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1689 if (rf
->channel
> 14) {
1691 * When TX power is below 0, we should increase it by 7 to
1692 * make it a positive value (Minimum value is -7).
1693 * However this means that values between 0 and 7 have
1694 * double meaning, and we should set a 7DBm boost flag.
1696 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1697 (info
->default_power1
>= 0));
1699 if (info
->default_power1
< 0)
1700 info
->default_power1
+= 7;
1702 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1704 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1705 (info
->default_power2
>= 0));
1707 if (info
->default_power2
< 0)
1708 info
->default_power2
+= 7;
1710 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1712 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1713 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1716 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1718 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1719 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1720 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1721 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1725 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1726 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1727 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1728 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1732 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1733 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1734 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1735 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1738 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1739 struct ieee80211_conf
*conf
,
1740 struct rf_channel
*rf
,
1741 struct channel_info
*info
)
1743 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1744 u8 rfcsr
, calib_tx
, calib_rx
;
1746 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1748 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1749 rt2x00_set_field8(&rfcsr
, RFCSR3_K
, rf
->rf3
);
1750 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1752 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1753 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1754 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1756 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1757 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1758 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1760 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1761 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1762 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1764 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1765 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1766 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
1767 rt2x00dev
->default_ant
.rx_chain_num
<= 1);
1768 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
,
1769 rt2x00dev
->default_ant
.rx_chain_num
<= 2);
1770 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1771 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
1772 rt2x00dev
->default_ant
.tx_chain_num
<= 1);
1773 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
,
1774 rt2x00dev
->default_ant
.tx_chain_num
<= 2);
1775 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1777 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1778 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1779 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1781 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1782 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1784 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1785 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1786 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1788 if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1789 calib_tx
= conf_is_ht40(conf
) ? 0x68 : 0x4f;
1790 calib_rx
= conf_is_ht40(conf
) ? 0x6f : 0x4f;
1792 if (conf_is_ht40(conf
)) {
1793 calib_tx
= drv_data
->calibration_bw40
;
1794 calib_rx
= drv_data
->calibration_bw40
;
1796 calib_tx
= drv_data
->calibration_bw20
;
1797 calib_rx
= drv_data
->calibration_bw20
;
1801 rt2800_rfcsr_read(rt2x00dev
, 24, &rfcsr
);
1802 rt2x00_set_field8(&rfcsr
, RFCSR24_TX_CALIB
, calib_tx
);
1803 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr
);
1805 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
1806 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_CALIB
, calib_rx
);
1807 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
1809 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1810 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1811 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1813 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1814 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1815 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1817 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1818 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1821 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
1822 struct ieee80211_conf
*conf
,
1823 struct rf_channel
*rf
,
1824 struct channel_info
*info
)
1826 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1830 if (rf
->channel
<= 14) {
1831 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
1832 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
1834 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
1835 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
1838 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1839 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1841 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1842 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1843 if (rf
->channel
<= 14)
1844 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
1846 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
1847 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1849 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
1850 if (rf
->channel
<= 14)
1851 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
1853 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
1854 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
1856 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1857 if (rf
->channel
<= 14) {
1858 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
1859 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1860 info
->default_power1
);
1862 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
1863 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1864 (info
->default_power1
& 0x3) |
1865 ((info
->default_power1
& 0xC) << 1));
1867 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1869 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1870 if (rf
->channel
<= 14) {
1871 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
1872 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1873 info
->default_power2
);
1875 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
1876 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1877 (info
->default_power2
& 0x3) |
1878 ((info
->default_power2
& 0xC) << 1));
1880 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1882 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1883 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1884 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1885 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
1886 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
1887 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
1888 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
1889 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1890 if (rf
->channel
<= 14) {
1891 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1892 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1894 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1895 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1897 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
1899 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1901 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1905 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
1907 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1909 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1913 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1915 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1916 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1917 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1919 if (conf_is_ht40(conf
)) {
1920 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw40
);
1921 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw40
);
1923 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw20
);
1924 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw20
);
1927 if (rf
->channel
<= 14) {
1928 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
1929 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
1930 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1931 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
1932 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1934 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
1935 drv_data
->txmixer_gain_24g
);
1936 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
1937 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1938 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
1939 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
1940 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
1941 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1942 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1943 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
1945 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1946 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT2
, 1);
1947 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT3
, 0);
1948 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT4
, 1);
1949 rt2x00_set_field8(&rfcsr
, RFCSR7_BITS67
, 0);
1950 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1951 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1952 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1953 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
1954 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
1956 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
1957 drv_data
->txmixer_gain_5g
);
1958 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
1959 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1960 if (rf
->channel
<= 64) {
1961 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
1962 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
1963 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1964 } else if (rf
->channel
<= 128) {
1965 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
1966 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
1967 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1969 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
1970 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
1971 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1973 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
1974 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
1975 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
1978 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1979 rt2x00_set_field32(®
, GPIO_CTRL_DIR7
, 0);
1980 if (rf
->channel
<= 14)
1981 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 1);
1983 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 0);
1984 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
1986 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1987 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1988 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1991 #define POWER_BOUND 0x27
1992 #define FREQ_OFFSET_BOUND 0x5f
1994 static void rt2800_config_channel_rf3290(struct rt2x00_dev
*rt2x00dev
,
1995 struct ieee80211_conf
*conf
,
1996 struct rf_channel
*rf
,
1997 struct channel_info
*info
)
2001 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2002 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2003 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2004 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2005 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2007 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2008 if (info
->default_power1
> POWER_BOUND
)
2009 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2011 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2012 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2014 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2015 if (rt2x00dev
->freq_offset
> FREQ_OFFSET_BOUND
)
2016 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, FREQ_OFFSET_BOUND
);
2018 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
2019 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2021 if (rf
->channel
<= 14) {
2022 if (rf
->channel
== 6)
2023 rt2800_bbp_write(rt2x00dev
, 68, 0x0c);
2025 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
2027 if (rf
->channel
>= 1 && rf
->channel
<= 6)
2028 rt2800_bbp_write(rt2x00dev
, 59, 0x0f);
2029 else if (rf
->channel
>= 7 && rf
->channel
<= 11)
2030 rt2800_bbp_write(rt2x00dev
, 59, 0x0e);
2031 else if (rf
->channel
>= 12 && rf
->channel
<= 14)
2032 rt2800_bbp_write(rt2x00dev
, 59, 0x0d);
2036 static void rt2800_config_channel_rf3322(struct rt2x00_dev
*rt2x00dev
,
2037 struct ieee80211_conf
*conf
,
2038 struct rf_channel
*rf
,
2039 struct channel_info
*info
)
2043 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2044 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2046 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
2047 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
2048 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
2050 if (info
->default_power1
> POWER_BOUND
)
2051 rt2800_rfcsr_write(rt2x00dev
, 47, POWER_BOUND
);
2053 rt2800_rfcsr_write(rt2x00dev
, 47, info
->default_power1
);
2055 if (info
->default_power2
> POWER_BOUND
)
2056 rt2800_rfcsr_write(rt2x00dev
, 48, POWER_BOUND
);
2058 rt2800_rfcsr_write(rt2x00dev
, 48, info
->default_power2
);
2060 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2061 if (rt2x00dev
->freq_offset
> FREQ_OFFSET_BOUND
)
2062 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, FREQ_OFFSET_BOUND
);
2064 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
2066 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2068 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2069 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2070 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2072 if ( rt2x00dev
->default_ant
.tx_chain_num
== 2 )
2073 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2075 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2077 if ( rt2x00dev
->default_ant
.rx_chain_num
== 2 )
2078 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2080 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2082 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2083 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2085 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2087 rt2800_rfcsr_write(rt2x00dev
, 31, 80);
2090 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
2091 struct ieee80211_conf
*conf
,
2092 struct rf_channel
*rf
,
2093 struct channel_info
*info
)
2097 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2098 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2099 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2100 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2101 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2103 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2104 if (info
->default_power1
> POWER_BOUND
)
2105 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2107 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2108 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2110 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2111 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2112 if (info
->default_power1
> POWER_BOUND
)
2113 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, POWER_BOUND
);
2115 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
,
2116 info
->default_power2
);
2117 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2120 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2121 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2122 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2123 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2125 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2126 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2127 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2128 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2129 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2131 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2132 if (rt2x00dev
->freq_offset
> FREQ_OFFSET_BOUND
)
2133 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, FREQ_OFFSET_BOUND
);
2135 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
2136 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2138 if (rf
->channel
<= 14) {
2139 int idx
= rf
->channel
-1;
2141 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
2142 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2143 /* r55/r59 value array of channel 1~14 */
2144 static const char r55_bt_rev
[] = {0x83, 0x83,
2145 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2146 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2147 static const char r59_bt_rev
[] = {0x0e, 0x0e,
2148 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2149 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2151 rt2800_rfcsr_write(rt2x00dev
, 55,
2153 rt2800_rfcsr_write(rt2x00dev
, 59,
2156 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
2157 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2158 0x88, 0x88, 0x86, 0x85, 0x84};
2160 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
2163 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2164 static const char r55_nonbt_rev
[] = {0x23, 0x23,
2165 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2166 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2167 static const char r59_nonbt_rev
[] = {0x07, 0x07,
2168 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2169 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2171 rt2800_rfcsr_write(rt2x00dev
, 55,
2172 r55_nonbt_rev
[idx
]);
2173 rt2800_rfcsr_write(rt2x00dev
, 59,
2174 r59_nonbt_rev
[idx
]);
2175 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
2176 rt2x00_rt(rt2x00dev
, RT5392
)) {
2177 static const char r59_non_bt
[] = {0x8f, 0x8f,
2178 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2179 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2181 rt2800_rfcsr_write(rt2x00dev
, 59,
2188 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
2189 struct ieee80211_conf
*conf
,
2190 struct rf_channel
*rf
,
2191 struct channel_info
*info
)
2194 unsigned int tx_pin
;
2197 if (rf
->channel
<= 14) {
2198 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
2199 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
2201 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
2202 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
2205 switch (rt2x00dev
->chip
.rf
) {
2211 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
2214 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
2217 rt2800_config_channel_rf3290(rt2x00dev
, conf
, rf
, info
);
2220 rt2800_config_channel_rf3322(rt2x00dev
, conf
, rf
, info
);
2227 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
2230 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
2233 if (rt2x00_rf(rt2x00dev
, RF3290
) ||
2234 rt2x00_rf(rt2x00dev
, RF3322
) ||
2235 rt2x00_rf(rt2x00dev
, RF5360
) ||
2236 rt2x00_rf(rt2x00dev
, RF5370
) ||
2237 rt2x00_rf(rt2x00dev
, RF5372
) ||
2238 rt2x00_rf(rt2x00dev
, RF5390
) ||
2239 rt2x00_rf(rt2x00dev
, RF5392
)) {
2240 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2241 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
2242 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
2243 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2245 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2246 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2247 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2251 * Change BBP settings
2253 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
2254 rt2800_bbp_write(rt2x00dev
, 27, 0x0);
2255 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
2256 rt2800_bbp_write(rt2x00dev
, 27, 0x20);
2257 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
2259 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2260 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2261 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2262 rt2800_bbp_write(rt2x00dev
, 86, 0);
2265 if (rf
->channel
<= 14) {
2266 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
2267 !rt2x00_rt(rt2x00dev
, RT5392
)) {
2268 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
2269 &rt2x00dev
->cap_flags
)) {
2270 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2271 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2273 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
2274 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2278 if (rt2x00_rt(rt2x00dev
, RT3572
))
2279 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
2281 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
2283 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
2284 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2286 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2289 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
2290 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
2291 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
2292 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
2293 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
2295 if (rt2x00_rt(rt2x00dev
, RT3572
))
2296 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
2300 /* Turn on unused PA or LNA when not using 1T or 1R */
2301 if (rt2x00dev
->default_ant
.tx_chain_num
== 2) {
2302 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
2304 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
2308 /* Turn on unused PA or LNA when not using 1T or 1R */
2309 if (rt2x00dev
->default_ant
.rx_chain_num
== 2) {
2310 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
2311 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
2314 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
2315 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
2316 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
2317 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
2318 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
2319 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
2321 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
2323 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
2325 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2327 if (rt2x00_rt(rt2x00dev
, RT3572
))
2328 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
2330 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2331 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
2332 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2334 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
2335 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
2336 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
2338 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2339 if (conf_is_ht40(conf
)) {
2340 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
2341 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2342 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
2344 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2345 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
2346 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
2353 * Clear channel statistic counters
2355 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
2356 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
2357 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
2362 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
2363 rt2800_bbp_read(rt2x00dev
, 49, &bbp
);
2364 rt2x00_set_field8(&bbp
, BBP49_UPDATE_FLAG
, 0);
2365 rt2800_bbp_write(rt2x00dev
, 49, bbp
);
2369 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
2378 * Read TSSI boundaries for temperature compensation from
2381 * Array idx 0 1 2 3 4 5 6 7 8
2382 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2383 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2385 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2386 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
2387 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2388 EEPROM_TSSI_BOUND_BG1_MINUS4
);
2389 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2390 EEPROM_TSSI_BOUND_BG1_MINUS3
);
2392 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
2393 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2394 EEPROM_TSSI_BOUND_BG2_MINUS2
);
2395 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2396 EEPROM_TSSI_BOUND_BG2_MINUS1
);
2398 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
2399 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2400 EEPROM_TSSI_BOUND_BG3_REF
);
2401 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2402 EEPROM_TSSI_BOUND_BG3_PLUS1
);
2404 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
2405 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2406 EEPROM_TSSI_BOUND_BG4_PLUS2
);
2407 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2408 EEPROM_TSSI_BOUND_BG4_PLUS3
);
2410 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
2411 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2412 EEPROM_TSSI_BOUND_BG5_PLUS4
);
2414 step
= rt2x00_get_field16(eeprom
,
2415 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
2417 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
2418 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2419 EEPROM_TSSI_BOUND_A1_MINUS4
);
2420 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2421 EEPROM_TSSI_BOUND_A1_MINUS3
);
2423 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
2424 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2425 EEPROM_TSSI_BOUND_A2_MINUS2
);
2426 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2427 EEPROM_TSSI_BOUND_A2_MINUS1
);
2429 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
2430 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2431 EEPROM_TSSI_BOUND_A3_REF
);
2432 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2433 EEPROM_TSSI_BOUND_A3_PLUS1
);
2435 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
2436 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2437 EEPROM_TSSI_BOUND_A4_PLUS2
);
2438 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2439 EEPROM_TSSI_BOUND_A4_PLUS3
);
2441 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
2442 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2443 EEPROM_TSSI_BOUND_A5_PLUS4
);
2445 step
= rt2x00_get_field16(eeprom
,
2446 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
2450 * Check if temperature compensation is supported.
2452 if (tssi_bounds
[4] == 0xff)
2456 * Read current TSSI (BBP 49).
2458 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
2461 * Compare TSSI value (BBP49) with the compensation boundaries
2462 * from the EEPROM and increase or decrease tx power.
2464 for (i
= 0; i
<= 3; i
++) {
2465 if (current_tssi
> tssi_bounds
[i
])
2470 for (i
= 8; i
>= 5; i
--) {
2471 if (current_tssi
< tssi_bounds
[i
])
2476 return (i
- 4) * step
;
2479 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
2480 enum ieee80211_band band
)
2487 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
2490 * HT40 compensation not required.
2492 if (eeprom
== 0xffff ||
2493 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2496 if (band
== IEEE80211_BAND_2GHZ
) {
2497 comp_en
= rt2x00_get_field16(eeprom
,
2498 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
2500 comp_type
= rt2x00_get_field16(eeprom
,
2501 EEPROM_TXPOWER_DELTA_TYPE_2G
);
2502 comp_value
= rt2x00_get_field16(eeprom
,
2503 EEPROM_TXPOWER_DELTA_VALUE_2G
);
2505 comp_value
= -comp_value
;
2508 comp_en
= rt2x00_get_field16(eeprom
,
2509 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
2511 comp_type
= rt2x00_get_field16(eeprom
,
2512 EEPROM_TXPOWER_DELTA_TYPE_5G
);
2513 comp_value
= rt2x00_get_field16(eeprom
,
2514 EEPROM_TXPOWER_DELTA_VALUE_5G
);
2516 comp_value
= -comp_value
;
2523 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
2524 enum ieee80211_band band
, int power_level
,
2525 u8 txpower
, int delta
)
2530 u8 eirp_txpower_criterion
;
2533 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
2535 * Check if eirp txpower exceed txpower_limit.
2536 * We use OFDM 6M as criterion and its eirp txpower
2537 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2538 * .11b data rate need add additional 4dbm
2539 * when calculating eirp txpower.
2541 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ 1,
2543 criterion
= rt2x00_get_field16(eeprom
,
2544 EEPROM_TXPOWER_BYRATE_RATE0
);
2546 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
,
2549 if (band
== IEEE80211_BAND_2GHZ
)
2550 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2551 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
2553 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2554 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
2556 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
2557 (is_rate_b
? 4 : 0) + delta
;
2559 reg_limit
= (eirp_txpower
> power_level
) ?
2560 (eirp_txpower
- power_level
) : 0;
2564 txpower
= max(0, txpower
+ delta
- reg_limit
);
2565 return min_t(u8
, txpower
, 0xc);
2568 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
2569 struct ieee80211_channel
*chan
,
2575 int i
, is_rate_b
, delta
, power_ctrl
;
2576 enum ieee80211_band band
= chan
->band
;
2579 * Calculate HT40 compensation delta
2581 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
2584 * calculate temperature compensation delta
2586 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
2589 * BBP_R1 controls TX power for all rates, it allow to set the following
2590 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2592 * TODO: we do not use +6 dBm option to do not increase power beyond
2593 * regulatory limit, however this could be utilized for devices with
2594 * CAPABILITY_POWER_LIMIT.
2596 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
2600 } else if (delta
<= -6) {
2606 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, power_ctrl
);
2607 rt2800_bbp_write(rt2x00dev
, 1, r1
);
2608 offset
= TX_PWR_CFG_0
;
2610 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
2611 /* just to be safe */
2612 if (offset
> TX_PWR_CFG_4
)
2615 rt2800_register_read(rt2x00dev
, offset
, ®
);
2617 /* read the next four txpower values */
2618 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
2621 is_rate_b
= i
? 0 : 1;
2623 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2624 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2625 * TX_PWR_CFG_4: unknown
2627 txpower
= rt2x00_get_field16(eeprom
,
2628 EEPROM_TXPOWER_BYRATE_RATE0
);
2629 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2630 power_level
, txpower
, delta
);
2631 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
2634 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2635 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2636 * TX_PWR_CFG_4: unknown
2638 txpower
= rt2x00_get_field16(eeprom
,
2639 EEPROM_TXPOWER_BYRATE_RATE1
);
2640 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2641 power_level
, txpower
, delta
);
2642 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
2645 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2646 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2647 * TX_PWR_CFG_4: unknown
2649 txpower
= rt2x00_get_field16(eeprom
,
2650 EEPROM_TXPOWER_BYRATE_RATE2
);
2651 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2652 power_level
, txpower
, delta
);
2653 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
2656 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2657 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2658 * TX_PWR_CFG_4: unknown
2660 txpower
= rt2x00_get_field16(eeprom
,
2661 EEPROM_TXPOWER_BYRATE_RATE3
);
2662 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2663 power_level
, txpower
, delta
);
2664 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
2666 /* read the next four txpower values */
2667 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
2672 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2673 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2674 * TX_PWR_CFG_4: unknown
2676 txpower
= rt2x00_get_field16(eeprom
,
2677 EEPROM_TXPOWER_BYRATE_RATE0
);
2678 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2679 power_level
, txpower
, delta
);
2680 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
2683 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2684 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2685 * TX_PWR_CFG_4: unknown
2687 txpower
= rt2x00_get_field16(eeprom
,
2688 EEPROM_TXPOWER_BYRATE_RATE1
);
2689 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2690 power_level
, txpower
, delta
);
2691 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
2694 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2695 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2696 * TX_PWR_CFG_4: unknown
2698 txpower
= rt2x00_get_field16(eeprom
,
2699 EEPROM_TXPOWER_BYRATE_RATE2
);
2700 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2701 power_level
, txpower
, delta
);
2702 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
2705 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2706 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2707 * TX_PWR_CFG_4: unknown
2709 txpower
= rt2x00_get_field16(eeprom
,
2710 EEPROM_TXPOWER_BYRATE_RATE3
);
2711 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2712 power_level
, txpower
, delta
);
2713 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
2715 rt2800_register_write(rt2x00dev
, offset
, reg
);
2717 /* next TX_PWR_CFG register */
2722 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
2724 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->hw
->conf
.channel
,
2725 rt2x00dev
->tx_power
);
2727 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
2729 void rt2800_vco_calibration(struct rt2x00_dev
*rt2x00dev
)
2735 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2736 * designed to be controlled in oscillation frequency by a voltage
2737 * input. Maybe the temperature will affect the frequency of
2738 * oscillation to be shifted. The VCO calibration will be called
2739 * periodically to adjust the frequency to be precision.
2742 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
2743 tx_pin
&= TX_PIN_CFG_PA_PE_DISABLE
;
2744 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2746 switch (rt2x00dev
->chip
.rf
) {
2753 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2754 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
2755 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2763 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2764 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2765 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2773 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
2774 if (rt2x00dev
->rf_channel
<= 14) {
2775 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2777 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
, 1);
2780 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
2784 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
2788 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2790 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
, 1);
2793 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
2797 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, 1);
2801 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2804 EXPORT_SYMBOL_GPL(rt2800_vco_calibration
);
2806 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
2807 struct rt2x00lib_conf
*libconf
)
2811 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2812 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
2813 libconf
->conf
->short_frame_max_tx_count
);
2814 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
2815 libconf
->conf
->long_frame_max_tx_count
);
2816 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2819 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
2820 struct rt2x00lib_conf
*libconf
)
2822 enum dev_state state
=
2823 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
2824 STATE_SLEEP
: STATE_AWAKE
;
2827 if (state
== STATE_SLEEP
) {
2828 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
2830 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2831 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
2832 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
2833 libconf
->conf
->listen_interval
- 1);
2834 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
2835 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2837 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2839 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2840 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
2841 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
2842 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
2843 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2845 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2849 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
2850 struct rt2x00lib_conf
*libconf
,
2851 const unsigned int flags
)
2853 /* Always recalculate LNA gain before changing configuration */
2854 rt2800_config_lna_gain(rt2x00dev
, libconf
);
2856 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2857 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
2858 &libconf
->rf
, &libconf
->channel
);
2859 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
,
2860 libconf
->conf
->power_level
);
2862 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
2863 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
,
2864 libconf
->conf
->power_level
);
2865 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
2866 rt2800_config_retry_limit(rt2x00dev
, libconf
);
2867 if (flags
& IEEE80211_CONF_CHANGE_PS
)
2868 rt2800_config_ps(rt2x00dev
, libconf
);
2870 EXPORT_SYMBOL_GPL(rt2800_config
);
2875 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2880 * Update FCS error count from register.
2882 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2883 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
2885 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
2887 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
2891 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2892 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2893 rt2x00_rt(rt2x00dev
, RT3071
) ||
2894 rt2x00_rt(rt2x00dev
, RT3090
) ||
2895 rt2x00_rt(rt2x00dev
, RT3290
) ||
2896 rt2x00_rt(rt2x00dev
, RT3390
) ||
2897 rt2x00_rt(rt2x00dev
, RT3572
) ||
2898 rt2x00_rt(rt2x00dev
, RT5390
) ||
2899 rt2x00_rt(rt2x00dev
, RT5392
))
2900 vgc
= 0x1c + (2 * rt2x00dev
->lna_gain
);
2902 vgc
= 0x2e + rt2x00dev
->lna_gain
;
2903 } else { /* 5GHZ band */
2904 if (rt2x00_rt(rt2x00dev
, RT3572
))
2905 vgc
= 0x22 + (rt2x00dev
->lna_gain
* 5) / 3;
2907 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2908 vgc
= 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
2910 vgc
= 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
2917 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
2918 struct link_qual
*qual
, u8 vgc_level
)
2920 if (qual
->vgc_level
!= vgc_level
) {
2921 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
2922 qual
->vgc_level
= vgc_level
;
2923 qual
->vgc_level_reg
= vgc_level
;
2927 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2929 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
2931 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
2933 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
2936 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
2940 * When RSSI is better then -80 increase VGC level with 0x10
2942 rt2800_set_vgc(rt2x00dev
, qual
,
2943 rt2800_get_default_vgc(rt2x00dev
) +
2944 ((qual
->rssi
> -80) * 0x10));
2946 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
2949 * Initialization functions.
2951 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
2958 rt2800_disable_wpdma(rt2x00dev
);
2960 ret
= rt2800_drv_init_registers(rt2x00dev
);
2964 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
2965 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
2966 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
2967 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
2968 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
2969 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
2971 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
2972 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
2973 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
2974 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
2975 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
2976 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
2978 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
2979 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
2981 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
2983 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
2984 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
2985 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
2986 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
2987 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
2988 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
2989 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
2990 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
2992 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
2994 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
2995 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
2996 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
2997 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
2999 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
3000 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
3001 if (rt2x00_get_field32(reg
, WLAN_EN
) == 1) {
3002 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 1);
3003 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
3006 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
3007 if (!(rt2x00_get_field32(reg
, LDO0_EN
) == 1)) {
3008 rt2x00_set_field32(®
, LDO0_EN
, 1);
3009 rt2x00_set_field32(®
, LDO_BGSEL
, 3);
3010 rt2800_register_write(rt2x00dev
, CMB_CTRL
, reg
);
3013 rt2800_register_read(rt2x00dev
, OSC_CTRL
, ®
);
3014 rt2x00_set_field32(®
, OSC_ROSC_EN
, 1);
3015 rt2x00_set_field32(®
, OSC_CAL_REQ
, 1);
3016 rt2x00_set_field32(®
, OSC_REF_CYCLE
, 0x27);
3017 rt2800_register_write(rt2x00dev
, OSC_CTRL
, reg
);
3019 rt2800_register_read(rt2x00dev
, COEX_CFG0
, ®
);
3020 rt2x00_set_field32(®
, COEX_CFG_ANT
, 0x5e);
3021 rt2800_register_write(rt2x00dev
, COEX_CFG0
, reg
);
3023 rt2800_register_read(rt2x00dev
, COEX_CFG2
, ®
);
3024 rt2x00_set_field32(®
, BT_COEX_CFG1
, 0x00);
3025 rt2x00_set_field32(®
, BT_COEX_CFG0
, 0x17);
3026 rt2x00_set_field32(®
, WL_COEX_CFG1
, 0x93);
3027 rt2x00_set_field32(®
, WL_COEX_CFG0
, 0x7f);
3028 rt2800_register_write(rt2x00dev
, COEX_CFG2
, reg
);
3030 rt2800_register_read(rt2x00dev
, PLL_CTRL
, ®
);
3031 rt2x00_set_field32(®
, PLL_CONTROL
, 1);
3032 rt2800_register_write(rt2x00dev
, PLL_CTRL
, reg
);
3035 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3036 rt2x00_rt(rt2x00dev
, RT3090
) ||
3037 rt2x00_rt(rt2x00dev
, RT3290
) ||
3038 rt2x00_rt(rt2x00dev
, RT3390
)) {
3040 if (rt2x00_rt(rt2x00dev
, RT3290
))
3041 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
3044 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
3047 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3048 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3049 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3050 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
3051 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3052 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
3053 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3056 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3059 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3061 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3062 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3064 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
3065 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3066 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
3068 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3069 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3071 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3072 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3073 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3074 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
3075 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3076 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
3077 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3078 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3079 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3080 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3081 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3082 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3083 rt2x00_rt(rt2x00dev
, RT5392
)) {
3084 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
3085 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3086 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3088 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
3089 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3092 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
3093 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
3094 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
3095 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
3096 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
3097 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
3098 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
3099 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
3100 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
3101 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
3103 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
3104 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
3105 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
3106 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
3107 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
3109 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
3110 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
3111 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
3112 rt2x00_rt(rt2x00dev
, RT2883
) ||
3113 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
3114 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
3116 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
3117 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
3118 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
3119 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
3121 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
3122 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
3123 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
3124 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
3125 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
3126 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
3127 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
3128 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
3129 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
3131 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
3133 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
3134 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
3135 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
3136 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
3137 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
3138 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
3139 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
3140 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
3142 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
3143 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
3144 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
3145 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
3146 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
3147 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
3148 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
3149 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
3150 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
3152 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
3153 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
3154 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
3155 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3156 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3157 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3158 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3159 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3160 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3161 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3162 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
3163 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
3165 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
3166 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
3167 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
3168 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3169 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3170 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3171 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3172 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3173 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3174 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3175 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
3176 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
3178 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
3179 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
3180 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
3181 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3182 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3183 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3184 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3185 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3186 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3187 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3188 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
3189 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
3191 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
3192 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
3193 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
3194 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3195 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3196 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3197 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3198 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
3199 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3200 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
3201 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
3202 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
3204 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
3205 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
3206 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
3207 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3208 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3209 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3210 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3211 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3212 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3213 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3214 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
3215 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
3217 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
3218 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
3219 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
3220 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3221 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3222 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3223 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3224 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
3225 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3226 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
3227 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
3228 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
3230 if (rt2x00_is_usb(rt2x00dev
)) {
3231 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
3233 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3234 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
3235 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
3236 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
3237 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
3238 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
3239 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
3240 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
3241 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
3242 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
3243 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3247 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3248 * although it is reserved.
3250 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
3251 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
3252 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
3253 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
3254 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
3255 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
3256 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
3257 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
3258 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
3259 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
3260 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
3261 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
3263 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
3265 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
3266 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
3267 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
3268 IEEE80211_MAX_RTS_THRESHOLD
);
3269 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
3270 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
3272 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
3275 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3276 * time should be set to 16. However, the original Ralink driver uses
3277 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3278 * connection problems with 11g + CTS protection. Hence, use the same
3279 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3281 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
3282 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
3283 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
3284 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
3285 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
3286 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
3287 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
3289 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
3292 * ASIC will keep garbage value after boot, clear encryption keys.
3294 for (i
= 0; i
< 4; i
++)
3295 rt2800_register_write(rt2x00dev
,
3296 SHARED_KEY_MODE_ENTRY(i
), 0);
3298 for (i
= 0; i
< 256; i
++) {
3299 rt2800_config_wcid(rt2x00dev
, NULL
, i
);
3300 rt2800_delete_wcid_attr(rt2x00dev
, i
);
3301 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
3307 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE0
);
3308 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE1
);
3309 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE2
);
3310 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE3
);
3311 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE4
);
3312 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE5
);
3313 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE6
);
3314 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE7
);
3316 if (rt2x00_is_usb(rt2x00dev
)) {
3317 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3318 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
3319 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3320 } else if (rt2x00_is_pcie(rt2x00dev
)) {
3321 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3322 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
3323 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3326 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
3327 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
3328 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
3329 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
3330 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
3331 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
3332 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
3333 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
3334 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
3335 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
3337 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
3338 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
3339 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
3340 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
3341 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
3342 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
3343 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
3344 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
3345 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
3346 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
3348 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
3349 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
3350 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
3351 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
3352 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
3353 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
3354 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
3355 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
3356 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
3357 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
3359 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
3360 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
3361 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
3362 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
3363 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
3364 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
3367 * Do not force the BA window size, we use the TXWI to set it
3369 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
3370 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
3371 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
3372 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
3375 * We must clear the error counters.
3376 * These registers are cleared on read,
3377 * so we may pass a useless variable to store the value.
3379 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
3380 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
3381 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
3382 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
3383 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
3384 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
3387 * Setup leadtime for pre tbtt interrupt to 6ms
3389 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
3390 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
3391 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
3394 * Set up channel statistics timer
3396 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
3397 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
3398 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
3399 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
3400 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
3401 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
3402 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
3407 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
3412 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
3413 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
3414 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
3417 udelay(REGISTER_BUSY_DELAY
);
3420 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
3424 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
3430 * BBP was enabled after firmware was loaded,
3431 * but we need to reactivate it now.
3433 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
3434 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
3437 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
3438 rt2800_bbp_read(rt2x00dev
, 0, &value
);
3439 if ((value
!= 0xff) && (value
!= 0x00))
3441 udelay(REGISTER_BUSY_DELAY
);
3444 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
3448 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
3455 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
3456 rt2800_wait_bbp_ready(rt2x00dev
)))
3459 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3460 rt2800_bbp_write(rt2x00dev
, 3, 0x00);
3461 rt2800_bbp_write(rt2x00dev
, 4, 0x50);
3464 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3465 rt2x00_rt(rt2x00dev
, RT5390
) ||
3466 rt2x00_rt(rt2x00dev
, RT5392
)) {
3467 rt2800_bbp_read(rt2x00dev
, 4, &value
);
3468 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
3469 rt2800_bbp_write(rt2x00dev
, 4, value
);
3472 if (rt2800_is_305x_soc(rt2x00dev
) ||
3473 rt2x00_rt(rt2x00dev
, RT3290
) ||
3474 rt2x00_rt(rt2x00dev
, RT3352
) ||
3475 rt2x00_rt(rt2x00dev
, RT3572
) ||
3476 rt2x00_rt(rt2x00dev
, RT5390
) ||
3477 rt2x00_rt(rt2x00dev
, RT5392
))
3478 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
3480 if (rt2x00_rt(rt2x00dev
, RT3352
))
3481 rt2800_bbp_write(rt2x00dev
, 47, 0x48);
3483 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
3484 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
3486 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3487 rt2x00_rt(rt2x00dev
, RT3352
) ||
3488 rt2x00_rt(rt2x00dev
, RT5390
) ||
3489 rt2x00_rt(rt2x00dev
, RT5392
))
3490 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
3492 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
3493 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
3494 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
3495 } else if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3496 rt2x00_rt(rt2x00dev
, RT3352
) ||
3497 rt2x00_rt(rt2x00dev
, RT5390
) ||
3498 rt2x00_rt(rt2x00dev
, RT5392
)) {
3499 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
3500 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
3501 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
3502 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
3504 if (rt2x00_rt(rt2x00dev
, RT3290
))
3505 rt2800_bbp_write(rt2x00dev
, 77, 0x58);
3507 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
3509 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
3510 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
3513 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3515 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3516 rt2x00_rt(rt2x00dev
, RT3071
) ||
3517 rt2x00_rt(rt2x00dev
, RT3090
) ||
3518 rt2x00_rt(rt2x00dev
, RT3390
) ||
3519 rt2x00_rt(rt2x00dev
, RT3572
) ||
3520 rt2x00_rt(rt2x00dev
, RT5390
) ||
3521 rt2x00_rt(rt2x00dev
, RT5392
)) {
3522 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
3523 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
3524 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
3525 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3526 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
3527 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
3528 } else if (rt2x00_rt(rt2x00dev
, RT3290
)) {
3529 rt2800_bbp_write(rt2x00dev
, 74, 0x0b);
3530 rt2800_bbp_write(rt2x00dev
, 79, 0x18);
3531 rt2800_bbp_write(rt2x00dev
, 80, 0x09);
3532 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
3533 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3534 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
3535 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
3536 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
3538 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
3541 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3542 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3543 rt2x00_rt(rt2x00dev
, RT5390
) ||
3544 rt2x00_rt(rt2x00dev
, RT5392
))
3545 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
3547 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
3549 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
3550 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
3551 else if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3552 rt2x00_rt(rt2x00dev
, RT5390
) ||
3553 rt2x00_rt(rt2x00dev
, RT5392
))
3554 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
3556 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
3558 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3559 rt2x00_rt(rt2x00dev
, RT3352
) ||
3560 rt2x00_rt(rt2x00dev
, RT5390
) ||
3561 rt2x00_rt(rt2x00dev
, RT5392
))
3562 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
3564 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
3566 if (rt2x00_rt(rt2x00dev
, RT3352
) ||
3567 rt2x00_rt(rt2x00dev
, RT5392
))
3568 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
3570 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
3572 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3573 rt2x00_rt(rt2x00dev
, RT3352
) ||
3574 rt2x00_rt(rt2x00dev
, RT5390
) ||
3575 rt2x00_rt(rt2x00dev
, RT5392
))
3576 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
3578 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
3580 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
3581 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
3582 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
3585 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3586 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3587 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3588 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
3589 rt2x00_rt(rt2x00dev
, RT3290
) ||
3590 rt2x00_rt(rt2x00dev
, RT3352
) ||
3591 rt2x00_rt(rt2x00dev
, RT3572
) ||
3592 rt2x00_rt(rt2x00dev
, RT5390
) ||
3593 rt2x00_rt(rt2x00dev
, RT5392
) ||
3594 rt2800_is_305x_soc(rt2x00dev
))
3595 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
3597 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
3599 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3600 rt2x00_rt(rt2x00dev
, RT3352
) ||
3601 rt2x00_rt(rt2x00dev
, RT5390
) ||
3602 rt2x00_rt(rt2x00dev
, RT5392
))
3603 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
3605 if (rt2800_is_305x_soc(rt2x00dev
))
3606 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
3607 else if (rt2x00_rt(rt2x00dev
, RT3290
))
3608 rt2800_bbp_write(rt2x00dev
, 105, 0x1c);
3609 else if (rt2x00_rt(rt2x00dev
, RT3352
))
3610 rt2800_bbp_write(rt2x00dev
, 105, 0x34);
3611 else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3612 rt2x00_rt(rt2x00dev
, RT5392
))
3613 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
3615 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
3617 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3618 rt2x00_rt(rt2x00dev
, RT5390
))
3619 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
3620 else if (rt2x00_rt(rt2x00dev
, RT3352
))
3621 rt2800_bbp_write(rt2x00dev
, 106, 0x05);
3622 else if (rt2x00_rt(rt2x00dev
, RT5392
))
3623 rt2800_bbp_write(rt2x00dev
, 106, 0x12);
3625 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
3627 if (rt2x00_rt(rt2x00dev
, RT3352
))
3628 rt2800_bbp_write(rt2x00dev
, 120, 0x50);
3630 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3631 rt2x00_rt(rt2x00dev
, RT5390
) ||
3632 rt2x00_rt(rt2x00dev
, RT5392
))
3633 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
3635 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
3636 rt2800_bbp_write(rt2x00dev
, 134, 0xd0);
3637 rt2800_bbp_write(rt2x00dev
, 135, 0xf6);
3640 if (rt2x00_rt(rt2x00dev
, RT3352
))
3641 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
3643 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3644 rt2x00_rt(rt2x00dev
, RT3090
) ||
3645 rt2x00_rt(rt2x00dev
, RT3390
) ||
3646 rt2x00_rt(rt2x00dev
, RT3572
) ||
3647 rt2x00_rt(rt2x00dev
, RT5390
) ||
3648 rt2x00_rt(rt2x00dev
, RT5392
)) {
3649 rt2800_bbp_read(rt2x00dev
, 138, &value
);
3651 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3652 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3654 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3657 rt2800_bbp_write(rt2x00dev
, 138, value
);
3660 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
3661 rt2800_bbp_write(rt2x00dev
, 67, 0x24);
3662 rt2800_bbp_write(rt2x00dev
, 143, 0x04);
3663 rt2800_bbp_write(rt2x00dev
, 142, 0x99);
3664 rt2800_bbp_write(rt2x00dev
, 150, 0x30);
3665 rt2800_bbp_write(rt2x00dev
, 151, 0x2e);
3666 rt2800_bbp_write(rt2x00dev
, 152, 0x20);
3667 rt2800_bbp_write(rt2x00dev
, 153, 0x34);
3668 rt2800_bbp_write(rt2x00dev
, 154, 0x40);
3669 rt2800_bbp_write(rt2x00dev
, 155, 0x3b);
3670 rt2800_bbp_write(rt2x00dev
, 253, 0x04);
3672 rt2800_bbp_read(rt2x00dev
, 47, &value
);
3673 rt2x00_set_field8(&value
, BBP47_TSSI_ADC6
, 1);
3674 rt2800_bbp_write(rt2x00dev
, 47, value
);
3676 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3677 rt2800_bbp_read(rt2x00dev
, 3, &value
);
3678 rt2x00_set_field8(&value
, BBP3_ADC_MODE_SWITCH
, 1);
3679 rt2x00_set_field8(&value
, BBP3_ADC_INIT_MODE
, 1);
3680 rt2800_bbp_write(rt2x00dev
, 3, value
);
3683 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3684 rt2800_bbp_write(rt2x00dev
, 163, 0xbd);
3685 /* Set ITxBF timeout to 0x9c40=1000msec */
3686 rt2800_bbp_write(rt2x00dev
, 179, 0x02);
3687 rt2800_bbp_write(rt2x00dev
, 180, 0x00);
3688 rt2800_bbp_write(rt2x00dev
, 182, 0x40);
3689 rt2800_bbp_write(rt2x00dev
, 180, 0x01);
3690 rt2800_bbp_write(rt2x00dev
, 182, 0x9c);
3691 rt2800_bbp_write(rt2x00dev
, 179, 0x00);
3692 /* Reprogram the inband interface to put right values in RXWI */
3693 rt2800_bbp_write(rt2x00dev
, 142, 0x04);
3694 rt2800_bbp_write(rt2x00dev
, 143, 0x3b);
3695 rt2800_bbp_write(rt2x00dev
, 142, 0x06);
3696 rt2800_bbp_write(rt2x00dev
, 143, 0xa0);
3697 rt2800_bbp_write(rt2x00dev
, 142, 0x07);
3698 rt2800_bbp_write(rt2x00dev
, 143, 0xa1);
3699 rt2800_bbp_write(rt2x00dev
, 142, 0x08);
3700 rt2800_bbp_write(rt2x00dev
, 143, 0xa2);
3702 rt2800_bbp_write(rt2x00dev
, 148, 0xc8);
3705 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3706 rt2x00_rt(rt2x00dev
, RT5392
)) {
3709 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3710 div_mode
= rt2x00_get_field16(eeprom
,
3711 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3712 ant
= (div_mode
== 3) ? 1 : 0;
3714 /* check if this is a Bluetooth combo card */
3715 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
3718 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
3719 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
3720 rt2x00_set_field32(®
, GPIO_CTRL_DIR6
, 0);
3721 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 0);
3722 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 0);
3724 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 1);
3726 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 1);
3727 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
3730 /* This chip has hardware antenna diversity*/
3731 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
3732 rt2800_bbp_write(rt2x00dev
, 150, 0); /* Disable Antenna Software OFDM */
3733 rt2800_bbp_write(rt2x00dev
, 151, 0); /* Disable Antenna Software CCK */
3734 rt2800_bbp_write(rt2x00dev
, 154, 0); /* Clear previously selected antenna */
3737 rt2800_bbp_read(rt2x00dev
, 152, &value
);
3739 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
3741 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
3742 rt2800_bbp_write(rt2x00dev
, 152, value
);
3744 /* Init frequency calibration */
3745 rt2800_bbp_write(rt2x00dev
, 142, 1);
3746 rt2800_bbp_write(rt2x00dev
, 143, 57);
3749 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
3750 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
3752 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
3753 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
3754 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
3755 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
3762 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
3763 bool bw40
, u8 rfcsr24
, u8 filter_target
)
3772 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3774 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3775 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
3776 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3778 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
3779 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
3780 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
3782 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3783 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
3784 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3787 * Set power & frequency of passband test tone
3789 rt2800_bbp_write(rt2x00dev
, 24, 0);
3791 for (i
= 0; i
< 100; i
++) {
3792 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3795 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
3801 * Set power & frequency of stopband test tone
3803 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
3805 for (i
= 0; i
< 100; i
++) {
3806 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3809 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
3811 if ((passband
- stopband
) <= filter_target
) {
3813 overtuned
+= ((passband
- stopband
) == filter_target
);
3817 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3820 rfcsr24
-= !!overtuned
;
3822 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3826 static int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
3828 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
3834 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
3835 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3836 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3837 !rt2x00_rt(rt2x00dev
, RT3290
) &&
3838 !rt2x00_rt(rt2x00dev
, RT3352
) &&
3839 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3840 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3841 !rt2x00_rt(rt2x00dev
, RT5390
) &&
3842 !rt2x00_rt(rt2x00dev
, RT5392
) &&
3843 !rt2800_is_305x_soc(rt2x00dev
))
3847 * Init RF calibration.
3849 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
3850 rt2x00_rt(rt2x00dev
, RT5390
) ||
3851 rt2x00_rt(rt2x00dev
, RT5392
)) {
3852 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
3853 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
3854 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3856 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 0);
3857 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3859 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3860 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
3861 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3863 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
3864 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3867 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3868 rt2x00_rt(rt2x00dev
, RT3071
) ||
3869 rt2x00_rt(rt2x00dev
, RT3090
)) {
3870 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3871 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3872 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3873 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
3874 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3875 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
3876 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3877 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
3878 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3879 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3880 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3881 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3882 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3883 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3884 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3885 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3886 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3887 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3888 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
3889 } else if (rt2x00_rt(rt2x00dev
, RT3290
)) {
3890 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
3891 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
3892 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
3893 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
3894 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
3895 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf3);
3896 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
3897 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
3898 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
3899 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
3900 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
3901 rt2800_rfcsr_write(rt2x00dev
, 18, 0x02);
3902 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
3903 rt2800_rfcsr_write(rt2x00dev
, 25, 0x83);
3904 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
3905 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
3906 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
3907 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
3908 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
3909 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
3910 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
3911 rt2800_rfcsr_write(rt2x00dev
, 34, 0x05);
3912 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
3913 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
3914 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
3915 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
3916 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
3917 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
3918 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
3919 rt2800_rfcsr_write(rt2x00dev
, 43, 0x7b);
3920 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
3921 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
3922 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
3923 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
3924 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
3925 rt2800_rfcsr_write(rt2x00dev
, 49, 0x98);
3926 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
3927 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
3928 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
3929 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
3930 rt2800_rfcsr_write(rt2x00dev
, 56, 0x02);
3931 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
3932 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
3933 rt2800_rfcsr_write(rt2x00dev
, 59, 0x09);
3934 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
3935 rt2800_rfcsr_write(rt2x00dev
, 61, 0xc1);
3936 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3937 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
3938 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
3939 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3940 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
3941 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3942 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
3943 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
3944 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
3945 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
3946 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
3947 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
3948 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3949 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
3950 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
3951 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3952 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3953 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
3954 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
3955 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
3956 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
3957 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
3958 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
3959 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3960 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
3961 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3962 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
3963 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3964 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3965 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
3966 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
3967 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
3968 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
3969 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3970 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
3971 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
3972 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3973 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
3974 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
3975 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
3976 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
3977 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
3978 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
3979 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
3980 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
3981 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
3982 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
3983 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
3984 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3985 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
3986 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
3987 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
3988 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
3989 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
3990 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
3991 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3992 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
3993 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3994 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
3995 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3996 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3997 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3998 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
3999 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
4000 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
4001 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
4002 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
4003 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
4004 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
4005 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
4006 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
4007 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
4008 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
4009 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
4010 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
4011 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
4012 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
4013 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
4014 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
4015 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
4016 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
4017 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
4018 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
4019 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
4020 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
4021 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
4022 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
4023 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
4024 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
4025 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
4026 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
4027 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
4028 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
4029 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
4030 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
4031 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
4032 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
4033 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
4035 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
4036 rt2800_rfcsr_write(rt2x00dev
, 0, 0xf0);
4037 rt2800_rfcsr_write(rt2x00dev
, 1, 0x23);
4038 rt2800_rfcsr_write(rt2x00dev
, 2, 0x50);
4039 rt2800_rfcsr_write(rt2x00dev
, 3, 0x18);
4040 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
4041 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
4042 rt2800_rfcsr_write(rt2x00dev
, 6, 0x33);
4043 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
4044 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
4045 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
4046 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd2);
4047 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
4048 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
4049 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
4050 rt2800_rfcsr_write(rt2x00dev
, 14, 0x5a);
4051 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
4052 rt2800_rfcsr_write(rt2x00dev
, 16, 0x01);
4053 rt2800_rfcsr_write(rt2x00dev
, 18, 0x45);
4054 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
4055 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
4056 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
4057 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
4058 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
4059 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
4060 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
4061 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
4062 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
4063 rt2800_rfcsr_write(rt2x00dev
, 28, 0x03);
4064 rt2800_rfcsr_write(rt2x00dev
, 29, 0x00);
4065 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
4066 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
4067 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
4068 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
4069 rt2800_rfcsr_write(rt2x00dev
, 34, 0x01);
4070 rt2800_rfcsr_write(rt2x00dev
, 35, 0x03);
4071 rt2800_rfcsr_write(rt2x00dev
, 36, 0xbd);
4072 rt2800_rfcsr_write(rt2x00dev
, 37, 0x3c);
4073 rt2800_rfcsr_write(rt2x00dev
, 38, 0x5f);
4074 rt2800_rfcsr_write(rt2x00dev
, 39, 0xc5);
4075 rt2800_rfcsr_write(rt2x00dev
, 40, 0x33);
4076 rt2800_rfcsr_write(rt2x00dev
, 41, 0x5b);
4077 rt2800_rfcsr_write(rt2x00dev
, 42, 0x5b);
4078 rt2800_rfcsr_write(rt2x00dev
, 43, 0xdb);
4079 rt2800_rfcsr_write(rt2x00dev
, 44, 0xdb);
4080 rt2800_rfcsr_write(rt2x00dev
, 45, 0xdb);
4081 rt2800_rfcsr_write(rt2x00dev
, 46, 0xdd);
4082 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0d);
4083 rt2800_rfcsr_write(rt2x00dev
, 48, 0x14);
4084 rt2800_rfcsr_write(rt2x00dev
, 49, 0x00);
4085 rt2800_rfcsr_write(rt2x00dev
, 50, 0x2d);
4086 rt2800_rfcsr_write(rt2x00dev
, 51, 0x7f);
4087 rt2800_rfcsr_write(rt2x00dev
, 52, 0x00);
4088 rt2800_rfcsr_write(rt2x00dev
, 53, 0x52);
4089 rt2800_rfcsr_write(rt2x00dev
, 54, 0x1b);
4090 rt2800_rfcsr_write(rt2x00dev
, 55, 0x7f);
4091 rt2800_rfcsr_write(rt2x00dev
, 56, 0x00);
4092 rt2800_rfcsr_write(rt2x00dev
, 57, 0x52);
4093 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1b);
4094 rt2800_rfcsr_write(rt2x00dev
, 59, 0x00);
4095 rt2800_rfcsr_write(rt2x00dev
, 60, 0x00);
4096 rt2800_rfcsr_write(rt2x00dev
, 61, 0x00);
4097 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
4098 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
4099 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
4100 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
4101 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
4102 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
4103 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
4104 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4105 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
4107 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
4108 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
4109 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
4110 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
4111 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
4112 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
4113 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
4114 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
4115 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
4116 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
4117 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
4119 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
4120 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
4121 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
4122 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
4123 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
4124 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4125 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
4127 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
4128 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
4129 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
4130 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
4131 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
4133 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
4134 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
4135 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
4136 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
4137 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
4138 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
4139 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
4140 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
4141 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
4142 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
4144 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4145 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
4147 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
4148 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
4149 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
4150 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
4151 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
4152 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
4153 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4154 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
4156 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
4157 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
4158 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
4159 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
4161 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
4162 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4163 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
4165 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
4166 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
4167 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
4168 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
4169 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
4170 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
4171 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
4173 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
4174 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
4175 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
4177 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
4178 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
4179 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
4180 } else if (rt2x00_rt(rt2x00dev
, RT5392
)) {
4181 rt2800_rfcsr_write(rt2x00dev
, 1, 0x17);
4182 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
4183 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
4184 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
4185 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
4186 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
4187 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
4188 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
4189 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
4190 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
4191 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
4192 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
4193 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
4194 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
4195 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4d);
4196 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
4197 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8d);
4198 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
4199 rt2800_rfcsr_write(rt2x00dev
, 23, 0x0b);
4200 rt2800_rfcsr_write(rt2x00dev
, 24, 0x44);
4201 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
4202 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
4203 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
4204 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
4205 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
4206 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
4207 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
4208 rt2800_rfcsr_write(rt2x00dev
, 32, 0x20);
4209 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
4210 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
4211 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
4212 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
4213 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
4214 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
4215 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
4216 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0f);
4217 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
4218 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
4219 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9b);
4220 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
4221 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
4222 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
4223 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0c);
4224 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
4225 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
4226 rt2800_rfcsr_write(rt2x00dev
, 50, 0x94);
4227 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3a);
4228 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
4229 rt2800_rfcsr_write(rt2x00dev
, 53, 0x44);
4230 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
4231 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
4232 rt2800_rfcsr_write(rt2x00dev
, 56, 0xa1);
4233 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
4234 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
4235 rt2800_rfcsr_write(rt2x00dev
, 59, 0x07);
4236 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
4237 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
4238 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
4239 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
4242 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
4243 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4244 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4245 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
4246 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4247 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4248 rt2x00_rt(rt2x00dev
, RT3090
)) {
4249 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
4251 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
4252 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
4253 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
4255 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4256 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4257 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4258 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
4259 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4260 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
4261 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
4263 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
4265 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4267 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
4268 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
4269 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
4270 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
4271 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
4272 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
4273 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
4274 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
4275 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
4276 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
4277 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
4279 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4280 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
4281 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4282 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4284 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
4285 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
4286 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
4287 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
4291 * Set RX Filter calibration for 20MHz and 40MHz
4293 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4294 drv_data
->calibration_bw20
=
4295 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
4296 drv_data
->calibration_bw40
=
4297 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
4298 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4299 rt2x00_rt(rt2x00dev
, RT3090
) ||
4300 rt2x00_rt(rt2x00dev
, RT3352
) ||
4301 rt2x00_rt(rt2x00dev
, RT3390
) ||
4302 rt2x00_rt(rt2x00dev
, RT3572
)) {
4303 drv_data
->calibration_bw20
=
4304 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
4305 drv_data
->calibration_bw40
=
4306 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
4310 * Save BBP 25 & 26 values for later use in channel switching
4312 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
4313 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
4315 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
4316 !rt2x00_rt(rt2x00dev
, RT5392
)) {
4318 * Set back to initial state
4320 rt2800_bbp_write(rt2x00dev
, 24, 0);
4322 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
4323 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
4324 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
4327 * Set BBP back to BW20
4329 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
4330 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
4331 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
4334 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
4335 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4336 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
4337 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
4338 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
4340 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
4341 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
4342 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
4344 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
4345 !rt2x00_rt(rt2x00dev
, RT5392
)) {
4346 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
4347 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
4348 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4349 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4350 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
4351 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
4352 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
4353 &rt2x00dev
->cap_flags
))
4354 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
4356 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
4357 drv_data
->txmixer_gain_24g
);
4358 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
4361 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
4362 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
4364 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4365 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4366 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
4367 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
4368 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
4369 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
4371 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
4374 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4375 rt2x00_rt(rt2x00dev
, RT3090
) ||
4376 rt2x00_rt(rt2x00dev
, RT3390
)) {
4377 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
4378 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
4379 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
4380 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
4381 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
4382 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
4383 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
4385 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
4386 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
4387 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
4389 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
4390 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
4391 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
4393 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
4394 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
4395 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
4398 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4399 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
4400 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
4401 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
4403 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
4404 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
4405 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
4406 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
4407 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
4410 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
4411 rt2800_rfcsr_read(rt2x00dev
, 29, &rfcsr
);
4412 rt2x00_set_field8(&rfcsr
, RFCSR29_RSSI_GAIN
, 3);
4413 rt2800_rfcsr_write(rt2x00dev
, 29, rfcsr
);
4416 if (rt2x00_rt(rt2x00dev
, RT5390
) ||
4417 rt2x00_rt(rt2x00dev
, RT5392
)) {
4418 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
4419 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
4420 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
4422 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
4423 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
4424 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
4426 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
4427 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
4428 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
4434 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
4440 * Initialize all registers.
4442 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
4443 rt2800_init_registers(rt2x00dev
) ||
4444 rt2800_init_bbp(rt2x00dev
) ||
4445 rt2800_init_rfcsr(rt2x00dev
)))
4449 * Send signal to firmware during boot time.
4451 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
4453 if (rt2x00_is_usb(rt2x00dev
) &&
4454 (rt2x00_rt(rt2x00dev
, RT3070
) ||
4455 rt2x00_rt(rt2x00dev
, RT3071
) ||
4456 rt2x00_rt(rt2x00dev
, RT3572
))) {
4458 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
4465 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
4466 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
4467 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
4468 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
4472 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
4473 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
4474 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
4475 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
4476 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
4477 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
4479 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
4480 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
4481 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
4482 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
4485 * Initialize LED control
4487 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
4488 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
4489 word
& 0xff, (word
>> 8) & 0xff);
4491 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
4492 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
4493 word
& 0xff, (word
>> 8) & 0xff);
4495 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
4496 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
4497 word
& 0xff, (word
>> 8) & 0xff);
4501 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
4503 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
4507 rt2800_disable_wpdma(rt2x00dev
);
4509 /* Wait for DMA, ignore error */
4510 rt2800_wait_wpdma_ready(rt2x00dev
);
4512 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
4513 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
4514 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
4515 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
4517 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
4519 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
4524 if (rt2x00_rt(rt2x00dev
, RT3290
))
4525 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
4527 efuse_ctrl_reg
= EFUSE_CTRL
;
4529 rt2800_register_read(rt2x00dev
, efuse_ctrl_reg
, ®
);
4530 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
4532 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
4534 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
4538 u16 efuse_data0_reg
;
4539 u16 efuse_data1_reg
;
4540 u16 efuse_data2_reg
;
4541 u16 efuse_data3_reg
;
4543 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
4544 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
4545 efuse_data0_reg
= EFUSE_DATA0_3290
;
4546 efuse_data1_reg
= EFUSE_DATA1_3290
;
4547 efuse_data2_reg
= EFUSE_DATA2_3290
;
4548 efuse_data3_reg
= EFUSE_DATA3_3290
;
4550 efuse_ctrl_reg
= EFUSE_CTRL
;
4551 efuse_data0_reg
= EFUSE_DATA0
;
4552 efuse_data1_reg
= EFUSE_DATA1
;
4553 efuse_data2_reg
= EFUSE_DATA2
;
4554 efuse_data3_reg
= EFUSE_DATA3
;
4556 mutex_lock(&rt2x00dev
->csr_mutex
);
4558 rt2800_register_read_lock(rt2x00dev
, efuse_ctrl_reg
, ®
);
4559 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
4560 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
4561 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
4562 rt2800_register_write_lock(rt2x00dev
, efuse_ctrl_reg
, reg
);
4564 /* Wait until the EEPROM has been loaded */
4565 rt2800_regbusy_read(rt2x00dev
, efuse_ctrl_reg
, EFUSE_CTRL_KICK
, ®
);
4566 /* Apparently the data is read from end to start */
4567 rt2800_register_read_lock(rt2x00dev
, efuse_data3_reg
, ®
);
4568 /* The returned value is in CPU order, but eeprom is le */
4569 *(u32
*)&rt2x00dev
->eeprom
[i
] = cpu_to_le32(reg
);
4570 rt2800_register_read_lock(rt2x00dev
, efuse_data2_reg
, ®
);
4571 *(u32
*)&rt2x00dev
->eeprom
[i
+ 2] = cpu_to_le32(reg
);
4572 rt2800_register_read_lock(rt2x00dev
, efuse_data1_reg
, ®
);
4573 *(u32
*)&rt2x00dev
->eeprom
[i
+ 4] = cpu_to_le32(reg
);
4574 rt2800_register_read_lock(rt2x00dev
, efuse_data0_reg
, ®
);
4575 *(u32
*)&rt2x00dev
->eeprom
[i
+ 6] = cpu_to_le32(reg
);
4577 mutex_unlock(&rt2x00dev
->csr_mutex
);
4580 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
4584 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
4585 rt2800_efuse_read(rt2x00dev
, i
);
4587 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
4589 static int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
4591 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
4594 u8 default_lna_gain
;
4599 rt2800_read_eeprom(rt2x00dev
);
4602 * Start validation of the data that has been read.
4604 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
4605 if (!is_valid_ether_addr(mac
)) {
4606 eth_random_addr(mac
);
4607 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
4610 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
4611 if (word
== 0xffff) {
4612 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
4613 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
4614 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
4615 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
4616 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
4617 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
4618 rt2x00_rt(rt2x00dev
, RT2872
)) {
4620 * There is a max of 2 RX streams for RT28x0 series
4622 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
4623 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
4624 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
4627 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
4628 if (word
== 0xffff) {
4629 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
4630 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
4631 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
4632 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
4633 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
4634 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
4635 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
4636 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
4637 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
4638 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
4639 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
4640 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
4641 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
4642 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
4643 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
4644 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
4645 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
4648 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
4649 if ((word
& 0x00ff) == 0x00ff) {
4650 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
4651 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
4652 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
4654 if ((word
& 0xff00) == 0xff00) {
4655 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
4656 LED_MODE_TXRX_ACTIVITY
);
4657 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
4658 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
4659 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
4660 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
4661 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
4662 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
4666 * During the LNA validation we are going to use
4667 * lna0 as correct value. Note that EEPROM_LNA
4668 * is never validated.
4670 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
4671 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
4673 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
4674 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
4675 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
4676 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
4677 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
4678 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
4680 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &word
);
4681 if ((word
& 0x00ff) != 0x00ff) {
4682 drv_data
->txmixer_gain_24g
=
4683 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_BG_VAL
);
4685 drv_data
->txmixer_gain_24g
= 0;
4688 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
4689 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
4690 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
4691 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
4692 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
4693 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
4695 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
4697 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_A
, &word
);
4698 if ((word
& 0x00ff) != 0x00ff) {
4699 drv_data
->txmixer_gain_5g
=
4700 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_A_VAL
);
4702 drv_data
->txmixer_gain_5g
= 0;
4705 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
4706 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
4707 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
4708 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
4709 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
4710 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
4712 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
4713 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
4714 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
4715 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
4716 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
4717 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
4719 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
4724 static int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
4731 * Read EEPROM word for configuration.
4733 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4736 * Identify RF chipset by EEPROM value
4737 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4738 * RT53xx: defined in "EEPROM_CHIP_ID" field
4740 if (rt2x00_rt(rt2x00dev
, RT3290
))
4741 rt2800_register_read(rt2x00dev
, MAC_CSR0_3290
, ®
);
4743 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
4745 if (rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT3290
||
4746 rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT5390
||
4747 rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT5392
)
4748 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &value
);
4750 value
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
4752 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
4753 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
4755 switch (rt2x00dev
->chip
.rt
) {
4770 ERROR(rt2x00dev
, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev
->chip
.rt
);
4774 switch (rt2x00dev
->chip
.rf
) {
4794 ERROR(rt2x00dev
, "Invalid RF chipset 0x%04x detected.\n",
4795 rt2x00dev
->chip
.rf
);
4800 * Identify default antenna configuration.
4802 rt2x00dev
->default_ant
.tx_chain_num
=
4803 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
4804 rt2x00dev
->default_ant
.rx_chain_num
=
4805 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
4807 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4809 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4810 rt2x00_rt(rt2x00dev
, RT3090
) ||
4811 rt2x00_rt(rt2x00dev
, RT3352
) ||
4812 rt2x00_rt(rt2x00dev
, RT3390
)) {
4813 value
= rt2x00_get_field16(eeprom
,
4814 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
4819 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
4820 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
4823 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
4824 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
4828 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
4829 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
4832 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
4833 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
; /* Unused */
4834 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
; /* Unused */
4838 * Determine external LNA informations.
4840 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
4841 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
4842 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
4843 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
4846 * Detect if this device has an hardware controlled radio.
4848 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
4849 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
4852 * Detect if this device has Bluetooth co-existence.
4854 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
4855 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
4858 * Read frequency offset and RF programming sequence.
4860 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
4861 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
4864 * Store led settings, for correct led behaviour.
4866 #ifdef CONFIG_RT2X00_LIB_LEDS
4867 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
4868 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
4869 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
4871 rt2x00dev
->led_mcu_reg
= eeprom
;
4872 #endif /* CONFIG_RT2X00_LIB_LEDS */
4875 * Check if support EIRP tx power limit feature.
4877 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
4879 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
4880 EIRP_MAX_TX_POWER_LIMIT
)
4881 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
4887 * RF value list for rt28xx
4888 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4890 static const struct rf_channel rf_vals
[] = {
4891 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4892 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4893 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4894 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4895 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4896 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4897 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4898 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4899 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4900 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4901 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4902 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4903 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4904 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4906 /* 802.11 UNI / HyperLan 2 */
4907 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4908 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4909 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4910 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4911 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4912 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4913 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4914 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4915 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4916 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4917 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4918 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4920 /* 802.11 HyperLan 2 */
4921 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4922 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4923 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4924 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4925 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4926 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4927 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4928 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4929 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4930 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4931 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4932 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4933 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4934 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4935 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4936 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4939 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4940 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4941 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4942 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4943 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4944 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4945 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4946 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4947 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4948 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4949 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4952 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4953 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4954 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4955 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4956 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4957 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4958 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4962 * RF value list for rt3xxx
4963 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4965 static const struct rf_channel rf_vals_3x
[] = {
4981 /* 802.11 UNI / HyperLan 2 */
4995 /* 802.11 HyperLan 2 */
5027 static int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
5029 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
5030 struct channel_info
*info
;
5031 char *default_power1
;
5032 char *default_power2
;
5037 * Disable powersaving as default on PCI devices.
5039 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
5040 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
5043 * Initialize all hw fields.
5045 rt2x00dev
->hw
->flags
=
5046 IEEE80211_HW_SIGNAL_DBM
|
5047 IEEE80211_HW_SUPPORTS_PS
|
5048 IEEE80211_HW_PS_NULLFUNC_STACK
|
5049 IEEE80211_HW_AMPDU_AGGREGATION
|
5050 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
5053 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5054 * unless we are capable of sending the buffered frames out after the
5055 * DTIM transmission using rt2x00lib_beacondone. This will send out
5056 * multicast and broadcast traffic immediately instead of buffering it
5057 * infinitly and thus dropping it after some time.
5059 if (!rt2x00_is_usb(rt2x00dev
))
5060 rt2x00dev
->hw
->flags
|=
5061 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
5063 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
5064 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
5065 rt2x00_eeprom_addr(rt2x00dev
,
5066 EEPROM_MAC_ADDR_0
));
5069 * As rt2800 has a global fallback table we cannot specify
5070 * more then one tx rate per frame but since the hw will
5071 * try several rates (based on the fallback table) we should
5072 * initialize max_report_rates to the maximum number of rates
5073 * we are going to try. Otherwise mac80211 will truncate our
5074 * reported tx rates and the rc algortihm will end up with
5077 rt2x00dev
->hw
->max_rates
= 1;
5078 rt2x00dev
->hw
->max_report_rates
= 7;
5079 rt2x00dev
->hw
->max_rate_tries
= 1;
5081 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5084 * Initialize hw_mode information.
5086 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
5087 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
5089 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
5090 rt2x00_rf(rt2x00dev
, RF2720
)) {
5091 spec
->num_channels
= 14;
5092 spec
->channels
= rf_vals
;
5093 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
5094 rt2x00_rf(rt2x00dev
, RF2750
)) {
5095 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
5096 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
5097 spec
->channels
= rf_vals
;
5098 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
5099 rt2x00_rf(rt2x00dev
, RF2020
) ||
5100 rt2x00_rf(rt2x00dev
, RF3021
) ||
5101 rt2x00_rf(rt2x00dev
, RF3022
) ||
5102 rt2x00_rf(rt2x00dev
, RF3290
) ||
5103 rt2x00_rf(rt2x00dev
, RF3320
) ||
5104 rt2x00_rf(rt2x00dev
, RF3322
) ||
5105 rt2x00_rf(rt2x00dev
, RF5360
) ||
5106 rt2x00_rf(rt2x00dev
, RF5370
) ||
5107 rt2x00_rf(rt2x00dev
, RF5372
) ||
5108 rt2x00_rf(rt2x00dev
, RF5390
) ||
5109 rt2x00_rf(rt2x00dev
, RF5392
)) {
5110 spec
->num_channels
= 14;
5111 spec
->channels
= rf_vals_3x
;
5112 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
5113 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
5114 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
5115 spec
->channels
= rf_vals_3x
;
5119 * Initialize HT information.
5121 if (!rt2x00_rf(rt2x00dev
, RF2020
))
5122 spec
->ht
.ht_supported
= true;
5124 spec
->ht
.ht_supported
= false;
5127 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
5128 IEEE80211_HT_CAP_GRN_FLD
|
5129 IEEE80211_HT_CAP_SGI_20
|
5130 IEEE80211_HT_CAP_SGI_40
;
5132 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
5133 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
5136 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
5137 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
5139 spec
->ht
.ampdu_factor
= 3;
5140 spec
->ht
.ampdu_density
= 4;
5141 spec
->ht
.mcs
.tx_params
=
5142 IEEE80211_HT_MCS_TX_DEFINED
|
5143 IEEE80211_HT_MCS_TX_RX_DIFF
|
5144 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
5145 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
5147 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
5149 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
5151 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
5153 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
5154 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
5159 * Create channel information array
5161 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
5165 spec
->channels_info
= info
;
5167 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
5168 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
5170 for (i
= 0; i
< 14; i
++) {
5171 info
[i
].default_power1
= default_power1
[i
];
5172 info
[i
].default_power2
= default_power2
[i
];
5175 if (spec
->num_channels
> 14) {
5176 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
5177 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
5179 for (i
= 14; i
< spec
->num_channels
; i
++) {
5180 info
[i
].default_power1
= default_power1
[i
];
5181 info
[i
].default_power2
= default_power2
[i
];
5185 switch (rt2x00dev
->chip
.rf
) {
5198 __set_bit(CAPABILITY_VCO_RECALIBRATION
, &rt2x00dev
->cap_flags
);
5205 int rt2800_probe_hw(struct rt2x00_dev
*rt2x00dev
)
5211 * Allocate eeprom data.
5213 retval
= rt2800_validate_eeprom(rt2x00dev
);
5217 retval
= rt2800_init_eeprom(rt2x00dev
);
5222 * Enable rfkill polling by setting GPIO direction of the
5223 * rfkill switch GPIO pin correctly.
5225 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
5226 rt2x00_set_field32(®
, GPIO_CTRL_DIR2
, 1);
5227 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
5230 * Initialize hw specifications.
5232 retval
= rt2800_probe_hw_mode(rt2x00dev
);
5237 * Set device capabilities.
5239 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
5240 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->cap_flags
);
5241 if (!rt2x00_is_usb(rt2x00dev
))
5242 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT
, &rt2x00dev
->cap_flags
);
5245 * Set device requirements.
5247 if (!rt2x00_is_soc(rt2x00dev
))
5248 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
5249 __set_bit(REQUIRE_L2PAD
, &rt2x00dev
->cap_flags
);
5250 __set_bit(REQUIRE_TXSTATUS_FIFO
, &rt2x00dev
->cap_flags
);
5251 if (!rt2800_hwcrypt_disabled(rt2x00dev
))
5252 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
5253 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
5254 __set_bit(REQUIRE_HT_TX_DESC
, &rt2x00dev
->cap_flags
);
5255 if (rt2x00_is_usb(rt2x00dev
))
5256 __set_bit(REQUIRE_PS_AUTOWAKE
, &rt2x00dev
->cap_flags
);
5258 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
5259 __set_bit(REQUIRE_TASKLET_CONTEXT
, &rt2x00dev
->cap_flags
);
5263 * Set the rssi offset.
5265 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
5269 EXPORT_SYMBOL_GPL(rt2800_probe_hw
);
5272 * IEEE80211 stack callback functions.
5274 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
5277 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
5278 struct mac_iveiv_entry iveiv_entry
;
5281 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
5282 rt2800_register_multiread(rt2x00dev
, offset
,
5283 &iveiv_entry
, sizeof(iveiv_entry
));
5285 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
5286 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
5288 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
5290 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
5292 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
5294 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
5296 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
5297 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
5298 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
5300 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
5301 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
5302 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
5304 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
5305 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
5306 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
5308 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
5309 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
5310 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
5312 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
5313 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
5314 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
5316 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
5317 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
5318 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
5320 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
5321 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
5322 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
5326 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
5328 int rt2800_conf_tx(struct ieee80211_hw
*hw
,
5329 struct ieee80211_vif
*vif
, u16 queue_idx
,
5330 const struct ieee80211_tx_queue_params
*params
)
5332 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
5333 struct data_queue
*queue
;
5334 struct rt2x00_field32 field
;
5340 * First pass the configuration through rt2x00lib, that will
5341 * update the queue settings and validate the input. After that
5342 * we are free to update the registers based on the value
5343 * in the queue parameter.
5345 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
5350 * We only need to perform additional register initialization
5356 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
5358 /* Update WMM TXOP register */
5359 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
5360 field
.bit_offset
= (queue_idx
& 1) * 16;
5361 field
.bit_mask
= 0xffff << field
.bit_offset
;
5363 rt2800_register_read(rt2x00dev
, offset
, ®
);
5364 rt2x00_set_field32(®
, field
, queue
->txop
);
5365 rt2800_register_write(rt2x00dev
, offset
, reg
);
5367 /* Update WMM registers */
5368 field
.bit_offset
= queue_idx
* 4;
5369 field
.bit_mask
= 0xf << field
.bit_offset
;
5371 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
5372 rt2x00_set_field32(®
, field
, queue
->aifs
);
5373 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
5375 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
5376 rt2x00_set_field32(®
, field
, queue
->cw_min
);
5377 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
5379 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
5380 rt2x00_set_field32(®
, field
, queue
->cw_max
);
5381 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
5383 /* Update EDCA registers */
5384 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
5386 rt2800_register_read(rt2x00dev
, offset
, ®
);
5387 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
5388 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
5389 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
5390 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
5391 rt2800_register_write(rt2x00dev
, offset
, reg
);
5395 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
5397 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
5399 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
5403 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
5404 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
5405 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
5406 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
5410 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
5412 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
5413 enum ieee80211_ampdu_mlme_action action
,
5414 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
5417 struct rt2x00_sta
*sta_priv
= (struct rt2x00_sta
*)sta
->drv_priv
;
5421 * Don't allow aggregation for stations the hardware isn't aware
5422 * of because tx status reports for frames to an unknown station
5423 * always contain wcid=255 and thus we can't distinguish between
5424 * multiple stations which leads to unwanted situations when the
5425 * hw reorders frames due to aggregation.
5427 if (sta_priv
->wcid
< 0)
5431 case IEEE80211_AMPDU_RX_START
:
5432 case IEEE80211_AMPDU_RX_STOP
:
5434 * The hw itself takes care of setting up BlockAck mechanisms.
5435 * So, we only have to allow mac80211 to nagotiate a BlockAck
5436 * agreement. Once that is done, the hw will BlockAck incoming
5437 * AMPDUs without further setup.
5440 case IEEE80211_AMPDU_TX_START
:
5441 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
5443 case IEEE80211_AMPDU_TX_STOP
:
5444 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
5446 case IEEE80211_AMPDU_TX_OPERATIONAL
:
5449 WARNING((struct rt2x00_dev
*)hw
->priv
, "Unknown AMPDU action\n");
5454 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
5456 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
5457 struct survey_info
*survey
)
5459 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
5460 struct ieee80211_conf
*conf
= &hw
->conf
;
5461 u32 idle
, busy
, busy_ext
;
5466 survey
->channel
= conf
->channel
;
5468 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
5469 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
5470 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
5473 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
5474 SURVEY_INFO_CHANNEL_TIME_BUSY
|
5475 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
5477 survey
->channel_time
= (idle
+ busy
) / 1000;
5478 survey
->channel_time_busy
= busy
/ 1000;
5479 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
5482 if (!(hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
))
5483 survey
->filled
|= SURVEY_INFO_IN_USE
;
5488 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
5490 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
5491 MODULE_VERSION(DRV_VERSION
);
5492 MODULE_DESCRIPTION("Ralink RT2800 library");
5493 MODULE_LICENSE("GPL");