2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
225 const u8 command
, const u8 token
,
226 const u8 arg0
, const u8 arg1
)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev
))
236 mutex_lock(&rt2x00dev
->csr_mutex
);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
243 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
244 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
245 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
246 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
247 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
250 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
251 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
254 mutex_unlock(&rt2x00dev
->csr_mutex
);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
258 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
263 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
264 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
265 if (reg
&& reg
!= ~0)
270 ERROR(rt2x00dev
, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
285 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
286 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
287 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
293 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
298 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
308 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
317 crc
= crc_ccitt(~0, data
, len
- 2);
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
327 return fw_crc
== crc
;
330 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
331 const u8
*data
, const size_t len
)
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
345 if (rt2x00_is_usb(rt2x00dev
)) {
354 * Validate the firmware length
356 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
357 return FW_BAD_LENGTH
;
360 * Check if the chipset requires one of the upper parts
363 if (rt2x00_is_usb(rt2x00dev
) &&
364 !rt2x00_rt(rt2x00dev
, RT2860
) &&
365 !rt2x00_rt(rt2x00dev
, RT2872
) &&
366 !rt2x00_rt(rt2x00dev
, RT3070
) &&
367 ((len
/ fw_len
) == 1))
368 return FW_BAD_VERSION
;
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
374 while (offset
< len
) {
375 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
385 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
386 const u8
*data
, const size_t len
)
392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
395 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
398 * Wait for stable hardware.
400 if (rt2800_wait_csr_ready(rt2x00dev
))
403 if (rt2x00_is_pci(rt2x00dev
)) {
404 if (rt2x00_rt(rt2x00dev
, RT3572
) ||
405 rt2x00_rt(rt2x00dev
, RT5390
)) {
406 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
407 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
408 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
409 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
411 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
415 * Disable DMA, will be reenabled later when enabling
418 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
419 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
420 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
421 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
422 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
423 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
424 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
427 * Write firmware to the device.
429 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
432 * Wait for device to stabilize.
434 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
435 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
436 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
441 if (i
== REGISTER_BUSY_COUNT
) {
442 ERROR(rt2x00dev
, "PBF system register not ready.\n");
447 * Initialize firmware.
449 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
450 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
455 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
457 void rt2800_write_tx_data(struct queue_entry
*entry
,
458 struct txentry_desc
*txdesc
)
460 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
464 * Initialize TX Info descriptor
466 rt2x00_desc_read(txwi
, 0, &word
);
467 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
468 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
469 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
470 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
471 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
472 rt2x00_set_field32(&word
, TXWI_W0_TS
,
473 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
474 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
475 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
476 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
477 txdesc
->u
.ht
.mpdu_density
);
478 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
479 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
480 rt2x00_set_field32(&word
, TXWI_W0_BW
,
481 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
482 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
483 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
484 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
485 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
486 rt2x00_desc_write(txwi
, 0, word
);
488 rt2x00_desc_read(txwi
, 1, &word
);
489 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
490 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
491 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
492 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
493 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
494 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
495 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
496 txdesc
->key_idx
: 0xff);
497 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
499 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
500 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
501 rt2x00_desc_write(txwi
, 1, word
);
504 * Always write 0 to IV/EIV fields, hardware will insert the IV
505 * from the IVEIV register when TXD_W3_WIV is set to 0.
506 * When TXD_W3_WIV is set to 1 it will use the IV data
507 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
508 * crypto entry in the registers should be used to encrypt the frame.
510 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
511 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
515 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
517 int rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
518 int rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
519 int rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
525 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
526 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
527 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
528 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
529 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
530 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
532 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
533 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
534 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
535 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
536 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
540 * Convert the value from the descriptor into the RSSI value
541 * If the value in the descriptor is 0, it is considered invalid
542 * and the default (extremely low) rssi value is assumed
544 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
545 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
546 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
549 * mac80211 only accepts a single RSSI value. Calculating the
550 * average doesn't deliver a fair answer either since -60:-60 would
551 * be considered equally good as -50:-70 while the second is the one
552 * which gives less energy...
554 rssi0
= max(rssi0
, rssi1
);
555 return max(rssi0
, rssi2
);
558 void rt2800_process_rxwi(struct queue_entry
*entry
,
559 struct rxdone_entry_desc
*rxdesc
)
561 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
564 rt2x00_desc_read(rxwi
, 0, &word
);
566 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
567 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
569 rt2x00_desc_read(rxwi
, 1, &word
);
571 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
572 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
574 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
575 rxdesc
->flags
|= RX_FLAG_40MHZ
;
578 * Detect RX rate, always use MCS as signal type.
580 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
581 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
582 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
585 * Mask of 0x8 bit to remove the short preamble flag.
587 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
588 rxdesc
->signal
&= ~0x8;
590 rt2x00_desc_read(rxwi
, 2, &word
);
593 * Convert descriptor AGC value to RSSI value.
595 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
598 * Remove RXWI descriptor from start of buffer.
600 skb_pull(entry
->skb
, RXWI_DESC_SIZE
);
602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
604 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
)
606 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
607 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
608 struct txdone_entry_desc txdesc
;
615 * Obtain the status about this packet.
618 txwi
= rt2800_drv_get_txwi(entry
);
619 rt2x00_desc_read(txwi
, 0, &word
);
621 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
622 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
624 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
625 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
628 * If a frame was meant to be sent as a single non-aggregated MPDU
629 * but ended up in an aggregate the used tx rate doesn't correlate
630 * with the one specified in the TXWI as the whole aggregate is sent
631 * with the same rate.
633 * For example: two frames are sent to rt2x00, the first one sets
634 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
635 * and requests MCS15. If the hw aggregates both frames into one
636 * AMDPU the tx status for both frames will contain MCS7 although
637 * the frame was sent successfully.
639 * Hence, replace the requested rate with the real tx rate to not
640 * confuse the rate control algortihm by providing clearly wrong
643 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
644 skbdesc
->tx_rate_idx
= real_mcs
;
648 if (aggr
== 1 || ampdu
== 1)
649 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
652 * Ralink has a retry mechanism using a global fallback
653 * table. We setup this fallback table to try the immediate
654 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
655 * always contains the MCS used for the last transmission, be
656 * it successful or not.
658 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
660 * Transmission succeeded. The number of retries is
663 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
664 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
667 * Transmission failed. The number of retries is
668 * always 7 in this case (for a total number of 8
671 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
672 txdesc
.retry
= rt2x00dev
->long_retry
;
676 * the frame was retried at least once
677 * -> hw used fallback rates
680 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
682 rt2x00lib_txdone(entry
, &txdesc
);
684 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
686 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
688 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
689 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
690 unsigned int beacon_base
;
691 unsigned int padding_len
;
695 * Disable beaconing while we are reloading the beacon data,
696 * otherwise we might be sending out invalid data.
698 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
700 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
701 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
704 * Add space for the TXWI in front of the skb.
706 skb_push(entry
->skb
, TXWI_DESC_SIZE
);
707 memset(entry
->skb
, 0, TXWI_DESC_SIZE
);
710 * Register descriptor details in skb frame descriptor.
712 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
713 skbdesc
->desc
= entry
->skb
->data
;
714 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
717 * Add the TXWI for the beacon to the skb.
719 rt2800_write_tx_data(entry
, txdesc
);
722 * Dump beacon to userspace through debugfs.
724 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
727 * Write entire beacon with TXWI and padding to register.
729 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
730 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
731 ERROR(rt2x00dev
, "Failure padding beacon, aborting\n");
732 /* skb freed by skb_pad() on failure */
734 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
738 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
739 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
740 entry
->skb
->len
+ padding_len
);
743 * Enable beaconing again.
745 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
746 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
749 * Clean up beacon skb.
751 dev_kfree_skb_any(entry
->skb
);
754 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
756 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
757 unsigned int beacon_base
)
762 * For the Beacon base registers we only need to clear
763 * the whole TXWI which (when set to 0) will invalidate
766 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
767 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
770 void rt2800_clear_beacon(struct queue_entry
*entry
)
772 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
776 * Disable beaconing while we are reloading the beacon data,
777 * otherwise we might be sending out invalid data.
779 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
780 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
781 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
786 rt2800_clear_beacon_register(rt2x00dev
,
787 HW_BEACON_OFFSET(entry
->entry_idx
));
790 * Enabled beaconing again.
792 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
793 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
795 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
797 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
798 const struct rt2x00debug rt2800_rt2x00debug
= {
799 .owner
= THIS_MODULE
,
801 .read
= rt2800_register_read
,
802 .write
= rt2800_register_write
,
803 .flags
= RT2X00DEBUGFS_OFFSET
,
804 .word_base
= CSR_REG_BASE
,
805 .word_size
= sizeof(u32
),
806 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
809 .read
= rt2x00_eeprom_read
,
810 .write
= rt2x00_eeprom_write
,
811 .word_base
= EEPROM_BASE
,
812 .word_size
= sizeof(u16
),
813 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
816 .read
= rt2800_bbp_read
,
817 .write
= rt2800_bbp_write
,
818 .word_base
= BBP_BASE
,
819 .word_size
= sizeof(u8
),
820 .word_count
= BBP_SIZE
/ sizeof(u8
),
823 .read
= rt2x00_rf_read
,
824 .write
= rt2800_rf_write
,
825 .word_base
= RF_BASE
,
826 .word_size
= sizeof(u32
),
827 .word_count
= RF_SIZE
/ sizeof(u32
),
830 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
831 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
833 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
837 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
838 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
840 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
842 #ifdef CONFIG_RT2X00_LIB_LEDS
843 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
844 enum led_brightness brightness
)
846 struct rt2x00_led
*led
=
847 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
848 unsigned int enabled
= brightness
!= LED_OFF
;
849 unsigned int bg_mode
=
850 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
851 unsigned int polarity
=
852 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
853 EEPROM_FREQ_LED_POLARITY
);
854 unsigned int ledmode
=
855 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
856 EEPROM_FREQ_LED_MODE
);
859 /* Check for SoC (SOC devices don't support MCU requests) */
860 if (rt2x00_is_soc(led
->rt2x00dev
)) {
861 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
863 /* Set LED Polarity */
864 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
867 if (led
->type
== LED_TYPE_RADIO
) {
868 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
870 } else if (led
->type
== LED_TYPE_ASSOC
) {
871 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
873 } else if (led
->type
== LED_TYPE_QUALITY
) {
874 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
878 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
881 if (led
->type
== LED_TYPE_RADIO
) {
882 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
884 } else if (led
->type
== LED_TYPE_ASSOC
) {
885 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
886 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
887 } else if (led
->type
== LED_TYPE_QUALITY
) {
889 * The brightness is divided into 6 levels (0 - 5),
890 * The specs tell us the following levels:
892 * to determine the level in a simple way we can simply
893 * work with bitshifting:
896 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
897 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
903 static int rt2800_blink_set(struct led_classdev
*led_cdev
,
904 unsigned long *delay_on
, unsigned long *delay_off
)
906 struct rt2x00_led
*led
=
907 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
910 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
911 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, *delay_on
);
912 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, *delay_off
);
913 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
918 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
919 struct rt2x00_led
*led
, enum led_type type
)
921 led
->rt2x00dev
= rt2x00dev
;
923 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
924 led
->led_dev
.blink_set
= rt2800_blink_set
;
925 led
->flags
= LED_INITIALIZED
;
927 #endif /* CONFIG_RT2X00_LIB_LEDS */
930 * Configuration handlers.
932 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
933 struct rt2x00lib_crypto
*crypto
,
934 struct ieee80211_key_conf
*key
)
936 struct mac_wcid_entry wcid_entry
;
937 struct mac_iveiv_entry iveiv_entry
;
941 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
943 if (crypto
->cmd
== SET_KEY
) {
944 rt2800_register_read(rt2x00dev
, offset
, ®
);
945 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
946 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
948 * Both the cipher as the BSS Idx numbers are split in a main
949 * value of 3 bits, and a extended field for adding one additional
952 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
953 (crypto
->cipher
& 0x7));
954 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
955 (crypto
->cipher
& 0x8) >> 3);
956 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
957 (crypto
->bssidx
& 0x7));
958 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
959 (crypto
->bssidx
& 0x8) >> 3);
960 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
961 rt2800_register_write(rt2x00dev
, offset
, reg
);
963 rt2800_register_write(rt2x00dev
, offset
, 0);
966 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
968 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
969 if ((crypto
->cipher
== CIPHER_TKIP
) ||
970 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
971 (crypto
->cipher
== CIPHER_AES
))
972 iveiv_entry
.iv
[3] |= 0x20;
973 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
974 rt2800_register_multiwrite(rt2x00dev
, offset
,
975 &iveiv_entry
, sizeof(iveiv_entry
));
977 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
979 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
980 if (crypto
->cmd
== SET_KEY
)
981 memcpy(wcid_entry
.mac
, crypto
->address
, ETH_ALEN
);
982 rt2800_register_multiwrite(rt2x00dev
, offset
,
983 &wcid_entry
, sizeof(wcid_entry
));
986 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
987 struct rt2x00lib_crypto
*crypto
,
988 struct ieee80211_key_conf
*key
)
990 struct hw_key_entry key_entry
;
991 struct rt2x00_field32 field
;
995 if (crypto
->cmd
== SET_KEY
) {
996 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
998 memcpy(key_entry
.key
, crypto
->key
,
999 sizeof(key_entry
.key
));
1000 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1001 sizeof(key_entry
.tx_mic
));
1002 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1003 sizeof(key_entry
.rx_mic
));
1005 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1006 rt2800_register_multiwrite(rt2x00dev
, offset
,
1007 &key_entry
, sizeof(key_entry
));
1011 * The cipher types are stored over multiple registers
1012 * starting with SHARED_KEY_MODE_BASE each word will have
1013 * 32 bits and contains the cipher types for 2 bssidx each.
1014 * Using the correct defines correctly will cause overhead,
1015 * so just calculate the correct offset.
1017 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1018 field
.bit_mask
= 0x7 << field
.bit_offset
;
1020 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1022 rt2800_register_read(rt2x00dev
, offset
, ®
);
1023 rt2x00_set_field32(®
, field
,
1024 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1025 rt2800_register_write(rt2x00dev
, offset
, reg
);
1028 * Update WCID information
1030 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1034 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1036 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev
*rt2x00dev
)
1042 * Search for the first free pairwise key entry and return the
1043 * corresponding index.
1045 * Make sure the WCID starts _after_ the last possible shared key
1048 * Since parts of the pairwise key table might be shared with
1049 * the beacon frame buffers 6 & 7 we should only write into the
1050 * first 222 entries.
1052 for (idx
= 33; idx
<= 222; idx
++) {
1053 offset
= MAC_WCID_ATTR_ENTRY(idx
);
1054 rt2800_register_read(rt2x00dev
, offset
, ®
);
1061 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1062 struct rt2x00lib_crypto
*crypto
,
1063 struct ieee80211_key_conf
*key
)
1065 struct hw_key_entry key_entry
;
1069 if (crypto
->cmd
== SET_KEY
) {
1070 idx
= rt2800_find_pairwise_keyslot(rt2x00dev
);
1073 key
->hw_key_idx
= idx
;
1075 memcpy(key_entry
.key
, crypto
->key
,
1076 sizeof(key_entry
.key
));
1077 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1078 sizeof(key_entry
.tx_mic
));
1079 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1080 sizeof(key_entry
.rx_mic
));
1082 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1083 rt2800_register_multiwrite(rt2x00dev
, offset
,
1084 &key_entry
, sizeof(key_entry
));
1088 * Update WCID information
1090 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1094 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1096 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1097 const unsigned int filter_flags
)
1102 * Start configuration steps.
1103 * Note that the version error will always be dropped
1104 * and broadcast frames will always be accepted since
1105 * there is no filter for it at this time.
1107 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1108 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1109 !(filter_flags
& FIF_FCSFAIL
));
1110 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1111 !(filter_flags
& FIF_PLCPFAIL
));
1112 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1113 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1114 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1115 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1116 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1117 !(filter_flags
& FIF_ALLMULTI
));
1118 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1119 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1120 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1121 !(filter_flags
& FIF_CONTROL
));
1122 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1123 !(filter_flags
& FIF_CONTROL
));
1124 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1125 !(filter_flags
& FIF_CONTROL
));
1126 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1127 !(filter_flags
& FIF_CONTROL
));
1128 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1129 !(filter_flags
& FIF_CONTROL
));
1130 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1131 !(filter_flags
& FIF_PSPOLL
));
1132 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
1133 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
1134 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1135 !(filter_flags
& FIF_CONTROL
));
1136 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1138 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1140 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1141 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1144 bool update_bssid
= false;
1146 if (flags
& CONFIG_UPDATE_TYPE
) {
1148 * Enable synchronisation.
1150 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1151 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1152 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1154 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1156 * Tune beacon queue transmit parameters for AP mode
1158 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1159 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1160 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1161 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1162 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1163 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1165 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1166 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1167 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1168 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1169 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1170 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1174 if (flags
& CONFIG_UPDATE_MAC
) {
1175 if (flags
& CONFIG_UPDATE_TYPE
&&
1176 conf
->sync
== TSF_SYNC_AP_NONE
) {
1178 * The BSSID register has to be set to our own mac
1179 * address in AP mode.
1181 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1182 update_bssid
= true;
1185 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1186 reg
= le32_to_cpu(conf
->mac
[1]);
1187 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1188 conf
->mac
[1] = cpu_to_le32(reg
);
1191 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1192 conf
->mac
, sizeof(conf
->mac
));
1195 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1196 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1197 reg
= le32_to_cpu(conf
->bssid
[1]);
1198 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1199 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1200 conf
->bssid
[1] = cpu_to_le32(reg
);
1203 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1204 conf
->bssid
, sizeof(conf
->bssid
));
1207 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1209 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1210 struct rt2x00lib_erp
*erp
)
1212 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1213 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1214 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1215 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1216 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1219 /* default protection rate for HT20: OFDM 24M */
1220 mm20_rate
= gf20_rate
= 0x4004;
1222 /* default protection rate for HT40: duplicate OFDM 24M */
1223 mm40_rate
= gf40_rate
= 0x4084;
1225 switch (protection
) {
1226 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1228 * All STAs in this BSS are HT20/40 but there might be
1229 * STAs not supporting greenfield mode.
1230 * => Disable protection for HT transmissions.
1232 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1235 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1237 * All STAs in this BSS are HT20 or HT20/40 but there
1238 * might be STAs not supporting greenfield mode.
1239 * => Protect all HT40 transmissions.
1241 mm20_mode
= gf20_mode
= 0;
1242 mm40_mode
= gf40_mode
= 2;
1245 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1247 * Nonmember protection:
1248 * According to 802.11n we _should_ protect all
1249 * HT transmissions (but we don't have to).
1251 * But if cts_protection is enabled we _shall_ protect
1252 * all HT transmissions using a CCK rate.
1254 * And if any station is non GF we _shall_ protect
1257 * We decide to protect everything
1258 * -> fall through to mixed mode.
1260 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1262 * Legacy STAs are present
1263 * => Protect all HT transmissions.
1265 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1268 * If erp protection is needed we have to protect HT
1269 * transmissions with CCK 11M long preamble.
1271 if (erp
->cts_protection
) {
1272 /* don't duplicate RTS/CTS in CCK mode */
1273 mm20_rate
= mm40_rate
= 0x0003;
1274 gf20_rate
= gf40_rate
= 0x0003;
1279 /* check for STAs not supporting greenfield mode */
1281 gf20_mode
= gf40_mode
= 2;
1283 /* Update HT protection config */
1284 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1285 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1286 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1287 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1289 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1290 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1291 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1292 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1294 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1295 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1296 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1297 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1299 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1300 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1301 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1302 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1305 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1310 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1311 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1312 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1313 !!erp
->short_preamble
);
1314 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1315 !!erp
->short_preamble
);
1316 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1319 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1320 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1321 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1322 erp
->cts_protection
? 2 : 0);
1323 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1326 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1327 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1329 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1332 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1333 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1334 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1336 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1338 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1339 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1340 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1343 if (changed
& BSS_CHANGED_BEACON_INT
) {
1344 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1345 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1346 erp
->beacon_int
* 16);
1347 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1350 if (changed
& BSS_CHANGED_HT
)
1351 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1353 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1355 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1359 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1361 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1362 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1363 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1364 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1366 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1367 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1369 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1371 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1372 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1373 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1374 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1375 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1376 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1377 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1378 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1379 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1380 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1381 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1383 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1384 (led_g_mode
<< 2) | led_r_mode
, 1);
1389 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1393 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1394 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1396 if (rt2x00_is_pci(rt2x00dev
)) {
1397 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1398 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1399 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1400 } else if (rt2x00_is_usb(rt2x00dev
))
1401 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1404 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1405 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
1406 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, gpio_bit3
);
1407 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1410 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1416 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1417 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1419 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1420 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1421 rt2800_config_3572bt_ant(rt2x00dev
);
1424 * Configure the TX antenna.
1426 switch (ant
->tx_chain_num
) {
1428 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1431 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1432 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1433 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1435 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1438 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1443 * Configure the RX antenna.
1445 switch (ant
->rx_chain_num
) {
1447 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1448 rt2x00_rt(rt2x00dev
, RT3090
) ||
1449 rt2x00_rt(rt2x00dev
, RT3390
)) {
1450 rt2x00_eeprom_read(rt2x00dev
,
1451 EEPROM_NIC_CONF1
, &eeprom
);
1452 if (rt2x00_get_field16(eeprom
,
1453 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1454 rt2800_set_ant_diversity(rt2x00dev
,
1455 rt2x00dev
->default_ant
.rx
);
1457 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1460 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1461 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1462 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1463 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1464 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1465 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1467 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1471 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1475 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1476 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1478 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1480 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1481 struct rt2x00lib_conf
*libconf
)
1486 if (libconf
->rf
.channel
<= 14) {
1487 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1488 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1489 } else if (libconf
->rf
.channel
<= 64) {
1490 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1491 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1492 } else if (libconf
->rf
.channel
<= 128) {
1493 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1494 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1496 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1497 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1500 rt2x00dev
->lna_gain
= lna_gain
;
1503 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1504 struct ieee80211_conf
*conf
,
1505 struct rf_channel
*rf
,
1506 struct channel_info
*info
)
1508 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1510 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1511 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1513 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1514 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1515 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1516 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1517 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1519 if (rf
->channel
> 14) {
1521 * When TX power is below 0, we should increase it by 7 to
1522 * make it a positive value (Minimum value is -7).
1523 * However this means that values between 0 and 7 have
1524 * double meaning, and we should set a 7DBm boost flag.
1526 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1527 (info
->default_power1
>= 0));
1529 if (info
->default_power1
< 0)
1530 info
->default_power1
+= 7;
1532 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1534 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1535 (info
->default_power2
>= 0));
1537 if (info
->default_power2
< 0)
1538 info
->default_power2
+= 7;
1540 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1542 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1543 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1546 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1548 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1549 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1550 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1551 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1555 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1556 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1557 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1558 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1562 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1563 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1564 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1565 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1568 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1569 struct ieee80211_conf
*conf
,
1570 struct rf_channel
*rf
,
1571 struct channel_info
*info
)
1575 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1576 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1578 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1579 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1580 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1582 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1583 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1584 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1586 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1587 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1588 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1590 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1591 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1592 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1594 rt2800_rfcsr_write(rt2x00dev
, 24,
1595 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1597 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1598 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1599 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1602 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
1603 struct ieee80211_conf
*conf
,
1604 struct rf_channel
*rf
,
1605 struct channel_info
*info
)
1610 if (rf
->channel
<= 14) {
1611 rt2800_bbp_write(rt2x00dev
, 25, 0x15);
1612 rt2800_bbp_write(rt2x00dev
, 26, 0x85);
1614 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
1615 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
1618 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1619 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1621 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1622 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1623 if (rf
->channel
<= 14)
1624 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
1626 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
1627 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1629 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
1630 if (rf
->channel
<= 14)
1631 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
1633 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
1634 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
1636 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1637 if (rf
->channel
<= 14) {
1638 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
1639 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1640 (info
->default_power1
& 0x3) |
1641 ((info
->default_power1
& 0xC) << 1));
1643 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
1644 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1645 (info
->default_power1
& 0x3) |
1646 ((info
->default_power1
& 0xC) << 1));
1648 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1650 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1651 if (rf
->channel
<= 14) {
1652 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
1653 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1654 (info
->default_power2
& 0x3) |
1655 ((info
->default_power2
& 0xC) << 1));
1657 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
1658 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1659 (info
->default_power2
& 0x3) |
1660 ((info
->default_power2
& 0xC) << 1));
1662 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1664 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1665 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1666 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1667 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1668 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
1669 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
1670 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1671 if (rf
->channel
<= 14) {
1672 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1673 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1675 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1676 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1678 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
1680 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1682 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1686 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
1688 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1690 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1694 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1696 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1697 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1698 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1700 rt2800_rfcsr_write(rt2x00dev
, 24,
1701 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1702 rt2800_rfcsr_write(rt2x00dev
, 31,
1703 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1705 if (rf
->channel
<= 14) {
1706 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
1707 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
1708 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1709 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
1710 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1711 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
1712 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1713 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
1714 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
1715 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
1716 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1717 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1718 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
1720 rt2800_rfcsr_write(rt2x00dev
, 7, 0x14);
1721 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1722 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1723 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
1724 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
1725 rt2800_rfcsr_write(rt2x00dev
, 16, 0x7a);
1726 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1727 if (rf
->channel
<= 64) {
1728 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
1729 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
1730 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1731 } else if (rf
->channel
<= 128) {
1732 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
1733 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
1734 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1736 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
1737 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
1738 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1740 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
1741 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
1742 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
1745 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1746 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT7
, 0);
1747 if (rf
->channel
<= 14)
1748 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 1);
1750 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 0);
1751 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1753 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1754 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1755 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1758 #define RT5390_POWER_BOUND 0x27
1759 #define RT5390_FREQ_OFFSET_BOUND 0x5f
1761 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
1762 struct ieee80211_conf
*conf
,
1763 struct rf_channel
*rf
,
1764 struct channel_info
*info
)
1768 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
1769 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
1770 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
1771 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
1772 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
1774 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
1775 if (info
->default_power1
> RT5390_POWER_BOUND
)
1776 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, RT5390_POWER_BOUND
);
1778 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
1779 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
1781 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1782 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1783 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
1784 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1785 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1786 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1788 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1789 if (rt2x00dev
->freq_offset
> RT5390_FREQ_OFFSET_BOUND
)
1790 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
,
1791 RT5390_FREQ_OFFSET_BOUND
);
1793 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
1794 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1796 if (rf
->channel
<= 14) {
1797 int idx
= rf
->channel
-1;
1799 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1800 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
1801 /* r55/r59 value array of channel 1~14 */
1802 static const char r55_bt_rev
[] = {0x83, 0x83,
1803 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1804 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1805 static const char r59_bt_rev
[] = {0x0e, 0x0e,
1806 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1807 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1809 rt2800_rfcsr_write(rt2x00dev
, 55,
1811 rt2800_rfcsr_write(rt2x00dev
, 59,
1814 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
1815 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1816 0x88, 0x88, 0x86, 0x85, 0x84};
1818 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
1821 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
1822 static const char r55_nonbt_rev
[] = {0x23, 0x23,
1823 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1824 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1825 static const char r59_nonbt_rev
[] = {0x07, 0x07,
1826 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1827 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1829 rt2800_rfcsr_write(rt2x00dev
, 55,
1830 r55_nonbt_rev
[idx
]);
1831 rt2800_rfcsr_write(rt2x00dev
, 59,
1832 r59_nonbt_rev
[idx
]);
1833 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
1834 static const char r59_non_bt
[] = {0x8f, 0x8f,
1835 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1836 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1838 rt2800_rfcsr_write(rt2x00dev
, 59,
1844 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1845 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
1846 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
1847 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1849 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1850 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1851 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1854 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
1855 struct ieee80211_conf
*conf
,
1856 struct rf_channel
*rf
,
1857 struct channel_info
*info
)
1860 unsigned int tx_pin
;
1863 if (rf
->channel
<= 14) {
1864 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
1865 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
1867 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
1868 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
1871 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
1872 rt2x00_rf(rt2x00dev
, RF3020
) ||
1873 rt2x00_rf(rt2x00dev
, RF3021
) ||
1874 rt2x00_rf(rt2x00dev
, RF3022
) ||
1875 rt2x00_rf(rt2x00dev
, RF3320
))
1876 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
1877 else if (rt2x00_rf(rt2x00dev
, RF3052
))
1878 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
1879 else if (rt2x00_rf(rt2x00dev
, RF5370
) ||
1880 rt2x00_rf(rt2x00dev
, RF5390
))
1881 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
1883 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
1886 * Change BBP settings
1888 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
1889 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
1890 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
1891 rt2800_bbp_write(rt2x00dev
, 86, 0);
1893 if (rf
->channel
<= 14) {
1894 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
1895 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
1896 &rt2x00dev
->cap_flags
)) {
1897 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1898 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1900 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
1901 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1905 if (rt2x00_rt(rt2x00dev
, RT3572
))
1906 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
1908 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
1910 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
1911 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1913 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1916 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
1917 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
1918 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
1919 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
1920 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
1922 if (rt2x00_rt(rt2x00dev
, RT3572
))
1923 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
1927 /* Turn on unused PA or LNA when not using 1T or 1R */
1928 if (rt2x00dev
->default_ant
.tx_chain_num
== 2) {
1929 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
1931 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
1935 /* Turn on unused PA or LNA when not using 1T or 1R */
1936 if (rt2x00dev
->default_ant
.rx_chain_num
== 2) {
1937 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
1938 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
1941 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
1942 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
1943 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
1944 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
1945 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1946 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
1948 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
1950 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
1952 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
1954 if (rt2x00_rt(rt2x00dev
, RT3572
))
1955 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
1957 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1958 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
1959 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1961 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
1962 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
1963 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
1965 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1966 if (conf_is_ht40(conf
)) {
1967 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
1968 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1969 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
1971 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1972 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
1973 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
1980 * Clear channel statistic counters
1982 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
1983 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
1984 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
1987 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
1996 * Read TSSI boundaries for temperature compensation from
1999 * Array idx 0 1 2 3 4 5 6 7 8
2000 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2001 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2003 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2004 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
2005 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2006 EEPROM_TSSI_BOUND_BG1_MINUS4
);
2007 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2008 EEPROM_TSSI_BOUND_BG1_MINUS3
);
2010 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
2011 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2012 EEPROM_TSSI_BOUND_BG2_MINUS2
);
2013 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2014 EEPROM_TSSI_BOUND_BG2_MINUS1
);
2016 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
2017 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2018 EEPROM_TSSI_BOUND_BG3_REF
);
2019 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2020 EEPROM_TSSI_BOUND_BG3_PLUS1
);
2022 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
2023 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2024 EEPROM_TSSI_BOUND_BG4_PLUS2
);
2025 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2026 EEPROM_TSSI_BOUND_BG4_PLUS3
);
2028 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
2029 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2030 EEPROM_TSSI_BOUND_BG5_PLUS4
);
2032 step
= rt2x00_get_field16(eeprom
,
2033 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
2035 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
2036 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2037 EEPROM_TSSI_BOUND_A1_MINUS4
);
2038 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2039 EEPROM_TSSI_BOUND_A1_MINUS3
);
2041 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
2042 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2043 EEPROM_TSSI_BOUND_A2_MINUS2
);
2044 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2045 EEPROM_TSSI_BOUND_A2_MINUS1
);
2047 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
2048 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2049 EEPROM_TSSI_BOUND_A3_REF
);
2050 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2051 EEPROM_TSSI_BOUND_A3_PLUS1
);
2053 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
2054 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2055 EEPROM_TSSI_BOUND_A4_PLUS2
);
2056 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2057 EEPROM_TSSI_BOUND_A4_PLUS3
);
2059 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
2060 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2061 EEPROM_TSSI_BOUND_A5_PLUS4
);
2063 step
= rt2x00_get_field16(eeprom
,
2064 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
2068 * Check if temperature compensation is supported.
2070 if (tssi_bounds
[4] == 0xff)
2074 * Read current TSSI (BBP 49).
2076 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
2079 * Compare TSSI value (BBP49) with the compensation boundaries
2080 * from the EEPROM and increase or decrease tx power.
2082 for (i
= 0; i
<= 3; i
++) {
2083 if (current_tssi
> tssi_bounds
[i
])
2088 for (i
= 8; i
>= 5; i
--) {
2089 if (current_tssi
< tssi_bounds
[i
])
2094 return (i
- 4) * step
;
2097 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
2098 enum ieee80211_band band
)
2105 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
2108 * HT40 compensation not required.
2110 if (eeprom
== 0xffff ||
2111 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2114 if (band
== IEEE80211_BAND_2GHZ
) {
2115 comp_en
= rt2x00_get_field16(eeprom
,
2116 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
2118 comp_type
= rt2x00_get_field16(eeprom
,
2119 EEPROM_TXPOWER_DELTA_TYPE_2G
);
2120 comp_value
= rt2x00_get_field16(eeprom
,
2121 EEPROM_TXPOWER_DELTA_VALUE_2G
);
2123 comp_value
= -comp_value
;
2126 comp_en
= rt2x00_get_field16(eeprom
,
2127 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
2129 comp_type
= rt2x00_get_field16(eeprom
,
2130 EEPROM_TXPOWER_DELTA_TYPE_5G
);
2131 comp_value
= rt2x00_get_field16(eeprom
,
2132 EEPROM_TXPOWER_DELTA_VALUE_5G
);
2134 comp_value
= -comp_value
;
2141 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
2142 enum ieee80211_band band
, int power_level
,
2143 u8 txpower
, int delta
)
2149 u8 eirp_txpower_criterion
;
2152 if (!((band
== IEEE80211_BAND_5GHZ
) && is_rate_b
))
2155 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
2157 * Check if eirp txpower exceed txpower_limit.
2158 * We use OFDM 6M as criterion and its eirp txpower
2159 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2160 * .11b data rate need add additional 4dbm
2161 * when calculating eirp txpower.
2163 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
2164 criterion
= rt2x00_get_field32(reg
, TX_PWR_CFG_0_6MBS
);
2166 rt2x00_eeprom_read(rt2x00dev
,
2167 EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
2169 if (band
== IEEE80211_BAND_2GHZ
)
2170 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2171 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
2173 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2174 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
2176 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
2177 (is_rate_b
? 4 : 0) + delta
;
2179 reg_limit
= (eirp_txpower
> power_level
) ?
2180 (eirp_txpower
- power_level
) : 0;
2184 return txpower
+ delta
- reg_limit
;
2187 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
2188 enum ieee80211_band band
,
2200 * Calculate HT40 compensation delta
2202 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
2205 * calculate temperature compensation delta
2207 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
2210 * set to normal bbp tx power control mode: +/- 0dBm
2212 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
2213 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, 0);
2214 rt2800_bbp_write(rt2x00dev
, 1, r1
);
2215 offset
= TX_PWR_CFG_0
;
2217 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
2218 /* just to be safe */
2219 if (offset
> TX_PWR_CFG_4
)
2222 rt2800_register_read(rt2x00dev
, offset
, ®
);
2224 /* read the next four txpower values */
2225 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
2228 is_rate_b
= i
? 0 : 1;
2230 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2231 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2232 * TX_PWR_CFG_4: unknown
2234 txpower
= rt2x00_get_field16(eeprom
,
2235 EEPROM_TXPOWER_BYRATE_RATE0
);
2236 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2237 power_level
, txpower
, delta
);
2238 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
2241 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2242 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2243 * TX_PWR_CFG_4: unknown
2245 txpower
= rt2x00_get_field16(eeprom
,
2246 EEPROM_TXPOWER_BYRATE_RATE1
);
2247 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2248 power_level
, txpower
, delta
);
2249 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
2252 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2253 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2254 * TX_PWR_CFG_4: unknown
2256 txpower
= rt2x00_get_field16(eeprom
,
2257 EEPROM_TXPOWER_BYRATE_RATE2
);
2258 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2259 power_level
, txpower
, delta
);
2260 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
2263 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2264 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2265 * TX_PWR_CFG_4: unknown
2267 txpower
= rt2x00_get_field16(eeprom
,
2268 EEPROM_TXPOWER_BYRATE_RATE3
);
2269 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2270 power_level
, txpower
, delta
);
2271 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
2273 /* read the next four txpower values */
2274 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
2279 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2280 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2281 * TX_PWR_CFG_4: unknown
2283 txpower
= rt2x00_get_field16(eeprom
,
2284 EEPROM_TXPOWER_BYRATE_RATE0
);
2285 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2286 power_level
, txpower
, delta
);
2287 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
2290 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2291 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2292 * TX_PWR_CFG_4: unknown
2294 txpower
= rt2x00_get_field16(eeprom
,
2295 EEPROM_TXPOWER_BYRATE_RATE1
);
2296 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2297 power_level
, txpower
, delta
);
2298 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
2301 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2302 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2303 * TX_PWR_CFG_4: unknown
2305 txpower
= rt2x00_get_field16(eeprom
,
2306 EEPROM_TXPOWER_BYRATE_RATE2
);
2307 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2308 power_level
, txpower
, delta
);
2309 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
2312 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2313 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2314 * TX_PWR_CFG_4: unknown
2316 txpower
= rt2x00_get_field16(eeprom
,
2317 EEPROM_TXPOWER_BYRATE_RATE3
);
2318 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2319 power_level
, txpower
, delta
);
2320 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
2322 rt2800_register_write(rt2x00dev
, offset
, reg
);
2324 /* next TX_PWR_CFG register */
2329 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
2331 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->curr_band
,
2332 rt2x00dev
->tx_power
);
2334 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
2336 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
2337 struct rt2x00lib_conf
*libconf
)
2341 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2342 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
2343 libconf
->conf
->short_frame_max_tx_count
);
2344 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
2345 libconf
->conf
->long_frame_max_tx_count
);
2346 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2349 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
2350 struct rt2x00lib_conf
*libconf
)
2352 enum dev_state state
=
2353 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
2354 STATE_SLEEP
: STATE_AWAKE
;
2357 if (state
== STATE_SLEEP
) {
2358 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
2360 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2361 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
2362 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
2363 libconf
->conf
->listen_interval
- 1);
2364 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
2365 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2367 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2369 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2370 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
2371 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
2372 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
2373 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2375 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2379 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
2380 struct rt2x00lib_conf
*libconf
,
2381 const unsigned int flags
)
2383 /* Always recalculate LNA gain before changing configuration */
2384 rt2800_config_lna_gain(rt2x00dev
, libconf
);
2386 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2387 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
2388 &libconf
->rf
, &libconf
->channel
);
2389 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2390 libconf
->conf
->power_level
);
2392 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
2393 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2394 libconf
->conf
->power_level
);
2395 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
2396 rt2800_config_retry_limit(rt2x00dev
, libconf
);
2397 if (flags
& IEEE80211_CONF_CHANGE_PS
)
2398 rt2800_config_ps(rt2x00dev
, libconf
);
2400 EXPORT_SYMBOL_GPL(rt2800_config
);
2405 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2410 * Update FCS error count from register.
2412 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2413 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
2415 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
2417 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
2419 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2420 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2421 rt2x00_rt(rt2x00dev
, RT3071
) ||
2422 rt2x00_rt(rt2x00dev
, RT3090
) ||
2423 rt2x00_rt(rt2x00dev
, RT3390
) ||
2424 rt2x00_rt(rt2x00dev
, RT5390
))
2425 return 0x1c + (2 * rt2x00dev
->lna_gain
);
2427 return 0x2e + rt2x00dev
->lna_gain
;
2430 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2431 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
2433 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
2436 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
2437 struct link_qual
*qual
, u8 vgc_level
)
2439 if (qual
->vgc_level
!= vgc_level
) {
2440 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
2441 qual
->vgc_level
= vgc_level
;
2442 qual
->vgc_level_reg
= vgc_level
;
2446 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2448 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
2450 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
2452 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
2455 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
2459 * When RSSI is better then -80 increase VGC level with 0x10
2461 rt2800_set_vgc(rt2x00dev
, qual
,
2462 rt2800_get_default_vgc(rt2x00dev
) +
2463 ((qual
->rssi
> -80) * 0x10));
2465 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
2468 * Initialization functions.
2470 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
2477 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2478 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2479 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2480 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2481 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2482 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
2483 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2485 ret
= rt2800_drv_init_registers(rt2x00dev
);
2489 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
2490 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
2491 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
2492 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
2493 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
2494 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
2496 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
2497 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
2498 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
2499 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
2500 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
2501 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
2503 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
2504 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
2506 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
2508 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
2509 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
2510 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
2511 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
2512 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
2513 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
2514 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
2515 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
2517 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
2519 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
2520 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
2521 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
2522 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
2524 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2525 rt2x00_rt(rt2x00dev
, RT3090
) ||
2526 rt2x00_rt(rt2x00dev
, RT3390
)) {
2527 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2528 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2529 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2530 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2531 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2532 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
2533 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
2534 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2537 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2540 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2542 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
2543 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2545 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
2546 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2547 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
2549 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2550 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2552 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2553 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2554 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2555 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
2556 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
2557 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2558 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2559 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
2560 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
2561 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2562 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2564 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
2565 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2568 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
2569 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
2570 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
2571 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
2572 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
2573 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
2574 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
2575 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
2576 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
2577 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
2579 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
2580 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
2581 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
2582 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
2583 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
2585 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
2586 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
2587 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
2588 rt2x00_rt(rt2x00dev
, RT2883
) ||
2589 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
2590 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
2592 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
2593 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
2594 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
2595 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
2597 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
2598 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
2599 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
2600 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
2601 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
2602 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
2603 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
2604 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
2605 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
2607 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
2609 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2610 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
2611 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
2612 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
2613 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
2614 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
2615 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
2616 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2618 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
2619 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
2620 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
2621 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
2622 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
2623 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
2624 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
2625 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
2626 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
2628 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2629 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
2630 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
2631 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2632 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2633 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2634 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2635 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2636 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2637 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2638 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
2639 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2641 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2642 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
2643 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
2644 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2645 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2646 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2647 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2648 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2649 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2650 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2651 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
2652 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2654 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2655 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
2656 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
2657 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2658 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2659 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2660 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2661 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2662 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2663 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2664 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
2665 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2667 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2668 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
2669 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
2670 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2671 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2672 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2673 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2674 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2675 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2676 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2677 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
2678 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2680 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2681 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
2682 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
2683 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2684 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2685 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2686 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2687 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2688 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2689 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2690 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
2691 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2693 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2694 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
2695 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
2696 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2697 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2698 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2699 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2700 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2701 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2702 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2703 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
2704 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2706 if (rt2x00_is_usb(rt2x00dev
)) {
2707 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
2709 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2710 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2711 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2712 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2713 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2714 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
2715 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
2716 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
2717 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
2718 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
2719 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2723 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2724 * although it is reserved.
2726 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
2727 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
2728 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
2729 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
2730 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
2731 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
2732 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
2733 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
2734 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
2735 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
2736 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
2737 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
2739 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
2741 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2742 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
2743 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
2744 IEEE80211_MAX_RTS_THRESHOLD
);
2745 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
2746 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2748 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
2751 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2752 * time should be set to 16. However, the original Ralink driver uses
2753 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2754 * connection problems with 11g + CTS protection. Hence, use the same
2755 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2757 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
2758 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
2759 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
2760 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
2761 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
2762 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
2763 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
2765 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
2768 * ASIC will keep garbage value after boot, clear encryption keys.
2770 for (i
= 0; i
< 4; i
++)
2771 rt2800_register_write(rt2x00dev
,
2772 SHARED_KEY_MODE_ENTRY(i
), 0);
2774 for (i
= 0; i
< 256; i
++) {
2775 static const u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
2776 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
2777 wcid
, sizeof(wcid
));
2779 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 0);
2780 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
2786 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE0
);
2787 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE1
);
2788 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE2
);
2789 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE3
);
2790 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE4
);
2791 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE5
);
2792 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE6
);
2793 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE7
);
2795 if (rt2x00_is_usb(rt2x00dev
)) {
2796 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2797 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
2798 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2799 } else if (rt2x00_is_pcie(rt2x00dev
)) {
2800 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2801 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
2802 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2805 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
2806 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
2807 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
2808 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
2809 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
2810 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
2811 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
2812 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
2813 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
2814 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
2816 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
2817 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
2818 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
2819 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
2820 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
2821 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
2822 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
2823 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
2824 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
2825 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
2827 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
2828 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
2829 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
2830 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
2831 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
2832 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
2833 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
2834 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
2835 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
2836 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
2838 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
2839 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
2840 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
2841 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
2842 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
2843 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
2846 * Do not force the BA window size, we use the TXWI to set it
2848 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
2849 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
2850 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
2851 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
2854 * We must clear the error counters.
2855 * These registers are cleared on read,
2856 * so we may pass a useless variable to store the value.
2858 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2859 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
2860 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
2861 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
2862 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
2863 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
2866 * Setup leadtime for pre tbtt interrupt to 6ms
2868 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
2869 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
2870 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
2873 * Set up channel statistics timer
2875 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
2876 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
2877 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
2878 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
2879 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
2880 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
2881 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
2886 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
2891 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2892 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
2893 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
2896 udelay(REGISTER_BUSY_DELAY
);
2899 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
2903 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
2909 * BBP was enabled after firmware was loaded,
2910 * but we need to reactivate it now.
2912 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
2913 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
2916 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2917 rt2800_bbp_read(rt2x00dev
, 0, &value
);
2918 if ((value
!= 0xff) && (value
!= 0x00))
2920 udelay(REGISTER_BUSY_DELAY
);
2923 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
2927 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
2934 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
2935 rt2800_wait_bbp_ready(rt2x00dev
)))
2938 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
2939 rt2800_bbp_read(rt2x00dev
, 4, &value
);
2940 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
2941 rt2800_bbp_write(rt2x00dev
, 4, value
);
2944 if (rt2800_is_305x_soc(rt2x00dev
) ||
2945 rt2x00_rt(rt2x00dev
, RT3572
) ||
2946 rt2x00_rt(rt2x00dev
, RT5390
))
2947 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
2949 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
2950 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
2952 if (rt2x00_rt(rt2x00dev
, RT5390
))
2953 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
2955 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2956 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2957 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
2958 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
2959 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
2960 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
2961 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2962 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
2963 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
2965 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
2966 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
2969 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2971 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2972 rt2x00_rt(rt2x00dev
, RT3071
) ||
2973 rt2x00_rt(rt2x00dev
, RT3090
) ||
2974 rt2x00_rt(rt2x00dev
, RT3390
) ||
2975 rt2x00_rt(rt2x00dev
, RT3572
) ||
2976 rt2x00_rt(rt2x00dev
, RT5390
)) {
2977 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
2978 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
2979 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
2980 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2981 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
2982 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
2984 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
2987 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2988 if (rt2x00_rt(rt2x00dev
, RT5390
))
2989 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
2991 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
2993 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
2994 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
2995 else if (rt2x00_rt(rt2x00dev
, RT5390
))
2996 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
2998 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
3000 if (rt2x00_rt(rt2x00dev
, RT5390
))
3001 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
3003 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
3005 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
3007 if (rt2x00_rt(rt2x00dev
, RT5390
))
3008 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
3010 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
3012 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3013 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3014 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3015 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
3016 rt2x00_rt(rt2x00dev
, RT3572
) ||
3017 rt2x00_rt(rt2x00dev
, RT5390
) ||
3018 rt2800_is_305x_soc(rt2x00dev
))
3019 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
3021 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
3023 if (rt2x00_rt(rt2x00dev
, RT5390
))
3024 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
3026 if (rt2800_is_305x_soc(rt2x00dev
))
3027 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
3028 else if (rt2x00_rt(rt2x00dev
, RT5390
))
3029 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
3031 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
3033 if (rt2x00_rt(rt2x00dev
, RT5390
))
3034 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
3036 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
3038 if (rt2x00_rt(rt2x00dev
, RT5390
))
3039 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
3041 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3042 rt2x00_rt(rt2x00dev
, RT3090
) ||
3043 rt2x00_rt(rt2x00dev
, RT3390
) ||
3044 rt2x00_rt(rt2x00dev
, RT3572
) ||
3045 rt2x00_rt(rt2x00dev
, RT5390
)) {
3046 rt2800_bbp_read(rt2x00dev
, 138, &value
);
3048 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3049 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3051 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3054 rt2800_bbp_write(rt2x00dev
, 138, value
);
3057 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3060 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3061 div_mode
= rt2x00_get_field16(eeprom
,
3062 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3063 ant
= (div_mode
== 3) ? 1 : 0;
3065 /* check if this is a Bluetooth combo card */
3066 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
3069 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
3070 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
3071 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT6
, 0);
3072 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 0);
3073 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 0);
3075 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 1);
3077 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 1);
3078 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
3081 rt2800_bbp_read(rt2x00dev
, 152, &value
);
3083 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
3085 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
3086 rt2800_bbp_write(rt2x00dev
, 152, value
);
3088 /* Init frequency calibration */
3089 rt2800_bbp_write(rt2x00dev
, 142, 1);
3090 rt2800_bbp_write(rt2x00dev
, 143, 57);
3093 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
3094 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
3096 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
3097 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
3098 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
3099 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
3106 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
3107 bool bw40
, u8 rfcsr24
, u8 filter_target
)
3116 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3118 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3119 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
3120 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3122 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
3123 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
3124 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
3126 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3127 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
3128 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3131 * Set power & frequency of passband test tone
3133 rt2800_bbp_write(rt2x00dev
, 24, 0);
3135 for (i
= 0; i
< 100; i
++) {
3136 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3139 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
3145 * Set power & frequency of stopband test tone
3147 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
3149 for (i
= 0; i
< 100; i
++) {
3150 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3153 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
3155 if ((passband
- stopband
) <= filter_target
) {
3157 overtuned
+= ((passband
- stopband
) == filter_target
);
3161 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3164 rfcsr24
-= !!overtuned
;
3166 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3170 static int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
3177 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
3178 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3179 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3180 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3181 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3182 !rt2x00_rt(rt2x00dev
, RT5390
) &&
3183 !rt2800_is_305x_soc(rt2x00dev
))
3187 * Init RF calibration.
3189 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3190 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
3191 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
3192 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3194 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 0);
3195 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3197 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3198 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
3199 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3201 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
3202 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3205 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3206 rt2x00_rt(rt2x00dev
, RT3071
) ||
3207 rt2x00_rt(rt2x00dev
, RT3090
)) {
3208 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3209 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3210 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3211 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
3212 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3213 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
3214 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3215 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
3216 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3217 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3218 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3219 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3220 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3221 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3222 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3223 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3224 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3225 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3226 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
3227 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3228 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
3229 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
3230 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3231 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
3232 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3233 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
3234 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
3235 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
3236 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
3237 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
3238 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
3239 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3240 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
3241 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
3242 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3243 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3244 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
3245 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
3246 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
3247 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
3248 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
3249 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
3250 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3251 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
3252 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3253 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
3254 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3255 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3256 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
3257 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
3258 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
3259 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
3260 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3261 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
3262 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
3263 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3264 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
3265 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
3266 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
3267 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
3268 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
3269 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
3270 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
3271 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
3272 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
3273 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
3274 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
3275 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3276 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
3277 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
3278 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
3279 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
3280 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
3281 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
3282 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3283 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
3284 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3285 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
3286 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3287 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3288 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3289 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
3290 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
3291 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
3292 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3293 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
3294 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
3295 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
3296 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
3297 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3298 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3299 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3300 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
3301 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
3302 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3303 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
3304 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3305 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
3306 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
3307 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3308 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3309 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3310 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3311 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3312 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3313 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3314 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3315 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3316 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
3317 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3318 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3319 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
3320 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
3321 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
3322 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
3323 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3324 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
3326 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3327 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
3328 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
3329 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
3330 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
3331 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3332 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
3334 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
3335 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
3336 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
3337 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
3338 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
3339 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
3340 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
3341 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
3342 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
3343 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
3344 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
3346 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
3347 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
3348 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
3349 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
3350 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
3351 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3352 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
3354 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
3355 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
3356 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
3357 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3358 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
3360 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3361 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
3362 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
3363 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
3364 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
3365 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
3366 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
3367 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
3368 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
3369 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
3371 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3372 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
3374 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
3375 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
3376 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
3377 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
3378 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
3379 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
3380 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3381 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
3383 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
3384 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
3385 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
3386 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
3388 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
3389 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3390 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
3392 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
3393 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
3394 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
3395 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
3396 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
3397 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
3398 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
3400 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
3401 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3402 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
3404 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
3405 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
3406 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
3409 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
3410 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3411 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3412 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3413 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3414 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3415 rt2x00_rt(rt2x00dev
, RT3090
)) {
3416 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
3418 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3419 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3420 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3422 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3423 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3424 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3425 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
3426 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3427 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
3428 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3430 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
3432 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3434 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3435 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3436 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3437 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3438 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3439 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3440 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3441 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3442 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3443 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3444 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3446 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3447 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3448 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3449 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3451 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3452 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3453 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3457 * Set RX Filter calibration for 20MHz and 40MHz
3459 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3460 rt2x00dev
->calibration
[0] =
3461 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
3462 rt2x00dev
->calibration
[1] =
3463 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
3464 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3465 rt2x00_rt(rt2x00dev
, RT3090
) ||
3466 rt2x00_rt(rt2x00dev
, RT3390
) ||
3467 rt2x00_rt(rt2x00dev
, RT3572
)) {
3468 rt2x00dev
->calibration
[0] =
3469 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
3470 rt2x00dev
->calibration
[1] =
3471 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
3474 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
3476 * Set back to initial state
3478 rt2800_bbp_write(rt2x00dev
, 24, 0);
3480 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3481 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
3482 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3485 * Set BBP back to BW20
3487 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3488 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
3489 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3492 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3493 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3494 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3495 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
3496 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
3498 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
3499 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
3500 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
3502 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
3503 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
3504 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
3505 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3506 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3507 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3508 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
3509 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
3510 &rt2x00dev
->cap_flags
))
3511 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
3513 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
3514 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
3515 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
3516 rt2x00_get_field16(eeprom
,
3517 EEPROM_TXMIXER_GAIN_BG_VAL
));
3518 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
3521 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
3522 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
3524 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
3525 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3526 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3527 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
3528 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3529 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
3531 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
3534 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3535 rt2x00_rt(rt2x00dev
, RT3090
) ||
3536 rt2x00_rt(rt2x00dev
, RT3390
)) {
3537 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
3538 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
3539 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
3540 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
3541 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
3542 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
3543 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
3545 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
3546 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
3547 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
3549 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
3550 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
3551 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
3553 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
3554 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
3555 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
3558 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3559 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
3560 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
3561 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
3563 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
3564 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
3565 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
3566 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
3567 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
3570 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3571 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
3572 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
3573 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
3575 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
3576 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
3577 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
3579 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3580 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
3581 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3587 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
3593 * Initialize all registers.
3595 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
3596 rt2800_init_registers(rt2x00dev
) ||
3597 rt2800_init_bbp(rt2x00dev
) ||
3598 rt2800_init_rfcsr(rt2x00dev
)))
3602 * Send signal to firmware during boot time.
3604 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
3606 if (rt2x00_is_usb(rt2x00dev
) &&
3607 (rt2x00_rt(rt2x00dev
, RT3070
) ||
3608 rt2x00_rt(rt2x00dev
, RT3071
) ||
3609 rt2x00_rt(rt2x00dev
, RT3572
))) {
3611 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
3618 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3619 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3620 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
3621 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3625 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3626 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
3627 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
3628 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
3629 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
3630 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3632 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3633 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3634 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
3635 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3638 * Initialize LED control
3640 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
3641 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
3642 word
& 0xff, (word
>> 8) & 0xff);
3644 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
3645 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
3646 word
& 0xff, (word
>> 8) & 0xff);
3648 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
3649 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
3650 word
& 0xff, (word
>> 8) & 0xff);
3654 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
3656 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
3660 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3661 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
3662 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
3663 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3665 /* Wait for DMA, ignore error */
3666 rt2800_wait_wpdma_ready(rt2x00dev
);
3668 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3669 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
3670 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
3671 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3673 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
3675 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
3679 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
3681 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
3683 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
3685 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
3689 mutex_lock(&rt2x00dev
->csr_mutex
);
3691 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
3692 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
3693 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
3694 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
3695 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
3697 /* Wait until the EEPROM has been loaded */
3698 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
3700 /* Apparently the data is read from end to start */
3701 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
3702 (u32
*)&rt2x00dev
->eeprom
[i
]);
3703 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
3704 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
3705 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
3706 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
3707 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
3708 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
3710 mutex_unlock(&rt2x00dev
->csr_mutex
);
3713 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
3717 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
3718 rt2800_efuse_read(rt2x00dev
, i
);
3720 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
3722 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
3726 u8 default_lna_gain
;
3729 * Start validation of the data that has been read.
3731 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
3732 if (!is_valid_ether_addr(mac
)) {
3733 random_ether_addr(mac
);
3734 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
3737 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
3738 if (word
== 0xffff) {
3739 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
3740 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
3741 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
3742 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
3743 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
3744 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
3745 rt2x00_rt(rt2x00dev
, RT2872
)) {
3747 * There is a max of 2 RX streams for RT28x0 series
3749 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
3750 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
3751 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
3754 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
3755 if (word
== 0xffff) {
3756 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
3757 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
3758 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
3759 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
3760 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
3761 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
3762 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
3763 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
3764 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
3765 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
3766 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
3767 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
3768 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
3769 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
3770 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
3771 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
3772 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
3775 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
3776 if ((word
& 0x00ff) == 0x00ff) {
3777 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
3778 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
3779 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
3781 if ((word
& 0xff00) == 0xff00) {
3782 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
3783 LED_MODE_TXRX_ACTIVITY
);
3784 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
3785 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
3786 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
3787 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
3788 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
3789 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
3793 * During the LNA validation we are going to use
3794 * lna0 as correct value. Note that EEPROM_LNA
3795 * is never validated.
3797 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
3798 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
3800 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
3801 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
3802 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
3803 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
3804 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
3805 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
3807 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
3808 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
3809 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
3810 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
3811 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
3812 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
3814 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
3816 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
3817 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
3818 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
3819 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
3820 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
3821 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
3823 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
3824 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
3825 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
3826 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
3827 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
3828 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
3830 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
3834 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
3836 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
3843 * Read EEPROM word for configuration.
3845 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3848 * Identify RF chipset by EEPROM value
3849 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3850 * RT53xx: defined in "EEPROM_CHIP_ID" field
3852 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
3853 if (rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT5390
)
3854 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &value
);
3856 value
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
3858 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
3859 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
3861 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
3862 !rt2x00_rt(rt2x00dev
, RT2872
) &&
3863 !rt2x00_rt(rt2x00dev
, RT2883
) &&
3864 !rt2x00_rt(rt2x00dev
, RT3070
) &&
3865 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3866 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3867 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3868 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3869 !rt2x00_rt(rt2x00dev
, RT5390
)) {
3870 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
3874 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
3875 !rt2x00_rf(rt2x00dev
, RF2850
) &&
3876 !rt2x00_rf(rt2x00dev
, RF2720
) &&
3877 !rt2x00_rf(rt2x00dev
, RF2750
) &&
3878 !rt2x00_rf(rt2x00dev
, RF3020
) &&
3879 !rt2x00_rf(rt2x00dev
, RF2020
) &&
3880 !rt2x00_rf(rt2x00dev
, RF3021
) &&
3881 !rt2x00_rf(rt2x00dev
, RF3022
) &&
3882 !rt2x00_rf(rt2x00dev
, RF3052
) &&
3883 !rt2x00_rf(rt2x00dev
, RF3320
) &&
3884 !rt2x00_rf(rt2x00dev
, RF5370
) &&
3885 !rt2x00_rf(rt2x00dev
, RF5390
)) {
3886 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
3891 * Identify default antenna configuration.
3893 rt2x00dev
->default_ant
.tx_chain_num
=
3894 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
3895 rt2x00dev
->default_ant
.rx_chain_num
=
3896 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
3898 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3900 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3901 rt2x00_rt(rt2x00dev
, RT3090
) ||
3902 rt2x00_rt(rt2x00dev
, RT3390
)) {
3903 value
= rt2x00_get_field16(eeprom
,
3904 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3909 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3910 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
3913 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3914 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
3918 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3919 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
3923 * Determine external LNA informations.
3925 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
3926 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
3927 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
3928 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
3931 * Detect if this device has an hardware controlled radio.
3933 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
3934 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
3937 * Detect if this device has Bluetooth co-existence.
3939 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
3940 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
3943 * Read frequency offset and RF programming sequence.
3945 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
3946 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
3949 * Store led settings, for correct led behaviour.
3951 #ifdef CONFIG_RT2X00_LIB_LEDS
3952 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
3953 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
3954 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
3956 rt2x00dev
->led_mcu_reg
= eeprom
;
3957 #endif /* CONFIG_RT2X00_LIB_LEDS */
3960 * Check if support EIRP tx power limit feature.
3962 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
3964 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
3965 EIRP_MAX_TX_POWER_LIMIT
)
3966 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
3970 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
3973 * RF value list for rt28xx
3974 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3976 static const struct rf_channel rf_vals
[] = {
3977 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3978 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3979 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3980 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3981 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3982 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3983 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3984 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3985 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3986 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3987 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3988 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3989 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3990 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3992 /* 802.11 UNI / HyperLan 2 */
3993 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3994 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3995 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3996 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3997 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3998 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3999 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4000 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4001 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4002 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4003 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4004 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4006 /* 802.11 HyperLan 2 */
4007 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4008 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4009 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4010 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4011 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4012 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4013 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4014 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4015 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4016 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4017 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4018 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4019 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4020 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4021 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4022 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4025 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4026 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4027 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4028 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4029 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4030 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4031 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4032 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4033 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4034 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4035 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4038 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4039 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4040 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4041 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4042 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4043 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4044 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4048 * RF value list for rt3xxx
4049 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4051 static const struct rf_channel rf_vals_3x
[] = {
4067 /* 802.11 UNI / HyperLan 2 */
4081 /* 802.11 HyperLan 2 */
4113 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
4115 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
4116 struct channel_info
*info
;
4117 char *default_power1
;
4118 char *default_power2
;
4123 * Disable powersaving as default on PCI devices.
4125 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
4126 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
4129 * Initialize all hw fields.
4131 rt2x00dev
->hw
->flags
=
4132 IEEE80211_HW_SIGNAL_DBM
|
4133 IEEE80211_HW_SUPPORTS_PS
|
4134 IEEE80211_HW_PS_NULLFUNC_STACK
|
4135 IEEE80211_HW_AMPDU_AGGREGATION
;
4137 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4138 * unless we are capable of sending the buffered frames out after the
4139 * DTIM transmission using rt2x00lib_beacondone. This will send out
4140 * multicast and broadcast traffic immediately instead of buffering it
4141 * infinitly and thus dropping it after some time.
4143 if (!rt2x00_is_usb(rt2x00dev
))
4144 rt2x00dev
->hw
->flags
|=
4145 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
4147 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
4148 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
4149 rt2x00_eeprom_addr(rt2x00dev
,
4150 EEPROM_MAC_ADDR_0
));
4153 * As rt2800 has a global fallback table we cannot specify
4154 * more then one tx rate per frame but since the hw will
4155 * try several rates (based on the fallback table) we should
4156 * initialize max_report_rates to the maximum number of rates
4157 * we are going to try. Otherwise mac80211 will truncate our
4158 * reported tx rates and the rc algortihm will end up with
4161 rt2x00dev
->hw
->max_rates
= 1;
4162 rt2x00dev
->hw
->max_report_rates
= 7;
4163 rt2x00dev
->hw
->max_rate_tries
= 1;
4165 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4168 * Initialize hw_mode information.
4170 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
4171 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
4173 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
4174 rt2x00_rf(rt2x00dev
, RF2720
)) {
4175 spec
->num_channels
= 14;
4176 spec
->channels
= rf_vals
;
4177 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
4178 rt2x00_rf(rt2x00dev
, RF2750
)) {
4179 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4180 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
4181 spec
->channels
= rf_vals
;
4182 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
4183 rt2x00_rf(rt2x00dev
, RF2020
) ||
4184 rt2x00_rf(rt2x00dev
, RF3021
) ||
4185 rt2x00_rf(rt2x00dev
, RF3022
) ||
4186 rt2x00_rf(rt2x00dev
, RF3320
) ||
4187 rt2x00_rf(rt2x00dev
, RF5370
) ||
4188 rt2x00_rf(rt2x00dev
, RF5390
)) {
4189 spec
->num_channels
= 14;
4190 spec
->channels
= rf_vals_3x
;
4191 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
4192 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4193 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
4194 spec
->channels
= rf_vals_3x
;
4198 * Initialize HT information.
4200 if (!rt2x00_rf(rt2x00dev
, RF2020
))
4201 spec
->ht
.ht_supported
= true;
4203 spec
->ht
.ht_supported
= false;
4206 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
4207 IEEE80211_HT_CAP_GRN_FLD
|
4208 IEEE80211_HT_CAP_SGI_20
|
4209 IEEE80211_HT_CAP_SGI_40
;
4211 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
4212 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
4215 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
4216 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
4218 spec
->ht
.ampdu_factor
= 3;
4219 spec
->ht
.ampdu_density
= 4;
4220 spec
->ht
.mcs
.tx_params
=
4221 IEEE80211_HT_MCS_TX_DEFINED
|
4222 IEEE80211_HT_MCS_TX_RX_DIFF
|
4223 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
4224 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
4226 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
4228 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
4230 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
4232 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
4233 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
4238 * Create channel information array
4240 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
4244 spec
->channels_info
= info
;
4246 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
4247 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
4249 for (i
= 0; i
< 14; i
++) {
4250 info
[i
].default_power1
= default_power1
[i
];
4251 info
[i
].default_power2
= default_power2
[i
];
4254 if (spec
->num_channels
> 14) {
4255 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
4256 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
4258 for (i
= 14; i
< spec
->num_channels
; i
++) {
4259 info
[i
].default_power1
= default_power1
[i
];
4260 info
[i
].default_power2
= default_power2
[i
];
4266 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
4269 * IEEE80211 stack callback functions.
4271 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
4274 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4275 struct mac_iveiv_entry iveiv_entry
;
4278 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
4279 rt2800_register_multiread(rt2x00dev
, offset
,
4280 &iveiv_entry
, sizeof(iveiv_entry
));
4282 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
4283 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
4285 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
4287 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
4289 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4291 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
4293 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
4294 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
4295 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
4297 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
4298 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
4299 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
4301 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
4302 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
4303 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
4305 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
4306 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
4307 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
4309 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
4310 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
4311 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
4313 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
4314 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
4315 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
4317 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
4318 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
4319 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
4323 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
4325 int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
4326 const struct ieee80211_tx_queue_params
*params
)
4328 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4329 struct data_queue
*queue
;
4330 struct rt2x00_field32 field
;
4336 * First pass the configuration through rt2x00lib, that will
4337 * update the queue settings and validate the input. After that
4338 * we are free to update the registers based on the value
4339 * in the queue parameter.
4341 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
4346 * We only need to perform additional register initialization
4352 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
4354 /* Update WMM TXOP register */
4355 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
4356 field
.bit_offset
= (queue_idx
& 1) * 16;
4357 field
.bit_mask
= 0xffff << field
.bit_offset
;
4359 rt2800_register_read(rt2x00dev
, offset
, ®
);
4360 rt2x00_set_field32(®
, field
, queue
->txop
);
4361 rt2800_register_write(rt2x00dev
, offset
, reg
);
4363 /* Update WMM registers */
4364 field
.bit_offset
= queue_idx
* 4;
4365 field
.bit_mask
= 0xf << field
.bit_offset
;
4367 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
4368 rt2x00_set_field32(®
, field
, queue
->aifs
);
4369 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
4371 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
4372 rt2x00_set_field32(®
, field
, queue
->cw_min
);
4373 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
4375 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
4376 rt2x00_set_field32(®
, field
, queue
->cw_max
);
4377 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
4379 /* Update EDCA registers */
4380 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
4382 rt2800_register_read(rt2x00dev
, offset
, ®
);
4383 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
4384 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
4385 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
4386 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
4387 rt2800_register_write(rt2x00dev
, offset
, reg
);
4391 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
4393 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
4395 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4399 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
4400 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
4401 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
4402 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
4406 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
4408 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
4409 enum ieee80211_ampdu_mlme_action action
,
4410 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
4416 case IEEE80211_AMPDU_RX_START
:
4417 case IEEE80211_AMPDU_RX_STOP
:
4419 * The hw itself takes care of setting up BlockAck mechanisms.
4420 * So, we only have to allow mac80211 to nagotiate a BlockAck
4421 * agreement. Once that is done, the hw will BlockAck incoming
4422 * AMPDUs without further setup.
4425 case IEEE80211_AMPDU_TX_START
:
4426 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4428 case IEEE80211_AMPDU_TX_STOP
:
4429 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4431 case IEEE80211_AMPDU_TX_OPERATIONAL
:
4434 WARNING((struct rt2x00_dev
*)hw
->priv
, "Unknown AMPDU action\n");
4439 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
4441 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
4442 struct survey_info
*survey
)
4444 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4445 struct ieee80211_conf
*conf
= &hw
->conf
;
4446 u32 idle
, busy
, busy_ext
;
4451 survey
->channel
= conf
->channel
;
4453 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
4454 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
4455 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
4458 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
4459 SURVEY_INFO_CHANNEL_TIME_BUSY
|
4460 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
4462 survey
->channel_time
= (idle
+ busy
) / 1000;
4463 survey
->channel_time_busy
= busy
/ 1000;
4464 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
4470 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
4472 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
4473 MODULE_VERSION(DRV_VERSION
);
4474 MODULE_DESCRIPTION("Ralink RT2800 library");
4475 MODULE_LICENSE("GPL");