2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
225 const u8 command
, const u8 token
,
226 const u8 arg0
, const u8 arg1
)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev
))
236 mutex_lock(&rt2x00dev
->csr_mutex
);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
243 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
244 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
245 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
246 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
247 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
250 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
251 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
254 mutex_unlock(&rt2x00dev
->csr_mutex
);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
258 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
263 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
264 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
265 if (reg
&& reg
!= ~0)
270 ERROR(rt2x00dev
, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
285 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
286 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
287 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
293 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
298 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
308 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
317 crc
= crc_ccitt(~0, data
, len
- 2);
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
327 return fw_crc
== crc
;
330 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
331 const u8
*data
, const size_t len
)
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
345 if (rt2x00_is_usb(rt2x00dev
)) {
354 * Validate the firmware length
356 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
357 return FW_BAD_LENGTH
;
360 * Check if the chipset requires one of the upper parts
363 if (rt2x00_is_usb(rt2x00dev
) &&
364 !rt2x00_rt(rt2x00dev
, RT2860
) &&
365 !rt2x00_rt(rt2x00dev
, RT2872
) &&
366 !rt2x00_rt(rt2x00dev
, RT3070
) &&
367 ((len
/ fw_len
) == 1))
368 return FW_BAD_VERSION
;
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
374 while (offset
< len
) {
375 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
385 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
386 const u8
*data
, const size_t len
)
392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
395 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
398 * Wait for stable hardware.
400 if (rt2800_wait_csr_ready(rt2x00dev
))
403 if (rt2x00_is_pci(rt2x00dev
))
404 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
407 * Disable DMA, will be reenabled later when enabling
410 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
411 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
412 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
413 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
414 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
415 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
416 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
419 * Write firmware to the device.
421 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
424 * Wait for device to stabilize.
426 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
427 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
428 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
433 if (i
== REGISTER_BUSY_COUNT
) {
434 ERROR(rt2x00dev
, "PBF system register not ready.\n");
439 * Initialize firmware.
441 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
442 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
447 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
449 void rt2800_write_tx_data(struct queue_entry
*entry
,
450 struct txentry_desc
*txdesc
)
452 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
456 * Initialize TX Info descriptor
458 rt2x00_desc_read(txwi
, 0, &word
);
459 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
460 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
461 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
462 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
463 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
464 rt2x00_set_field32(&word
, TXWI_W0_TS
,
465 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
466 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
467 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
468 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
, txdesc
->mpdu_density
);
469 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->txop
);
470 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->mcs
);
471 rt2x00_set_field32(&word
, TXWI_W0_BW
,
472 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
473 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
474 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
475 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->stbc
);
476 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
477 rt2x00_desc_write(txwi
, 0, word
);
479 rt2x00_desc_read(txwi
, 1, &word
);
480 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
481 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
482 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
483 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
484 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->ba_size
);
485 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
486 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
487 txdesc
->key_idx
: 0xff);
488 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
490 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, txdesc
->qid
);
491 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
492 rt2x00_desc_write(txwi
, 1, word
);
495 * Always write 0 to IV/EIV fields, hardware will insert the IV
496 * from the IVEIV register when TXD_W3_WIV is set to 0.
497 * When TXD_W3_WIV is set to 1 it will use the IV data
498 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
499 * crypto entry in the registers should be used to encrypt the frame.
501 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
502 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
504 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
506 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
508 int rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
509 int rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
510 int rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
516 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
517 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
518 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
519 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
520 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
521 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
523 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
524 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
525 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
526 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
527 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
531 * Convert the value from the descriptor into the RSSI value
532 * If the value in the descriptor is 0, it is considered invalid
533 * and the default (extremely low) rssi value is assumed
535 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
536 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
537 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
540 * mac80211 only accepts a single RSSI value. Calculating the
541 * average doesn't deliver a fair answer either since -60:-60 would
542 * be considered equally good as -50:-70 while the second is the one
543 * which gives less energy...
545 rssi0
= max(rssi0
, rssi1
);
546 return max(rssi0
, rssi2
);
549 void rt2800_process_rxwi(struct queue_entry
*entry
,
550 struct rxdone_entry_desc
*rxdesc
)
552 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
555 rt2x00_desc_read(rxwi
, 0, &word
);
557 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
558 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
560 rt2x00_desc_read(rxwi
, 1, &word
);
562 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
563 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
565 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
566 rxdesc
->flags
|= RX_FLAG_40MHZ
;
569 * Detect RX rate, always use MCS as signal type.
571 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
572 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
573 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
576 * Mask of 0x8 bit to remove the short preamble flag.
578 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
579 rxdesc
->signal
&= ~0x8;
581 rt2x00_desc_read(rxwi
, 2, &word
);
584 * Convert descriptor AGC value to RSSI value.
586 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
589 * Remove RXWI descriptor from start of buffer.
591 skb_pull(entry
->skb
, RXWI_DESC_SIZE
);
593 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
595 static bool rt2800_txdone_entry_check(struct queue_entry
*entry
, u32 reg
)
600 int tx_wcid
, tx_ack
, tx_pid
;
602 wcid
= rt2x00_get_field32(reg
, TX_STA_FIFO_WCID
);
603 ack
= rt2x00_get_field32(reg
, TX_STA_FIFO_TX_ACK_REQUIRED
);
604 pid
= rt2x00_get_field32(reg
, TX_STA_FIFO_PID_TYPE
);
607 * This frames has returned with an IO error,
608 * so the status report is not intended for this
611 if (test_bit(ENTRY_DATA_IO_FAILED
, &entry
->flags
)) {
612 rt2x00lib_txdone_noinfo(entry
, TXDONE_FAILURE
);
617 * Validate if this TX status report is intended for
618 * this entry by comparing the WCID/ACK/PID fields.
620 txwi
= rt2800_drv_get_txwi(entry
);
622 rt2x00_desc_read(txwi
, 1, &word
);
623 tx_wcid
= rt2x00_get_field32(word
, TXWI_W1_WIRELESS_CLI_ID
);
624 tx_ack
= rt2x00_get_field32(word
, TXWI_W1_ACK
);
625 tx_pid
= rt2x00_get_field32(word
, TXWI_W1_PACKETID
);
627 if ((wcid
!= tx_wcid
) || (ack
!= tx_ack
) || (pid
!= tx_pid
)) {
628 WARNING(entry
->queue
->rt2x00dev
,
629 "TX status report missed for queue %d entry %d\n",
630 entry
->queue
->qid
, entry
->entry_idx
);
631 rt2x00lib_txdone_noinfo(entry
, TXDONE_UNKNOWN
);
638 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
)
640 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
641 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
642 struct txdone_entry_desc txdesc
;
649 * Obtain the status about this packet.
652 txwi
= rt2800_drv_get_txwi(entry
);
653 rt2x00_desc_read(txwi
, 0, &word
);
655 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
656 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
658 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
659 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
662 * If a frame was meant to be sent as a single non-aggregated MPDU
663 * but ended up in an aggregate the used tx rate doesn't correlate
664 * with the one specified in the TXWI as the whole aggregate is sent
665 * with the same rate.
667 * For example: two frames are sent to rt2x00, the first one sets
668 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
669 * and requests MCS15. If the hw aggregates both frames into one
670 * AMDPU the tx status for both frames will contain MCS7 although
671 * the frame was sent successfully.
673 * Hence, replace the requested rate with the real tx rate to not
674 * confuse the rate control algortihm by providing clearly wrong
677 if (aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
) {
678 skbdesc
->tx_rate_idx
= real_mcs
;
683 * Ralink has a retry mechanism using a global fallback
684 * table. We setup this fallback table to try the immediate
685 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
686 * always contains the MCS used for the last transmission, be
687 * it successful or not.
689 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
691 * Transmission succeeded. The number of retries is
694 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
695 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
698 * Transmission failed. The number of retries is
699 * always 7 in this case (for a total number of 8
702 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
703 txdesc
.retry
= rt2x00dev
->long_retry
;
707 * the frame was retried at least once
708 * -> hw used fallback rates
711 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
713 rt2x00lib_txdone(entry
, &txdesc
);
715 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
717 void rt2800_txdone(struct rt2x00_dev
*rt2x00dev
)
719 struct data_queue
*queue
;
720 struct queue_entry
*entry
;
726 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727 * at most X times and also stop processing once the TX_STA_FIFO_VALID
728 * flag is not set anymore.
730 * The legacy drivers use X=TX_RING_SIZE but state in a comment
731 * that the TX_STA_FIFO stack has a size of 16. We stick to our
732 * tx ring size for now.
734 for (i
= 0; i
< rt2x00dev
->ops
->tx
->entry_num
; i
++) {
735 rt2800_register_read(rt2x00dev
, TX_STA_FIFO
, ®
);
736 if (!rt2x00_get_field32(reg
, TX_STA_FIFO_VALID
))
740 * Skip this entry when it contains an invalid
741 * queue identication number.
743 pid
= rt2x00_get_field32(reg
, TX_STA_FIFO_PID_QUEUE
);
747 queue
= rt2x00queue_get_queue(rt2x00dev
, pid
);
748 if (unlikely(!queue
))
752 * Inside each queue, we process each entry in a chronological
753 * order. We first check that the queue is not empty.
756 while (!rt2x00queue_empty(queue
)) {
757 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
758 if (rt2800_txdone_entry_check(entry
, reg
))
762 if (!entry
|| rt2x00queue_empty(queue
))
765 rt2800_txdone_entry(entry
, reg
);
768 EXPORT_SYMBOL_GPL(rt2800_txdone
);
770 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
772 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
773 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
774 unsigned int beacon_base
;
778 * Disable beaconing while we are reloading the beacon data,
779 * otherwise we might be sending out invalid data.
781 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
782 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
783 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
786 * Add space for the TXWI in front of the skb.
788 skb_push(entry
->skb
, TXWI_DESC_SIZE
);
789 memset(entry
->skb
, 0, TXWI_DESC_SIZE
);
792 * Register descriptor details in skb frame descriptor.
794 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
795 skbdesc
->desc
= entry
->skb
->data
;
796 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
799 * Add the TXWI for the beacon to the skb.
801 rt2800_write_tx_data(entry
, txdesc
);
804 * Dump beacon to userspace through debugfs.
806 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
809 * Write entire beacon with TXWI to register.
811 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
812 rt2800_register_multiwrite(rt2x00dev
, beacon_base
,
813 entry
->skb
->data
, entry
->skb
->len
);
816 * Enable beaconing again.
818 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
819 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 1);
820 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
821 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
824 * Clean up beacon skb.
826 dev_kfree_skb_any(entry
->skb
);
829 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
831 static void inline rt2800_clear_beacon(struct rt2x00_dev
*rt2x00dev
,
832 unsigned int beacon_base
)
837 * For the Beacon base registers we only need to clear
838 * the whole TXWI which (when set to 0) will invalidate
841 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
842 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
845 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
846 const struct rt2x00debug rt2800_rt2x00debug
= {
847 .owner
= THIS_MODULE
,
849 .read
= rt2800_register_read
,
850 .write
= rt2800_register_write
,
851 .flags
= RT2X00DEBUGFS_OFFSET
,
852 .word_base
= CSR_REG_BASE
,
853 .word_size
= sizeof(u32
),
854 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
857 .read
= rt2x00_eeprom_read
,
858 .write
= rt2x00_eeprom_write
,
859 .word_base
= EEPROM_BASE
,
860 .word_size
= sizeof(u16
),
861 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
864 .read
= rt2800_bbp_read
,
865 .write
= rt2800_bbp_write
,
866 .word_base
= BBP_BASE
,
867 .word_size
= sizeof(u8
),
868 .word_count
= BBP_SIZE
/ sizeof(u8
),
871 .read
= rt2x00_rf_read
,
872 .write
= rt2800_rf_write
,
873 .word_base
= RF_BASE
,
874 .word_size
= sizeof(u32
),
875 .word_count
= RF_SIZE
/ sizeof(u32
),
878 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
879 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
881 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
885 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
886 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
888 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
890 #ifdef CONFIG_RT2X00_LIB_LEDS
891 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
892 enum led_brightness brightness
)
894 struct rt2x00_led
*led
=
895 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
896 unsigned int enabled
= brightness
!= LED_OFF
;
897 unsigned int bg_mode
=
898 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
899 unsigned int polarity
=
900 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
901 EEPROM_FREQ_LED_POLARITY
);
902 unsigned int ledmode
=
903 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
904 EEPROM_FREQ_LED_MODE
);
906 if (led
->type
== LED_TYPE_RADIO
) {
907 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
909 } else if (led
->type
== LED_TYPE_ASSOC
) {
910 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
911 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
912 } else if (led
->type
== LED_TYPE_QUALITY
) {
914 * The brightness is divided into 6 levels (0 - 5),
915 * The specs tell us the following levels:
917 * to determine the level in a simple way we can simply
918 * work with bitshifting:
921 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
922 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
927 static int rt2800_blink_set(struct led_classdev
*led_cdev
,
928 unsigned long *delay_on
, unsigned long *delay_off
)
930 struct rt2x00_led
*led
=
931 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
934 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
935 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, *delay_on
);
936 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, *delay_off
);
937 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
942 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
943 struct rt2x00_led
*led
, enum led_type type
)
945 led
->rt2x00dev
= rt2x00dev
;
947 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
948 led
->led_dev
.blink_set
= rt2800_blink_set
;
949 led
->flags
= LED_INITIALIZED
;
951 #endif /* CONFIG_RT2X00_LIB_LEDS */
954 * Configuration handlers.
956 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
957 struct rt2x00lib_crypto
*crypto
,
958 struct ieee80211_key_conf
*key
)
960 struct mac_wcid_entry wcid_entry
;
961 struct mac_iveiv_entry iveiv_entry
;
965 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
967 if (crypto
->cmd
== SET_KEY
) {
968 rt2800_register_read(rt2x00dev
, offset
, ®
);
969 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
970 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
972 * Both the cipher as the BSS Idx numbers are split in a main
973 * value of 3 bits, and a extended field for adding one additional
976 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
977 (crypto
->cipher
& 0x7));
978 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
979 (crypto
->cipher
& 0x8) >> 3);
980 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
981 (crypto
->bssidx
& 0x7));
982 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
983 (crypto
->bssidx
& 0x8) >> 3);
984 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
985 rt2800_register_write(rt2x00dev
, offset
, reg
);
987 rt2800_register_write(rt2x00dev
, offset
, 0);
990 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
992 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
993 if ((crypto
->cipher
== CIPHER_TKIP
) ||
994 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
995 (crypto
->cipher
== CIPHER_AES
))
996 iveiv_entry
.iv
[3] |= 0x20;
997 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
998 rt2800_register_multiwrite(rt2x00dev
, offset
,
999 &iveiv_entry
, sizeof(iveiv_entry
));
1001 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
1003 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
1004 if (crypto
->cmd
== SET_KEY
)
1005 memcpy(&wcid_entry
, crypto
->address
, ETH_ALEN
);
1006 rt2800_register_multiwrite(rt2x00dev
, offset
,
1007 &wcid_entry
, sizeof(wcid_entry
));
1010 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1011 struct rt2x00lib_crypto
*crypto
,
1012 struct ieee80211_key_conf
*key
)
1014 struct hw_key_entry key_entry
;
1015 struct rt2x00_field32 field
;
1019 if (crypto
->cmd
== SET_KEY
) {
1020 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1022 memcpy(key_entry
.key
, crypto
->key
,
1023 sizeof(key_entry
.key
));
1024 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1025 sizeof(key_entry
.tx_mic
));
1026 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1027 sizeof(key_entry
.rx_mic
));
1029 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1030 rt2800_register_multiwrite(rt2x00dev
, offset
,
1031 &key_entry
, sizeof(key_entry
));
1035 * The cipher types are stored over multiple registers
1036 * starting with SHARED_KEY_MODE_BASE each word will have
1037 * 32 bits and contains the cipher types for 2 bssidx each.
1038 * Using the correct defines correctly will cause overhead,
1039 * so just calculate the correct offset.
1041 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1042 field
.bit_mask
= 0x7 << field
.bit_offset
;
1044 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1046 rt2800_register_read(rt2x00dev
, offset
, ®
);
1047 rt2x00_set_field32(®
, field
,
1048 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1049 rt2800_register_write(rt2x00dev
, offset
, reg
);
1052 * Update WCID information
1054 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1058 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1060 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1061 struct rt2x00lib_crypto
*crypto
,
1062 struct ieee80211_key_conf
*key
)
1064 struct hw_key_entry key_entry
;
1067 if (crypto
->cmd
== SET_KEY
) {
1069 * 1 pairwise key is possible per AID, this means that the AID
1070 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1071 * last possible shared key entry.
1073 * Since parts of the pairwise key table might be shared with
1074 * the beacon frame buffers 6 & 7 we should only write into the
1075 * first 222 entries.
1077 if (crypto
->aid
> (222 - 32))
1080 key
->hw_key_idx
= 32 + crypto
->aid
;
1082 memcpy(key_entry
.key
, crypto
->key
,
1083 sizeof(key_entry
.key
));
1084 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1085 sizeof(key_entry
.tx_mic
));
1086 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1087 sizeof(key_entry
.rx_mic
));
1089 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1090 rt2800_register_multiwrite(rt2x00dev
, offset
,
1091 &key_entry
, sizeof(key_entry
));
1095 * Update WCID information
1097 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1101 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1103 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1104 const unsigned int filter_flags
)
1109 * Start configuration steps.
1110 * Note that the version error will always be dropped
1111 * and broadcast frames will always be accepted since
1112 * there is no filter for it at this time.
1114 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1115 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1116 !(filter_flags
& FIF_FCSFAIL
));
1117 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1118 !(filter_flags
& FIF_PLCPFAIL
));
1119 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1120 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1121 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1122 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1123 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1124 !(filter_flags
& FIF_ALLMULTI
));
1125 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1126 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1127 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1128 !(filter_flags
& FIF_CONTROL
));
1129 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1130 !(filter_flags
& FIF_CONTROL
));
1131 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1132 !(filter_flags
& FIF_CONTROL
));
1133 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1134 !(filter_flags
& FIF_CONTROL
));
1135 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1136 !(filter_flags
& FIF_CONTROL
));
1137 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1138 !(filter_flags
& FIF_PSPOLL
));
1139 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
1140 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
1141 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1142 !(filter_flags
& FIF_CONTROL
));
1143 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1145 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1147 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1148 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1152 if (flags
& CONFIG_UPDATE_TYPE
) {
1154 * Clear current synchronisation setup.
1156 rt2800_clear_beacon(rt2x00dev
,
1157 HW_BEACON_OFFSET(intf
->beacon
->entry_idx
));
1159 * Enable synchronisation.
1161 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1162 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
1163 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1164 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
,
1165 (conf
->sync
== TSF_SYNC_ADHOC
||
1166 conf
->sync
== TSF_SYNC_AP_NONE
));
1167 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1170 * Enable pre tbtt interrupt for beaconing modes
1172 rt2800_register_read(rt2x00dev
, INT_TIMER_EN
, ®
);
1173 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
,
1174 (conf
->sync
== TSF_SYNC_AP_NONE
));
1175 rt2800_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
1179 if (flags
& CONFIG_UPDATE_MAC
) {
1180 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1181 reg
= le32_to_cpu(conf
->mac
[1]);
1182 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1183 conf
->mac
[1] = cpu_to_le32(reg
);
1186 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1187 conf
->mac
, sizeof(conf
->mac
));
1190 if (flags
& CONFIG_UPDATE_BSSID
) {
1191 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1192 reg
= le32_to_cpu(conf
->bssid
[1]);
1193 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1194 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1195 conf
->bssid
[1] = cpu_to_le32(reg
);
1198 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1199 conf
->bssid
, sizeof(conf
->bssid
));
1202 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1204 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1205 struct rt2x00lib_erp
*erp
)
1207 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1208 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1209 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1210 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1211 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1214 /* default protection rate for HT20: OFDM 24M */
1215 mm20_rate
= gf20_rate
= 0x4004;
1217 /* default protection rate for HT40: duplicate OFDM 24M */
1218 mm40_rate
= gf40_rate
= 0x4084;
1220 switch (protection
) {
1221 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1223 * All STAs in this BSS are HT20/40 but there might be
1224 * STAs not supporting greenfield mode.
1225 * => Disable protection for HT transmissions.
1227 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1230 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1232 * All STAs in this BSS are HT20 or HT20/40 but there
1233 * might be STAs not supporting greenfield mode.
1234 * => Protect all HT40 transmissions.
1236 mm20_mode
= gf20_mode
= 0;
1237 mm40_mode
= gf40_mode
= 2;
1240 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1242 * Nonmember protection:
1243 * According to 802.11n we _should_ protect all
1244 * HT transmissions (but we don't have to).
1246 * But if cts_protection is enabled we _shall_ protect
1247 * all HT transmissions using a CCK rate.
1249 * And if any station is non GF we _shall_ protect
1252 * We decide to protect everything
1253 * -> fall through to mixed mode.
1255 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1257 * Legacy STAs are present
1258 * => Protect all HT transmissions.
1260 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1263 * If erp protection is needed we have to protect HT
1264 * transmissions with CCK 11M long preamble.
1266 if (erp
->cts_protection
) {
1267 /* don't duplicate RTS/CTS in CCK mode */
1268 mm20_rate
= mm40_rate
= 0x0003;
1269 gf20_rate
= gf40_rate
= 0x0003;
1274 /* check for STAs not supporting greenfield mode */
1276 gf20_mode
= gf40_mode
= 2;
1278 /* Update HT protection config */
1279 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1280 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1281 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1282 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1284 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1285 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1286 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1287 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1289 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1290 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1291 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1292 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1294 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1295 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1296 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1297 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1300 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1305 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1306 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1307 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1308 !!erp
->short_preamble
);
1309 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1310 !!erp
->short_preamble
);
1311 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1314 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1315 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1316 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1317 erp
->cts_protection
? 2 : 0);
1318 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1321 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1322 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1324 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1327 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1328 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1329 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1331 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1333 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1334 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1335 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1338 if (changed
& BSS_CHANGED_BEACON_INT
) {
1339 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1340 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1341 erp
->beacon_int
* 16);
1342 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1345 if (changed
& BSS_CHANGED_HT
)
1346 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1348 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1350 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1355 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1356 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1359 * Configure the TX antenna.
1361 switch ((int)ant
->tx
) {
1363 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1366 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1369 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1374 * Configure the RX antenna.
1376 switch ((int)ant
->rx
) {
1378 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1381 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1384 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1388 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1389 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1391 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1393 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1394 struct rt2x00lib_conf
*libconf
)
1399 if (libconf
->rf
.channel
<= 14) {
1400 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1401 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1402 } else if (libconf
->rf
.channel
<= 64) {
1403 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1404 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1405 } else if (libconf
->rf
.channel
<= 128) {
1406 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1407 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1409 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1410 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1413 rt2x00dev
->lna_gain
= lna_gain
;
1416 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1417 struct ieee80211_conf
*conf
,
1418 struct rf_channel
*rf
,
1419 struct channel_info
*info
)
1421 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1423 if (rt2x00dev
->default_ant
.tx
== 1)
1424 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1426 if (rt2x00dev
->default_ant
.rx
== 1) {
1427 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1428 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1429 } else if (rt2x00dev
->default_ant
.rx
== 2)
1430 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1432 if (rf
->channel
> 14) {
1434 * When TX power is below 0, we should increase it by 7 to
1435 * make it a positive value (Minumum value is -7).
1436 * However this means that values between 0 and 7 have
1437 * double meaning, and we should set a 7DBm boost flag.
1439 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1440 (info
->default_power1
>= 0));
1442 if (info
->default_power1
< 0)
1443 info
->default_power1
+= 7;
1445 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1447 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1448 (info
->default_power2
>= 0));
1450 if (info
->default_power2
< 0)
1451 info
->default_power2
+= 7;
1453 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1455 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1456 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1459 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1461 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1462 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1463 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1464 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1468 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1469 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1470 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1471 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1475 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1476 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1477 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1478 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1481 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1482 struct ieee80211_conf
*conf
,
1483 struct rf_channel
*rf
,
1484 struct channel_info
*info
)
1488 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1489 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1491 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1492 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1493 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1495 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1496 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1497 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1499 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1500 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1501 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1503 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1504 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1505 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1507 rt2800_rfcsr_write(rt2x00dev
, 24,
1508 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1510 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1511 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1512 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1515 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
1516 struct ieee80211_conf
*conf
,
1517 struct rf_channel
*rf
,
1518 struct channel_info
*info
)
1521 unsigned int tx_pin
;
1524 if (rf
->channel
<= 14) {
1525 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
1526 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
1528 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
1529 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
1532 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
1533 rt2x00_rf(rt2x00dev
, RF3020
) ||
1534 rt2x00_rf(rt2x00dev
, RF3021
) ||
1535 rt2x00_rf(rt2x00dev
, RF3022
) ||
1536 rt2x00_rf(rt2x00dev
, RF3052
))
1537 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
1539 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
1542 * Change BBP settings
1544 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
1545 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
1546 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
1547 rt2800_bbp_write(rt2x00dev
, 86, 0);
1549 if (rf
->channel
<= 14) {
1550 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1551 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1552 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1554 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
1555 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1558 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
1560 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
1561 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1563 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1566 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
1567 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
1568 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
1569 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
1570 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
1574 /* Turn on unused PA or LNA when not using 1T or 1R */
1575 if (rt2x00dev
->default_ant
.tx
!= 1) {
1576 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
1577 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
1580 /* Turn on unused PA or LNA when not using 1T or 1R */
1581 if (rt2x00dev
->default_ant
.rx
!= 1) {
1582 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
1583 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
1586 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
1587 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
1588 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
1589 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
1590 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, rf
->channel
<= 14);
1591 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
1593 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
1595 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1596 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
1597 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1599 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
1600 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
1601 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
1603 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1604 if (conf_is_ht40(conf
)) {
1605 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
1606 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1607 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
1609 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1610 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
1611 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
1618 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
1619 const int max_txpower
)
1622 u8 max_value
= (u8
)max_txpower
;
1630 * set to normal tx power mode: +/- 0dBm
1632 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1633 rt2x00_set_field8(&r1
, BBP1_TX_POWER
, 0);
1634 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1637 * The eeprom contains the tx power values for each rate. These
1638 * values map to 100% tx power. Each 16bit word contains four tx
1639 * power values and the order is the same as used in the TX_PWR_CFG
1642 offset
= TX_PWR_CFG_0
;
1644 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
1645 /* just to be safe */
1646 if (offset
> TX_PWR_CFG_4
)
1649 rt2800_register_read(rt2x00dev
, offset
, ®
);
1651 /* read the next four txpower values */
1652 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
1655 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1656 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1657 * TX_PWR_CFG_4: unknown */
1658 txpower
= rt2x00_get_field16(eeprom
,
1659 EEPROM_TXPOWER_BYRATE_RATE0
);
1660 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
,
1661 min(txpower
, max_value
));
1663 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1664 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1665 * TX_PWR_CFG_4: unknown */
1666 txpower
= rt2x00_get_field16(eeprom
,
1667 EEPROM_TXPOWER_BYRATE_RATE1
);
1668 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
,
1669 min(txpower
, max_value
));
1671 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1672 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1673 * TX_PWR_CFG_4: unknown */
1674 txpower
= rt2x00_get_field16(eeprom
,
1675 EEPROM_TXPOWER_BYRATE_RATE2
);
1676 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
,
1677 min(txpower
, max_value
));
1679 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1680 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1681 * TX_PWR_CFG_4: unknown */
1682 txpower
= rt2x00_get_field16(eeprom
,
1683 EEPROM_TXPOWER_BYRATE_RATE3
);
1684 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
,
1685 min(txpower
, max_value
));
1687 /* read the next four txpower values */
1688 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
1691 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1692 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1693 * TX_PWR_CFG_4: unknown */
1694 txpower
= rt2x00_get_field16(eeprom
,
1695 EEPROM_TXPOWER_BYRATE_RATE0
);
1696 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
,
1697 min(txpower
, max_value
));
1699 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1700 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1701 * TX_PWR_CFG_4: unknown */
1702 txpower
= rt2x00_get_field16(eeprom
,
1703 EEPROM_TXPOWER_BYRATE_RATE1
);
1704 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
,
1705 min(txpower
, max_value
));
1707 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1708 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1709 * TX_PWR_CFG_4: unknown */
1710 txpower
= rt2x00_get_field16(eeprom
,
1711 EEPROM_TXPOWER_BYRATE_RATE2
);
1712 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
,
1713 min(txpower
, max_value
));
1715 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1716 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1717 * TX_PWR_CFG_4: unknown */
1718 txpower
= rt2x00_get_field16(eeprom
,
1719 EEPROM_TXPOWER_BYRATE_RATE3
);
1720 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
,
1721 min(txpower
, max_value
));
1723 rt2800_register_write(rt2x00dev
, offset
, reg
);
1725 /* next TX_PWR_CFG register */
1730 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
1731 struct rt2x00lib_conf
*libconf
)
1735 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1736 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
1737 libconf
->conf
->short_frame_max_tx_count
);
1738 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
1739 libconf
->conf
->long_frame_max_tx_count
);
1740 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1743 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
1744 struct rt2x00lib_conf
*libconf
)
1746 enum dev_state state
=
1747 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
1748 STATE_SLEEP
: STATE_AWAKE
;
1751 if (state
== STATE_SLEEP
) {
1752 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
1754 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1755 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
1756 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
1757 libconf
->conf
->listen_interval
- 1);
1758 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
1759 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1761 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1763 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1764 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
1765 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
1766 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
1767 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1769 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1773 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
1774 struct rt2x00lib_conf
*libconf
,
1775 const unsigned int flags
)
1777 /* Always recalculate LNA gain before changing configuration */
1778 rt2800_config_lna_gain(rt2x00dev
, libconf
);
1780 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
1781 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
1782 &libconf
->rf
, &libconf
->channel
);
1783 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
1784 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1785 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1786 rt2800_config_retry_limit(rt2x00dev
, libconf
);
1787 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1788 rt2800_config_ps(rt2x00dev
, libconf
);
1790 EXPORT_SYMBOL_GPL(rt2800_config
);
1795 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1800 * Update FCS error count from register.
1802 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1803 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
1805 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
1807 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
1809 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
1810 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1811 rt2x00_rt(rt2x00dev
, RT3071
) ||
1812 rt2x00_rt(rt2x00dev
, RT3090
) ||
1813 rt2x00_rt(rt2x00dev
, RT3390
))
1814 return 0x1c + (2 * rt2x00dev
->lna_gain
);
1816 return 0x2e + rt2x00dev
->lna_gain
;
1819 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
1820 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
1822 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
1825 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1826 struct link_qual
*qual
, u8 vgc_level
)
1828 if (qual
->vgc_level
!= vgc_level
) {
1829 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
1830 qual
->vgc_level
= vgc_level
;
1831 qual
->vgc_level_reg
= vgc_level
;
1835 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1837 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
1839 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
1841 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
1844 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
1848 * When RSSI is better then -80 increase VGC level with 0x10
1850 rt2800_set_vgc(rt2x00dev
, qual
,
1851 rt2800_get_default_vgc(rt2x00dev
) +
1852 ((qual
->rssi
> -80) * 0x10));
1854 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
1857 * Initialization functions.
1859 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
1866 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1867 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1868 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1869 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1870 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1871 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
1872 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1874 ret
= rt2800_drv_init_registers(rt2x00dev
);
1878 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
1879 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
1880 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
1881 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
1882 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
1883 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
1885 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
1886 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
1887 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
1888 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
1889 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
1890 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
1892 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
1893 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1895 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1897 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1898 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
1899 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
1900 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
1901 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
1902 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1903 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
1904 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1906 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
1908 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1909 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
1910 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
1911 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1913 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1914 rt2x00_rt(rt2x00dev
, RT3090
) ||
1915 rt2x00_rt(rt2x00dev
, RT3390
)) {
1916 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1917 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1918 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1919 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1920 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
1921 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1922 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
1923 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1926 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1929 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1931 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1932 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1934 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1935 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1936 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
1938 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1939 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1941 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
1942 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1943 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1944 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000001f);
1946 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
1947 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1950 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
1951 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
1952 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
1953 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
1954 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
1955 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
1956 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
1957 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
1958 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
1959 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
1961 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
1962 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
1963 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
1964 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
1965 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
1967 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
1968 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
1969 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
1970 rt2x00_rt(rt2x00dev
, RT2883
) ||
1971 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
1972 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
1974 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
1975 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
1976 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
1977 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
1979 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1980 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
1981 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
1982 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
1983 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
1984 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
1985 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
1986 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
1987 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1989 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
1991 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1992 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
1993 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
1994 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
1995 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
1996 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
1997 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
1998 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2000 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
2001 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
2002 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
2003 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
2004 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
2005 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
2006 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
2007 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
2008 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
2010 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2011 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
2012 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
2013 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV
, 1);
2014 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2015 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2016 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2017 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2018 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2019 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2020 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
2021 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2023 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2024 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
2025 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
2026 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV
, 1);
2027 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2028 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2029 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2030 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2031 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2032 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2033 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
2034 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2036 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2037 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
2038 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
2039 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV
, 1);
2040 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2041 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2042 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2043 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2044 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2045 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2046 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
2047 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2049 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2050 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
2051 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
2052 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV
, 1);
2053 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2054 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2055 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2056 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2057 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2058 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2059 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
2060 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2062 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2063 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
2064 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
2065 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV
, 1);
2066 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2067 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2068 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2069 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2070 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2071 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2072 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
2073 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2075 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2076 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
2077 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
2078 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV
, 1);
2079 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2080 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2081 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2082 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2083 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2084 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2085 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
2086 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2088 if (rt2x00_is_usb(rt2x00dev
)) {
2089 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
2091 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2092 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2093 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2094 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2095 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2096 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
2097 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
2098 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
2099 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
2100 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
2101 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2105 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2106 * although it is reserved.
2108 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
2109 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
2110 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
2111 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
2112 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
2113 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
2114 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
2115 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
2116 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
2117 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
2118 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
2119 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
2121 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
2123 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2124 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
2125 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
2126 IEEE80211_MAX_RTS_THRESHOLD
);
2127 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
2128 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2130 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
2133 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2134 * time should be set to 16. However, the original Ralink driver uses
2135 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2136 * connection problems with 11g + CTS protection. Hence, use the same
2137 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2139 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
2140 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
2141 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
2142 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
2143 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
2144 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
2145 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
2147 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
2150 * ASIC will keep garbage value after boot, clear encryption keys.
2152 for (i
= 0; i
< 4; i
++)
2153 rt2800_register_write(rt2x00dev
,
2154 SHARED_KEY_MODE_ENTRY(i
), 0);
2156 for (i
= 0; i
< 256; i
++) {
2157 u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
2158 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
2159 wcid
, sizeof(wcid
));
2161 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 1);
2162 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
2168 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE0
);
2169 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE1
);
2170 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE2
);
2171 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE3
);
2172 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE4
);
2173 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE5
);
2174 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE6
);
2175 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE7
);
2177 if (rt2x00_is_usb(rt2x00dev
)) {
2178 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2179 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
2180 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2183 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
2184 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
2185 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
2186 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
2187 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
2188 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
2189 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
2190 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
2191 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
2192 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
2194 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
2195 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
2196 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
2197 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
2198 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
2199 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
2200 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
2201 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
2202 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
2203 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
2205 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
2206 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
2207 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
2208 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
2209 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
2210 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
2211 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
2212 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
2213 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
2214 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
2216 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
2217 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
2218 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
2219 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
2220 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
2221 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
2224 * Do not force the BA window size, we use the TXWI to set it
2226 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
2227 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
2228 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
2229 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
2232 * We must clear the error counters.
2233 * These registers are cleared on read,
2234 * so we may pass a useless variable to store the value.
2236 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2237 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
2238 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
2239 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
2240 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
2241 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
2244 * Setup leadtime for pre tbtt interrupt to 6ms
2246 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
2247 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
2248 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
2253 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
2258 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2259 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
2260 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
2263 udelay(REGISTER_BUSY_DELAY
);
2266 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
2270 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
2276 * BBP was enabled after firmware was loaded,
2277 * but we need to reactivate it now.
2279 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
2280 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
2283 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2284 rt2800_bbp_read(rt2x00dev
, 0, &value
);
2285 if ((value
!= 0xff) && (value
!= 0x00))
2287 udelay(REGISTER_BUSY_DELAY
);
2290 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
2294 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
2301 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
2302 rt2800_wait_bbp_ready(rt2x00dev
)))
2305 if (rt2800_is_305x_soc(rt2x00dev
))
2306 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
2308 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
2309 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
2311 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2312 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2313 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
2315 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
2316 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
2319 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2321 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2322 rt2x00_rt(rt2x00dev
, RT3071
) ||
2323 rt2x00_rt(rt2x00dev
, RT3090
) ||
2324 rt2x00_rt(rt2x00dev
, RT3390
)) {
2325 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
2326 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
2327 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
2328 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2329 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
2330 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
2332 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
2335 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2336 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
2338 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
2339 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
2341 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
2343 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
2344 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
2345 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
2347 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2348 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2349 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2350 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
2351 rt2800_is_305x_soc(rt2x00dev
))
2352 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
2354 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
2356 if (rt2800_is_305x_soc(rt2x00dev
))
2357 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
2359 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
2360 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
2362 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2363 rt2x00_rt(rt2x00dev
, RT3090
) ||
2364 rt2x00_rt(rt2x00dev
, RT3390
)) {
2365 rt2800_bbp_read(rt2x00dev
, 138, &value
);
2367 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2368 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
2370 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
2373 rt2800_bbp_write(rt2x00dev
, 138, value
);
2377 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
2378 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
2380 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
2381 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
2382 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
2383 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
2390 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
2391 bool bw40
, u8 rfcsr24
, u8 filter_target
)
2400 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
2402 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2403 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
2404 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2406 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
2407 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
2408 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
2411 * Set power & frequency of passband test tone
2413 rt2800_bbp_write(rt2x00dev
, 24, 0);
2415 for (i
= 0; i
< 100; i
++) {
2416 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
2419 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
2425 * Set power & frequency of stopband test tone
2427 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
2429 for (i
= 0; i
< 100; i
++) {
2430 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
2433 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
2435 if ((passband
- stopband
) <= filter_target
) {
2437 overtuned
+= ((passband
- stopband
) == filter_target
);
2441 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
2444 rfcsr24
-= !!overtuned
;
2446 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
2450 static int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
2457 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
2458 !rt2x00_rt(rt2x00dev
, RT3071
) &&
2459 !rt2x00_rt(rt2x00dev
, RT3090
) &&
2460 !rt2x00_rt(rt2x00dev
, RT3390
) &&
2461 !rt2800_is_305x_soc(rt2x00dev
))
2465 * Init RF calibration.
2467 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2468 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2469 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2471 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
2472 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2474 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2475 rt2x00_rt(rt2x00dev
, RT3071
) ||
2476 rt2x00_rt(rt2x00dev
, RT3090
)) {
2477 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
2478 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
2479 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
2480 rt2800_rfcsr_write(rt2x00dev
, 7, 0x70);
2481 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
2482 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
2483 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
2484 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
2485 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
2486 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
2487 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
2488 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
2489 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
2490 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
2491 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
2492 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
2493 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
2494 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2495 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
2496 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
2497 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
2498 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
2499 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
2500 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
2501 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
2502 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
2503 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
2504 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
2505 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
2506 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
2507 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
2508 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
2509 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
2510 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
2511 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
2512 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
2513 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
2514 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
2515 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
2516 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
2517 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
2518 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
2519 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
2520 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
2521 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
2522 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
2523 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
2524 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
2525 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
2526 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
2527 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
2528 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
2529 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2530 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
2531 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
2532 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
2533 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
2534 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
2535 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
2536 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
2537 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
2538 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
2539 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
2540 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
2541 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
2542 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
2543 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
2544 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
2545 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
2546 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
2547 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
2548 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
2549 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
2550 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
2551 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
2552 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
2553 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
2554 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
2555 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2556 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
2557 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
2558 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
2559 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
2560 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
2561 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
2565 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
2566 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2567 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
2568 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
2569 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2570 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2571 rt2x00_rt(rt2x00dev
, RT3090
)) {
2572 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2573 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
2574 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2576 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
2578 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2579 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
2580 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2581 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
2582 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2583 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
2584 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
2586 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
2588 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2589 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
2590 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
2591 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
2592 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
2596 * Set RX Filter calibration for 20MHz and 40MHz
2598 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
2599 rt2x00dev
->calibration
[0] =
2600 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
2601 rt2x00dev
->calibration
[1] =
2602 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
2603 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2604 rt2x00_rt(rt2x00dev
, RT3090
) ||
2605 rt2x00_rt(rt2x00dev
, RT3390
)) {
2606 rt2x00dev
->calibration
[0] =
2607 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
2608 rt2x00dev
->calibration
[1] =
2609 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
2613 * Set back to initial state
2615 rt2800_bbp_write(rt2x00dev
, 24, 0);
2617 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
2618 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
2619 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
2622 * set BBP back to BW20
2624 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2625 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
2626 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2628 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2629 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2630 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2631 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
2632 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
2634 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
2635 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
2636 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
2638 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2639 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
2640 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2641 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2642 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2643 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
2644 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
2646 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
2647 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
2648 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
2649 rt2x00_get_field16(eeprom
,
2650 EEPROM_TXMIXER_GAIN_BG_VAL
));
2651 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2653 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
2654 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
2656 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2657 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
2658 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
2659 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
2660 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
2662 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
2665 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2666 rt2x00_rt(rt2x00dev
, RT3090
) ||
2667 rt2x00_rt(rt2x00dev
, RT3390
)) {
2668 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2669 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2670 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2671 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2672 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2673 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2674 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2676 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
2677 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
2678 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
2680 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
2681 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
2682 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
2684 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
2685 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
2686 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
2689 if (rt2x00_rt(rt2x00dev
, RT3070
) || rt2x00_rt(rt2x00dev
, RT3071
)) {
2690 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
2691 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2692 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
))
2693 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
2695 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
2696 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
2697 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
2698 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
2699 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
2705 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
2711 * Initialize all registers.
2713 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
2714 rt2800_init_registers(rt2x00dev
) ||
2715 rt2800_init_bbp(rt2x00dev
) ||
2716 rt2800_init_rfcsr(rt2x00dev
)))
2720 * Send signal to firmware during boot time.
2722 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
2724 if (rt2x00_is_usb(rt2x00dev
) &&
2725 (rt2x00_rt(rt2x00dev
, RT3070
) ||
2726 rt2x00_rt(rt2x00dev
, RT3071
) ||
2727 rt2x00_rt(rt2x00dev
, RT3572
))) {
2729 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
2736 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
2737 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
2738 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
2739 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
2743 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2744 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
2745 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
2746 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
2747 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
2748 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2750 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
2751 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
2752 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
2753 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
2756 * Initialize LED control
2758 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED1
, &word
);
2759 rt2800_mcu_request(rt2x00dev
, MCU_LED_1
, 0xff,
2760 word
& 0xff, (word
>> 8) & 0xff);
2762 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED2
, &word
);
2763 rt2800_mcu_request(rt2x00dev
, MCU_LED_2
, 0xff,
2764 word
& 0xff, (word
>> 8) & 0xff);
2766 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED3
, &word
);
2767 rt2800_mcu_request(rt2x00dev
, MCU_LED_3
, 0xff,
2768 word
& 0xff, (word
>> 8) & 0xff);
2772 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
2774 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
2778 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2779 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2780 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2781 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2782 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2783 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
2784 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2786 /* Wait for DMA, ignore error */
2787 rt2800_wait_wpdma_ready(rt2x00dev
);
2789 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
2790 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
2791 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
2792 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
2794 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0);
2795 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, 0);
2797 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
2799 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
2803 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
2805 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
2807 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
2809 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
2813 mutex_lock(&rt2x00dev
->csr_mutex
);
2815 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
2816 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
2817 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
2818 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
2819 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
2821 /* Wait until the EEPROM has been loaded */
2822 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
2824 /* Apparently the data is read from end to start */
2825 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
2826 (u32
*)&rt2x00dev
->eeprom
[i
]);
2827 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
2828 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
2829 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
2830 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
2831 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
2832 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
2834 mutex_unlock(&rt2x00dev
->csr_mutex
);
2837 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
2841 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
2842 rt2800_efuse_read(rt2x00dev
, i
);
2844 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
2846 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2850 u8 default_lna_gain
;
2853 * Start validation of the data that has been read.
2855 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2856 if (!is_valid_ether_addr(mac
)) {
2857 random_ether_addr(mac
);
2858 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2861 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2862 if (word
== 0xffff) {
2863 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2864 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TXPATH
, 1);
2865 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2820
);
2866 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2867 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2868 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
2869 rt2x00_rt(rt2x00dev
, RT2872
)) {
2871 * There is a max of 2 RX streams for RT28x0 series
2873 if (rt2x00_get_field16(word
, EEPROM_ANTENNA_RXPATH
) > 2)
2874 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2875 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2878 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2879 if (word
== 0xffff) {
2880 rt2x00_set_field16(&word
, EEPROM_NIC_HW_RADIO
, 0);
2881 rt2x00_set_field16(&word
, EEPROM_NIC_DYNAMIC_TX_AGC
, 0);
2882 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2883 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2884 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2885 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_BG
, 0);
2886 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_A
, 0);
2887 rt2x00_set_field16(&word
, EEPROM_NIC_WPS_PBC
, 0);
2888 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_BG
, 0);
2889 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_A
, 0);
2890 rt2x00_set_field16(&word
, EEPROM_NIC_ANT_DIVERSITY
, 0);
2891 rt2x00_set_field16(&word
, EEPROM_NIC_DAC_TEST
, 0);
2892 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2893 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2896 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2897 if ((word
& 0x00ff) == 0x00ff) {
2898 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2899 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2900 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2902 if ((word
& 0xff00) == 0xff00) {
2903 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
2904 LED_MODE_TXRX_ACTIVITY
);
2905 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
2906 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2907 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED1
, 0x5555);
2908 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED2
, 0x2221);
2909 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED3
, 0xa9f8);
2910 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
2914 * During the LNA validation we are going to use
2915 * lna0 as correct value. Note that EEPROM_LNA
2916 * is never validated.
2918 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
2919 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
2921 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
2922 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
2923 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
2924 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
2925 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
2926 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
2928 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
2929 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
2930 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
2931 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
2932 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
2933 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
2935 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
2937 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
2938 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
2939 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
2940 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
2941 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
2942 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
2944 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
2945 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
2946 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
2947 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
2948 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
2949 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
2951 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
2953 rt2x00_eeprom_read(rt2x00dev
, EEPROM_MAX_TX_POWER
, &word
);
2954 if (rt2x00_get_field16(word
, EEPROM_MAX_TX_POWER_24GHZ
) == 0xff)
2955 rt2x00_set_field16(&word
, EEPROM_MAX_TX_POWER_24GHZ
, MAX_G_TXPOWER
);
2956 if (rt2x00_get_field16(word
, EEPROM_MAX_TX_POWER_5GHZ
) == 0xff)
2957 rt2x00_set_field16(&word
, EEPROM_MAX_TX_POWER_5GHZ
, MAX_A_TXPOWER
);
2958 rt2x00_eeprom_write(rt2x00dev
, EEPROM_MAX_TX_POWER
, word
);
2962 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
2964 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2971 * Read EEPROM word for configuration.
2973 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2976 * Identify RF chipset.
2978 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2979 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2981 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2982 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2984 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
2985 !rt2x00_rt(rt2x00dev
, RT2872
) &&
2986 !rt2x00_rt(rt2x00dev
, RT2883
) &&
2987 !rt2x00_rt(rt2x00dev
, RT3070
) &&
2988 !rt2x00_rt(rt2x00dev
, RT3071
) &&
2989 !rt2x00_rt(rt2x00dev
, RT3090
) &&
2990 !rt2x00_rt(rt2x00dev
, RT3390
) &&
2991 !rt2x00_rt(rt2x00dev
, RT3572
)) {
2992 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
2996 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
2997 !rt2x00_rf(rt2x00dev
, RF2850
) &&
2998 !rt2x00_rf(rt2x00dev
, RF2720
) &&
2999 !rt2x00_rf(rt2x00dev
, RF2750
) &&
3000 !rt2x00_rf(rt2x00dev
, RF3020
) &&
3001 !rt2x00_rf(rt2x00dev
, RF2020
) &&
3002 !rt2x00_rf(rt2x00dev
, RF3021
) &&
3003 !rt2x00_rf(rt2x00dev
, RF3022
) &&
3004 !rt2x00_rf(rt2x00dev
, RF3052
)) {
3005 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
3010 * Identify default antenna configuration.
3012 rt2x00dev
->default_ant
.tx
=
3013 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
);
3014 rt2x00dev
->default_ant
.rx
=
3015 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
);
3018 * Read frequency offset and RF programming sequence.
3020 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
3021 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
3024 * Read external LNA informations.
3026 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
3028 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
3029 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
3030 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
3031 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
3034 * Detect if this device has an hardware controlled radio.
3036 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_HW_RADIO
))
3037 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
3040 * Store led settings, for correct led behaviour.
3042 #ifdef CONFIG_RT2X00_LIB_LEDS
3043 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
3044 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
3045 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
3047 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &rt2x00dev
->led_mcu_reg
);
3048 #endif /* CONFIG_RT2X00_LIB_LEDS */
3052 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
3055 * RF value list for rt28xx
3056 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3058 static const struct rf_channel rf_vals
[] = {
3059 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3060 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3061 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3062 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3063 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3064 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3065 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3066 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3067 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3068 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3069 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3070 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3071 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3072 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3074 /* 802.11 UNI / HyperLan 2 */
3075 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3076 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3077 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3078 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3079 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3080 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3081 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3082 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3083 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3084 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3085 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3086 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3088 /* 802.11 HyperLan 2 */
3089 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3090 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3091 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3092 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3093 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3094 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3095 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3096 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3097 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3098 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3099 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3100 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3101 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3102 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3103 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3104 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3107 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3108 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3109 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3110 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3111 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3112 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3113 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3114 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3115 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3116 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3117 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3120 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3121 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3122 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3123 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3124 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3125 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3126 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3130 * RF value list for rt3xxx
3131 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3133 static const struct rf_channel rf_vals_3x
[] = {
3149 /* 802.11 UNI / HyperLan 2 */
3163 /* 802.11 HyperLan 2 */
3195 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
3197 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
3198 struct channel_info
*info
;
3199 char *default_power1
;
3200 char *default_power2
;
3202 unsigned short max_power
;
3206 * Disable powersaving as default on PCI devices.
3208 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
3209 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
3212 * Initialize all hw fields.
3214 rt2x00dev
->hw
->flags
=
3215 IEEE80211_HW_SIGNAL_DBM
|
3216 IEEE80211_HW_SUPPORTS_PS
|
3217 IEEE80211_HW_PS_NULLFUNC_STACK
|
3218 IEEE80211_HW_AMPDU_AGGREGATION
;
3220 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3221 * unless we are capable of sending the buffered frames out after the
3222 * DTIM transmission using rt2x00lib_beacondone. This will send out
3223 * multicast and broadcast traffic immediately instead of buffering it
3224 * infinitly and thus dropping it after some time.
3226 if (!rt2x00_is_usb(rt2x00dev
))
3227 rt2x00dev
->hw
->flags
|=
3228 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
3230 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
3231 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
3232 rt2x00_eeprom_addr(rt2x00dev
,
3233 EEPROM_MAC_ADDR_0
));
3236 * As rt2800 has a global fallback table we cannot specify
3237 * more then one tx rate per frame but since the hw will
3238 * try several rates (based on the fallback table) we should
3239 * initialize max_report_rates to the maximum number of rates
3240 * we are going to try. Otherwise mac80211 will truncate our
3241 * reported tx rates and the rc algortihm will end up with
3244 rt2x00dev
->hw
->max_rates
= 1;
3245 rt2x00dev
->hw
->max_report_rates
= 7;
3246 rt2x00dev
->hw
->max_rate_tries
= 1;
3248 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
3251 * Initialize hw_mode information.
3253 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
3254 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
3256 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
3257 rt2x00_rf(rt2x00dev
, RF2720
)) {
3258 spec
->num_channels
= 14;
3259 spec
->channels
= rf_vals
;
3260 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
3261 rt2x00_rf(rt2x00dev
, RF2750
)) {
3262 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
3263 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
3264 spec
->channels
= rf_vals
;
3265 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
3266 rt2x00_rf(rt2x00dev
, RF2020
) ||
3267 rt2x00_rf(rt2x00dev
, RF3021
) ||
3268 rt2x00_rf(rt2x00dev
, RF3022
)) {
3269 spec
->num_channels
= 14;
3270 spec
->channels
= rf_vals_3x
;
3271 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
3272 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
3273 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
3274 spec
->channels
= rf_vals_3x
;
3278 * Initialize HT information.
3280 if (!rt2x00_rf(rt2x00dev
, RF2020
))
3281 spec
->ht
.ht_supported
= true;
3283 spec
->ht
.ht_supported
= false;
3286 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
3287 IEEE80211_HT_CAP_GRN_FLD
|
3288 IEEE80211_HT_CAP_SGI_20
|
3289 IEEE80211_HT_CAP_SGI_40
;
3291 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) >= 2)
3292 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
3295 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) <<
3296 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
3298 spec
->ht
.ampdu_factor
= 3;
3299 spec
->ht
.ampdu_density
= 4;
3300 spec
->ht
.mcs
.tx_params
=
3301 IEEE80211_HT_MCS_TX_DEFINED
|
3302 IEEE80211_HT_MCS_TX_RX_DIFF
|
3303 ((rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) - 1) <<
3304 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
3306 switch (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
)) {
3308 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
3310 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
3312 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
3313 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
3318 * Create channel information array
3320 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
3324 spec
->channels_info
= info
;
3326 rt2x00_eeprom_read(rt2x00dev
, EEPROM_MAX_TX_POWER
, &eeprom
);
3327 max_power
= rt2x00_get_field16(eeprom
, EEPROM_MAX_TX_POWER_24GHZ
);
3328 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
3329 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
3331 for (i
= 0; i
< 14; i
++) {
3332 info
[i
].max_power
= max_power
;
3333 info
[i
].default_power1
= TXPOWER_G_FROM_DEV(default_power1
[i
]);
3334 info
[i
].default_power2
= TXPOWER_G_FROM_DEV(default_power2
[i
]);
3337 if (spec
->num_channels
> 14) {
3338 max_power
= rt2x00_get_field16(eeprom
, EEPROM_MAX_TX_POWER_5GHZ
);
3339 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
3340 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
3342 for (i
= 14; i
< spec
->num_channels
; i
++) {
3343 info
[i
].max_power
= max_power
;
3344 info
[i
].default_power1
= TXPOWER_A_FROM_DEV(default_power1
[i
]);
3345 info
[i
].default_power2
= TXPOWER_A_FROM_DEV(default_power2
[i
]);
3351 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
3354 * IEEE80211 stack callback functions.
3356 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
3359 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3360 struct mac_iveiv_entry iveiv_entry
;
3363 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
3364 rt2800_register_multiread(rt2x00dev
, offset
,
3365 &iveiv_entry
, sizeof(iveiv_entry
));
3367 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
3368 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
3370 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
3372 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
3374 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3376 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
3378 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
3379 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
3380 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
3382 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
3383 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
3384 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
3386 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
3387 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
3388 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
3390 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
3391 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
3392 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
3394 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
3395 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
3396 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
3398 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
3399 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
3400 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
3402 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
3403 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
3404 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
3408 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
3410 int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
3411 const struct ieee80211_tx_queue_params
*params
)
3413 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3414 struct data_queue
*queue
;
3415 struct rt2x00_field32 field
;
3421 * First pass the configuration through rt2x00lib, that will
3422 * update the queue settings and validate the input. After that
3423 * we are free to update the registers based on the value
3424 * in the queue parameter.
3426 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
3431 * We only need to perform additional register initialization
3437 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
3439 /* Update WMM TXOP register */
3440 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
3441 field
.bit_offset
= (queue_idx
& 1) * 16;
3442 field
.bit_mask
= 0xffff << field
.bit_offset
;
3444 rt2800_register_read(rt2x00dev
, offset
, ®
);
3445 rt2x00_set_field32(®
, field
, queue
->txop
);
3446 rt2800_register_write(rt2x00dev
, offset
, reg
);
3448 /* Update WMM registers */
3449 field
.bit_offset
= queue_idx
* 4;
3450 field
.bit_mask
= 0xf << field
.bit_offset
;
3452 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
3453 rt2x00_set_field32(®
, field
, queue
->aifs
);
3454 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
3456 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
3457 rt2x00_set_field32(®
, field
, queue
->cw_min
);
3458 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
3460 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
3461 rt2x00_set_field32(®
, field
, queue
->cw_max
);
3462 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
3464 /* Update EDCA registers */
3465 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
3467 rt2800_register_read(rt2x00dev
, offset
, ®
);
3468 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
3469 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
3470 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
3471 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
3472 rt2800_register_write(rt2x00dev
, offset
, reg
);
3476 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
3478 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
3480 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3484 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
3485 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
3486 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
3487 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
3491 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
3493 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
3494 enum ieee80211_ampdu_mlme_action action
,
3495 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
)
3500 case IEEE80211_AMPDU_RX_START
:
3501 case IEEE80211_AMPDU_RX_STOP
:
3503 * The hw itself takes care of setting up BlockAck mechanisms.
3504 * So, we only have to allow mac80211 to nagotiate a BlockAck
3505 * agreement. Once that is done, the hw will BlockAck incoming
3506 * AMPDUs without further setup.
3509 case IEEE80211_AMPDU_TX_START
:
3510 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
3512 case IEEE80211_AMPDU_TX_STOP
:
3513 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
3515 case IEEE80211_AMPDU_TX_OPERATIONAL
:
3518 WARNING((struct rt2x00_dev
*)hw
->priv
, "Unknown AMPDU action\n");
3523 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
3525 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
3526 MODULE_VERSION(DRV_VERSION
);
3527 MODULE_DESCRIPTION("Ralink RT2800 library");
3528 MODULE_LICENSE("GPL");