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rt2800: add write_with_rx_chain function
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
225 {
226 u32 reg;
227 int i, count;
228
229 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
230 if (rt2x00_get_field32(reg, WLAN_EN))
231 return 0;
232
233 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
234 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
235 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
236 rt2x00_set_field32(&reg, WLAN_EN, 1);
237 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
238
239 udelay(REGISTER_BUSY_DELAY);
240
241 count = 0;
242 do {
243 /*
244 * Check PLL_LD & XTAL_RDY.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
247 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
248 if (rt2x00_get_field32(reg, PLL_LD) &&
249 rt2x00_get_field32(reg, XTAL_RDY))
250 break;
251 udelay(REGISTER_BUSY_DELAY);
252 }
253
254 if (i >= REGISTER_BUSY_COUNT) {
255
256 if (count >= 10)
257 return -EIO;
258
259 rt2800_register_write(rt2x00dev, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY);
261 rt2800_register_write(rt2x00dev, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY);
263 rt2800_register_write(rt2x00dev, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY);
265 count++;
266 } else {
267 count = 0;
268 }
269
270 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
271 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
272 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
273 rt2x00_set_field32(&reg, WLAN_RESET, 1);
274 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
275 udelay(10);
276 rt2x00_set_field32(&reg, WLAN_RESET, 0);
277 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
278 udelay(10);
279 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
280 } while (count != 0);
281
282 return 0;
283 }
284
285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
286 const u8 command, const u8 token,
287 const u8 arg0, const u8 arg1)
288 {
289 u32 reg;
290
291 /*
292 * SOC devices don't support MCU requests.
293 */
294 if (rt2x00_is_soc(rt2x00dev))
295 return;
296
297 mutex_lock(&rt2x00dev->csr_mutex);
298
299 /*
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
302 */
303 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
304 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
305 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
306 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
307 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
308 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
309
310 reg = 0;
311 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
312 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
313 }
314
315 mutex_unlock(&rt2x00dev->csr_mutex);
316 }
317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
318
319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
320 {
321 unsigned int i = 0;
322 u32 reg;
323
324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
325 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
326 if (reg && reg != ~0)
327 return 0;
328 msleep(1);
329 }
330
331 ERROR(rt2x00dev, "Unstable hardware.\n");
332 return -EBUSY;
333 }
334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
335
336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
337 {
338 unsigned int i;
339 u32 reg;
340
341 /*
342 * Some devices are really slow to respond here. Wait a whole second
343 * before timing out.
344 */
345 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
346 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
347 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
348 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
349 return 0;
350
351 msleep(10);
352 }
353
354 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
355 return -EACCES;
356 }
357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
358
359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
360 {
361 u32 reg;
362
363 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
364 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
365 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
370 }
371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
372
373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
374 {
375 u16 fw_crc;
376 u16 crc;
377
378 /*
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
381 * algorithm.
382 */
383 fw_crc = (data[len - 2] << 8 | data[len - 1]);
384
385 /*
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
391 */
392 crc = crc_ccitt(~0, data, len - 2);
393
394 /*
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
398 * value.
399 */
400 crc = swab16(crc);
401
402 return fw_crc == crc;
403 }
404
405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
406 const u8 *data, const size_t len)
407 {
408 size_t offset = 0;
409 size_t fw_len;
410 bool multiple;
411
412 /*
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
420 */
421 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
422 fw_len = 4096;
423 else
424 fw_len = 8192;
425
426 multiple = true;
427 /*
428 * Validate the firmware length
429 */
430 if (len != fw_len && (!multiple || (len % fw_len) != 0))
431 return FW_BAD_LENGTH;
432
433 /*
434 * Check if the chipset requires one of the upper parts
435 * of the firmware.
436 */
437 if (rt2x00_is_usb(rt2x00dev) &&
438 !rt2x00_rt(rt2x00dev, RT2860) &&
439 !rt2x00_rt(rt2x00dev, RT2872) &&
440 !rt2x00_rt(rt2x00dev, RT3070) &&
441 ((len / fw_len) == 1))
442 return FW_BAD_VERSION;
443
444 /*
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
447 */
448 while (offset < len) {
449 if (!rt2800_check_firmware_crc(data + offset, fw_len))
450 return FW_BAD_CRC;
451
452 offset += fw_len;
453 }
454
455 return FW_OK;
456 }
457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
458
459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
460 const u8 *data, const size_t len)
461 {
462 unsigned int i;
463 u32 reg;
464 int retval;
465
466 if (rt2x00_rt(rt2x00dev, RT3290)) {
467 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
468 if (retval)
469 return -EBUSY;
470 }
471
472 /*
473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
475 */
476 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
477
478 /*
479 * Wait for stable hardware.
480 */
481 if (rt2800_wait_csr_ready(rt2x00dev))
482 return -EBUSY;
483
484 if (rt2x00_is_pci(rt2x00dev)) {
485 if (rt2x00_rt(rt2x00dev, RT3290) ||
486 rt2x00_rt(rt2x00dev, RT3572) ||
487 rt2x00_rt(rt2x00dev, RT5390) ||
488 rt2x00_rt(rt2x00dev, RT5392)) {
489 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
490 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
491 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
492 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
493 }
494 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
495 }
496
497 rt2800_disable_wpdma(rt2x00dev);
498
499 /*
500 * Write firmware to the device.
501 */
502 rt2800_drv_write_firmware(rt2x00dev, data, len);
503
504 /*
505 * Wait for device to stabilize.
506 */
507 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
508 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
509 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
510 break;
511 msleep(1);
512 }
513
514 if (i == REGISTER_BUSY_COUNT) {
515 ERROR(rt2x00dev, "PBF system register not ready.\n");
516 return -EBUSY;
517 }
518
519 /*
520 * Disable DMA, will be reenabled later when enabling
521 * the radio.
522 */
523 rt2800_disable_wpdma(rt2x00dev);
524
525 /*
526 * Initialize firmware.
527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
530 if (rt2x00_is_usb(rt2x00dev)) {
531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
532 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
533 }
534 msleep(1);
535
536 return 0;
537 }
538 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
539
540 void rt2800_write_tx_data(struct queue_entry *entry,
541 struct txentry_desc *txdesc)
542 {
543 __le32 *txwi = rt2800_drv_get_txwi(entry);
544 u32 word;
545
546 /*
547 * Initialize TX Info descriptor
548 */
549 rt2x00_desc_read(txwi, 0, &word);
550 rt2x00_set_field32(&word, TXWI_W0_FRAG,
551 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
552 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
553 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
554 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
555 rt2x00_set_field32(&word, TXWI_W0_TS,
556 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
557 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
558 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
559 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
560 txdesc->u.ht.mpdu_density);
561 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
562 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
563 rt2x00_set_field32(&word, TXWI_W0_BW,
564 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
565 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
566 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
567 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
568 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
569 rt2x00_desc_write(txwi, 0, word);
570
571 rt2x00_desc_read(txwi, 1, &word);
572 rt2x00_set_field32(&word, TXWI_W1_ACK,
573 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
574 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
575 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
576 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
577 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
578 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
579 txdesc->key_idx : txdesc->u.ht.wcid);
580 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
581 txdesc->length);
582 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
583 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
584 rt2x00_desc_write(txwi, 1, word);
585
586 /*
587 * Always write 0 to IV/EIV fields, hardware will insert the IV
588 * from the IVEIV register when TXD_W3_WIV is set to 0.
589 * When TXD_W3_WIV is set to 1 it will use the IV data
590 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
591 * crypto entry in the registers should be used to encrypt the frame.
592 */
593 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
594 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
595 }
596 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
597
598 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
599 {
600 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
601 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
602 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
603 u16 eeprom;
604 u8 offset0;
605 u8 offset1;
606 u8 offset2;
607
608 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
609 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
610 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
611 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
612 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
613 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
614 } else {
615 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
616 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
617 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
618 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
619 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
620 }
621
622 /*
623 * Convert the value from the descriptor into the RSSI value
624 * If the value in the descriptor is 0, it is considered invalid
625 * and the default (extremely low) rssi value is assumed
626 */
627 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
628 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
629 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
630
631 /*
632 * mac80211 only accepts a single RSSI value. Calculating the
633 * average doesn't deliver a fair answer either since -60:-60 would
634 * be considered equally good as -50:-70 while the second is the one
635 * which gives less energy...
636 */
637 rssi0 = max(rssi0, rssi1);
638 return (int)max(rssi0, rssi2);
639 }
640
641 void rt2800_process_rxwi(struct queue_entry *entry,
642 struct rxdone_entry_desc *rxdesc)
643 {
644 __le32 *rxwi = (__le32 *) entry->skb->data;
645 u32 word;
646
647 rt2x00_desc_read(rxwi, 0, &word);
648
649 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
650 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
651
652 rt2x00_desc_read(rxwi, 1, &word);
653
654 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
655 rxdesc->flags |= RX_FLAG_SHORT_GI;
656
657 if (rt2x00_get_field32(word, RXWI_W1_BW))
658 rxdesc->flags |= RX_FLAG_40MHZ;
659
660 /*
661 * Detect RX rate, always use MCS as signal type.
662 */
663 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
664 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
665 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
666
667 /*
668 * Mask of 0x8 bit to remove the short preamble flag.
669 */
670 if (rxdesc->rate_mode == RATE_MODE_CCK)
671 rxdesc->signal &= ~0x8;
672
673 rt2x00_desc_read(rxwi, 2, &word);
674
675 /*
676 * Convert descriptor AGC value to RSSI value.
677 */
678 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
679
680 /*
681 * Remove RXWI descriptor from start of buffer.
682 */
683 skb_pull(entry->skb, RXWI_DESC_SIZE);
684 }
685 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
686
687 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
688 {
689 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
690 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
691 struct txdone_entry_desc txdesc;
692 u32 word;
693 u16 mcs, real_mcs;
694 int aggr, ampdu;
695
696 /*
697 * Obtain the status about this packet.
698 */
699 txdesc.flags = 0;
700 rt2x00_desc_read(txwi, 0, &word);
701
702 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
703 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
704
705 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
706 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
707
708 /*
709 * If a frame was meant to be sent as a single non-aggregated MPDU
710 * but ended up in an aggregate the used tx rate doesn't correlate
711 * with the one specified in the TXWI as the whole aggregate is sent
712 * with the same rate.
713 *
714 * For example: two frames are sent to rt2x00, the first one sets
715 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
716 * and requests MCS15. If the hw aggregates both frames into one
717 * AMDPU the tx status for both frames will contain MCS7 although
718 * the frame was sent successfully.
719 *
720 * Hence, replace the requested rate with the real tx rate to not
721 * confuse the rate control algortihm by providing clearly wrong
722 * data.
723 */
724 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
725 skbdesc->tx_rate_idx = real_mcs;
726 mcs = real_mcs;
727 }
728
729 if (aggr == 1 || ampdu == 1)
730 __set_bit(TXDONE_AMPDU, &txdesc.flags);
731
732 /*
733 * Ralink has a retry mechanism using a global fallback
734 * table. We setup this fallback table to try the immediate
735 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
736 * always contains the MCS used for the last transmission, be
737 * it successful or not.
738 */
739 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
740 /*
741 * Transmission succeeded. The number of retries is
742 * mcs - real_mcs
743 */
744 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
745 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
746 } else {
747 /*
748 * Transmission failed. The number of retries is
749 * always 7 in this case (for a total number of 8
750 * frames sent).
751 */
752 __set_bit(TXDONE_FAILURE, &txdesc.flags);
753 txdesc.retry = rt2x00dev->long_retry;
754 }
755
756 /*
757 * the frame was retried at least once
758 * -> hw used fallback rates
759 */
760 if (txdesc.retry)
761 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
762
763 rt2x00lib_txdone(entry, &txdesc);
764 }
765 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
766
767 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
768 {
769 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
770 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
771 unsigned int beacon_base;
772 unsigned int padding_len;
773 u32 orig_reg, reg;
774
775 /*
776 * Disable beaconing while we are reloading the beacon data,
777 * otherwise we might be sending out invalid data.
778 */
779 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
780 orig_reg = reg;
781 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
782 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
783
784 /*
785 * Add space for the TXWI in front of the skb.
786 */
787 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
788
789 /*
790 * Register descriptor details in skb frame descriptor.
791 */
792 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
793 skbdesc->desc = entry->skb->data;
794 skbdesc->desc_len = TXWI_DESC_SIZE;
795
796 /*
797 * Add the TXWI for the beacon to the skb.
798 */
799 rt2800_write_tx_data(entry, txdesc);
800
801 /*
802 * Dump beacon to userspace through debugfs.
803 */
804 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
805
806 /*
807 * Write entire beacon with TXWI and padding to register.
808 */
809 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
810 if (padding_len && skb_pad(entry->skb, padding_len)) {
811 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
812 /* skb freed by skb_pad() on failure */
813 entry->skb = NULL;
814 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
815 return;
816 }
817
818 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
819 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
820 entry->skb->len + padding_len);
821
822 /*
823 * Enable beaconing again.
824 */
825 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
826 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
827
828 /*
829 * Clean up beacon skb.
830 */
831 dev_kfree_skb_any(entry->skb);
832 entry->skb = NULL;
833 }
834 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
835
836 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
837 unsigned int beacon_base)
838 {
839 int i;
840
841 /*
842 * For the Beacon base registers we only need to clear
843 * the whole TXWI which (when set to 0) will invalidate
844 * the entire beacon.
845 */
846 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
847 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
848 }
849
850 void rt2800_clear_beacon(struct queue_entry *entry)
851 {
852 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
853 u32 reg;
854
855 /*
856 * Disable beaconing while we are reloading the beacon data,
857 * otherwise we might be sending out invalid data.
858 */
859 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
860 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
861 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
862
863 /*
864 * Clear beacon.
865 */
866 rt2800_clear_beacon_register(rt2x00dev,
867 HW_BEACON_OFFSET(entry->entry_idx));
868
869 /*
870 * Enabled beaconing again.
871 */
872 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
873 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
874 }
875 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
876
877 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
878 const struct rt2x00debug rt2800_rt2x00debug = {
879 .owner = THIS_MODULE,
880 .csr = {
881 .read = rt2800_register_read,
882 .write = rt2800_register_write,
883 .flags = RT2X00DEBUGFS_OFFSET,
884 .word_base = CSR_REG_BASE,
885 .word_size = sizeof(u32),
886 .word_count = CSR_REG_SIZE / sizeof(u32),
887 },
888 .eeprom = {
889 .read = rt2x00_eeprom_read,
890 .write = rt2x00_eeprom_write,
891 .word_base = EEPROM_BASE,
892 .word_size = sizeof(u16),
893 .word_count = EEPROM_SIZE / sizeof(u16),
894 },
895 .bbp = {
896 .read = rt2800_bbp_read,
897 .write = rt2800_bbp_write,
898 .word_base = BBP_BASE,
899 .word_size = sizeof(u8),
900 .word_count = BBP_SIZE / sizeof(u8),
901 },
902 .rf = {
903 .read = rt2x00_rf_read,
904 .write = rt2800_rf_write,
905 .word_base = RF_BASE,
906 .word_size = sizeof(u32),
907 .word_count = RF_SIZE / sizeof(u32),
908 },
909 .rfcsr = {
910 .read = rt2800_rfcsr_read,
911 .write = rt2800_rfcsr_write,
912 .word_base = RFCSR_BASE,
913 .word_size = sizeof(u8),
914 .word_count = RFCSR_SIZE / sizeof(u8),
915 },
916 };
917 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
918 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
919
920 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
921 {
922 u32 reg;
923
924 if (rt2x00_rt(rt2x00dev, RT3290)) {
925 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
926 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
927 } else {
928 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
929 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
930 }
931 }
932 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
933
934 #ifdef CONFIG_RT2X00_LIB_LEDS
935 static void rt2800_brightness_set(struct led_classdev *led_cdev,
936 enum led_brightness brightness)
937 {
938 struct rt2x00_led *led =
939 container_of(led_cdev, struct rt2x00_led, led_dev);
940 unsigned int enabled = brightness != LED_OFF;
941 unsigned int bg_mode =
942 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
943 unsigned int polarity =
944 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
945 EEPROM_FREQ_LED_POLARITY);
946 unsigned int ledmode =
947 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
948 EEPROM_FREQ_LED_MODE);
949 u32 reg;
950
951 /* Check for SoC (SOC devices don't support MCU requests) */
952 if (rt2x00_is_soc(led->rt2x00dev)) {
953 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
954
955 /* Set LED Polarity */
956 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
957
958 /* Set LED Mode */
959 if (led->type == LED_TYPE_RADIO) {
960 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
961 enabled ? 3 : 0);
962 } else if (led->type == LED_TYPE_ASSOC) {
963 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
964 enabled ? 3 : 0);
965 } else if (led->type == LED_TYPE_QUALITY) {
966 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
967 enabled ? 3 : 0);
968 }
969
970 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
971
972 } else {
973 if (led->type == LED_TYPE_RADIO) {
974 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
975 enabled ? 0x20 : 0);
976 } else if (led->type == LED_TYPE_ASSOC) {
977 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
978 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
979 } else if (led->type == LED_TYPE_QUALITY) {
980 /*
981 * The brightness is divided into 6 levels (0 - 5),
982 * The specs tell us the following levels:
983 * 0, 1 ,3, 7, 15, 31
984 * to determine the level in a simple way we can simply
985 * work with bitshifting:
986 * (1 << level) - 1
987 */
988 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
989 (1 << brightness / (LED_FULL / 6)) - 1,
990 polarity);
991 }
992 }
993 }
994
995 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
996 struct rt2x00_led *led, enum led_type type)
997 {
998 led->rt2x00dev = rt2x00dev;
999 led->type = type;
1000 led->led_dev.brightness_set = rt2800_brightness_set;
1001 led->flags = LED_INITIALIZED;
1002 }
1003 #endif /* CONFIG_RT2X00_LIB_LEDS */
1004
1005 /*
1006 * Configuration handlers.
1007 */
1008 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1009 const u8 *address,
1010 int wcid)
1011 {
1012 struct mac_wcid_entry wcid_entry;
1013 u32 offset;
1014
1015 offset = MAC_WCID_ENTRY(wcid);
1016
1017 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1018 if (address)
1019 memcpy(wcid_entry.mac, address, ETH_ALEN);
1020
1021 rt2800_register_multiwrite(rt2x00dev, offset,
1022 &wcid_entry, sizeof(wcid_entry));
1023 }
1024
1025 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1026 {
1027 u32 offset;
1028 offset = MAC_WCID_ATTR_ENTRY(wcid);
1029 rt2800_register_write(rt2x00dev, offset, 0);
1030 }
1031
1032 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1033 int wcid, u32 bssidx)
1034 {
1035 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1036 u32 reg;
1037
1038 /*
1039 * The BSS Idx numbers is split in a main value of 3 bits,
1040 * and a extended field for adding one additional bit to the value.
1041 */
1042 rt2800_register_read(rt2x00dev, offset, &reg);
1043 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1044 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1045 (bssidx & 0x8) >> 3);
1046 rt2800_register_write(rt2x00dev, offset, reg);
1047 }
1048
1049 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1050 struct rt2x00lib_crypto *crypto,
1051 struct ieee80211_key_conf *key)
1052 {
1053 struct mac_iveiv_entry iveiv_entry;
1054 u32 offset;
1055 u32 reg;
1056
1057 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1058
1059 if (crypto->cmd == SET_KEY) {
1060 rt2800_register_read(rt2x00dev, offset, &reg);
1061 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1062 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1063 /*
1064 * Both the cipher as the BSS Idx numbers are split in a main
1065 * value of 3 bits, and a extended field for adding one additional
1066 * bit to the value.
1067 */
1068 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1069 (crypto->cipher & 0x7));
1070 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1071 (crypto->cipher & 0x8) >> 3);
1072 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1073 rt2800_register_write(rt2x00dev, offset, reg);
1074 } else {
1075 /* Delete the cipher without touching the bssidx */
1076 rt2800_register_read(rt2x00dev, offset, &reg);
1077 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1078 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1079 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1080 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1081 rt2800_register_write(rt2x00dev, offset, reg);
1082 }
1083
1084 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1085
1086 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1087 if ((crypto->cipher == CIPHER_TKIP) ||
1088 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1089 (crypto->cipher == CIPHER_AES))
1090 iveiv_entry.iv[3] |= 0x20;
1091 iveiv_entry.iv[3] |= key->keyidx << 6;
1092 rt2800_register_multiwrite(rt2x00dev, offset,
1093 &iveiv_entry, sizeof(iveiv_entry));
1094 }
1095
1096 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1097 struct rt2x00lib_crypto *crypto,
1098 struct ieee80211_key_conf *key)
1099 {
1100 struct hw_key_entry key_entry;
1101 struct rt2x00_field32 field;
1102 u32 offset;
1103 u32 reg;
1104
1105 if (crypto->cmd == SET_KEY) {
1106 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1107
1108 memcpy(key_entry.key, crypto->key,
1109 sizeof(key_entry.key));
1110 memcpy(key_entry.tx_mic, crypto->tx_mic,
1111 sizeof(key_entry.tx_mic));
1112 memcpy(key_entry.rx_mic, crypto->rx_mic,
1113 sizeof(key_entry.rx_mic));
1114
1115 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1116 rt2800_register_multiwrite(rt2x00dev, offset,
1117 &key_entry, sizeof(key_entry));
1118 }
1119
1120 /*
1121 * The cipher types are stored over multiple registers
1122 * starting with SHARED_KEY_MODE_BASE each word will have
1123 * 32 bits and contains the cipher types for 2 bssidx each.
1124 * Using the correct defines correctly will cause overhead,
1125 * so just calculate the correct offset.
1126 */
1127 field.bit_offset = 4 * (key->hw_key_idx % 8);
1128 field.bit_mask = 0x7 << field.bit_offset;
1129
1130 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1131
1132 rt2800_register_read(rt2x00dev, offset, &reg);
1133 rt2x00_set_field32(&reg, field,
1134 (crypto->cmd == SET_KEY) * crypto->cipher);
1135 rt2800_register_write(rt2x00dev, offset, reg);
1136
1137 /*
1138 * Update WCID information
1139 */
1140 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1141 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1142 crypto->bssidx);
1143 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1144
1145 return 0;
1146 }
1147 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1148
1149 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1150 {
1151 struct mac_wcid_entry wcid_entry;
1152 int idx;
1153 u32 offset;
1154
1155 /*
1156 * Search for the first free WCID entry and return the corresponding
1157 * index.
1158 *
1159 * Make sure the WCID starts _after_ the last possible shared key
1160 * entry (>32).
1161 *
1162 * Since parts of the pairwise key table might be shared with
1163 * the beacon frame buffers 6 & 7 we should only write into the
1164 * first 222 entries.
1165 */
1166 for (idx = 33; idx <= 222; idx++) {
1167 offset = MAC_WCID_ENTRY(idx);
1168 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1169 sizeof(wcid_entry));
1170 if (is_broadcast_ether_addr(wcid_entry.mac))
1171 return idx;
1172 }
1173
1174 /*
1175 * Use -1 to indicate that we don't have any more space in the WCID
1176 * table.
1177 */
1178 return -1;
1179 }
1180
1181 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1182 struct rt2x00lib_crypto *crypto,
1183 struct ieee80211_key_conf *key)
1184 {
1185 struct hw_key_entry key_entry;
1186 u32 offset;
1187
1188 if (crypto->cmd == SET_KEY) {
1189 /*
1190 * Allow key configuration only for STAs that are
1191 * known by the hw.
1192 */
1193 if (crypto->wcid < 0)
1194 return -ENOSPC;
1195 key->hw_key_idx = crypto->wcid;
1196
1197 memcpy(key_entry.key, crypto->key,
1198 sizeof(key_entry.key));
1199 memcpy(key_entry.tx_mic, crypto->tx_mic,
1200 sizeof(key_entry.tx_mic));
1201 memcpy(key_entry.rx_mic, crypto->rx_mic,
1202 sizeof(key_entry.rx_mic));
1203
1204 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1205 rt2800_register_multiwrite(rt2x00dev, offset,
1206 &key_entry, sizeof(key_entry));
1207 }
1208
1209 /*
1210 * Update WCID information
1211 */
1212 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1213
1214 return 0;
1215 }
1216 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1217
1218 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1219 struct ieee80211_sta *sta)
1220 {
1221 int wcid;
1222 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1223
1224 /*
1225 * Find next free WCID.
1226 */
1227 wcid = rt2800_find_wcid(rt2x00dev);
1228
1229 /*
1230 * Store selected wcid even if it is invalid so that we can
1231 * later decide if the STA is uploaded into the hw.
1232 */
1233 sta_priv->wcid = wcid;
1234
1235 /*
1236 * No space left in the device, however, we can still communicate
1237 * with the STA -> No error.
1238 */
1239 if (wcid < 0)
1240 return 0;
1241
1242 /*
1243 * Clean up WCID attributes and write STA address to the device.
1244 */
1245 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1246 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1247 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1248 rt2x00lib_get_bssidx(rt2x00dev, vif));
1249 return 0;
1250 }
1251 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1252
1253 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1254 {
1255 /*
1256 * Remove WCID entry, no need to clean the attributes as they will
1257 * get renewed when the WCID is reused.
1258 */
1259 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1260
1261 return 0;
1262 }
1263 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1264
1265 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1266 const unsigned int filter_flags)
1267 {
1268 u32 reg;
1269
1270 /*
1271 * Start configuration steps.
1272 * Note that the version error will always be dropped
1273 * and broadcast frames will always be accepted since
1274 * there is no filter for it at this time.
1275 */
1276 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1277 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1278 !(filter_flags & FIF_FCSFAIL));
1279 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1280 !(filter_flags & FIF_PLCPFAIL));
1281 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1282 !(filter_flags & FIF_PROMISC_IN_BSS));
1283 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1284 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1285 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1286 !(filter_flags & FIF_ALLMULTI));
1287 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1288 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1289 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1290 !(filter_flags & FIF_CONTROL));
1291 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1292 !(filter_flags & FIF_CONTROL));
1293 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1294 !(filter_flags & FIF_CONTROL));
1295 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1296 !(filter_flags & FIF_CONTROL));
1297 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1298 !(filter_flags & FIF_CONTROL));
1299 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1300 !(filter_flags & FIF_PSPOLL));
1301 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1302 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1303 !(filter_flags & FIF_CONTROL));
1304 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1305 !(filter_flags & FIF_CONTROL));
1306 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1307 }
1308 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1309
1310 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1311 struct rt2x00intf_conf *conf, const unsigned int flags)
1312 {
1313 u32 reg;
1314 bool update_bssid = false;
1315
1316 if (flags & CONFIG_UPDATE_TYPE) {
1317 /*
1318 * Enable synchronisation.
1319 */
1320 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1321 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1322 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1323
1324 if (conf->sync == TSF_SYNC_AP_NONE) {
1325 /*
1326 * Tune beacon queue transmit parameters for AP mode
1327 */
1328 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1329 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1330 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1331 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1332 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1333 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1334 } else {
1335 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1336 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1337 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1338 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1339 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1340 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1341 }
1342 }
1343
1344 if (flags & CONFIG_UPDATE_MAC) {
1345 if (flags & CONFIG_UPDATE_TYPE &&
1346 conf->sync == TSF_SYNC_AP_NONE) {
1347 /*
1348 * The BSSID register has to be set to our own mac
1349 * address in AP mode.
1350 */
1351 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1352 update_bssid = true;
1353 }
1354
1355 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1356 reg = le32_to_cpu(conf->mac[1]);
1357 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1358 conf->mac[1] = cpu_to_le32(reg);
1359 }
1360
1361 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1362 conf->mac, sizeof(conf->mac));
1363 }
1364
1365 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1366 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1367 reg = le32_to_cpu(conf->bssid[1]);
1368 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1369 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1370 conf->bssid[1] = cpu_to_le32(reg);
1371 }
1372
1373 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1374 conf->bssid, sizeof(conf->bssid));
1375 }
1376 }
1377 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1378
1379 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1380 struct rt2x00lib_erp *erp)
1381 {
1382 bool any_sta_nongf = !!(erp->ht_opmode &
1383 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1384 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1385 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1386 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1387 u32 reg;
1388
1389 /* default protection rate for HT20: OFDM 24M */
1390 mm20_rate = gf20_rate = 0x4004;
1391
1392 /* default protection rate for HT40: duplicate OFDM 24M */
1393 mm40_rate = gf40_rate = 0x4084;
1394
1395 switch (protection) {
1396 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1397 /*
1398 * All STAs in this BSS are HT20/40 but there might be
1399 * STAs not supporting greenfield mode.
1400 * => Disable protection for HT transmissions.
1401 */
1402 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1403
1404 break;
1405 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1406 /*
1407 * All STAs in this BSS are HT20 or HT20/40 but there
1408 * might be STAs not supporting greenfield mode.
1409 * => Protect all HT40 transmissions.
1410 */
1411 mm20_mode = gf20_mode = 0;
1412 mm40_mode = gf40_mode = 2;
1413
1414 break;
1415 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1416 /*
1417 * Nonmember protection:
1418 * According to 802.11n we _should_ protect all
1419 * HT transmissions (but we don't have to).
1420 *
1421 * But if cts_protection is enabled we _shall_ protect
1422 * all HT transmissions using a CCK rate.
1423 *
1424 * And if any station is non GF we _shall_ protect
1425 * GF transmissions.
1426 *
1427 * We decide to protect everything
1428 * -> fall through to mixed mode.
1429 */
1430 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1431 /*
1432 * Legacy STAs are present
1433 * => Protect all HT transmissions.
1434 */
1435 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1436
1437 /*
1438 * If erp protection is needed we have to protect HT
1439 * transmissions with CCK 11M long preamble.
1440 */
1441 if (erp->cts_protection) {
1442 /* don't duplicate RTS/CTS in CCK mode */
1443 mm20_rate = mm40_rate = 0x0003;
1444 gf20_rate = gf40_rate = 0x0003;
1445 }
1446 break;
1447 }
1448
1449 /* check for STAs not supporting greenfield mode */
1450 if (any_sta_nongf)
1451 gf20_mode = gf40_mode = 2;
1452
1453 /* Update HT protection config */
1454 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1455 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1456 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1457 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1458
1459 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1460 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1461 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1462 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1463
1464 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1465 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1466 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1467 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1468
1469 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1470 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1471 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1472 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1473 }
1474
1475 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1476 u32 changed)
1477 {
1478 u32 reg;
1479
1480 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1481 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1482 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1483 !!erp->short_preamble);
1484 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1485 !!erp->short_preamble);
1486 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1487 }
1488
1489 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1490 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1491 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1492 erp->cts_protection ? 2 : 0);
1493 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1494 }
1495
1496 if (changed & BSS_CHANGED_BASIC_RATES) {
1497 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1498 erp->basic_rates);
1499 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1500 }
1501
1502 if (changed & BSS_CHANGED_ERP_SLOT) {
1503 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1504 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1505 erp->slot_time);
1506 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1507
1508 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1509 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1510 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1511 }
1512
1513 if (changed & BSS_CHANGED_BEACON_INT) {
1514 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1515 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1516 erp->beacon_int * 16);
1517 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1518 }
1519
1520 if (changed & BSS_CHANGED_HT)
1521 rt2800_config_ht_opmode(rt2x00dev, erp);
1522 }
1523 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1524
1525 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1526 {
1527 u32 reg;
1528 u16 eeprom;
1529 u8 led_ctrl, led_g_mode, led_r_mode;
1530
1531 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1532 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1533 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1534 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1535 } else {
1536 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1537 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1538 }
1539 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1540
1541 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1542 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1543 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1544 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1545 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1546 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1547 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1548 if (led_ctrl == 0 || led_ctrl > 0x40) {
1549 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1550 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1551 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1552 } else {
1553 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1554 (led_g_mode << 2) | led_r_mode, 1);
1555 }
1556 }
1557 }
1558
1559 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1560 enum antenna ant)
1561 {
1562 u32 reg;
1563 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1564 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1565
1566 if (rt2x00_is_pci(rt2x00dev)) {
1567 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1568 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1569 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1570 } else if (rt2x00_is_usb(rt2x00dev))
1571 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1572 eesk_pin, 0);
1573
1574 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1575 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1576 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1577 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1578 }
1579
1580 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1581 {
1582 u8 r1;
1583 u8 r3;
1584 u16 eeprom;
1585
1586 rt2800_bbp_read(rt2x00dev, 1, &r1);
1587 rt2800_bbp_read(rt2x00dev, 3, &r3);
1588
1589 if (rt2x00_rt(rt2x00dev, RT3572) &&
1590 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1591 rt2800_config_3572bt_ant(rt2x00dev);
1592
1593 /*
1594 * Configure the TX antenna.
1595 */
1596 switch (ant->tx_chain_num) {
1597 case 1:
1598 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1599 break;
1600 case 2:
1601 if (rt2x00_rt(rt2x00dev, RT3572) &&
1602 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1603 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1604 else
1605 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1606 break;
1607 case 3:
1608 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1609 break;
1610 }
1611
1612 /*
1613 * Configure the RX antenna.
1614 */
1615 switch (ant->rx_chain_num) {
1616 case 1:
1617 if (rt2x00_rt(rt2x00dev, RT3070) ||
1618 rt2x00_rt(rt2x00dev, RT3090) ||
1619 rt2x00_rt(rt2x00dev, RT3352) ||
1620 rt2x00_rt(rt2x00dev, RT3390)) {
1621 rt2x00_eeprom_read(rt2x00dev,
1622 EEPROM_NIC_CONF1, &eeprom);
1623 if (rt2x00_get_field16(eeprom,
1624 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1625 rt2800_set_ant_diversity(rt2x00dev,
1626 rt2x00dev->default_ant.rx);
1627 }
1628 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1629 break;
1630 case 2:
1631 if (rt2x00_rt(rt2x00dev, RT3572) &&
1632 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1633 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1634 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1635 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1636 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1637 } else {
1638 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1639 }
1640 break;
1641 case 3:
1642 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1643 break;
1644 }
1645
1646 rt2800_bbp_write(rt2x00dev, 3, r3);
1647 rt2800_bbp_write(rt2x00dev, 1, r1);
1648 }
1649 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1650
1651 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1652 struct rt2x00lib_conf *libconf)
1653 {
1654 u16 eeprom;
1655 short lna_gain;
1656
1657 if (libconf->rf.channel <= 14) {
1658 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1659 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1660 } else if (libconf->rf.channel <= 64) {
1661 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1662 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1663 } else if (libconf->rf.channel <= 128) {
1664 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1665 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1666 } else {
1667 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1668 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1669 }
1670
1671 rt2x00dev->lna_gain = lna_gain;
1672 }
1673
1674 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1675 struct ieee80211_conf *conf,
1676 struct rf_channel *rf,
1677 struct channel_info *info)
1678 {
1679 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1680
1681 if (rt2x00dev->default_ant.tx_chain_num == 1)
1682 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1683
1684 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1685 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1686 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1687 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1688 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1689
1690 if (rf->channel > 14) {
1691 /*
1692 * When TX power is below 0, we should increase it by 7 to
1693 * make it a positive value (Minimum value is -7).
1694 * However this means that values between 0 and 7 have
1695 * double meaning, and we should set a 7DBm boost flag.
1696 */
1697 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1698 (info->default_power1 >= 0));
1699
1700 if (info->default_power1 < 0)
1701 info->default_power1 += 7;
1702
1703 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1704
1705 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1706 (info->default_power2 >= 0));
1707
1708 if (info->default_power2 < 0)
1709 info->default_power2 += 7;
1710
1711 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1712 } else {
1713 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1714 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1715 }
1716
1717 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1718
1719 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1720 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1721 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1722 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1723
1724 udelay(200);
1725
1726 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1727 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1728 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1729 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1730
1731 udelay(200);
1732
1733 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1734 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1735 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1736 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1737 }
1738
1739 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1740 struct ieee80211_conf *conf,
1741 struct rf_channel *rf,
1742 struct channel_info *info)
1743 {
1744 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1745 u8 rfcsr, calib_tx, calib_rx;
1746
1747 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1748
1749 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1750 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1751 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1752
1753 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1754 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1755 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1756
1757 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1758 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1759 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1760
1761 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1762 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1763 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1764
1765 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1766 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1767 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1768 rt2x00dev->default_ant.rx_chain_num <= 1);
1769 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1770 rt2x00dev->default_ant.rx_chain_num <= 2);
1771 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1772 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1773 rt2x00dev->default_ant.tx_chain_num <= 1);
1774 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1775 rt2x00dev->default_ant.tx_chain_num <= 2);
1776 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1777
1778 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1779 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1780 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1781 msleep(1);
1782 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1783 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1784
1785 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1786 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1787 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1788
1789 if (rt2x00_rt(rt2x00dev, RT3390)) {
1790 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1791 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1792 } else {
1793 if (conf_is_ht40(conf)) {
1794 calib_tx = drv_data->calibration_bw40;
1795 calib_rx = drv_data->calibration_bw40;
1796 } else {
1797 calib_tx = drv_data->calibration_bw20;
1798 calib_rx = drv_data->calibration_bw20;
1799 }
1800 }
1801
1802 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1803 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1804 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1805
1806 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1807 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1808 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1809
1810 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1811 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1812 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1813
1814 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1815 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1816 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1817 msleep(1);
1818 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1819 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1820 }
1821
1822 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1823 struct ieee80211_conf *conf,
1824 struct rf_channel *rf,
1825 struct channel_info *info)
1826 {
1827 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1828 u8 rfcsr;
1829 u32 reg;
1830
1831 if (rf->channel <= 14) {
1832 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1833 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1834 } else {
1835 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1836 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1837 }
1838
1839 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1840 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1841
1842 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1843 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1844 if (rf->channel <= 14)
1845 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1846 else
1847 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1848 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1849
1850 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1851 if (rf->channel <= 14)
1852 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1853 else
1854 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1855 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1856
1857 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1858 if (rf->channel <= 14) {
1859 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1860 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1861 info->default_power1);
1862 } else {
1863 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1864 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1865 (info->default_power1 & 0x3) |
1866 ((info->default_power1 & 0xC) << 1));
1867 }
1868 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1869
1870 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1871 if (rf->channel <= 14) {
1872 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1873 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1874 info->default_power2);
1875 } else {
1876 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1877 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1878 (info->default_power2 & 0x3) |
1879 ((info->default_power2 & 0xC) << 1));
1880 }
1881 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1882
1883 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1884 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1885 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1886 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1887 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1888 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1889 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1890 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1891 if (rf->channel <= 14) {
1892 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1893 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1894 }
1895 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1896 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1897 } else {
1898 switch (rt2x00dev->default_ant.tx_chain_num) {
1899 case 1:
1900 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1901 case 2:
1902 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1903 break;
1904 }
1905
1906 switch (rt2x00dev->default_ant.rx_chain_num) {
1907 case 1:
1908 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1909 case 2:
1910 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1911 break;
1912 }
1913 }
1914 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1915
1916 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1917 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1918 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1919
1920 if (conf_is_ht40(conf)) {
1921 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1922 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1923 } else {
1924 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1925 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1926 }
1927
1928 if (rf->channel <= 14) {
1929 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1930 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1931 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1932 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1933 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1934 rfcsr = 0x4c;
1935 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1936 drv_data->txmixer_gain_24g);
1937 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1938 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1939 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1940 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1941 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1942 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1943 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1944 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1945 } else {
1946 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1947 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1948 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1949 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1950 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1951 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1952 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1953 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1954 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1955 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1956 rfcsr = 0x7a;
1957 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1958 drv_data->txmixer_gain_5g);
1959 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1960 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1961 if (rf->channel <= 64) {
1962 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1963 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1964 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1965 } else if (rf->channel <= 128) {
1966 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1967 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1968 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1969 } else {
1970 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1971 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1972 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1973 }
1974 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1975 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1976 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1977 }
1978
1979 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1980 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1981 if (rf->channel <= 14)
1982 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1983 else
1984 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1985 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1986
1987 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1988 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1989 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1990 }
1991
1992 #define POWER_BOUND 0x27
1993 #define POWER_BOUND_5G 0x2b
1994 #define FREQ_OFFSET_BOUND 0x5f
1995
1996 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1997 {
1998 u8 rfcsr;
1999
2000 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2001 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2002 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2003 else
2004 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2005 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2006 }
2007
2008 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2009 struct ieee80211_conf *conf,
2010 struct rf_channel *rf,
2011 struct channel_info *info)
2012 {
2013 u8 rfcsr;
2014
2015 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2016 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2017 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2018 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2019 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2020
2021 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2022 if (info->default_power1 > POWER_BOUND)
2023 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2024 else
2025 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2026 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2027
2028 rt2800_adjust_freq_offset(rt2x00dev);
2029
2030 if (rf->channel <= 14) {
2031 if (rf->channel == 6)
2032 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2033 else
2034 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2035
2036 if (rf->channel >= 1 && rf->channel <= 6)
2037 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2038 else if (rf->channel >= 7 && rf->channel <= 11)
2039 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2040 else if (rf->channel >= 12 && rf->channel <= 14)
2041 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2042 }
2043 }
2044
2045 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2046 struct ieee80211_conf *conf,
2047 struct rf_channel *rf,
2048 struct channel_info *info)
2049 {
2050 u8 rfcsr;
2051
2052 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2053 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2054
2055 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2056 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2057 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2058
2059 if (info->default_power1 > POWER_BOUND)
2060 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2061 else
2062 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2063
2064 if (info->default_power2 > POWER_BOUND)
2065 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2066 else
2067 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2068
2069 rt2800_adjust_freq_offset(rt2x00dev);
2070
2071 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2072 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2073 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2074
2075 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2076 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2077 else
2078 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2079
2080 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2081 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2082 else
2083 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2084
2085 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2086 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2087
2088 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2089
2090 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2091 }
2092
2093 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2094 struct ieee80211_conf *conf,
2095 struct rf_channel *rf,
2096 struct channel_info *info)
2097 {
2098 u8 rfcsr;
2099
2100 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2101 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2102 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2103 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2104 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2105
2106 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2107 if (info->default_power1 > POWER_BOUND)
2108 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2109 else
2110 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2111 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2112
2113 if (rt2x00_rt(rt2x00dev, RT5392)) {
2114 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2115 if (info->default_power1 > POWER_BOUND)
2116 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2117 else
2118 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2119 info->default_power2);
2120 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2121 }
2122
2123 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2124 if (rt2x00_rt(rt2x00dev, RT5392)) {
2125 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2126 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2127 }
2128 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2129 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2130 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2131 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2132 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2133
2134 rt2800_adjust_freq_offset(rt2x00dev);
2135
2136 if (rf->channel <= 14) {
2137 int idx = rf->channel-1;
2138
2139 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2140 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2141 /* r55/r59 value array of channel 1~14 */
2142 static const char r55_bt_rev[] = {0x83, 0x83,
2143 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2144 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2145 static const char r59_bt_rev[] = {0x0e, 0x0e,
2146 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2147 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2148
2149 rt2800_rfcsr_write(rt2x00dev, 55,
2150 r55_bt_rev[idx]);
2151 rt2800_rfcsr_write(rt2x00dev, 59,
2152 r59_bt_rev[idx]);
2153 } else {
2154 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2155 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2156 0x88, 0x88, 0x86, 0x85, 0x84};
2157
2158 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2159 }
2160 } else {
2161 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2162 static const char r55_nonbt_rev[] = {0x23, 0x23,
2163 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2164 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2165 static const char r59_nonbt_rev[] = {0x07, 0x07,
2166 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2167 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2168
2169 rt2800_rfcsr_write(rt2x00dev, 55,
2170 r55_nonbt_rev[idx]);
2171 rt2800_rfcsr_write(rt2x00dev, 59,
2172 r59_nonbt_rev[idx]);
2173 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2174 rt2x00_rt(rt2x00dev, RT5392)) {
2175 static const char r59_non_bt[] = {0x8f, 0x8f,
2176 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2177 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2178
2179 rt2800_rfcsr_write(rt2x00dev, 59,
2180 r59_non_bt[idx]);
2181 }
2182 }
2183 }
2184 }
2185
2186 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2187 struct ieee80211_conf *conf,
2188 struct rf_channel *rf,
2189 struct channel_info *info)
2190 {
2191 u8 rfcsr, ep_reg;
2192 u32 reg;
2193 int power_bound;
2194
2195 /* TODO */
2196 const bool is_11b = false;
2197 const bool is_type_ep = false;
2198
2199 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2200 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2201 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2202 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2203
2204 /* Order of values on rf_channel entry: N, K, mod, R */
2205 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2206
2207 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2208 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2209 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2210 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2211 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2212
2213 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2214 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2215 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2216 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2217
2218 if (rf->channel <= 14) {
2219 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2220 /* FIXME: RF11 owerwrite ? */
2221 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2222 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2223 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2224 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2225 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2226 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2227 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2228 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2229 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2230 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2231 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2232 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2233 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2234 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2235 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2236 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2237 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2238 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2239 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2240 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2241 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2242 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2243 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2244 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2245 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2246 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2247 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2248 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2249
2250 /* TODO RF27 <- tssi */
2251
2252 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2253 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2254 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2255
2256 if (is_11b) {
2257 /* CCK */
2258 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2259 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2260 if (is_type_ep)
2261 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2262 else
2263 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2264 } else {
2265 /* OFDM */
2266 if (is_type_ep)
2267 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2268 else
2269 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2270 }
2271
2272 power_bound = POWER_BOUND;
2273 ep_reg = 0x2;
2274 } else {
2275 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2276 /* FIMXE: RF11 overwrite */
2277 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2278 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2279 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2280 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2281 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2282 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2283 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2284 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2285 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2286 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2287 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2288 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2289 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2290 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2291
2292 /* TODO RF27 <- tssi */
2293
2294 if (rf->channel >= 36 && rf->channel <= 64) {
2295
2296 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2297 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2298 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2299 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2300 if (rf->channel <= 50)
2301 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2302 else if (rf->channel >= 52)
2303 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2304 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2305 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2306 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2307 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2308 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2309 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2310 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2311 if (rf->channel <= 50) {
2312 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2313 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2314 } else if (rf->channel >= 52) {
2315 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2316 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2317 }
2318
2319 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2320 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2321 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2322
2323 } else if (rf->channel >= 100 && rf->channel <= 165) {
2324
2325 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2326 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2327 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2328 if (rf->channel <= 153) {
2329 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2330 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2331 } else if (rf->channel >= 155) {
2332 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2333 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2334 }
2335 if (rf->channel <= 138) {
2336 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2337 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2338 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2339 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2340 } else if (rf->channel >= 140) {
2341 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2342 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2343 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2344 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2345 }
2346 if (rf->channel <= 124)
2347 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2348 else if (rf->channel >= 126)
2349 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2350 if (rf->channel <= 138)
2351 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2352 else if (rf->channel >= 140)
2353 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2354 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2355 if (rf->channel <= 138)
2356 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2357 else if (rf->channel >= 140)
2358 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2359 if (rf->channel <= 128)
2360 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2361 else if (rf->channel >= 130)
2362 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2363 if (rf->channel <= 116)
2364 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2365 else if (rf->channel >= 118)
2366 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2367 if (rf->channel <= 138)
2368 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2369 else if (rf->channel >= 140)
2370 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2371 if (rf->channel <= 116)
2372 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2373 else if (rf->channel >= 118)
2374 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2375 }
2376
2377 power_bound = POWER_BOUND_5G;
2378 ep_reg = 0x3;
2379 }
2380
2381 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2382 if (info->default_power1 > power_bound)
2383 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2384 else
2385 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2386 if (is_type_ep)
2387 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2388 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2389
2390 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2391 if (info->default_power1 > power_bound)
2392 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2393 else
2394 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2395 if (is_type_ep)
2396 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2397 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2398
2399 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2400 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2401 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2402
2403 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2404 rt2x00dev->default_ant.tx_chain_num >= 1);
2405 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2406 rt2x00dev->default_ant.tx_chain_num == 2);
2407 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2408
2409 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2410 rt2x00dev->default_ant.rx_chain_num >= 1);
2411 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2412 rt2x00dev->default_ant.rx_chain_num == 2);
2413 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2414
2415 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2416 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2417
2418 if (conf_is_ht40(conf))
2419 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2420 else
2421 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2422
2423 if (!is_11b) {
2424 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2425 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2426 }
2427
2428 /* TODO proper frequency adjustment */
2429 rt2800_adjust_freq_offset(rt2x00dev);
2430
2431 /* TODO merge with others */
2432 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2433 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2434 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2435
2436 /* BBP settings */
2437 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2438 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2439 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2440
2441 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2442 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2443 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2444 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2445
2446 /* GLRT band configuration */
2447 rt2800_bbp_write(rt2x00dev, 195, 128);
2448 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2449 rt2800_bbp_write(rt2x00dev, 195, 129);
2450 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2451 rt2800_bbp_write(rt2x00dev, 195, 130);
2452 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2453 rt2800_bbp_write(rt2x00dev, 195, 131);
2454 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2455 rt2800_bbp_write(rt2x00dev, 195, 133);
2456 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2457 rt2800_bbp_write(rt2x00dev, 195, 124);
2458 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2459 }
2460
2461 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2462 const unsigned int word,
2463 const u8 value)
2464 {
2465 u8 chain, reg;
2466
2467 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2468 rt2800_bbp_read(rt2x00dev, 27, &reg);
2469 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2470 rt2800_bbp_write(rt2x00dev, 27, reg);
2471
2472 rt2800_bbp_write(rt2x00dev, word, value);
2473 }
2474 }
2475
2476
2477 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2478 {
2479 u8 cal;
2480
2481 /* TODO */
2482 if (WARN_ON_ONCE(channel > 14))
2483 return;
2484
2485 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2486 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2487 rt2800_bbp_write(rt2x00dev, 159, cal);
2488
2489 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2490 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2491 rt2800_bbp_write(rt2x00dev, 159, cal);
2492
2493 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2494 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2495 rt2800_bbp_write(rt2x00dev, 159, cal);
2496
2497 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2498 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2499 rt2800_bbp_write(rt2x00dev, 159, cal);
2500
2501 /* RF IQ compensation control */
2502 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2503 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2504 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2505
2506 /* RF IQ imbalance compensation control */
2507 rt2800_bbp_write(rt2x00dev, 158, 0x03);
2508 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2509 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2510 }
2511
2512 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2513 struct ieee80211_conf *conf,
2514 struct rf_channel *rf,
2515 struct channel_info *info)
2516 {
2517 u32 reg;
2518 unsigned int tx_pin;
2519 u8 bbp, rfcsr;
2520
2521 if (rf->channel <= 14) {
2522 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2523 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2524 } else {
2525 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2526 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2527 }
2528
2529 switch (rt2x00dev->chip.rf) {
2530 case RF2020:
2531 case RF3020:
2532 case RF3021:
2533 case RF3022:
2534 case RF3320:
2535 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2536 break;
2537 case RF3052:
2538 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2539 break;
2540 case RF3290:
2541 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2542 break;
2543 case RF3322:
2544 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2545 break;
2546 case RF5360:
2547 case RF5370:
2548 case RF5372:
2549 case RF5390:
2550 case RF5392:
2551 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2552 break;
2553 case RF5592:
2554 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2555 break;
2556 default:
2557 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2558 }
2559
2560 if (rt2x00_rf(rt2x00dev, RF3290) ||
2561 rt2x00_rf(rt2x00dev, RF3322) ||
2562 rt2x00_rf(rt2x00dev, RF5360) ||
2563 rt2x00_rf(rt2x00dev, RF5370) ||
2564 rt2x00_rf(rt2x00dev, RF5372) ||
2565 rt2x00_rf(rt2x00dev, RF5390) ||
2566 rt2x00_rf(rt2x00dev, RF5392)) {
2567 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2568 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2569 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2570 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2571
2572 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2573 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2574 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2575 }
2576
2577 /*
2578 * Change BBP settings
2579 */
2580 if (rt2x00_rt(rt2x00dev, RT3352)) {
2581 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2582 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2583 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2584 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2585 } else {
2586 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2587 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2588 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2589 rt2800_bbp_write(rt2x00dev, 86, 0);
2590 }
2591
2592 if (rf->channel <= 14) {
2593 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2594 !rt2x00_rt(rt2x00dev, RT5392)) {
2595 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2596 &rt2x00dev->cap_flags)) {
2597 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2598 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2599 } else {
2600 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2601 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2602 }
2603 }
2604 } else {
2605 if (rt2x00_rt(rt2x00dev, RT3572))
2606 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2607 else
2608 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2609
2610 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2611 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2612 else
2613 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2614 }
2615
2616 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2617 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2618 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2619 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2620 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2621
2622 if (rt2x00_rt(rt2x00dev, RT3572))
2623 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2624
2625 tx_pin = 0;
2626
2627 /* Turn on unused PA or LNA when not using 1T or 1R */
2628 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2629 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2630 rf->channel > 14);
2631 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2632 rf->channel <= 14);
2633 }
2634
2635 /* Turn on unused PA or LNA when not using 1T or 1R */
2636 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2637 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2638 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2639 }
2640
2641 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2642 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2643 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2644 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2645 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2646 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2647 else
2648 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2649 rf->channel <= 14);
2650 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2651
2652 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2653
2654 if (rt2x00_rt(rt2x00dev, RT3572))
2655 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2656
2657 if (rt2x00_rt(rt2x00dev, RT5592)) {
2658 rt2800_bbp_write(rt2x00dev, 195, 141);
2659 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2660
2661 /* TODO AGC adjust */
2662 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2663 }
2664
2665 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2666 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2667 rt2800_bbp_write(rt2x00dev, 4, bbp);
2668
2669 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2670 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2671 rt2800_bbp_write(rt2x00dev, 3, bbp);
2672
2673 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2674 if (conf_is_ht40(conf)) {
2675 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2676 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2677 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2678 } else {
2679 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2680 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2681 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2682 }
2683 }
2684
2685 msleep(1);
2686
2687 /*
2688 * Clear channel statistic counters
2689 */
2690 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2691 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2692 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2693
2694 /*
2695 * Clear update flag
2696 */
2697 if (rt2x00_rt(rt2x00dev, RT3352)) {
2698 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2699 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2700 rt2800_bbp_write(rt2x00dev, 49, bbp);
2701 }
2702 }
2703
2704 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2705 {
2706 u8 tssi_bounds[9];
2707 u8 current_tssi;
2708 u16 eeprom;
2709 u8 step;
2710 int i;
2711
2712 /*
2713 * Read TSSI boundaries for temperature compensation from
2714 * the EEPROM.
2715 *
2716 * Array idx 0 1 2 3 4 5 6 7 8
2717 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2718 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2719 */
2720 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2721 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2722 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2723 EEPROM_TSSI_BOUND_BG1_MINUS4);
2724 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2725 EEPROM_TSSI_BOUND_BG1_MINUS3);
2726
2727 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2728 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2729 EEPROM_TSSI_BOUND_BG2_MINUS2);
2730 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2731 EEPROM_TSSI_BOUND_BG2_MINUS1);
2732
2733 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2734 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2735 EEPROM_TSSI_BOUND_BG3_REF);
2736 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2737 EEPROM_TSSI_BOUND_BG3_PLUS1);
2738
2739 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2740 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2741 EEPROM_TSSI_BOUND_BG4_PLUS2);
2742 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2743 EEPROM_TSSI_BOUND_BG4_PLUS3);
2744
2745 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2746 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2747 EEPROM_TSSI_BOUND_BG5_PLUS4);
2748
2749 step = rt2x00_get_field16(eeprom,
2750 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2751 } else {
2752 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2753 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2754 EEPROM_TSSI_BOUND_A1_MINUS4);
2755 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2756 EEPROM_TSSI_BOUND_A1_MINUS3);
2757
2758 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2759 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2760 EEPROM_TSSI_BOUND_A2_MINUS2);
2761 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2762 EEPROM_TSSI_BOUND_A2_MINUS1);
2763
2764 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2765 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2766 EEPROM_TSSI_BOUND_A3_REF);
2767 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2768 EEPROM_TSSI_BOUND_A3_PLUS1);
2769
2770 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2771 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2772 EEPROM_TSSI_BOUND_A4_PLUS2);
2773 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2774 EEPROM_TSSI_BOUND_A4_PLUS3);
2775
2776 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2777 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2778 EEPROM_TSSI_BOUND_A5_PLUS4);
2779
2780 step = rt2x00_get_field16(eeprom,
2781 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2782 }
2783
2784 /*
2785 * Check if temperature compensation is supported.
2786 */
2787 if (tssi_bounds[4] == 0xff || step == 0xff)
2788 return 0;
2789
2790 /*
2791 * Read current TSSI (BBP 49).
2792 */
2793 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2794
2795 /*
2796 * Compare TSSI value (BBP49) with the compensation boundaries
2797 * from the EEPROM and increase or decrease tx power.
2798 */
2799 for (i = 0; i <= 3; i++) {
2800 if (current_tssi > tssi_bounds[i])
2801 break;
2802 }
2803
2804 if (i == 4) {
2805 for (i = 8; i >= 5; i--) {
2806 if (current_tssi < tssi_bounds[i])
2807 break;
2808 }
2809 }
2810
2811 return (i - 4) * step;
2812 }
2813
2814 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2815 enum ieee80211_band band)
2816 {
2817 u16 eeprom;
2818 u8 comp_en;
2819 u8 comp_type;
2820 int comp_value = 0;
2821
2822 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2823
2824 /*
2825 * HT40 compensation not required.
2826 */
2827 if (eeprom == 0xffff ||
2828 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2829 return 0;
2830
2831 if (band == IEEE80211_BAND_2GHZ) {
2832 comp_en = rt2x00_get_field16(eeprom,
2833 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2834 if (comp_en) {
2835 comp_type = rt2x00_get_field16(eeprom,
2836 EEPROM_TXPOWER_DELTA_TYPE_2G);
2837 comp_value = rt2x00_get_field16(eeprom,
2838 EEPROM_TXPOWER_DELTA_VALUE_2G);
2839 if (!comp_type)
2840 comp_value = -comp_value;
2841 }
2842 } else {
2843 comp_en = rt2x00_get_field16(eeprom,
2844 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2845 if (comp_en) {
2846 comp_type = rt2x00_get_field16(eeprom,
2847 EEPROM_TXPOWER_DELTA_TYPE_5G);
2848 comp_value = rt2x00_get_field16(eeprom,
2849 EEPROM_TXPOWER_DELTA_VALUE_5G);
2850 if (!comp_type)
2851 comp_value = -comp_value;
2852 }
2853 }
2854
2855 return comp_value;
2856 }
2857
2858 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2859 int power_level, int max_power)
2860 {
2861 int delta;
2862
2863 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2864 return 0;
2865
2866 /*
2867 * XXX: We don't know the maximum transmit power of our hardware since
2868 * the EEPROM doesn't expose it. We only know that we are calibrated
2869 * to 100% tx power.
2870 *
2871 * Hence, we assume the regulatory limit that cfg80211 calulated for
2872 * the current channel is our maximum and if we are requested to lower
2873 * the value we just reduce our tx power accordingly.
2874 */
2875 delta = power_level - max_power;
2876 return min(delta, 0);
2877 }
2878
2879 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2880 enum ieee80211_band band, int power_level,
2881 u8 txpower, int delta)
2882 {
2883 u16 eeprom;
2884 u8 criterion;
2885 u8 eirp_txpower;
2886 u8 eirp_txpower_criterion;
2887 u8 reg_limit;
2888
2889 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2890 /*
2891 * Check if eirp txpower exceed txpower_limit.
2892 * We use OFDM 6M as criterion and its eirp txpower
2893 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2894 * .11b data rate need add additional 4dbm
2895 * when calculating eirp txpower.
2896 */
2897 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2898 &eeprom);
2899 criterion = rt2x00_get_field16(eeprom,
2900 EEPROM_TXPOWER_BYRATE_RATE0);
2901
2902 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2903 &eeprom);
2904
2905 if (band == IEEE80211_BAND_2GHZ)
2906 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2907 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2908 else
2909 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2910 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2911
2912 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2913 (is_rate_b ? 4 : 0) + delta;
2914
2915 reg_limit = (eirp_txpower > power_level) ?
2916 (eirp_txpower - power_level) : 0;
2917 } else
2918 reg_limit = 0;
2919
2920 txpower = max(0, txpower + delta - reg_limit);
2921 return min_t(u8, txpower, 0xc);
2922 }
2923
2924 /*
2925 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2926 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2927 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2928 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2929 * Reference per rate transmit power values are located in the EEPROM at
2930 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2931 * current conditions (i.e. band, bandwidth, temperature, user settings).
2932 */
2933 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2934 struct ieee80211_channel *chan,
2935 int power_level)
2936 {
2937 u8 txpower, r1;
2938 u16 eeprom;
2939 u32 reg, offset;
2940 int i, is_rate_b, delta, power_ctrl;
2941 enum ieee80211_band band = chan->band;
2942
2943 /*
2944 * Calculate HT40 compensation. For 40MHz we need to add or subtract
2945 * value read from EEPROM (different for 2GHz and for 5GHz).
2946 */
2947 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2948
2949 /*
2950 * Calculate temperature compensation. Depends on measurement of current
2951 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
2952 * to temperature or maybe other factors) is smaller or bigger than
2953 * expected. We adjust it, based on TSSI reference and boundaries values
2954 * provided in EEPROM.
2955 */
2956 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2957
2958 /*
2959 * Decrease power according to user settings, on devices with unknown
2960 * maximum tx power. For other devices we take user power_level into
2961 * consideration on rt2800_compensate_txpower().
2962 */
2963 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
2964 chan->max_power);
2965
2966 /*
2967 * BBP_R1 controls TX power for all rates, it allow to set the following
2968 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2969 *
2970 * TODO: we do not use +6 dBm option to do not increase power beyond
2971 * regulatory limit, however this could be utilized for devices with
2972 * CAPABILITY_POWER_LIMIT.
2973 */
2974 rt2800_bbp_read(rt2x00dev, 1, &r1);
2975 if (delta <= -12) {
2976 power_ctrl = 2;
2977 delta += 12;
2978 } else if (delta <= -6) {
2979 power_ctrl = 1;
2980 delta += 6;
2981 } else {
2982 power_ctrl = 0;
2983 }
2984 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
2985 rt2800_bbp_write(rt2x00dev, 1, r1);
2986 offset = TX_PWR_CFG_0;
2987
2988 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2989 /* just to be safe */
2990 if (offset > TX_PWR_CFG_4)
2991 break;
2992
2993 rt2800_register_read(rt2x00dev, offset, &reg);
2994
2995 /* read the next four txpower values */
2996 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2997 &eeprom);
2998
2999 is_rate_b = i ? 0 : 1;
3000 /*
3001 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3002 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3003 * TX_PWR_CFG_4: unknown
3004 */
3005 txpower = rt2x00_get_field16(eeprom,
3006 EEPROM_TXPOWER_BYRATE_RATE0);
3007 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3008 power_level, txpower, delta);
3009 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
3010
3011 /*
3012 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3013 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3014 * TX_PWR_CFG_4: unknown
3015 */
3016 txpower = rt2x00_get_field16(eeprom,
3017 EEPROM_TXPOWER_BYRATE_RATE1);
3018 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3019 power_level, txpower, delta);
3020 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
3021
3022 /*
3023 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3024 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
3025 * TX_PWR_CFG_4: unknown
3026 */
3027 txpower = rt2x00_get_field16(eeprom,
3028 EEPROM_TXPOWER_BYRATE_RATE2);
3029 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3030 power_level, txpower, delta);
3031 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
3032
3033 /*
3034 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3035 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
3036 * TX_PWR_CFG_4: unknown
3037 */
3038 txpower = rt2x00_get_field16(eeprom,
3039 EEPROM_TXPOWER_BYRATE_RATE3);
3040 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3041 power_level, txpower, delta);
3042 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
3043
3044 /* read the next four txpower values */
3045 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
3046 &eeprom);
3047
3048 is_rate_b = 0;
3049 /*
3050 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3051 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3052 * TX_PWR_CFG_4: unknown
3053 */
3054 txpower = rt2x00_get_field16(eeprom,
3055 EEPROM_TXPOWER_BYRATE_RATE0);
3056 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3057 power_level, txpower, delta);
3058 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3059
3060 /*
3061 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3062 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3063 * TX_PWR_CFG_4: unknown
3064 */
3065 txpower = rt2x00_get_field16(eeprom,
3066 EEPROM_TXPOWER_BYRATE_RATE1);
3067 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3068 power_level, txpower, delta);
3069 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3070
3071 /*
3072 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3073 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3074 * TX_PWR_CFG_4: unknown
3075 */
3076 txpower = rt2x00_get_field16(eeprom,
3077 EEPROM_TXPOWER_BYRATE_RATE2);
3078 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3079 power_level, txpower, delta);
3080 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3081
3082 /*
3083 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3084 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3085 * TX_PWR_CFG_4: unknown
3086 */
3087 txpower = rt2x00_get_field16(eeprom,
3088 EEPROM_TXPOWER_BYRATE_RATE3);
3089 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3090 power_level, txpower, delta);
3091 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3092
3093 rt2800_register_write(rt2x00dev, offset, reg);
3094
3095 /* next TX_PWR_CFG register */
3096 offset += 4;
3097 }
3098 }
3099
3100 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3101 {
3102 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
3103 rt2x00dev->tx_power);
3104 }
3105 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3106
3107 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3108 {
3109 u32 tx_pin;
3110 u8 rfcsr;
3111
3112 /*
3113 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3114 * designed to be controlled in oscillation frequency by a voltage
3115 * input. Maybe the temperature will affect the frequency of
3116 * oscillation to be shifted. The VCO calibration will be called
3117 * periodically to adjust the frequency to be precision.
3118 */
3119
3120 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3121 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3122 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3123
3124 switch (rt2x00dev->chip.rf) {
3125 case RF2020:
3126 case RF3020:
3127 case RF3021:
3128 case RF3022:
3129 case RF3320:
3130 case RF3052:
3131 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3132 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3133 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3134 break;
3135 case RF3290:
3136 case RF5360:
3137 case RF5370:
3138 case RF5372:
3139 case RF5390:
3140 case RF5392:
3141 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3142 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3143 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3144 break;
3145 default:
3146 return;
3147 }
3148
3149 mdelay(1);
3150
3151 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3152 if (rt2x00dev->rf_channel <= 14) {
3153 switch (rt2x00dev->default_ant.tx_chain_num) {
3154 case 3:
3155 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3156 /* fall through */
3157 case 2:
3158 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3159 /* fall through */
3160 case 1:
3161 default:
3162 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3163 break;
3164 }
3165 } else {
3166 switch (rt2x00dev->default_ant.tx_chain_num) {
3167 case 3:
3168 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3169 /* fall through */
3170 case 2:
3171 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3172 /* fall through */
3173 case 1:
3174 default:
3175 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3176 break;
3177 }
3178 }
3179 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3180
3181 }
3182 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3183
3184 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3185 struct rt2x00lib_conf *libconf)
3186 {
3187 u32 reg;
3188
3189 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3190 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3191 libconf->conf->short_frame_max_tx_count);
3192 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3193 libconf->conf->long_frame_max_tx_count);
3194 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3195 }
3196
3197 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3198 struct rt2x00lib_conf *libconf)
3199 {
3200 enum dev_state state =
3201 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3202 STATE_SLEEP : STATE_AWAKE;
3203 u32 reg;
3204
3205 if (state == STATE_SLEEP) {
3206 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3207
3208 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3209 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3210 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3211 libconf->conf->listen_interval - 1);
3212 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3213 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3214
3215 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3216 } else {
3217 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3218 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3219 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3220 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3221 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3222
3223 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3224 }
3225 }
3226
3227 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3228 struct rt2x00lib_conf *libconf,
3229 const unsigned int flags)
3230 {
3231 /* Always recalculate LNA gain before changing configuration */
3232 rt2800_config_lna_gain(rt2x00dev, libconf);
3233
3234 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3235 rt2800_config_channel(rt2x00dev, libconf->conf,
3236 &libconf->rf, &libconf->channel);
3237 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3238 libconf->conf->power_level);
3239 }
3240 if (flags & IEEE80211_CONF_CHANGE_POWER)
3241 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3242 libconf->conf->power_level);
3243 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3244 rt2800_config_retry_limit(rt2x00dev, libconf);
3245 if (flags & IEEE80211_CONF_CHANGE_PS)
3246 rt2800_config_ps(rt2x00dev, libconf);
3247 }
3248 EXPORT_SYMBOL_GPL(rt2800_config);
3249
3250 /*
3251 * Link tuning
3252 */
3253 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3254 {
3255 u32 reg;
3256
3257 /*
3258 * Update FCS error count from register.
3259 */
3260 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3261 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3262 }
3263 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3264
3265 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3266 {
3267 u8 vgc;
3268
3269 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3270 if (rt2x00_rt(rt2x00dev, RT3070) ||
3271 rt2x00_rt(rt2x00dev, RT3071) ||
3272 rt2x00_rt(rt2x00dev, RT3090) ||
3273 rt2x00_rt(rt2x00dev, RT3290) ||
3274 rt2x00_rt(rt2x00dev, RT3390) ||
3275 rt2x00_rt(rt2x00dev, RT3572) ||
3276 rt2x00_rt(rt2x00dev, RT5390) ||
3277 rt2x00_rt(rt2x00dev, RT5392))
3278 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3279 else
3280 vgc = 0x2e + rt2x00dev->lna_gain;
3281 } else { /* 5GHZ band */
3282 if (rt2x00_rt(rt2x00dev, RT3572))
3283 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3284 else {
3285 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3286 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3287 else
3288 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3289 }
3290 }
3291
3292 return vgc;
3293 }
3294
3295 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3296 struct link_qual *qual, u8 vgc_level)
3297 {
3298 if (qual->vgc_level != vgc_level) {
3299 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3300 qual->vgc_level = vgc_level;
3301 qual->vgc_level_reg = vgc_level;
3302 }
3303 }
3304
3305 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3306 {
3307 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3308 }
3309 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3310
3311 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3312 const u32 count)
3313 {
3314 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3315 return;
3316
3317 /*
3318 * When RSSI is better then -80 increase VGC level with 0x10
3319 */
3320 rt2800_set_vgc(rt2x00dev, qual,
3321 rt2800_get_default_vgc(rt2x00dev) +
3322 ((qual->rssi > -80) * 0x10));
3323 }
3324 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3325
3326 /*
3327 * Initialization functions.
3328 */
3329 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3330 {
3331 u32 reg;
3332 u16 eeprom;
3333 unsigned int i;
3334 int ret;
3335
3336 rt2800_disable_wpdma(rt2x00dev);
3337
3338 ret = rt2800_drv_init_registers(rt2x00dev);
3339 if (ret)
3340 return ret;
3341
3342 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3343 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3344 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3345 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3346 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3347 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3348
3349 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3350 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3351 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3352 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3353 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3354 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3355
3356 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3357 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3358
3359 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3360
3361 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3362 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3363 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3364 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3365 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3366 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3367 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3368 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3369
3370 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3371
3372 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3373 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3374 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3375 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3376
3377 if (rt2x00_rt(rt2x00dev, RT3290)) {
3378 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3379 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3380 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3381 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3382 }
3383
3384 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3385 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3386 rt2x00_set_field32(&reg, LDO0_EN, 1);
3387 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3388 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3389 }
3390
3391 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3392 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3393 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3394 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3395 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3396
3397 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3398 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3399 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3400
3401 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3402 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3403 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3404 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3405 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3406 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3407
3408 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3409 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3410 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3411 }
3412
3413 if (rt2x00_rt(rt2x00dev, RT3071) ||
3414 rt2x00_rt(rt2x00dev, RT3090) ||
3415 rt2x00_rt(rt2x00dev, RT3290) ||
3416 rt2x00_rt(rt2x00dev, RT3390)) {
3417
3418 if (rt2x00_rt(rt2x00dev, RT3290))
3419 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3420 0x00000404);
3421 else
3422 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3423 0x00000400);
3424
3425 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3426 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3427 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3428 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3429 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3430 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3431 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3432 0x0000002c);
3433 else
3434 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3435 0x0000000f);
3436 } else {
3437 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3438 }
3439 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3440 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3441
3442 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3443 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3444 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3445 } else {
3446 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3447 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3448 }
3449 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3450 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3451 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3452 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3453 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3454 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3455 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3456 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3457 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3458 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3459 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3460 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3461 rt2x00_rt(rt2x00dev, RT5392) ||
3462 rt2x00_rt(rt2x00dev, RT5592)) {
3463 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3464 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3465 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3466 } else {
3467 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3468 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3469 }
3470
3471 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3472 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3473 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3474 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3475 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3476 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3477 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3478 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3479 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3480 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3481
3482 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3483 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3484 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3485 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3486 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3487
3488 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3489 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3490 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3491 rt2x00_rt(rt2x00dev, RT2883) ||
3492 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3493 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3494 else
3495 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3496 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3497 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3498 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3499
3500 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3501 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3502 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3503 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3504 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3505 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3506 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3507 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3508 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3509
3510 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3511
3512 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3513 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3514 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3515 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3516 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3517 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3518 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3519 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3520
3521 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3522 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3523 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3524 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3525 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3526 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3527 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3528 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3529 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3530
3531 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3532 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3533 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3534 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3535 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3536 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3537 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3538 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3539 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3540 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3541 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3542 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3543
3544 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3545 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3546 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3547 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3548 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3549 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3550 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3551 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3552 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3553 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3554 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3555 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3556
3557 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3558 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3559 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3560 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3561 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3562 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3563 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3564 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3565 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3566 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3567 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3568 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3569
3570 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3571 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3572 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3573 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3574 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3575 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3576 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3577 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3578 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3579 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3580 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3581 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3582
3583 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3584 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3585 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3586 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3587 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3588 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3589 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3590 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3591 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3592 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3593 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3594 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3595
3596 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3597 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3598 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3599 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3600 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3601 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3602 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3603 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3604 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3605 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3606 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3607 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3608
3609 if (rt2x00_is_usb(rt2x00dev)) {
3610 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3611
3612 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3613 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3614 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3615 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3616 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3617 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3618 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3619 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3620 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3621 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3622 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3623 }
3624
3625 /*
3626 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3627 * although it is reserved.
3628 */
3629 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3630 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3631 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3632 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3633 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3634 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3635 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3636 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3637 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3638 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3639 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3640 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3641
3642 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3643 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3644
3645 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3646 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3647 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3648 IEEE80211_MAX_RTS_THRESHOLD);
3649 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3650 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3651
3652 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3653
3654 /*
3655 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3656 * time should be set to 16. However, the original Ralink driver uses
3657 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3658 * connection problems with 11g + CTS protection. Hence, use the same
3659 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3660 */
3661 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3662 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3663 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3664 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3665 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3666 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3667 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3668
3669 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3670
3671 /*
3672 * ASIC will keep garbage value after boot, clear encryption keys.
3673 */
3674 for (i = 0; i < 4; i++)
3675 rt2800_register_write(rt2x00dev,
3676 SHARED_KEY_MODE_ENTRY(i), 0);
3677
3678 for (i = 0; i < 256; i++) {
3679 rt2800_config_wcid(rt2x00dev, NULL, i);
3680 rt2800_delete_wcid_attr(rt2x00dev, i);
3681 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3682 }
3683
3684 /*
3685 * Clear all beacons
3686 */
3687 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3688 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3689 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3690 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3691 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3692 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3693 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3694 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3695
3696 if (rt2x00_is_usb(rt2x00dev)) {
3697 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3698 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3699 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3700 } else if (rt2x00_is_pcie(rt2x00dev)) {
3701 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3702 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3703 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3704 }
3705
3706 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3707 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3708 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3709 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3710 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3711 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3712 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3713 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3714 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3715 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3716
3717 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3718 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3719 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3720 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3721 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3722 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3723 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3724 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3725 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3726 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3727
3728 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3729 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3730 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3731 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3732 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3733 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3734 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3735 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3736 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3737 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3738
3739 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3740 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3741 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3742 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3743 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3744 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3745
3746 /*
3747 * Do not force the BA window size, we use the TXWI to set it
3748 */
3749 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3750 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3751 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3752 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3753
3754 /*
3755 * We must clear the error counters.
3756 * These registers are cleared on read,
3757 * so we may pass a useless variable to store the value.
3758 */
3759 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3760 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3761 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3762 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3763 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3764 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3765
3766 /*
3767 * Setup leadtime for pre tbtt interrupt to 6ms
3768 */
3769 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3770 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3771 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3772
3773 /*
3774 * Set up channel statistics timer
3775 */
3776 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3777 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3778 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3779 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3780 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3781 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3782 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3783
3784 return 0;
3785 }
3786
3787 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3788 {
3789 unsigned int i;
3790 u32 reg;
3791
3792 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3793 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3794 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3795 return 0;
3796
3797 udelay(REGISTER_BUSY_DELAY);
3798 }
3799
3800 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3801 return -EACCES;
3802 }
3803
3804 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3805 {
3806 unsigned int i;
3807 u8 value;
3808
3809 /*
3810 * BBP was enabled after firmware was loaded,
3811 * but we need to reactivate it now.
3812 */
3813 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3814 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3815 msleep(1);
3816
3817 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3818 rt2800_bbp_read(rt2x00dev, 0, &value);
3819 if ((value != 0xff) && (value != 0x00))
3820 return 0;
3821 udelay(REGISTER_BUSY_DELAY);
3822 }
3823
3824 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3825 return -EACCES;
3826 }
3827
3828 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3829 {
3830 u8 value;
3831
3832 rt2800_bbp_read(rt2x00dev, 4, &value);
3833 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3834 rt2800_bbp_write(rt2x00dev, 4, value);
3835 }
3836
3837 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3838 {
3839 rt2800_bbp_write(rt2x00dev, 142, 1);
3840 rt2800_bbp_write(rt2x00dev, 143, 57);
3841 }
3842
3843 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3844 {
3845 const u8 glrt_table[] = {
3846 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3847 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3848 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3849 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3850 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3851 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3853 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3854 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
3855 };
3856 int i;
3857
3858 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3859 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3860 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3861 }
3862 };
3863
3864 static void rt2800_init_bbb_early(struct rt2x00_dev *rt2x00dev)
3865 {
3866 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3867 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3868 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3869 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3870 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3871 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3872 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3873 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3874 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3875 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3876 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3877 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3878 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3879 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3880 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3881 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3882 }
3883
3884 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3885 {
3886 int ant, div_mode;
3887 u16 eeprom;
3888 u8 value;
3889
3890 rt2800_init_bbb_early(rt2x00dev);
3891
3892 rt2800_bbp_read(rt2x00dev, 105, &value);
3893 rt2x00_set_field8(&value, BBP105_MLD,
3894 rt2x00dev->default_ant.rx_chain_num == 2);
3895 rt2800_bbp_write(rt2x00dev, 105, value);
3896
3897 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3898
3899 rt2800_bbp_write(rt2x00dev, 20, 0x06);
3900 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3901 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3902 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3903 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3904 rt2800_bbp_write(rt2x00dev, 70, 0x05);
3905 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3906 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3907 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3908 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3909 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3910 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3911 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3912 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3913 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3914 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3915 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3916 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3917 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3918 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3919 /* FIXME BBP105 owerwrite */
3920 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3921 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3922 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3923 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3924 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3925 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3926
3927 /* Initialize GLRT (Generalized Likehood Radio Test) */
3928 rt2800_init_bbp_5592_glrt(rt2x00dev);
3929
3930 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3931
3932 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3933 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
3934 ant = (div_mode == 3) ? 1 : 0;
3935 rt2800_bbp_read(rt2x00dev, 152, &value);
3936 if (ant == 0) {
3937 /* Main antenna */
3938 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3939 } else {
3940 /* Auxiliary antenna */
3941 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3942 }
3943 rt2800_bbp_write(rt2x00dev, 152, value);
3944
3945 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
3946 rt2800_bbp_read(rt2x00dev, 254, &value);
3947 rt2x00_set_field8(&value, BBP254_BIT7, 1);
3948 rt2800_bbp_write(rt2x00dev, 254, value);
3949 }
3950
3951 rt2800_init_freq_calibration(rt2x00dev);
3952
3953 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3954 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
3955 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3956 }
3957
3958 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3959 {
3960 unsigned int i;
3961 u16 eeprom;
3962 u8 reg_id;
3963 u8 value;
3964
3965 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3966 rt2800_wait_bbp_ready(rt2x00dev)))
3967 return -EACCES;
3968
3969 if (rt2x00_rt(rt2x00dev, RT5592)) {
3970 rt2800_init_bbp_5592(rt2x00dev);
3971 return 0;
3972 }
3973
3974 if (rt2x00_rt(rt2x00dev, RT3352)) {
3975 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3976 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3977 }
3978
3979 if (rt2x00_rt(rt2x00dev, RT3290) ||
3980 rt2x00_rt(rt2x00dev, RT5390) ||
3981 rt2x00_rt(rt2x00dev, RT5392))
3982 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3983
3984 if (rt2800_is_305x_soc(rt2x00dev) ||
3985 rt2x00_rt(rt2x00dev, RT3290) ||
3986 rt2x00_rt(rt2x00dev, RT3352) ||
3987 rt2x00_rt(rt2x00dev, RT3572) ||
3988 rt2x00_rt(rt2x00dev, RT5390) ||
3989 rt2x00_rt(rt2x00dev, RT5392))
3990 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3991
3992 if (rt2x00_rt(rt2x00dev, RT3352))
3993 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3994
3995 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3996 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3997
3998 if (rt2x00_rt(rt2x00dev, RT3290) ||
3999 rt2x00_rt(rt2x00dev, RT3352) ||
4000 rt2x00_rt(rt2x00dev, RT5390) ||
4001 rt2x00_rt(rt2x00dev, RT5392))
4002 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4003
4004 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4005 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4006 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4007 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
4008 rt2x00_rt(rt2x00dev, RT3352) ||
4009 rt2x00_rt(rt2x00dev, RT5390) ||
4010 rt2x00_rt(rt2x00dev, RT5392)) {
4011 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4012 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4013 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4014 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4015
4016 if (rt2x00_rt(rt2x00dev, RT3290))
4017 rt2800_bbp_write(rt2x00dev, 77, 0x58);
4018 else
4019 rt2800_bbp_write(rt2x00dev, 77, 0x59);
4020 } else {
4021 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4022 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4023 }
4024
4025 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4026
4027 if (rt2x00_rt(rt2x00dev, RT3070) ||
4028 rt2x00_rt(rt2x00dev, RT3071) ||
4029 rt2x00_rt(rt2x00dev, RT3090) ||
4030 rt2x00_rt(rt2x00dev, RT3390) ||
4031 rt2x00_rt(rt2x00dev, RT3572) ||
4032 rt2x00_rt(rt2x00dev, RT5390) ||
4033 rt2x00_rt(rt2x00dev, RT5392)) {
4034 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4035 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4036 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4037 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4038 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4039 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4040 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
4041 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4042 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4043 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4044 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4045 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4046 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4047 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4048 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4049 } else {
4050 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4051 }
4052
4053 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4054 if (rt2x00_rt(rt2x00dev, RT3290) ||
4055 rt2x00_rt(rt2x00dev, RT5390) ||
4056 rt2x00_rt(rt2x00dev, RT5392))
4057 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4058 else
4059 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4060
4061 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4062 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4063 else if (rt2x00_rt(rt2x00dev, RT3290) ||
4064 rt2x00_rt(rt2x00dev, RT5390) ||
4065 rt2x00_rt(rt2x00dev, RT5392))
4066 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4067 else
4068 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4069
4070 if (rt2x00_rt(rt2x00dev, RT3290) ||
4071 rt2x00_rt(rt2x00dev, RT3352) ||
4072 rt2x00_rt(rt2x00dev, RT5390) ||
4073 rt2x00_rt(rt2x00dev, RT5392))
4074 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4075 else
4076 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4077
4078 if (rt2x00_rt(rt2x00dev, RT3352) ||
4079 rt2x00_rt(rt2x00dev, RT5392))
4080 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4081
4082 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4083
4084 if (rt2x00_rt(rt2x00dev, RT3290) ||
4085 rt2x00_rt(rt2x00dev, RT3352) ||
4086 rt2x00_rt(rt2x00dev, RT5390) ||
4087 rt2x00_rt(rt2x00dev, RT5392))
4088 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4089 else
4090 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4091
4092 if (rt2x00_rt(rt2x00dev, RT5392)) {
4093 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4094 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4095 }
4096
4097 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4098 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4099 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
4100 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
4101 rt2x00_rt(rt2x00dev, RT3290) ||
4102 rt2x00_rt(rt2x00dev, RT3352) ||
4103 rt2x00_rt(rt2x00dev, RT3572) ||
4104 rt2x00_rt(rt2x00dev, RT5390) ||
4105 rt2x00_rt(rt2x00dev, RT5392) ||
4106 rt2800_is_305x_soc(rt2x00dev))
4107 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4108 else
4109 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4110
4111 if (rt2x00_rt(rt2x00dev, RT3290) ||
4112 rt2x00_rt(rt2x00dev, RT3352) ||
4113 rt2x00_rt(rt2x00dev, RT5390) ||
4114 rt2x00_rt(rt2x00dev, RT5392))
4115 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4116
4117 if (rt2800_is_305x_soc(rt2x00dev))
4118 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4119 else if (rt2x00_rt(rt2x00dev, RT3290))
4120 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4121 else if (rt2x00_rt(rt2x00dev, RT3352))
4122 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4123 else if (rt2x00_rt(rt2x00dev, RT5390) ||
4124 rt2x00_rt(rt2x00dev, RT5392))
4125 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4126 else
4127 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4128
4129 if (rt2x00_rt(rt2x00dev, RT3290) ||
4130 rt2x00_rt(rt2x00dev, RT5390))
4131 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4132 else if (rt2x00_rt(rt2x00dev, RT3352))
4133 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4134 else if (rt2x00_rt(rt2x00dev, RT5392))
4135 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4136 else
4137 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4138
4139 if (rt2x00_rt(rt2x00dev, RT3352))
4140 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4141
4142 if (rt2x00_rt(rt2x00dev, RT3290) ||
4143 rt2x00_rt(rt2x00dev, RT5390) ||
4144 rt2x00_rt(rt2x00dev, RT5392))
4145 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4146
4147 if (rt2x00_rt(rt2x00dev, RT5392)) {
4148 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4149 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4150 }
4151
4152 if (rt2x00_rt(rt2x00dev, RT3352))
4153 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4154
4155 if (rt2x00_rt(rt2x00dev, RT3071) ||
4156 rt2x00_rt(rt2x00dev, RT3090) ||
4157 rt2x00_rt(rt2x00dev, RT3390) ||
4158 rt2x00_rt(rt2x00dev, RT3572) ||
4159 rt2x00_rt(rt2x00dev, RT5390) ||
4160 rt2x00_rt(rt2x00dev, RT5392)) {
4161 rt2800_bbp_read(rt2x00dev, 138, &value);
4162
4163 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4164 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4165 value |= 0x20;
4166 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4167 value &= ~0x02;
4168
4169 rt2800_bbp_write(rt2x00dev, 138, value);
4170 }
4171
4172 if (rt2x00_rt(rt2x00dev, RT3290)) {
4173 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4174 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4175 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4176 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4177 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4178 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4179 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4180 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4181 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4182 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4183
4184 rt2800_bbp_read(rt2x00dev, 47, &value);
4185 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4186 rt2800_bbp_write(rt2x00dev, 47, value);
4187
4188 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4189 rt2800_bbp_read(rt2x00dev, 3, &value);
4190 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4191 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4192 rt2800_bbp_write(rt2x00dev, 3, value);
4193 }
4194
4195 if (rt2x00_rt(rt2x00dev, RT3352)) {
4196 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4197 /* Set ITxBF timeout to 0x9c40=1000msec */
4198 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4199 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4200 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4201 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4202 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4203 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4204 /* Reprogram the inband interface to put right values in RXWI */
4205 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4206 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4207 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4208 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4209 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4210 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4211 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4212 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4213
4214 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4215 }
4216
4217 if (rt2x00_rt(rt2x00dev, RT5390) ||
4218 rt2x00_rt(rt2x00dev, RT5392)) {
4219 int ant, div_mode;
4220
4221 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4222 div_mode = rt2x00_get_field16(eeprom,
4223 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4224 ant = (div_mode == 3) ? 1 : 0;
4225
4226 /* check if this is a Bluetooth combo card */
4227 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4228 u32 reg;
4229
4230 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4231 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4232 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4233 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4234 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4235 if (ant == 0)
4236 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4237 else if (ant == 1)
4238 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4239 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4240 }
4241
4242 /* This chip has hardware antenna diversity*/
4243 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4244 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4245 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4246 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4247 }
4248
4249 rt2800_bbp_read(rt2x00dev, 152, &value);
4250 if (ant == 0)
4251 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4252 else
4253 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4254 rt2800_bbp_write(rt2x00dev, 152, value);
4255
4256 rt2800_init_freq_calibration(rt2x00dev);
4257 }
4258
4259 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4260 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4261
4262 if (eeprom != 0xffff && eeprom != 0x0000) {
4263 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4264 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4265 rt2800_bbp_write(rt2x00dev, reg_id, value);
4266 }
4267 }
4268
4269 return 0;
4270 }
4271
4272 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
4273 bool bw40, u8 rfcsr24, u8 filter_target)
4274 {
4275 unsigned int i;
4276 u8 bbp;
4277 u8 rfcsr;
4278 u8 passband;
4279 u8 stopband;
4280 u8 overtuned = 0;
4281
4282 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4283
4284 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4285 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4286 rt2800_bbp_write(rt2x00dev, 4, bbp);
4287
4288 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4289 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4290 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4291
4292 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4293 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4294 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4295
4296 /*
4297 * Set power & frequency of passband test tone
4298 */
4299 rt2800_bbp_write(rt2x00dev, 24, 0);
4300
4301 for (i = 0; i < 100; i++) {
4302 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4303 msleep(1);
4304
4305 rt2800_bbp_read(rt2x00dev, 55, &passband);
4306 if (passband)
4307 break;
4308 }
4309
4310 /*
4311 * Set power & frequency of stopband test tone
4312 */
4313 rt2800_bbp_write(rt2x00dev, 24, 0x06);
4314
4315 for (i = 0; i < 100; i++) {
4316 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4317 msleep(1);
4318
4319 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4320
4321 if ((passband - stopband) <= filter_target) {
4322 rfcsr24++;
4323 overtuned += ((passband - stopband) == filter_target);
4324 } else
4325 break;
4326
4327 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4328 }
4329
4330 rfcsr24 -= !!overtuned;
4331
4332 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4333 return rfcsr24;
4334 }
4335
4336 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4337 {
4338 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4339 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4340 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4341 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4342 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4343 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4344 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4345 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4346 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4347 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4348 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4349 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4350 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4351 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4352 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4353 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4354 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4355 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4356 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4357 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4358 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4359 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4360 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4361 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4362 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4363 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4364 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4365 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4366 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4367 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4368 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4369 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4370 }
4371
4372 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4373 {
4374 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4375 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4376 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4377 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4378 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4379 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4380 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4381 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4382 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4383 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4384 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4385 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4386 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4387 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4388 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4389 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4390 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4391 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4392 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4393 }
4394
4395 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4396 {
4397 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4398 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4399 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4400 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4401 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4402 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4403 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4404 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4405 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4406 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4407 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4408 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4409 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4410 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4411 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4412 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4413 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4414 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4415 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4416 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4417 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4418 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4419 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4420 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4421 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4422 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4423 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4424 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4425 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4426 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4427 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4428 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4429 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4430 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4431 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4432 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4433 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4434 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4435 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4436 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4437 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4438 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4439 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4440 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4441 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4442 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4443 }
4444
4445 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4446 {
4447 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4448 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4449 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4450 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4451 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4452 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4453 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4454 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4455 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4456 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4457 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4458 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4459 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4460 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4461 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4462 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4463 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4464 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4465 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4466 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4467 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4468 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4469 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4470 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4471 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4472 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4473 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4474 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4475 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4476 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4477 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4478 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4479 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4480 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4481 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4482 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4483 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4484 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4485 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4486 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4487 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4488 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4489 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4490 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4491 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4492 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4493 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4494 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4495 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4496 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4497 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4498 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4499 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4500 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4501 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4502 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4503 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4504 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4505 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4506 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4507 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4508 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4509 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4510 }
4511
4512 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4513 {
4514 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4515 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4516 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4517 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4518 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4519 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4520 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4521 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4522 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4523 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4524 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4525 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4526 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4527 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4528 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4529 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4530 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4531 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4532 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4533 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4534 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4535 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4536 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4537 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4538 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4539 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4540 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4541 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4542 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4543 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4544 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4545 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4546 }
4547
4548 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4549 {
4550 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4551 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4552 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4553 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4554 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4555 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4556 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4557 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4558 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4559 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4560 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4561 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4562 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4563 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4564 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4565 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4566 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4567 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4568 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4569 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4570 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4571 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4572 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4573 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4574 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4575 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4576 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4577 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4578 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4579 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4580 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4581 }
4582
4583 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4584 {
4585 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4586 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4587 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4588 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4589 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4590 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4591 else
4592 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4593 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4594 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4595 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4596 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4597 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4598 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4599 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4600 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4601 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4602 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4603
4604 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4605 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4606 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4607 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4608 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4609 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4610 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4611 else
4612 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4613 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4614 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4615 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4616 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4617
4618 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4619 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4620 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4621 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4622 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4623 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4624 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4625 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4626 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4627 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4628
4629 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4630 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4631 else
4632 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4633 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4634 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4635 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4636 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4637 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4638 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4639 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4640 else
4641 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4642 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4643 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4644 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4645
4646 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4647 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4648 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4649 else
4650 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4651 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4652 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4653 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4654 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4655 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4656 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4657
4658 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4659 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4660 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4661 else
4662 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4663 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4664 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4665 }
4666
4667 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4668 {
4669 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4670 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4671 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4672 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4673 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4674 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4675 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4676 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4677 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4678 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4679 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4680 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4681 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4682 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4683 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4684 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4685 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4686 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4687 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4688 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4689 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4690 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4691 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4692 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4693 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4694 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4695 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4696 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4697 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4698 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4699 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4700 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4701 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4702 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4703 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4704 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4705 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4706 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4707 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4708 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4709 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4710 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4711 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4712 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4713 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4714 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4715 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4716 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4717 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4718 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4719 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4720 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4721 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4722 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4723 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4724 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4725 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4726 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4727 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4728 }
4729
4730 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
4731 {
4732 u8 reg;
4733 u16 eeprom;
4734
4735 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
4736 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4737 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4738 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4739 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
4740 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4741 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4742 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4743 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4744 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4745 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
4746 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
4747 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
4748 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4749 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4750 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4751 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4752 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4753 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4754 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
4755 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
4756 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4757
4758 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4759 msleep(1);
4760
4761 rt2800_adjust_freq_offset(rt2x00dev);
4762
4763 rt2800_bbp_read(rt2x00dev, 138, &reg);
4764
4765 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4766 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4767 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4768 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4769 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4770 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4771
4772 rt2800_bbp_write(rt2x00dev, 138, reg);
4773
4774 /* Enable DC filter */
4775 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4776 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4777
4778 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4779 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4780 rt2800_rfcsr_write(rt2x00dev, 38, reg);
4781
4782 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4783 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4784 rt2800_rfcsr_write(rt2x00dev, 39, reg);
4785
4786 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4787
4788 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4789 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4790 rt2800_rfcsr_write(rt2x00dev, 30, reg);
4791 }
4792
4793 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4794 {
4795 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4796 u8 rfcsr;
4797 u8 bbp;
4798 u32 reg;
4799 u16 eeprom;
4800
4801 if (!rt2x00_rt(rt2x00dev, RT3070) &&
4802 !rt2x00_rt(rt2x00dev, RT3071) &&
4803 !rt2x00_rt(rt2x00dev, RT3090) &&
4804 !rt2x00_rt(rt2x00dev, RT3290) &&
4805 !rt2x00_rt(rt2x00dev, RT3352) &&
4806 !rt2x00_rt(rt2x00dev, RT3390) &&
4807 !rt2x00_rt(rt2x00dev, RT3572) &&
4808 !rt2x00_rt(rt2x00dev, RT5390) &&
4809 !rt2x00_rt(rt2x00dev, RT5392) &&
4810 !rt2x00_rt(rt2x00dev, RT5392) &&
4811 !rt2x00_rt(rt2x00dev, RT5592) &&
4812 !rt2800_is_305x_soc(rt2x00dev))
4813 return 0;
4814
4815 /*
4816 * Init RF calibration.
4817 */
4818
4819 if (rt2x00_rt(rt2x00dev, RT3290) ||
4820 rt2x00_rt(rt2x00dev, RT5390) ||
4821 rt2x00_rt(rt2x00dev, RT5392)) {
4822 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4823 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4824 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4825 msleep(1);
4826 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4827 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4828 } else {
4829 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4830 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4831 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4832 msleep(1);
4833 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4834 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4835 }
4836
4837 if (rt2800_is_305x_soc(rt2x00dev)) {
4838 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4839 return 0;
4840 }
4841
4842 switch (rt2x00dev->chip.rt) {
4843 case RT3070:
4844 case RT3071:
4845 case RT3090:
4846 rt2800_init_rfcsr_30xx(rt2x00dev);
4847 break;
4848 case RT3290:
4849 rt2800_init_rfcsr_3290(rt2x00dev);
4850 break;
4851 case RT3352:
4852 rt2800_init_rfcsr_3352(rt2x00dev);
4853 break;
4854 case RT3390:
4855 rt2800_init_rfcsr_3390(rt2x00dev);
4856 break;
4857 case RT3572:
4858 rt2800_init_rfcsr_3572(rt2x00dev);
4859 break;
4860 case RT5390:
4861 rt2800_init_rfcsr_5390(rt2x00dev);
4862 break;
4863 case RT5392:
4864 rt2800_init_rfcsr_5392(rt2x00dev);
4865 break;
4866 case RT5592:
4867 rt2800_init_rfcsr_5592(rt2x00dev);
4868 return 0;
4869 }
4870
4871 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4872 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4873 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4874 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4875 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4876 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4877 rt2x00_rt(rt2x00dev, RT3090)) {
4878 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4879
4880 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4881 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4882 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4883
4884 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4885 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4886 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4887 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4888 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4889 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4890 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4891 else
4892 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4893 }
4894 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4895
4896 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4897 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4898 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4899 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4900 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4901 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4902 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4903 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4904 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4905 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4906 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4907
4908 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4909 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4910 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4911 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4912 msleep(1);
4913 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4914 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4915 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4916 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4917 }
4918
4919 /*
4920 * Set RX Filter calibration for 20MHz and 40MHz
4921 */
4922 if (rt2x00_rt(rt2x00dev, RT3070)) {
4923 drv_data->calibration_bw20 =
4924 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4925 drv_data->calibration_bw40 =
4926 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4927 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4928 rt2x00_rt(rt2x00dev, RT3090) ||
4929 rt2x00_rt(rt2x00dev, RT3352) ||
4930 rt2x00_rt(rt2x00dev, RT3390) ||
4931 rt2x00_rt(rt2x00dev, RT3572)) {
4932 drv_data->calibration_bw20 =
4933 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4934 drv_data->calibration_bw40 =
4935 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4936 }
4937
4938 /*
4939 * Save BBP 25 & 26 values for later use in channel switching
4940 */
4941 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4942 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4943
4944 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4945 !rt2x00_rt(rt2x00dev, RT5392)) {
4946 /*
4947 * Set back to initial state
4948 */
4949 rt2800_bbp_write(rt2x00dev, 24, 0);
4950
4951 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4952 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4953 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4954
4955 /*
4956 * Set BBP back to BW20
4957 */
4958 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4959 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4960 rt2800_bbp_write(rt2x00dev, 4, bbp);
4961 }
4962
4963 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4964 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4965 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4966 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E) ||
4967 rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
4968 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4969
4970 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4971 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4972 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4973
4974 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4975 !rt2x00_rt(rt2x00dev, RT5392)) {
4976 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4977 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4978 if (rt2x00_rt(rt2x00dev, RT3070) ||
4979 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4980 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4981 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4982 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4983 &rt2x00dev->cap_flags))
4984 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4985 }
4986 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4987 drv_data->txmixer_gain_24g);
4988 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4989 }
4990
4991 if (rt2x00_rt(rt2x00dev, RT3090) ||
4992 rt2x00_rt(rt2x00dev, RT5592)) {
4993 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4994
4995 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4996 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4997 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4998 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4999 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5000 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5001
5002 rt2800_bbp_write(rt2x00dev, 138, bbp);
5003 }
5004
5005 if (rt2x00_rt(rt2x00dev, RT3071) ||
5006 rt2x00_rt(rt2x00dev, RT3090) ||
5007 rt2x00_rt(rt2x00dev, RT3390)) {
5008 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5009 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5010 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5011 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5012 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5013 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5014 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5015
5016 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5017 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5018 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5019
5020 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5021 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5022 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5023
5024 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5025 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5026 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5027 }
5028
5029 if (rt2x00_rt(rt2x00dev, RT3070)) {
5030 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5031 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5032 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5033 else
5034 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5035 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5036 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5037 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5038 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5039 }
5040
5041 if (rt2x00_rt(rt2x00dev, RT3290)) {
5042 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
5043 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
5044 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
5045 }
5046
5047 if (rt2x00_rt(rt2x00dev, RT5390) ||
5048 rt2x00_rt(rt2x00dev, RT5392) ||
5049 rt2x00_rt(rt2x00dev, RT5592)) {
5050 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5051 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5052 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5053
5054 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5055 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5056 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5057
5058 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5059 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5060 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5061 }
5062
5063 return 0;
5064 }
5065
5066 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5067 {
5068 u32 reg;
5069 u16 word;
5070
5071 /*
5072 * Initialize all registers.
5073 */
5074 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
5075 rt2800_init_registers(rt2x00dev)))
5076 return -EIO;
5077
5078 /*
5079 * Send signal to firmware during boot time.
5080 */
5081 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5082 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5083 if (rt2x00_is_usb(rt2x00dev)) {
5084 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5085 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5086 }
5087 msleep(1);
5088
5089 if (unlikely(rt2800_init_bbp(rt2x00dev) ||
5090 rt2800_init_rfcsr(rt2x00dev)))
5091 return -EIO;
5092
5093 if (rt2x00_is_usb(rt2x00dev) &&
5094 (rt2x00_rt(rt2x00dev, RT3070) ||
5095 rt2x00_rt(rt2x00dev, RT3071) ||
5096 rt2x00_rt(rt2x00dev, RT3572))) {
5097 udelay(200);
5098 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5099 udelay(10);
5100 }
5101
5102 /*
5103 * Enable RX.
5104 */
5105 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5106 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5107 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5108 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5109
5110 udelay(50);
5111
5112 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5113 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5114 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5115 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5116 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5117 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5118
5119 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5120 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5121 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5122 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5123
5124 /*
5125 * Initialize LED control
5126 */
5127 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
5128 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
5129 word & 0xff, (word >> 8) & 0xff);
5130
5131 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5132 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
5133 word & 0xff, (word >> 8) & 0xff);
5134
5135 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5136 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
5137 word & 0xff, (word >> 8) & 0xff);
5138
5139 return 0;
5140 }
5141 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5142
5143 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5144 {
5145 u32 reg;
5146
5147 rt2800_disable_wpdma(rt2x00dev);
5148
5149 /* Wait for DMA, ignore error */
5150 rt2800_wait_wpdma_ready(rt2x00dev);
5151
5152 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5153 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5154 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5155 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5156 }
5157 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
5158
5159 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5160 {
5161 u32 reg;
5162 u16 efuse_ctrl_reg;
5163
5164 if (rt2x00_rt(rt2x00dev, RT3290))
5165 efuse_ctrl_reg = EFUSE_CTRL_3290;
5166 else
5167 efuse_ctrl_reg = EFUSE_CTRL;
5168
5169 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
5170 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5171 }
5172 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5173
5174 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5175 {
5176 u32 reg;
5177 u16 efuse_ctrl_reg;
5178 u16 efuse_data0_reg;
5179 u16 efuse_data1_reg;
5180 u16 efuse_data2_reg;
5181 u16 efuse_data3_reg;
5182
5183 if (rt2x00_rt(rt2x00dev, RT3290)) {
5184 efuse_ctrl_reg = EFUSE_CTRL_3290;
5185 efuse_data0_reg = EFUSE_DATA0_3290;
5186 efuse_data1_reg = EFUSE_DATA1_3290;
5187 efuse_data2_reg = EFUSE_DATA2_3290;
5188 efuse_data3_reg = EFUSE_DATA3_3290;
5189 } else {
5190 efuse_ctrl_reg = EFUSE_CTRL;
5191 efuse_data0_reg = EFUSE_DATA0;
5192 efuse_data1_reg = EFUSE_DATA1;
5193 efuse_data2_reg = EFUSE_DATA2;
5194 efuse_data3_reg = EFUSE_DATA3;
5195 }
5196 mutex_lock(&rt2x00dev->csr_mutex);
5197
5198 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5199 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5200 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5201 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5202 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5203
5204 /* Wait until the EEPROM has been loaded */
5205 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5206 /* Apparently the data is read from end to start */
5207 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5208 /* The returned value is in CPU order, but eeprom is le */
5209 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5210 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5211 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5212 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5213 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5214 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5215 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5216
5217 mutex_unlock(&rt2x00dev->csr_mutex);
5218 }
5219
5220 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5221 {
5222 unsigned int i;
5223
5224 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5225 rt2800_efuse_read(rt2x00dev, i);
5226
5227 return 0;
5228 }
5229 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5230
5231 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5232 {
5233 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5234 u16 word;
5235 u8 *mac;
5236 u8 default_lna_gain;
5237 int retval;
5238
5239 /*
5240 * Read the EEPROM.
5241 */
5242 retval = rt2800_read_eeprom(rt2x00dev);
5243 if (retval)
5244 return retval;
5245
5246 /*
5247 * Start validation of the data that has been read.
5248 */
5249 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5250 if (!is_valid_ether_addr(mac)) {
5251 eth_random_addr(mac);
5252 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
5253 }
5254
5255 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5256 if (word == 0xffff) {
5257 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5258 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5259 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5260 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5261 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5262 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5263 rt2x00_rt(rt2x00dev, RT2872)) {
5264 /*
5265 * There is a max of 2 RX streams for RT28x0 series
5266 */
5267 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5268 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5269 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5270 }
5271
5272 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5273 if (word == 0xffff) {
5274 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5275 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5276 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5277 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5278 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5279 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5280 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5281 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5282 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5283 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5284 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5285 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5286 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5287 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5288 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5289 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5290 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
5291 }
5292
5293 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5294 if ((word & 0x00ff) == 0x00ff) {
5295 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5296 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5297 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
5298 }
5299 if ((word & 0xff00) == 0xff00) {
5300 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5301 LED_MODE_TXRX_ACTIVITY);
5302 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5303 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5304 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5305 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5306 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5307 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
5308 }
5309
5310 /*
5311 * During the LNA validation we are going to use
5312 * lna0 as correct value. Note that EEPROM_LNA
5313 * is never validated.
5314 */
5315 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5316 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5317
5318 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5319 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5320 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5321 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5322 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5323 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5324
5325 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5326 if ((word & 0x00ff) != 0x00ff) {
5327 drv_data->txmixer_gain_24g =
5328 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5329 } else {
5330 drv_data->txmixer_gain_24g = 0;
5331 }
5332
5333 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5334 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5335 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5336 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5337 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5338 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5339 default_lna_gain);
5340 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5341
5342 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5343 if ((word & 0x00ff) != 0x00ff) {
5344 drv_data->txmixer_gain_5g =
5345 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5346 } else {
5347 drv_data->txmixer_gain_5g = 0;
5348 }
5349
5350 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5351 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5352 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5353 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5354 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5355 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5356
5357 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5358 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5359 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5360 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5361 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5362 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5363 default_lna_gain);
5364 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5365
5366 return 0;
5367 }
5368
5369 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5370 {
5371 u32 reg;
5372 u16 value;
5373 u16 eeprom;
5374
5375 /*
5376 * Read EEPROM word for configuration.
5377 */
5378 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5379
5380 /*
5381 * Identify RF chipset by EEPROM value
5382 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5383 * RT53xx: defined in "EEPROM_CHIP_ID" field
5384 */
5385 if (rt2x00_rt(rt2x00dev, RT3290))
5386 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
5387 else
5388 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
5389
5390 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
5391 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
5392 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
5393 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
5394 else
5395 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5396
5397 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
5398 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
5399
5400 switch (rt2x00dev->chip.rt) {
5401 case RT2860:
5402 case RT2872:
5403 case RT2883:
5404 case RT3070:
5405 case RT3071:
5406 case RT3090:
5407 case RT3290:
5408 case RT3352:
5409 case RT3390:
5410 case RT3572:
5411 case RT5390:
5412 case RT5392:
5413 case RT5592:
5414 break;
5415 default:
5416 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
5417 return -ENODEV;
5418 }
5419
5420 switch (rt2x00dev->chip.rf) {
5421 case RF2820:
5422 case RF2850:
5423 case RF2720:
5424 case RF2750:
5425 case RF3020:
5426 case RF2020:
5427 case RF3021:
5428 case RF3022:
5429 case RF3052:
5430 case RF3290:
5431 case RF3320:
5432 case RF3322:
5433 case RF5360:
5434 case RF5370:
5435 case RF5372:
5436 case RF5390:
5437 case RF5392:
5438 case RF5592:
5439 break;
5440 default:
5441 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
5442 rt2x00dev->chip.rf);
5443 return -ENODEV;
5444 }
5445
5446 /*
5447 * Identify default antenna configuration.
5448 */
5449 rt2x00dev->default_ant.tx_chain_num =
5450 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5451 rt2x00dev->default_ant.rx_chain_num =
5452 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5453
5454 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5455
5456 if (rt2x00_rt(rt2x00dev, RT3070) ||
5457 rt2x00_rt(rt2x00dev, RT3090) ||
5458 rt2x00_rt(rt2x00dev, RT3352) ||
5459 rt2x00_rt(rt2x00dev, RT3390)) {
5460 value = rt2x00_get_field16(eeprom,
5461 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5462 switch (value) {
5463 case 0:
5464 case 1:
5465 case 2:
5466 rt2x00dev->default_ant.tx = ANTENNA_A;
5467 rt2x00dev->default_ant.rx = ANTENNA_A;
5468 break;
5469 case 3:
5470 rt2x00dev->default_ant.tx = ANTENNA_A;
5471 rt2x00dev->default_ant.rx = ANTENNA_B;
5472 break;
5473 }
5474 } else {
5475 rt2x00dev->default_ant.tx = ANTENNA_A;
5476 rt2x00dev->default_ant.rx = ANTENNA_A;
5477 }
5478
5479 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5480 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5481 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5482 }
5483
5484 /*
5485 * Determine external LNA informations.
5486 */
5487 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5488 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5489 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5490 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5491
5492 /*
5493 * Detect if this device has an hardware controlled radio.
5494 */
5495 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5496 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5497
5498 /*
5499 * Detect if this device has Bluetooth co-existence.
5500 */
5501 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5502 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5503
5504 /*
5505 * Read frequency offset and RF programming sequence.
5506 */
5507 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5508 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5509
5510 /*
5511 * Store led settings, for correct led behaviour.
5512 */
5513 #ifdef CONFIG_RT2X00_LIB_LEDS
5514 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5515 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5516 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5517
5518 rt2x00dev->led_mcu_reg = eeprom;
5519 #endif /* CONFIG_RT2X00_LIB_LEDS */
5520
5521 /*
5522 * Check if support EIRP tx power limit feature.
5523 */
5524 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5525
5526 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5527 EIRP_MAX_TX_POWER_LIMIT)
5528 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5529
5530 return 0;
5531 }
5532
5533 /*
5534 * RF value list for rt28xx
5535 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5536 */
5537 static const struct rf_channel rf_vals[] = {
5538 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5539 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5540 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5541 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5542 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5543 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5544 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5545 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5546 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5547 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5548 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5549 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5550 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5551 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5552
5553 /* 802.11 UNI / HyperLan 2 */
5554 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5555 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5556 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5557 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5558 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5559 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5560 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5561 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5562 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5563 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5564 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5565 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5566
5567 /* 802.11 HyperLan 2 */
5568 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5569 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5570 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5571 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5572 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5573 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5574 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5575 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5576 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5577 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5578 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5579 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5580 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5581 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5582 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5583 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5584
5585 /* 802.11 UNII */
5586 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5587 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5588 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5589 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5590 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5591 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5592 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5593 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5594 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5595 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5596 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5597
5598 /* 802.11 Japan */
5599 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5600 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5601 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5602 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5603 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5604 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5605 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5606 };
5607
5608 /*
5609 * RF value list for rt3xxx
5610 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5611 */
5612 static const struct rf_channel rf_vals_3x[] = {
5613 {1, 241, 2, 2 },
5614 {2, 241, 2, 7 },
5615 {3, 242, 2, 2 },
5616 {4, 242, 2, 7 },
5617 {5, 243, 2, 2 },
5618 {6, 243, 2, 7 },
5619 {7, 244, 2, 2 },
5620 {8, 244, 2, 7 },
5621 {9, 245, 2, 2 },
5622 {10, 245, 2, 7 },
5623 {11, 246, 2, 2 },
5624 {12, 246, 2, 7 },
5625 {13, 247, 2, 2 },
5626 {14, 248, 2, 4 },
5627
5628 /* 802.11 UNI / HyperLan 2 */
5629 {36, 0x56, 0, 4},
5630 {38, 0x56, 0, 6},
5631 {40, 0x56, 0, 8},
5632 {44, 0x57, 0, 0},
5633 {46, 0x57, 0, 2},
5634 {48, 0x57, 0, 4},
5635 {52, 0x57, 0, 8},
5636 {54, 0x57, 0, 10},
5637 {56, 0x58, 0, 0},
5638 {60, 0x58, 0, 4},
5639 {62, 0x58, 0, 6},
5640 {64, 0x58, 0, 8},
5641
5642 /* 802.11 HyperLan 2 */
5643 {100, 0x5b, 0, 8},
5644 {102, 0x5b, 0, 10},
5645 {104, 0x5c, 0, 0},
5646 {108, 0x5c, 0, 4},
5647 {110, 0x5c, 0, 6},
5648 {112, 0x5c, 0, 8},
5649 {116, 0x5d, 0, 0},
5650 {118, 0x5d, 0, 2},
5651 {120, 0x5d, 0, 4},
5652 {124, 0x5d, 0, 8},
5653 {126, 0x5d, 0, 10},
5654 {128, 0x5e, 0, 0},
5655 {132, 0x5e, 0, 4},
5656 {134, 0x5e, 0, 6},
5657 {136, 0x5e, 0, 8},
5658 {140, 0x5f, 0, 0},
5659
5660 /* 802.11 UNII */
5661 {149, 0x5f, 0, 9},
5662 {151, 0x5f, 0, 11},
5663 {153, 0x60, 0, 1},
5664 {157, 0x60, 0, 5},
5665 {159, 0x60, 0, 7},
5666 {161, 0x60, 0, 9},
5667 {165, 0x61, 0, 1},
5668 {167, 0x61, 0, 3},
5669 {169, 0x61, 0, 5},
5670 {171, 0x61, 0, 7},
5671 {173, 0x61, 0, 9},
5672 };
5673
5674 static const struct rf_channel rf_vals_5592_xtal20[] = {
5675 /* Channel, N, K, mod, R */
5676 {1, 482, 4, 10, 3},
5677 {2, 483, 4, 10, 3},
5678 {3, 484, 4, 10, 3},
5679 {4, 485, 4, 10, 3},
5680 {5, 486, 4, 10, 3},
5681 {6, 487, 4, 10, 3},
5682 {7, 488, 4, 10, 3},
5683 {8, 489, 4, 10, 3},
5684 {9, 490, 4, 10, 3},
5685 {10, 491, 4, 10, 3},
5686 {11, 492, 4, 10, 3},
5687 {12, 493, 4, 10, 3},
5688 {13, 494, 4, 10, 3},
5689 {14, 496, 8, 10, 3},
5690 {36, 172, 8, 12, 1},
5691 {38, 173, 0, 12, 1},
5692 {40, 173, 4, 12, 1},
5693 {42, 173, 8, 12, 1},
5694 {44, 174, 0, 12, 1},
5695 {46, 174, 4, 12, 1},
5696 {48, 174, 8, 12, 1},
5697 {50, 175, 0, 12, 1},
5698 {52, 175, 4, 12, 1},
5699 {54, 175, 8, 12, 1},
5700 {56, 176, 0, 12, 1},
5701 {58, 176, 4, 12, 1},
5702 {60, 176, 8, 12, 1},
5703 {62, 177, 0, 12, 1},
5704 {64, 177, 4, 12, 1},
5705 {100, 183, 4, 12, 1},
5706 {102, 183, 8, 12, 1},
5707 {104, 184, 0, 12, 1},
5708 {106, 184, 4, 12, 1},
5709 {108, 184, 8, 12, 1},
5710 {110, 185, 0, 12, 1},
5711 {112, 185, 4, 12, 1},
5712 {114, 185, 8, 12, 1},
5713 {116, 186, 0, 12, 1},
5714 {118, 186, 4, 12, 1},
5715 {120, 186, 8, 12, 1},
5716 {122, 187, 0, 12, 1},
5717 {124, 187, 4, 12, 1},
5718 {126, 187, 8, 12, 1},
5719 {128, 188, 0, 12, 1},
5720 {130, 188, 4, 12, 1},
5721 {132, 188, 8, 12, 1},
5722 {134, 189, 0, 12, 1},
5723 {136, 189, 4, 12, 1},
5724 {138, 189, 8, 12, 1},
5725 {140, 190, 0, 12, 1},
5726 {149, 191, 6, 12, 1},
5727 {151, 191, 10, 12, 1},
5728 {153, 192, 2, 12, 1},
5729 {155, 192, 6, 12, 1},
5730 {157, 192, 10, 12, 1},
5731 {159, 193, 2, 12, 1},
5732 {161, 193, 6, 12, 1},
5733 {165, 194, 2, 12, 1},
5734 {184, 164, 0, 12, 1},
5735 {188, 164, 4, 12, 1},
5736 {192, 165, 8, 12, 1},
5737 {196, 166, 0, 12, 1},
5738 };
5739
5740 static const struct rf_channel rf_vals_5592_xtal40[] = {
5741 /* Channel, N, K, mod, R */
5742 {1, 241, 2, 10, 3},
5743 {2, 241, 7, 10, 3},
5744 {3, 242, 2, 10, 3},
5745 {4, 242, 7, 10, 3},
5746 {5, 243, 2, 10, 3},
5747 {6, 243, 7, 10, 3},
5748 {7, 244, 2, 10, 3},
5749 {8, 244, 7, 10, 3},
5750 {9, 245, 2, 10, 3},
5751 {10, 245, 7, 10, 3},
5752 {11, 246, 2, 10, 3},
5753 {12, 246, 7, 10, 3},
5754 {13, 247, 2, 10, 3},
5755 {14, 248, 4, 10, 3},
5756 {36, 86, 4, 12, 1},
5757 {38, 86, 6, 12, 1},
5758 {40, 86, 8, 12, 1},
5759 {42, 86, 10, 12, 1},
5760 {44, 87, 0, 12, 1},
5761 {46, 87, 2, 12, 1},
5762 {48, 87, 4, 12, 1},
5763 {50, 87, 6, 12, 1},
5764 {52, 87, 8, 12, 1},
5765 {54, 87, 10, 12, 1},
5766 {56, 88, 0, 12, 1},
5767 {58, 88, 2, 12, 1},
5768 {60, 88, 4, 12, 1},
5769 {62, 88, 6, 12, 1},
5770 {64, 88, 8, 12, 1},
5771 {100, 91, 8, 12, 1},
5772 {102, 91, 10, 12, 1},
5773 {104, 92, 0, 12, 1},
5774 {106, 92, 2, 12, 1},
5775 {108, 92, 4, 12, 1},
5776 {110, 92, 6, 12, 1},
5777 {112, 92, 8, 12, 1},
5778 {114, 92, 10, 12, 1},
5779 {116, 93, 0, 12, 1},
5780 {118, 93, 2, 12, 1},
5781 {120, 93, 4, 12, 1},
5782 {122, 93, 6, 12, 1},
5783 {124, 93, 8, 12, 1},
5784 {126, 93, 10, 12, 1},
5785 {128, 94, 0, 12, 1},
5786 {130, 94, 2, 12, 1},
5787 {132, 94, 4, 12, 1},
5788 {134, 94, 6, 12, 1},
5789 {136, 94, 8, 12, 1},
5790 {138, 94, 10, 12, 1},
5791 {140, 95, 0, 12, 1},
5792 {149, 95, 9, 12, 1},
5793 {151, 95, 11, 12, 1},
5794 {153, 96, 1, 12, 1},
5795 {155, 96, 3, 12, 1},
5796 {157, 96, 5, 12, 1},
5797 {159, 96, 7, 12, 1},
5798 {161, 96, 9, 12, 1},
5799 {165, 97, 1, 12, 1},
5800 {184, 82, 0, 12, 1},
5801 {188, 82, 4, 12, 1},
5802 {192, 82, 8, 12, 1},
5803 {196, 83, 0, 12, 1},
5804 };
5805
5806 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5807 {
5808 struct hw_mode_spec *spec = &rt2x00dev->spec;
5809 struct channel_info *info;
5810 char *default_power1;
5811 char *default_power2;
5812 unsigned int i;
5813 u16 eeprom;
5814 u32 reg;
5815
5816 /*
5817 * Disable powersaving as default on PCI devices.
5818 */
5819 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5820 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5821
5822 /*
5823 * Initialize all hw fields.
5824 */
5825 rt2x00dev->hw->flags =
5826 IEEE80211_HW_SIGNAL_DBM |
5827 IEEE80211_HW_SUPPORTS_PS |
5828 IEEE80211_HW_PS_NULLFUNC_STACK |
5829 IEEE80211_HW_AMPDU_AGGREGATION |
5830 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5831
5832 /*
5833 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5834 * unless we are capable of sending the buffered frames out after the
5835 * DTIM transmission using rt2x00lib_beacondone. This will send out
5836 * multicast and broadcast traffic immediately instead of buffering it
5837 * infinitly and thus dropping it after some time.
5838 */
5839 if (!rt2x00_is_usb(rt2x00dev))
5840 rt2x00dev->hw->flags |=
5841 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5842
5843 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5844 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5845 rt2x00_eeprom_addr(rt2x00dev,
5846 EEPROM_MAC_ADDR_0));
5847
5848 /*
5849 * As rt2800 has a global fallback table we cannot specify
5850 * more then one tx rate per frame but since the hw will
5851 * try several rates (based on the fallback table) we should
5852 * initialize max_report_rates to the maximum number of rates
5853 * we are going to try. Otherwise mac80211 will truncate our
5854 * reported tx rates and the rc algortihm will end up with
5855 * incorrect data.
5856 */
5857 rt2x00dev->hw->max_rates = 1;
5858 rt2x00dev->hw->max_report_rates = 7;
5859 rt2x00dev->hw->max_rate_tries = 1;
5860
5861 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5862
5863 /*
5864 * Initialize hw_mode information.
5865 */
5866 spec->supported_bands = SUPPORT_BAND_2GHZ;
5867 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5868
5869 if (rt2x00_rf(rt2x00dev, RF2820) ||
5870 rt2x00_rf(rt2x00dev, RF2720)) {
5871 spec->num_channels = 14;
5872 spec->channels = rf_vals;
5873 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5874 rt2x00_rf(rt2x00dev, RF2750)) {
5875 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5876 spec->num_channels = ARRAY_SIZE(rf_vals);
5877 spec->channels = rf_vals;
5878 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5879 rt2x00_rf(rt2x00dev, RF2020) ||
5880 rt2x00_rf(rt2x00dev, RF3021) ||
5881 rt2x00_rf(rt2x00dev, RF3022) ||
5882 rt2x00_rf(rt2x00dev, RF3290) ||
5883 rt2x00_rf(rt2x00dev, RF3320) ||
5884 rt2x00_rf(rt2x00dev, RF3322) ||
5885 rt2x00_rf(rt2x00dev, RF5360) ||
5886 rt2x00_rf(rt2x00dev, RF5370) ||
5887 rt2x00_rf(rt2x00dev, RF5372) ||
5888 rt2x00_rf(rt2x00dev, RF5390) ||
5889 rt2x00_rf(rt2x00dev, RF5392)) {
5890 spec->num_channels = 14;
5891 spec->channels = rf_vals_3x;
5892 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5893 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5894 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5895 spec->channels = rf_vals_3x;
5896 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5897 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5898
5899 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5900 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5901 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5902 spec->channels = rf_vals_5592_xtal40;
5903 } else {
5904 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5905 spec->channels = rf_vals_5592_xtal20;
5906 }
5907 }
5908
5909 if (WARN_ON_ONCE(!spec->channels))
5910 return -ENODEV;
5911
5912 /*
5913 * Initialize HT information.
5914 */
5915 if (!rt2x00_rf(rt2x00dev, RF2020))
5916 spec->ht.ht_supported = true;
5917 else
5918 spec->ht.ht_supported = false;
5919
5920 spec->ht.cap =
5921 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5922 IEEE80211_HT_CAP_GRN_FLD |
5923 IEEE80211_HT_CAP_SGI_20 |
5924 IEEE80211_HT_CAP_SGI_40;
5925
5926 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5927 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5928
5929 spec->ht.cap |=
5930 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5931 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5932
5933 spec->ht.ampdu_factor = 3;
5934 spec->ht.ampdu_density = 4;
5935 spec->ht.mcs.tx_params =
5936 IEEE80211_HT_MCS_TX_DEFINED |
5937 IEEE80211_HT_MCS_TX_RX_DIFF |
5938 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5939 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5940
5941 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5942 case 3:
5943 spec->ht.mcs.rx_mask[2] = 0xff;
5944 case 2:
5945 spec->ht.mcs.rx_mask[1] = 0xff;
5946 case 1:
5947 spec->ht.mcs.rx_mask[0] = 0xff;
5948 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5949 break;
5950 }
5951
5952 /*
5953 * Create channel information array
5954 */
5955 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5956 if (!info)
5957 return -ENOMEM;
5958
5959 spec->channels_info = info;
5960
5961 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5962 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5963
5964 for (i = 0; i < 14; i++) {
5965 info[i].default_power1 = default_power1[i];
5966 info[i].default_power2 = default_power2[i];
5967 }
5968
5969 if (spec->num_channels > 14) {
5970 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5971 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5972
5973 for (i = 14; i < spec->num_channels; i++) {
5974 info[i].default_power1 = default_power1[i];
5975 info[i].default_power2 = default_power2[i];
5976 }
5977 }
5978
5979 switch (rt2x00dev->chip.rf) {
5980 case RF2020:
5981 case RF3020:
5982 case RF3021:
5983 case RF3022:
5984 case RF3320:
5985 case RF3052:
5986 case RF3290:
5987 case RF5360:
5988 case RF5370:
5989 case RF5372:
5990 case RF5390:
5991 case RF5392:
5992 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5993 break;
5994 }
5995
5996 return 0;
5997 }
5998
5999 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
6000 {
6001 int retval;
6002 u32 reg;
6003
6004 /*
6005 * Allocate eeprom data.
6006 */
6007 retval = rt2800_validate_eeprom(rt2x00dev);
6008 if (retval)
6009 return retval;
6010
6011 retval = rt2800_init_eeprom(rt2x00dev);
6012 if (retval)
6013 return retval;
6014
6015 /*
6016 * Enable rfkill polling by setting GPIO direction of the
6017 * rfkill switch GPIO pin correctly.
6018 */
6019 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6020 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
6021 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6022
6023 /*
6024 * Initialize hw specifications.
6025 */
6026 retval = rt2800_probe_hw_mode(rt2x00dev);
6027 if (retval)
6028 return retval;
6029
6030 /*
6031 * Set device capabilities.
6032 */
6033 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
6034 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
6035 if (!rt2x00_is_usb(rt2x00dev))
6036 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
6037
6038 /*
6039 * Set device requirements.
6040 */
6041 if (!rt2x00_is_soc(rt2x00dev))
6042 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
6043 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
6044 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
6045 if (!rt2800_hwcrypt_disabled(rt2x00dev))
6046 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
6047 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
6048 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
6049 if (rt2x00_is_usb(rt2x00dev))
6050 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
6051 else {
6052 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
6053 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
6054 }
6055
6056 /*
6057 * Set the rssi offset.
6058 */
6059 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6060
6061 return 0;
6062 }
6063 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
6064
6065 /*
6066 * IEEE80211 stack callback functions.
6067 */
6068 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6069 u16 *iv16)
6070 {
6071 struct rt2x00_dev *rt2x00dev = hw->priv;
6072 struct mac_iveiv_entry iveiv_entry;
6073 u32 offset;
6074
6075 offset = MAC_IVEIV_ENTRY(hw_key_idx);
6076 rt2800_register_multiread(rt2x00dev, offset,
6077 &iveiv_entry, sizeof(iveiv_entry));
6078
6079 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6080 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
6081 }
6082 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
6083
6084 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
6085 {
6086 struct rt2x00_dev *rt2x00dev = hw->priv;
6087 u32 reg;
6088 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6089
6090 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6091 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6092 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6093
6094 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6095 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6096 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6097
6098 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6099 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6100 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6101
6102 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6103 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6104 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6105
6106 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6107 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6108 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6109
6110 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6111 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6112 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6113
6114 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6115 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6116 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6117
6118 return 0;
6119 }
6120 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
6121
6122 int rt2800_conf_tx(struct ieee80211_hw *hw,
6123 struct ieee80211_vif *vif, u16 queue_idx,
6124 const struct ieee80211_tx_queue_params *params)
6125 {
6126 struct rt2x00_dev *rt2x00dev = hw->priv;
6127 struct data_queue *queue;
6128 struct rt2x00_field32 field;
6129 int retval;
6130 u32 reg;
6131 u32 offset;
6132
6133 /*
6134 * First pass the configuration through rt2x00lib, that will
6135 * update the queue settings and validate the input. After that
6136 * we are free to update the registers based on the value
6137 * in the queue parameter.
6138 */
6139 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
6140 if (retval)
6141 return retval;
6142
6143 /*
6144 * We only need to perform additional register initialization
6145 * for WMM queues/
6146 */
6147 if (queue_idx >= 4)
6148 return 0;
6149
6150 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
6151
6152 /* Update WMM TXOP register */
6153 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6154 field.bit_offset = (queue_idx & 1) * 16;
6155 field.bit_mask = 0xffff << field.bit_offset;
6156
6157 rt2800_register_read(rt2x00dev, offset, &reg);
6158 rt2x00_set_field32(&reg, field, queue->txop);
6159 rt2800_register_write(rt2x00dev, offset, reg);
6160
6161 /* Update WMM registers */
6162 field.bit_offset = queue_idx * 4;
6163 field.bit_mask = 0xf << field.bit_offset;
6164
6165 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6166 rt2x00_set_field32(&reg, field, queue->aifs);
6167 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6168
6169 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6170 rt2x00_set_field32(&reg, field, queue->cw_min);
6171 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6172
6173 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6174 rt2x00_set_field32(&reg, field, queue->cw_max);
6175 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6176
6177 /* Update EDCA registers */
6178 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6179
6180 rt2800_register_read(rt2x00dev, offset, &reg);
6181 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6182 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6183 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6184 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6185 rt2800_register_write(rt2x00dev, offset, reg);
6186
6187 return 0;
6188 }
6189 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6190
6191 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6192 {
6193 struct rt2x00_dev *rt2x00dev = hw->priv;
6194 u64 tsf;
6195 u32 reg;
6196
6197 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6198 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6199 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6200 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6201
6202 return tsf;
6203 }
6204 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6205
6206 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6207 enum ieee80211_ampdu_mlme_action action,
6208 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6209 u8 buf_size)
6210 {
6211 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6212 int ret = 0;
6213
6214 /*
6215 * Don't allow aggregation for stations the hardware isn't aware
6216 * of because tx status reports for frames to an unknown station
6217 * always contain wcid=255 and thus we can't distinguish between
6218 * multiple stations which leads to unwanted situations when the
6219 * hw reorders frames due to aggregation.
6220 */
6221 if (sta_priv->wcid < 0)
6222 return 1;
6223
6224 switch (action) {
6225 case IEEE80211_AMPDU_RX_START:
6226 case IEEE80211_AMPDU_RX_STOP:
6227 /*
6228 * The hw itself takes care of setting up BlockAck mechanisms.
6229 * So, we only have to allow mac80211 to nagotiate a BlockAck
6230 * agreement. Once that is done, the hw will BlockAck incoming
6231 * AMPDUs without further setup.
6232 */
6233 break;
6234 case IEEE80211_AMPDU_TX_START:
6235 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6236 break;
6237 case IEEE80211_AMPDU_TX_STOP_CONT:
6238 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6239 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6240 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6241 break;
6242 case IEEE80211_AMPDU_TX_OPERATIONAL:
6243 break;
6244 default:
6245 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
6246 }
6247
6248 return ret;
6249 }
6250 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6251
6252 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6253 struct survey_info *survey)
6254 {
6255 struct rt2x00_dev *rt2x00dev = hw->priv;
6256 struct ieee80211_conf *conf = &hw->conf;
6257 u32 idle, busy, busy_ext;
6258
6259 if (idx != 0)
6260 return -ENOENT;
6261
6262 survey->channel = conf->channel;
6263
6264 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6265 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6266 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6267
6268 if (idle || busy) {
6269 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6270 SURVEY_INFO_CHANNEL_TIME_BUSY |
6271 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6272
6273 survey->channel_time = (idle + busy) / 1000;
6274 survey->channel_time_busy = busy / 1000;
6275 survey->channel_time_ext_busy = busy_ext / 1000;
6276 }
6277
6278 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6279 survey->filled |= SURVEY_INFO_IN_USE;
6280
6281 return 0;
6282
6283 }
6284 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6285
6286 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6287 MODULE_VERSION(DRV_VERSION);
6288 MODULE_DESCRIPTION("Ralink RT2800 library");
6289 MODULE_LICENSE("GPL");
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