2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
225 const u8 command
, const u8 token
,
226 const u8 arg0
, const u8 arg1
)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev
))
236 mutex_lock(&rt2x00dev
->csr_mutex
);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
243 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
244 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
245 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
246 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
247 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
250 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
251 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
254 mutex_unlock(&rt2x00dev
->csr_mutex
);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
258 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
263 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
264 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
265 if (reg
&& reg
!= ~0)
270 ERROR(rt2x00dev
, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
280 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
281 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
282 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
283 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
289 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
292 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
294 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
300 * The last 2 bytes in the firmware array are the crc checksum itself,
301 * this means that we should never pass those 2 bytes to the crc
304 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
307 * Use the crc ccitt algorithm.
308 * This will return the same value as the legacy driver which
309 * used bit ordering reversion on the both the firmware bytes
310 * before input input as well as on the final output.
311 * Obviously using crc ccitt directly is much more efficient.
313 crc
= crc_ccitt(~0, data
, len
- 2);
316 * There is a small difference between the crc-itu-t + bitrev and
317 * the crc-ccitt crc calculation. In the latter method the 2 bytes
318 * will be swapped, use swab16 to convert the crc to the correct
323 return fw_crc
== crc
;
326 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
327 const u8
*data
, const size_t len
)
334 * PCI(e) & SOC devices require firmware with a length
335 * of 8kb. USB devices require firmware files with a length
336 * of 4kb. Certain USB chipsets however require different firmware,
337 * which Ralink only provides attached to the original firmware
338 * file. Thus for USB devices, firmware files have a length
339 * which is a multiple of 4kb.
341 if (rt2x00_is_usb(rt2x00dev
)) {
350 * Validate the firmware length
352 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
353 return FW_BAD_LENGTH
;
356 * Check if the chipset requires one of the upper parts
359 if (rt2x00_is_usb(rt2x00dev
) &&
360 !rt2x00_rt(rt2x00dev
, RT2860
) &&
361 !rt2x00_rt(rt2x00dev
, RT2872
) &&
362 !rt2x00_rt(rt2x00dev
, RT3070
) &&
363 ((len
/ fw_len
) == 1))
364 return FW_BAD_VERSION
;
367 * 8kb firmware files must be checked as if it were
368 * 2 separate firmware files.
370 while (offset
< len
) {
371 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
379 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
381 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
382 const u8
*data
, const size_t len
)
388 * If driver doesn't wake up firmware here,
389 * rt2800_load_firmware will hang forever when interface is up again.
391 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
394 * Wait for stable hardware.
396 if (rt2800_wait_csr_ready(rt2x00dev
))
399 if (rt2x00_is_pci(rt2x00dev
))
400 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
403 * Disable DMA, will be reenabled later when enabling
406 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
407 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
408 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
409 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
410 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
411 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
412 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
415 * Write firmware to the device.
417 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
420 * Wait for device to stabilize.
422 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
423 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
424 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
429 if (i
== REGISTER_BUSY_COUNT
) {
430 ERROR(rt2x00dev
, "PBF system register not ready.\n");
435 * Initialize firmware.
437 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
438 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
443 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
445 void rt2800_write_tx_data(struct queue_entry
*entry
,
446 struct txentry_desc
*txdesc
)
448 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
452 * Initialize TX Info descriptor
454 rt2x00_desc_read(txwi
, 0, &word
);
455 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
456 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
457 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
458 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
459 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
460 rt2x00_set_field32(&word
, TXWI_W0_TS
,
461 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
462 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
463 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
464 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
, txdesc
->mpdu_density
);
465 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->txop
);
466 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->mcs
);
467 rt2x00_set_field32(&word
, TXWI_W0_BW
,
468 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
469 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
470 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
471 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->stbc
);
472 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
473 rt2x00_desc_write(txwi
, 0, word
);
475 rt2x00_desc_read(txwi
, 1, &word
);
476 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
477 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
478 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
479 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
480 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->ba_size
);
481 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
482 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
483 txdesc
->key_idx
: 0xff);
484 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
486 rt2x00_set_field32(&word
, TXWI_W1_PACKETID
, txdesc
->qid
+ 1);
487 rt2x00_desc_write(txwi
, 1, word
);
490 * Always write 0 to IV/EIV fields, hardware will insert the IV
491 * from the IVEIV register when TXD_W3_WIV is set to 0.
492 * When TXD_W3_WIV is set to 1 it will use the IV data
493 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
494 * crypto entry in the registers should be used to encrypt the frame.
496 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
497 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
499 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
501 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxwi_w2
)
503 int rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
504 int rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
505 int rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
511 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
512 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
513 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
514 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
515 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
516 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
518 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
519 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
520 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
521 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
522 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
526 * Convert the value from the descriptor into the RSSI value
527 * If the value in the descriptor is 0, it is considered invalid
528 * and the default (extremely low) rssi value is assumed
530 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
531 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
532 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
535 * mac80211 only accepts a single RSSI value. Calculating the
536 * average doesn't deliver a fair answer either since -60:-60 would
537 * be considered equally good as -50:-70 while the second is the one
538 * which gives less energy...
540 rssi0
= max(rssi0
, rssi1
);
541 return max(rssi0
, rssi2
);
544 void rt2800_process_rxwi(struct queue_entry
*entry
,
545 struct rxdone_entry_desc
*rxdesc
)
547 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
550 rt2x00_desc_read(rxwi
, 0, &word
);
552 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
553 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
555 rt2x00_desc_read(rxwi
, 1, &word
);
557 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
558 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
560 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
561 rxdesc
->flags
|= RX_FLAG_40MHZ
;
564 * Detect RX rate, always use MCS as signal type.
566 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
567 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
568 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
571 * Mask of 0x8 bit to remove the short preamble flag.
573 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
574 rxdesc
->signal
&= ~0x8;
576 rt2x00_desc_read(rxwi
, 2, &word
);
579 * Convert descriptor AGC value to RSSI value.
581 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
584 * Remove RXWI descriptor from start of buffer.
586 skb_pull(entry
->skb
, RXWI_DESC_SIZE
);
588 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
590 static bool rt2800_txdone_entry_check(struct queue_entry
*entry
, u32 reg
)
595 int tx_wcid
, tx_ack
, tx_pid
;
597 wcid
= rt2x00_get_field32(reg
, TX_STA_FIFO_WCID
);
598 ack
= rt2x00_get_field32(reg
, TX_STA_FIFO_TX_ACK_REQUIRED
);
599 pid
= rt2x00_get_field32(reg
, TX_STA_FIFO_PID_TYPE
);
602 * This frames has returned with an IO error,
603 * so the status report is not intended for this
606 if (test_bit(ENTRY_DATA_IO_FAILED
, &entry
->flags
)) {
607 rt2x00lib_txdone_noinfo(entry
, TXDONE_FAILURE
);
612 * Validate if this TX status report is intended for
613 * this entry by comparing the WCID/ACK/PID fields.
615 txwi
= rt2800_drv_get_txwi(entry
);
617 rt2x00_desc_read(txwi
, 1, &word
);
618 tx_wcid
= rt2x00_get_field32(word
, TXWI_W1_WIRELESS_CLI_ID
);
619 tx_ack
= rt2x00_get_field32(word
, TXWI_W1_ACK
);
620 tx_pid
= rt2x00_get_field32(word
, TXWI_W1_PACKETID
);
622 if ((wcid
!= tx_wcid
) || (ack
!= tx_ack
) || (pid
!= tx_pid
)) {
623 WARNING(entry
->queue
->rt2x00dev
,
624 "TX status report missed for queue %d entry %d\n",
625 entry
->queue
->qid
, entry
->entry_idx
);
626 rt2x00lib_txdone_noinfo(entry
, TXDONE_UNKNOWN
);
633 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
)
635 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
636 struct txdone_entry_desc txdesc
;
642 * Obtain the status about this packet.
645 txwi
= rt2800_drv_get_txwi(entry
);
646 rt2x00_desc_read(txwi
, 0, &word
);
647 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
648 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
651 * Ralink has a retry mechanism using a global fallback
652 * table. We setup this fallback table to try the immediate
653 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
654 * always contains the MCS used for the last transmission, be
655 * it successful or not.
657 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
659 * Transmission succeeded. The number of retries is
662 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
663 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
666 * Transmission failed. The number of retries is
667 * always 7 in this case (for a total number of 8
670 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
671 txdesc
.retry
= rt2x00dev
->long_retry
;
675 * the frame was retried at least once
676 * -> hw used fallback rates
679 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
681 rt2x00lib_txdone(entry
, &txdesc
);
683 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
685 void rt2800_txdone(struct rt2x00_dev
*rt2x00dev
)
687 struct data_queue
*queue
;
688 struct queue_entry
*entry
;
694 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
695 * at most X times and also stop processing once the TX_STA_FIFO_VALID
696 * flag is not set anymore.
698 * The legacy drivers use X=TX_RING_SIZE but state in a comment
699 * that the TX_STA_FIFO stack has a size of 16. We stick to our
700 * tx ring size for now.
702 for (i
= 0; i
< TX_ENTRIES
; i
++) {
703 rt2800_register_read(rt2x00dev
, TX_STA_FIFO
, ®
);
704 if (!rt2x00_get_field32(reg
, TX_STA_FIFO_VALID
))
708 * Skip this entry when it contains an invalid
709 * queue identication number.
711 pid
= rt2x00_get_field32(reg
, TX_STA_FIFO_PID_TYPE
) - 1;
715 queue
= rt2x00queue_get_queue(rt2x00dev
, pid
);
716 if (unlikely(!queue
))
720 * Inside each queue, we process each entry in a chronological
721 * order. We first check that the queue is not empty.
724 while (!rt2x00queue_empty(queue
)) {
725 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
726 if (rt2800_txdone_entry_check(entry
, reg
))
730 if (!entry
|| rt2x00queue_empty(queue
))
733 rt2800_txdone_entry(entry
, reg
);
736 EXPORT_SYMBOL_GPL(rt2800_txdone
);
738 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
740 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
741 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
742 unsigned int beacon_base
;
746 * Disable beaconing while we are reloading the beacon data,
747 * otherwise we might be sending out invalid data.
749 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
750 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
751 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
754 * Add space for the TXWI in front of the skb.
756 skb_push(entry
->skb
, TXWI_DESC_SIZE
);
757 memset(entry
->skb
, 0, TXWI_DESC_SIZE
);
760 * Register descriptor details in skb frame descriptor.
762 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
763 skbdesc
->desc
= entry
->skb
->data
;
764 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
767 * Add the TXWI for the beacon to the skb.
769 rt2800_write_tx_data(entry
, txdesc
);
772 * Dump beacon to userspace through debugfs.
774 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
777 * Write entire beacon with TXWI to register.
779 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
780 rt2800_register_multiwrite(rt2x00dev
, beacon_base
,
781 entry
->skb
->data
, entry
->skb
->len
);
784 * Enable beaconing again.
786 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
787 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 1);
788 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
789 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
792 * Clean up beacon skb.
794 dev_kfree_skb_any(entry
->skb
);
797 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
799 static void inline rt2800_clear_beacon(struct rt2x00_dev
*rt2x00dev
,
800 unsigned int beacon_base
)
805 * For the Beacon base registers we only need to clear
806 * the whole TXWI which (when set to 0) will invalidate
809 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
810 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
813 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
814 const struct rt2x00debug rt2800_rt2x00debug
= {
815 .owner
= THIS_MODULE
,
817 .read
= rt2800_register_read
,
818 .write
= rt2800_register_write
,
819 .flags
= RT2X00DEBUGFS_OFFSET
,
820 .word_base
= CSR_REG_BASE
,
821 .word_size
= sizeof(u32
),
822 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
825 .read
= rt2x00_eeprom_read
,
826 .write
= rt2x00_eeprom_write
,
827 .word_base
= EEPROM_BASE
,
828 .word_size
= sizeof(u16
),
829 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
832 .read
= rt2800_bbp_read
,
833 .write
= rt2800_bbp_write
,
834 .word_base
= BBP_BASE
,
835 .word_size
= sizeof(u8
),
836 .word_count
= BBP_SIZE
/ sizeof(u8
),
839 .read
= rt2x00_rf_read
,
840 .write
= rt2800_rf_write
,
841 .word_base
= RF_BASE
,
842 .word_size
= sizeof(u32
),
843 .word_count
= RF_SIZE
/ sizeof(u32
),
846 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
847 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
849 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
853 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
854 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
856 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
858 #ifdef CONFIG_RT2X00_LIB_LEDS
859 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
860 enum led_brightness brightness
)
862 struct rt2x00_led
*led
=
863 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
864 unsigned int enabled
= brightness
!= LED_OFF
;
865 unsigned int bg_mode
=
866 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
867 unsigned int polarity
=
868 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
869 EEPROM_FREQ_LED_POLARITY
);
870 unsigned int ledmode
=
871 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
872 EEPROM_FREQ_LED_MODE
);
874 if (led
->type
== LED_TYPE_RADIO
) {
875 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
877 } else if (led
->type
== LED_TYPE_ASSOC
) {
878 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
879 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
880 } else if (led
->type
== LED_TYPE_QUALITY
) {
882 * The brightness is divided into 6 levels (0 - 5),
883 * The specs tell us the following levels:
885 * to determine the level in a simple way we can simply
886 * work with bitshifting:
889 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
890 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
895 static int rt2800_blink_set(struct led_classdev
*led_cdev
,
896 unsigned long *delay_on
, unsigned long *delay_off
)
898 struct rt2x00_led
*led
=
899 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
902 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
903 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, *delay_on
);
904 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, *delay_off
);
905 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
910 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
911 struct rt2x00_led
*led
, enum led_type type
)
913 led
->rt2x00dev
= rt2x00dev
;
915 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
916 led
->led_dev
.blink_set
= rt2800_blink_set
;
917 led
->flags
= LED_INITIALIZED
;
919 #endif /* CONFIG_RT2X00_LIB_LEDS */
922 * Configuration handlers.
924 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
925 struct rt2x00lib_crypto
*crypto
,
926 struct ieee80211_key_conf
*key
)
928 struct mac_wcid_entry wcid_entry
;
929 struct mac_iveiv_entry iveiv_entry
;
933 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
935 if (crypto
->cmd
== SET_KEY
) {
936 rt2800_register_read(rt2x00dev
, offset
, ®
);
937 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
938 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
940 * Both the cipher as the BSS Idx numbers are split in a main
941 * value of 3 bits, and a extended field for adding one additional
944 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
945 (crypto
->cipher
& 0x7));
946 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
947 (crypto
->cipher
& 0x8) >> 3);
948 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
949 (crypto
->bssidx
& 0x7));
950 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
951 (crypto
->bssidx
& 0x8) >> 3);
952 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
953 rt2800_register_write(rt2x00dev
, offset
, reg
);
955 rt2800_register_write(rt2x00dev
, offset
, 0);
958 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
960 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
961 if ((crypto
->cipher
== CIPHER_TKIP
) ||
962 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
963 (crypto
->cipher
== CIPHER_AES
))
964 iveiv_entry
.iv
[3] |= 0x20;
965 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
966 rt2800_register_multiwrite(rt2x00dev
, offset
,
967 &iveiv_entry
, sizeof(iveiv_entry
));
969 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
971 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
972 if (crypto
->cmd
== SET_KEY
)
973 memcpy(&wcid_entry
, crypto
->address
, ETH_ALEN
);
974 rt2800_register_multiwrite(rt2x00dev
, offset
,
975 &wcid_entry
, sizeof(wcid_entry
));
978 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
979 struct rt2x00lib_crypto
*crypto
,
980 struct ieee80211_key_conf
*key
)
982 struct hw_key_entry key_entry
;
983 struct rt2x00_field32 field
;
987 if (crypto
->cmd
== SET_KEY
) {
988 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
990 memcpy(key_entry
.key
, crypto
->key
,
991 sizeof(key_entry
.key
));
992 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
993 sizeof(key_entry
.tx_mic
));
994 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
995 sizeof(key_entry
.rx_mic
));
997 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
998 rt2800_register_multiwrite(rt2x00dev
, offset
,
999 &key_entry
, sizeof(key_entry
));
1003 * The cipher types are stored over multiple registers
1004 * starting with SHARED_KEY_MODE_BASE each word will have
1005 * 32 bits and contains the cipher types for 2 bssidx each.
1006 * Using the correct defines correctly will cause overhead,
1007 * so just calculate the correct offset.
1009 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1010 field
.bit_mask
= 0x7 << field
.bit_offset
;
1012 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1014 rt2800_register_read(rt2x00dev
, offset
, ®
);
1015 rt2x00_set_field32(®
, field
,
1016 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1017 rt2800_register_write(rt2x00dev
, offset
, reg
);
1020 * Update WCID information
1022 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1026 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1028 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1029 struct rt2x00lib_crypto
*crypto
,
1030 struct ieee80211_key_conf
*key
)
1032 struct hw_key_entry key_entry
;
1035 if (crypto
->cmd
== SET_KEY
) {
1037 * 1 pairwise key is possible per AID, this means that the AID
1038 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1039 * last possible shared key entry.
1041 * Since parts of the pairwise key table might be shared with
1042 * the beacon frame buffers 6 & 7 we should only write into the
1043 * first 222 entries.
1045 if (crypto
->aid
> (222 - 32))
1048 key
->hw_key_idx
= 32 + crypto
->aid
;
1050 memcpy(key_entry
.key
, crypto
->key
,
1051 sizeof(key_entry
.key
));
1052 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1053 sizeof(key_entry
.tx_mic
));
1054 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1055 sizeof(key_entry
.rx_mic
));
1057 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1058 rt2800_register_multiwrite(rt2x00dev
, offset
,
1059 &key_entry
, sizeof(key_entry
));
1063 * Update WCID information
1065 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1069 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1071 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1072 const unsigned int filter_flags
)
1077 * Start configuration steps.
1078 * Note that the version error will always be dropped
1079 * and broadcast frames will always be accepted since
1080 * there is no filter for it at this time.
1082 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1083 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1084 !(filter_flags
& FIF_FCSFAIL
));
1085 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1086 !(filter_flags
& FIF_PLCPFAIL
));
1087 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1088 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1089 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1090 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1091 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1092 !(filter_flags
& FIF_ALLMULTI
));
1093 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1094 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1095 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1096 !(filter_flags
& FIF_CONTROL
));
1097 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1098 !(filter_flags
& FIF_CONTROL
));
1099 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1100 !(filter_flags
& FIF_CONTROL
));
1101 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1102 !(filter_flags
& FIF_CONTROL
));
1103 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1104 !(filter_flags
& FIF_CONTROL
));
1105 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1106 !(filter_flags
& FIF_PSPOLL
));
1107 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
1108 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
1109 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1110 !(filter_flags
& FIF_CONTROL
));
1111 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1113 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1115 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1116 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1120 if (flags
& CONFIG_UPDATE_TYPE
) {
1122 * Clear current synchronisation setup.
1124 rt2800_clear_beacon(rt2x00dev
,
1125 HW_BEACON_OFFSET(intf
->beacon
->entry_idx
));
1127 * Enable synchronisation.
1129 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1130 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
1131 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1132 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
,
1133 (conf
->sync
== TSF_SYNC_ADHOC
||
1134 conf
->sync
== TSF_SYNC_AP_NONE
));
1135 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1138 * Enable pre tbtt interrupt for beaconing modes
1140 rt2800_register_read(rt2x00dev
, INT_TIMER_EN
, ®
);
1141 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
,
1142 (conf
->sync
== TSF_SYNC_AP_NONE
));
1143 rt2800_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
1147 if (flags
& CONFIG_UPDATE_MAC
) {
1148 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1149 reg
= le32_to_cpu(conf
->mac
[1]);
1150 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1151 conf
->mac
[1] = cpu_to_le32(reg
);
1154 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1155 conf
->mac
, sizeof(conf
->mac
));
1158 if (flags
& CONFIG_UPDATE_BSSID
) {
1159 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1160 reg
= le32_to_cpu(conf
->bssid
[1]);
1161 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1162 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1163 conf
->bssid
[1] = cpu_to_le32(reg
);
1166 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1167 conf
->bssid
, sizeof(conf
->bssid
));
1170 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1172 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1173 struct rt2x00lib_erp
*erp
)
1175 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1176 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1177 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1178 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1179 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1182 /* default protection rate for HT20: OFDM 24M */
1183 mm20_rate
= gf20_rate
= 0x4004;
1185 /* default protection rate for HT40: duplicate OFDM 24M */
1186 mm40_rate
= gf40_rate
= 0x4084;
1188 switch (protection
) {
1189 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1191 * All STAs in this BSS are HT20/40 but there might be
1192 * STAs not supporting greenfield mode.
1193 * => Disable protection for HT transmissions.
1195 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1198 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1200 * All STAs in this BSS are HT20 or HT20/40 but there
1201 * might be STAs not supporting greenfield mode.
1202 * => Protect all HT40 transmissions.
1204 mm20_mode
= gf20_mode
= 0;
1205 mm40_mode
= gf40_mode
= 2;
1208 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1210 * Nonmember protection:
1211 * According to 802.11n we _should_ protect all
1212 * HT transmissions (but we don't have to).
1214 * But if cts_protection is enabled we _shall_ protect
1215 * all HT transmissions using a CCK rate.
1217 * And if any station is non GF we _shall_ protect
1220 * We decide to protect everything
1221 * -> fall through to mixed mode.
1223 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1225 * Legacy STAs are present
1226 * => Protect all HT transmissions.
1228 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1231 * If erp protection is needed we have to protect HT
1232 * transmissions with CCK 11M long preamble.
1234 if (erp
->cts_protection
) {
1235 /* don't duplicate RTS/CTS in CCK mode */
1236 mm20_rate
= mm40_rate
= 0x0003;
1237 gf20_rate
= gf40_rate
= 0x0003;
1242 /* check for STAs not supporting greenfield mode */
1244 gf20_mode
= gf40_mode
= 2;
1246 /* Update HT protection config */
1247 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1248 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1249 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1250 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1252 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1253 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1254 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1255 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1257 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1258 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1259 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1260 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1262 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1263 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1264 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1265 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1268 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1273 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1274 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1275 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1276 !!erp
->short_preamble
);
1277 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1278 !!erp
->short_preamble
);
1279 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1282 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1283 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1284 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1285 erp
->cts_protection
? 2 : 0);
1286 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1289 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1290 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1292 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1295 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1296 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1297 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1299 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1301 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1302 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1303 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1306 if (changed
& BSS_CHANGED_BEACON_INT
) {
1307 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1308 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1309 erp
->beacon_int
* 16);
1310 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1313 if (changed
& BSS_CHANGED_HT
)
1314 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1316 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1318 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1323 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1324 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1327 * Configure the TX antenna.
1329 switch ((int)ant
->tx
) {
1331 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1334 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1337 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1342 * Configure the RX antenna.
1344 switch ((int)ant
->rx
) {
1346 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1349 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1352 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1356 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1357 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1359 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1361 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1362 struct rt2x00lib_conf
*libconf
)
1367 if (libconf
->rf
.channel
<= 14) {
1368 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1369 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1370 } else if (libconf
->rf
.channel
<= 64) {
1371 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1372 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1373 } else if (libconf
->rf
.channel
<= 128) {
1374 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1375 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1377 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1378 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1381 rt2x00dev
->lna_gain
= lna_gain
;
1384 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1385 struct ieee80211_conf
*conf
,
1386 struct rf_channel
*rf
,
1387 struct channel_info
*info
)
1389 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1391 if (rt2x00dev
->default_ant
.tx
== 1)
1392 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1394 if (rt2x00dev
->default_ant
.rx
== 1) {
1395 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1396 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1397 } else if (rt2x00dev
->default_ant
.rx
== 2)
1398 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1400 if (rf
->channel
> 14) {
1402 * When TX power is below 0, we should increase it by 7 to
1403 * make it a positive value (Minumum value is -7).
1404 * However this means that values between 0 and 7 have
1405 * double meaning, and we should set a 7DBm boost flag.
1407 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1408 (info
->default_power1
>= 0));
1410 if (info
->default_power1
< 0)
1411 info
->default_power1
+= 7;
1413 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1415 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1416 (info
->default_power2
>= 0));
1418 if (info
->default_power2
< 0)
1419 info
->default_power2
+= 7;
1421 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1423 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1424 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1427 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1429 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1430 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1431 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1432 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1436 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1437 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1438 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1439 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1443 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1444 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1445 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1446 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1449 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1450 struct ieee80211_conf
*conf
,
1451 struct rf_channel
*rf
,
1452 struct channel_info
*info
)
1456 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1457 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1459 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1460 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1461 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1463 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1464 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1465 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1467 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1468 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1469 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1471 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1472 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1473 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1475 rt2800_rfcsr_write(rt2x00dev
, 24,
1476 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1478 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1479 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1480 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1483 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
1484 struct ieee80211_conf
*conf
,
1485 struct rf_channel
*rf
,
1486 struct channel_info
*info
)
1489 unsigned int tx_pin
;
1492 if (rf
->channel
<= 14) {
1493 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
1494 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
1496 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
1497 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
1500 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
1501 rt2x00_rf(rt2x00dev
, RF3020
) ||
1502 rt2x00_rf(rt2x00dev
, RF3021
) ||
1503 rt2x00_rf(rt2x00dev
, RF3022
) ||
1504 rt2x00_rf(rt2x00dev
, RF3052
))
1505 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
1507 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
1510 * Change BBP settings
1512 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
1513 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
1514 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
1515 rt2800_bbp_write(rt2x00dev
, 86, 0);
1517 if (rf
->channel
<= 14) {
1518 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1519 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1520 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1522 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
1523 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1526 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
1528 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
1529 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1531 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1534 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
1535 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
1536 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
1537 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
1538 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
1542 /* Turn on unused PA or LNA when not using 1T or 1R */
1543 if (rt2x00dev
->default_ant
.tx
!= 1) {
1544 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
1545 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
1548 /* Turn on unused PA or LNA when not using 1T or 1R */
1549 if (rt2x00dev
->default_ant
.rx
!= 1) {
1550 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
1551 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
1554 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
1555 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
1556 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
1557 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
1558 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, rf
->channel
<= 14);
1559 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
1561 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
1563 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1564 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
1565 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1567 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
1568 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
1569 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
1571 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1572 if (conf_is_ht40(conf
)) {
1573 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
1574 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1575 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
1577 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1578 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
1579 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
1586 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
1587 const int max_txpower
)
1590 u8 max_value
= (u8
)max_txpower
;
1598 * set to normal tx power mode: +/- 0dBm
1600 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1601 rt2x00_set_field8(&r1
, BBP1_TX_POWER
, 0);
1602 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1605 * The eeprom contains the tx power values for each rate. These
1606 * values map to 100% tx power. Each 16bit word contains four tx
1607 * power values and the order is the same as used in the TX_PWR_CFG
1610 offset
= TX_PWR_CFG_0
;
1612 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
1613 /* just to be safe */
1614 if (offset
> TX_PWR_CFG_4
)
1617 rt2800_register_read(rt2x00dev
, offset
, ®
);
1619 /* read the next four txpower values */
1620 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
1623 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1624 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1625 * TX_PWR_CFG_4: unknown */
1626 txpower
= rt2x00_get_field16(eeprom
,
1627 EEPROM_TXPOWER_BYRATE_RATE0
);
1628 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
,
1629 min(txpower
, max_value
));
1631 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1632 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1633 * TX_PWR_CFG_4: unknown */
1634 txpower
= rt2x00_get_field16(eeprom
,
1635 EEPROM_TXPOWER_BYRATE_RATE1
);
1636 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
,
1637 min(txpower
, max_value
));
1639 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1640 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1641 * TX_PWR_CFG_4: unknown */
1642 txpower
= rt2x00_get_field16(eeprom
,
1643 EEPROM_TXPOWER_BYRATE_RATE2
);
1644 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
,
1645 min(txpower
, max_value
));
1647 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1648 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1649 * TX_PWR_CFG_4: unknown */
1650 txpower
= rt2x00_get_field16(eeprom
,
1651 EEPROM_TXPOWER_BYRATE_RATE3
);
1652 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
,
1653 min(txpower
, max_value
));
1655 /* read the next four txpower values */
1656 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
1659 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1660 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1661 * TX_PWR_CFG_4: unknown */
1662 txpower
= rt2x00_get_field16(eeprom
,
1663 EEPROM_TXPOWER_BYRATE_RATE0
);
1664 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
,
1665 min(txpower
, max_value
));
1667 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1668 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1669 * TX_PWR_CFG_4: unknown */
1670 txpower
= rt2x00_get_field16(eeprom
,
1671 EEPROM_TXPOWER_BYRATE_RATE1
);
1672 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
,
1673 min(txpower
, max_value
));
1675 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1676 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1677 * TX_PWR_CFG_4: unknown */
1678 txpower
= rt2x00_get_field16(eeprom
,
1679 EEPROM_TXPOWER_BYRATE_RATE2
);
1680 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
,
1681 min(txpower
, max_value
));
1683 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1684 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1685 * TX_PWR_CFG_4: unknown */
1686 txpower
= rt2x00_get_field16(eeprom
,
1687 EEPROM_TXPOWER_BYRATE_RATE3
);
1688 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
,
1689 min(txpower
, max_value
));
1691 rt2800_register_write(rt2x00dev
, offset
, reg
);
1693 /* next TX_PWR_CFG register */
1698 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
1699 struct rt2x00lib_conf
*libconf
)
1703 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1704 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
1705 libconf
->conf
->short_frame_max_tx_count
);
1706 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
1707 libconf
->conf
->long_frame_max_tx_count
);
1708 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1711 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
1712 struct rt2x00lib_conf
*libconf
)
1714 enum dev_state state
=
1715 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
1716 STATE_SLEEP
: STATE_AWAKE
;
1719 if (state
== STATE_SLEEP
) {
1720 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
1722 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1723 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
1724 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
1725 libconf
->conf
->listen_interval
- 1);
1726 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
1727 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1729 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1731 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1732 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
1733 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
1734 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
1735 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1737 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1741 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
1742 struct rt2x00lib_conf
*libconf
,
1743 const unsigned int flags
)
1745 /* Always recalculate LNA gain before changing configuration */
1746 rt2800_config_lna_gain(rt2x00dev
, libconf
);
1748 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
1749 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
1750 &libconf
->rf
, &libconf
->channel
);
1751 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
1752 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1753 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1754 rt2800_config_retry_limit(rt2x00dev
, libconf
);
1755 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1756 rt2800_config_ps(rt2x00dev
, libconf
);
1758 EXPORT_SYMBOL_GPL(rt2800_config
);
1763 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1768 * Update FCS error count from register.
1770 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1771 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
1773 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
1775 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
1777 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
1778 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1779 rt2x00_rt(rt2x00dev
, RT3071
) ||
1780 rt2x00_rt(rt2x00dev
, RT3090
) ||
1781 rt2x00_rt(rt2x00dev
, RT3390
))
1782 return 0x1c + (2 * rt2x00dev
->lna_gain
);
1784 return 0x2e + rt2x00dev
->lna_gain
;
1787 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
1788 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
1790 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
1793 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1794 struct link_qual
*qual
, u8 vgc_level
)
1796 if (qual
->vgc_level
!= vgc_level
) {
1797 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
1798 qual
->vgc_level
= vgc_level
;
1799 qual
->vgc_level_reg
= vgc_level
;
1803 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1805 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
1807 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
1809 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
1812 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
1816 * When RSSI is better then -80 increase VGC level with 0x10
1818 rt2800_set_vgc(rt2x00dev
, qual
,
1819 rt2800_get_default_vgc(rt2x00dev
) +
1820 ((qual
->rssi
> -80) * 0x10));
1822 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
1825 * Initialization functions.
1827 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
1834 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1835 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1836 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1837 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1838 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1839 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
1840 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1842 ret
= rt2800_drv_init_registers(rt2x00dev
);
1846 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
1847 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
1848 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
1849 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
1850 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
1851 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
1853 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
1854 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
1855 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
1856 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
1857 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
1858 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
1860 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
1861 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1863 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1865 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1866 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
1867 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
1868 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
1869 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
1870 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1871 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
1872 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1874 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
1876 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1877 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
1878 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
1879 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1881 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1882 rt2x00_rt(rt2x00dev
, RT3090
) ||
1883 rt2x00_rt(rt2x00dev
, RT3390
)) {
1884 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1885 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1886 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1887 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1888 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
1889 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1890 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
1891 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1894 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1897 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1899 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1900 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1902 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1903 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1904 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
1906 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1907 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1909 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
1910 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1911 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1912 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000001f);
1914 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
1915 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1918 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
1919 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
1920 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
1921 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
1922 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
1923 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
1924 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
1925 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
1926 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
1927 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
1929 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
1930 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
1931 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
1932 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
1933 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
1935 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
1936 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
1937 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
1938 rt2x00_rt(rt2x00dev
, RT2883
) ||
1939 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
1940 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
1942 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
1943 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
1944 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
1945 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
1947 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1948 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
1949 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
1950 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
1951 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
1952 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
1953 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
1954 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
1955 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1957 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
1959 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1960 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
1961 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
1962 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
1963 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
1964 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
1965 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
1966 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1968 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1969 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
1970 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
1971 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
1972 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
1973 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
1974 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
1975 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
1976 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1978 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
1979 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
1980 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
1981 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV
, 1);
1982 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1983 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1984 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1985 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1986 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1987 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1988 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
1989 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
1991 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1992 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
1993 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
1994 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV
, 1);
1995 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1996 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1997 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1998 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1999 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2000 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2001 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
2002 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2004 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2005 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
2006 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
2007 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV
, 1);
2008 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2009 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2010 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2011 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2012 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2013 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2014 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
2015 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2017 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2018 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
2019 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
2020 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV
, 1);
2021 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2022 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2023 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2024 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2025 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2026 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2027 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
2028 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2030 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2031 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
2032 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
2033 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV
, 1);
2034 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2035 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2036 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2037 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2038 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2039 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2040 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
2041 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2043 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2044 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
2045 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
2046 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV
, 1);
2047 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2048 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2049 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2050 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2051 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2052 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2053 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
2054 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2056 if (rt2x00_is_usb(rt2x00dev
)) {
2057 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
2059 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2060 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2061 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2062 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2063 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2064 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
2065 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
2066 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
2067 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
2068 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
2069 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2072 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, 0x0000583f);
2073 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
2075 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2076 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
2077 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
2078 IEEE80211_MAX_RTS_THRESHOLD
);
2079 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
2080 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2082 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
2085 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2086 * time should be set to 16. However, the original Ralink driver uses
2087 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2088 * connection problems with 11g + CTS protection. Hence, use the same
2089 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2091 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
2092 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
2093 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
2094 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
2095 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
2096 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
2097 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
2099 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
2102 * ASIC will keep garbage value after boot, clear encryption keys.
2104 for (i
= 0; i
< 4; i
++)
2105 rt2800_register_write(rt2x00dev
,
2106 SHARED_KEY_MODE_ENTRY(i
), 0);
2108 for (i
= 0; i
< 256; i
++) {
2109 u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
2110 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
2111 wcid
, sizeof(wcid
));
2113 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 1);
2114 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
2120 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE0
);
2121 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE1
);
2122 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE2
);
2123 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE3
);
2124 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE4
);
2125 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE5
);
2126 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE6
);
2127 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE7
);
2129 if (rt2x00_is_usb(rt2x00dev
)) {
2130 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2131 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
2132 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2135 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
2136 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
2137 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
2138 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
2139 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
2140 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
2141 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
2142 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
2143 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
2144 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
2146 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
2147 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
2148 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
2149 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
2150 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
2151 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
2152 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
2153 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
2154 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
2155 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
2157 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
2158 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
2159 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
2160 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
2161 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
2162 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
2163 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
2164 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
2165 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
2166 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
2168 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
2169 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
2170 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
2171 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
2172 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
2173 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
2176 * Do not force the BA window size, we use the TXWI to set it
2178 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
2179 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
2180 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
2181 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
2184 * We must clear the error counters.
2185 * These registers are cleared on read,
2186 * so we may pass a useless variable to store the value.
2188 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2189 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
2190 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
2191 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
2192 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
2193 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
2196 * Setup leadtime for pre tbtt interrupt to 6ms
2198 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
2199 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
2200 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
2205 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
2210 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2211 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
2212 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
2215 udelay(REGISTER_BUSY_DELAY
);
2218 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
2222 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
2228 * BBP was enabled after firmware was loaded,
2229 * but we need to reactivate it now.
2231 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
2232 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
2235 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2236 rt2800_bbp_read(rt2x00dev
, 0, &value
);
2237 if ((value
!= 0xff) && (value
!= 0x00))
2239 udelay(REGISTER_BUSY_DELAY
);
2242 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
2246 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
2253 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
2254 rt2800_wait_bbp_ready(rt2x00dev
)))
2257 if (rt2800_is_305x_soc(rt2x00dev
))
2258 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
2260 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
2261 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
2263 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2264 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2265 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
2267 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
2268 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
2271 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2273 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2274 rt2x00_rt(rt2x00dev
, RT3071
) ||
2275 rt2x00_rt(rt2x00dev
, RT3090
) ||
2276 rt2x00_rt(rt2x00dev
, RT3390
)) {
2277 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
2278 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
2279 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
2280 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2281 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
2282 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
2284 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
2287 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2288 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
2290 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
2291 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
2293 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
2295 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
2296 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
2297 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
2299 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2300 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2301 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2302 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
2303 rt2800_is_305x_soc(rt2x00dev
))
2304 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
2306 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
2308 if (rt2800_is_305x_soc(rt2x00dev
))
2309 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
2311 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
2312 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
2314 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2315 rt2x00_rt(rt2x00dev
, RT3090
) ||
2316 rt2x00_rt(rt2x00dev
, RT3390
)) {
2317 rt2800_bbp_read(rt2x00dev
, 138, &value
);
2319 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2320 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
2322 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
2325 rt2800_bbp_write(rt2x00dev
, 138, value
);
2329 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
2330 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
2332 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
2333 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
2334 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
2335 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
2342 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
2343 bool bw40
, u8 rfcsr24
, u8 filter_target
)
2352 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
2354 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2355 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
2356 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2358 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
2359 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
2360 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
2363 * Set power & frequency of passband test tone
2365 rt2800_bbp_write(rt2x00dev
, 24, 0);
2367 for (i
= 0; i
< 100; i
++) {
2368 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
2371 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
2377 * Set power & frequency of stopband test tone
2379 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
2381 for (i
= 0; i
< 100; i
++) {
2382 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
2385 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
2387 if ((passband
- stopband
) <= filter_target
) {
2389 overtuned
+= ((passband
- stopband
) == filter_target
);
2393 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
2396 rfcsr24
-= !!overtuned
;
2398 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
2402 static int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
2409 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
2410 !rt2x00_rt(rt2x00dev
, RT3071
) &&
2411 !rt2x00_rt(rt2x00dev
, RT3090
) &&
2412 !rt2x00_rt(rt2x00dev
, RT3390
) &&
2413 !rt2800_is_305x_soc(rt2x00dev
))
2417 * Init RF calibration.
2419 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2420 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
2421 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2423 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
2424 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2426 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2427 rt2x00_rt(rt2x00dev
, RT3071
) ||
2428 rt2x00_rt(rt2x00dev
, RT3090
)) {
2429 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
2430 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
2431 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
2432 rt2800_rfcsr_write(rt2x00dev
, 7, 0x70);
2433 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
2434 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
2435 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
2436 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
2437 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
2438 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
2439 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
2440 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
2441 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
2442 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
2443 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
2444 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
2445 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
2446 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2447 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
2448 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
2449 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
2450 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
2451 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
2452 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
2453 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
2454 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
2455 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
2456 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
2457 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
2458 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
2459 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
2460 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
2461 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
2462 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
2463 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
2464 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
2465 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
2466 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
2467 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
2468 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
2469 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
2470 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
2471 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
2472 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
2473 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
2474 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
2475 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
2476 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
2477 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
2478 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
2479 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
2480 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
2481 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2482 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
2483 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
2484 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
2485 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
2486 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
2487 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
2488 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
2489 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
2490 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
2491 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
2492 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
2493 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
2494 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
2495 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
2496 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
2497 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
2498 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
2499 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
2500 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
2501 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
2502 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
2503 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
2504 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
2505 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
2506 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
2507 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2508 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
2509 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
2510 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
2511 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
2512 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
2513 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
2517 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
2518 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2519 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
2520 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
2521 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2522 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2523 rt2x00_rt(rt2x00dev
, RT3090
)) {
2524 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2525 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
2526 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2528 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
2530 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2531 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
2532 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2533 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
2534 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2535 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
2536 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
2538 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
2540 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2541 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
2542 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
2543 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
2544 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
2548 * Set RX Filter calibration for 20MHz and 40MHz
2550 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
2551 rt2x00dev
->calibration
[0] =
2552 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
2553 rt2x00dev
->calibration
[1] =
2554 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
2555 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2556 rt2x00_rt(rt2x00dev
, RT3090
) ||
2557 rt2x00_rt(rt2x00dev
, RT3390
)) {
2558 rt2x00dev
->calibration
[0] =
2559 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
2560 rt2x00dev
->calibration
[1] =
2561 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
2565 * Set back to initial state
2567 rt2800_bbp_write(rt2x00dev
, 24, 0);
2569 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
2570 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
2571 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
2574 * set BBP back to BW20
2576 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2577 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
2578 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2580 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2581 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2582 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2583 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
2584 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
2586 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
2587 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
2588 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
2590 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2591 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
2592 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2593 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2594 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2595 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
2596 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
2598 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
2599 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
2600 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
2601 rt2x00_get_field16(eeprom
,
2602 EEPROM_TXMIXER_GAIN_BG_VAL
));
2603 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2605 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
2606 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
2608 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2609 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
2610 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
2611 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
2612 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
2614 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
2617 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2618 rt2x00_rt(rt2x00dev
, RT3090
) ||
2619 rt2x00_rt(rt2x00dev
, RT3390
)) {
2620 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2621 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2622 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2623 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2624 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2625 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2626 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2628 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
2629 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
2630 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
2632 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
2633 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
2634 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
2636 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
2637 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
2638 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
2641 if (rt2x00_rt(rt2x00dev
, RT3070
) || rt2x00_rt(rt2x00dev
, RT3071
)) {
2642 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
2643 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2644 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
))
2645 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
2647 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
2648 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
2649 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
2650 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
2651 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
2657 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
2663 * Initialize all registers.
2665 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
2666 rt2800_init_registers(rt2x00dev
) ||
2667 rt2800_init_bbp(rt2x00dev
) ||
2668 rt2800_init_rfcsr(rt2x00dev
)))
2672 * Send signal to firmware during boot time.
2674 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
2676 if (rt2x00_is_usb(rt2x00dev
) &&
2677 (rt2x00_rt(rt2x00dev
, RT3070
) ||
2678 rt2x00_rt(rt2x00dev
, RT3071
) ||
2679 rt2x00_rt(rt2x00dev
, RT3572
))) {
2681 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
2688 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
2689 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
2690 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
2691 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
2695 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2696 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
2697 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
2698 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
2699 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
2700 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2702 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
2703 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
2704 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
2705 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
2708 * Initialize LED control
2710 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED1
, &word
);
2711 rt2800_mcu_request(rt2x00dev
, MCU_LED_1
, 0xff,
2712 word
& 0xff, (word
>> 8) & 0xff);
2714 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED2
, &word
);
2715 rt2800_mcu_request(rt2x00dev
, MCU_LED_2
, 0xff,
2716 word
& 0xff, (word
>> 8) & 0xff);
2718 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED3
, &word
);
2719 rt2800_mcu_request(rt2x00dev
, MCU_LED_3
, 0xff,
2720 word
& 0xff, (word
>> 8) & 0xff);
2724 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
2726 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
2730 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2731 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2732 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2733 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2734 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2735 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
2736 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2738 /* Wait for DMA, ignore error */
2739 rt2800_wait_wpdma_ready(rt2x00dev
);
2741 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
2742 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
2743 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
2744 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
2746 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0);
2747 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, 0);
2749 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
2751 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
2755 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
2757 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
2759 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
2761 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
2765 mutex_lock(&rt2x00dev
->csr_mutex
);
2767 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
2768 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
2769 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
2770 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
2771 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
2773 /* Wait until the EEPROM has been loaded */
2774 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
2776 /* Apparently the data is read from end to start */
2777 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
2778 (u32
*)&rt2x00dev
->eeprom
[i
]);
2779 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
2780 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
2781 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
2782 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
2783 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
2784 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
2786 mutex_unlock(&rt2x00dev
->csr_mutex
);
2789 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
2793 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
2794 rt2800_efuse_read(rt2x00dev
, i
);
2796 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
2798 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2802 u8 default_lna_gain
;
2805 * Start validation of the data that has been read.
2807 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2808 if (!is_valid_ether_addr(mac
)) {
2809 random_ether_addr(mac
);
2810 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2813 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2814 if (word
== 0xffff) {
2815 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2816 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TXPATH
, 1);
2817 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2820
);
2818 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2819 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2820 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
2821 rt2x00_rt(rt2x00dev
, RT2872
)) {
2823 * There is a max of 2 RX streams for RT28x0 series
2825 if (rt2x00_get_field16(word
, EEPROM_ANTENNA_RXPATH
) > 2)
2826 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2827 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2830 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2831 if (word
== 0xffff) {
2832 rt2x00_set_field16(&word
, EEPROM_NIC_HW_RADIO
, 0);
2833 rt2x00_set_field16(&word
, EEPROM_NIC_DYNAMIC_TX_AGC
, 0);
2834 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2835 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2836 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2837 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_BG
, 0);
2838 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_A
, 0);
2839 rt2x00_set_field16(&word
, EEPROM_NIC_WPS_PBC
, 0);
2840 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_BG
, 0);
2841 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_A
, 0);
2842 rt2x00_set_field16(&word
, EEPROM_NIC_ANT_DIVERSITY
, 0);
2843 rt2x00_set_field16(&word
, EEPROM_NIC_DAC_TEST
, 0);
2844 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2845 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2848 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2849 if ((word
& 0x00ff) == 0x00ff) {
2850 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2851 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2852 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2854 if ((word
& 0xff00) == 0xff00) {
2855 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
2856 LED_MODE_TXRX_ACTIVITY
);
2857 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
2858 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2859 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED1
, 0x5555);
2860 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED2
, 0x2221);
2861 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED3
, 0xa9f8);
2862 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
2866 * During the LNA validation we are going to use
2867 * lna0 as correct value. Note that EEPROM_LNA
2868 * is never validated.
2870 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
2871 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
2873 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
2874 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
2875 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
2876 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
2877 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
2878 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
2880 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
2881 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
2882 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
2883 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
2884 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
2885 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
2887 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
2889 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
2890 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
2891 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
2892 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
2893 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
2894 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
2896 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
2897 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
2898 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
2899 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
2900 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
2901 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
2903 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
2905 rt2x00_eeprom_read(rt2x00dev
, EEPROM_MAX_TX_POWER
, &word
);
2906 if (rt2x00_get_field16(word
, EEPROM_MAX_TX_POWER_24GHZ
) == 0xff)
2907 rt2x00_set_field16(&word
, EEPROM_MAX_TX_POWER_24GHZ
, MAX_G_TXPOWER
);
2908 if (rt2x00_get_field16(word
, EEPROM_MAX_TX_POWER_5GHZ
) == 0xff)
2909 rt2x00_set_field16(&word
, EEPROM_MAX_TX_POWER_5GHZ
, MAX_A_TXPOWER
);
2910 rt2x00_eeprom_write(rt2x00dev
, EEPROM_MAX_TX_POWER
, word
);
2914 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
2916 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2923 * Read EEPROM word for configuration.
2925 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2928 * Identify RF chipset.
2930 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2931 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2933 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2934 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2936 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
2937 !rt2x00_rt(rt2x00dev
, RT2872
) &&
2938 !rt2x00_rt(rt2x00dev
, RT2883
) &&
2939 !rt2x00_rt(rt2x00dev
, RT3070
) &&
2940 !rt2x00_rt(rt2x00dev
, RT3071
) &&
2941 !rt2x00_rt(rt2x00dev
, RT3090
) &&
2942 !rt2x00_rt(rt2x00dev
, RT3390
) &&
2943 !rt2x00_rt(rt2x00dev
, RT3572
)) {
2944 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
2948 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
2949 !rt2x00_rf(rt2x00dev
, RF2850
) &&
2950 !rt2x00_rf(rt2x00dev
, RF2720
) &&
2951 !rt2x00_rf(rt2x00dev
, RF2750
) &&
2952 !rt2x00_rf(rt2x00dev
, RF3020
) &&
2953 !rt2x00_rf(rt2x00dev
, RF2020
) &&
2954 !rt2x00_rf(rt2x00dev
, RF3021
) &&
2955 !rt2x00_rf(rt2x00dev
, RF3022
) &&
2956 !rt2x00_rf(rt2x00dev
, RF3052
)) {
2957 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2962 * Identify default antenna configuration.
2964 rt2x00dev
->default_ant
.tx
=
2965 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
);
2966 rt2x00dev
->default_ant
.rx
=
2967 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
);
2970 * Read frequency offset and RF programming sequence.
2972 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2973 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2976 * Read external LNA informations.
2978 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2980 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2981 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2982 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2983 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2986 * Detect if this device has an hardware controlled radio.
2988 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_HW_RADIO
))
2989 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2992 * Store led settings, for correct led behaviour.
2994 #ifdef CONFIG_RT2X00_LIB_LEDS
2995 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2996 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2997 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
2999 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &rt2x00dev
->led_mcu_reg
);
3000 #endif /* CONFIG_RT2X00_LIB_LEDS */
3004 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
3007 * RF value list for rt28xx
3008 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3010 static const struct rf_channel rf_vals
[] = {
3011 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3012 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3013 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3014 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3015 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3016 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3017 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3018 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3019 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3020 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3021 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3022 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3023 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3024 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3026 /* 802.11 UNI / HyperLan 2 */
3027 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3028 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3029 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3030 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3031 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3032 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3033 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3034 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3035 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3036 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3037 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3038 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3040 /* 802.11 HyperLan 2 */
3041 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3042 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3043 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3044 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3045 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3046 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3047 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3048 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3049 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3050 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3051 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3052 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3053 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3054 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3055 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3056 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3059 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3060 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3061 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3062 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3063 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3064 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3065 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3066 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3067 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3068 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3069 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3072 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3073 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3074 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3075 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3076 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3077 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3078 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3082 * RF value list for rt3xxx
3083 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3085 static const struct rf_channel rf_vals_3x
[] = {
3101 /* 802.11 UNI / HyperLan 2 */
3115 /* 802.11 HyperLan 2 */
3147 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
3149 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
3150 struct channel_info
*info
;
3151 char *default_power1
;
3152 char *default_power2
;
3154 unsigned short max_power
;
3158 * Disable powersaving as default on PCI devices.
3160 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
3161 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
3164 * Initialize all hw fields.
3166 rt2x00dev
->hw
->flags
=
3167 IEEE80211_HW_SIGNAL_DBM
|
3168 IEEE80211_HW_SUPPORTS_PS
|
3169 IEEE80211_HW_PS_NULLFUNC_STACK
|
3170 IEEE80211_HW_AMPDU_AGGREGATION
;
3172 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3173 * unless we are capable of sending the buffered frames out after the
3174 * DTIM transmission using rt2x00lib_beacondone. This will send out
3175 * multicast and broadcast traffic immediately instead of buffering it
3176 * infinitly and thus dropping it after some time.
3178 if (!rt2x00_is_usb(rt2x00dev
))
3179 rt2x00dev
->hw
->flags
|=
3180 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
3182 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
3183 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
3184 rt2x00_eeprom_addr(rt2x00dev
,
3185 EEPROM_MAC_ADDR_0
));
3188 * As rt2800 has a global fallback table we cannot specify
3189 * more then one tx rate per frame but since the hw will
3190 * try several rates (based on the fallback table) we should
3191 * initialize max_report_rates to the maximum number of rates
3192 * we are going to try. Otherwise mac80211 will truncate our
3193 * reported tx rates and the rc algortihm will end up with
3196 rt2x00dev
->hw
->max_rates
= 1;
3197 rt2x00dev
->hw
->max_report_rates
= 7;
3198 rt2x00dev
->hw
->max_rate_tries
= 1;
3200 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
3203 * Initialize hw_mode information.
3205 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
3206 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
3208 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
3209 rt2x00_rf(rt2x00dev
, RF2720
)) {
3210 spec
->num_channels
= 14;
3211 spec
->channels
= rf_vals
;
3212 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
3213 rt2x00_rf(rt2x00dev
, RF2750
)) {
3214 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
3215 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
3216 spec
->channels
= rf_vals
;
3217 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
3218 rt2x00_rf(rt2x00dev
, RF2020
) ||
3219 rt2x00_rf(rt2x00dev
, RF3021
) ||
3220 rt2x00_rf(rt2x00dev
, RF3022
)) {
3221 spec
->num_channels
= 14;
3222 spec
->channels
= rf_vals_3x
;
3223 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
3224 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
3225 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
3226 spec
->channels
= rf_vals_3x
;
3230 * Initialize HT information.
3232 if (!rt2x00_rf(rt2x00dev
, RF2020
))
3233 spec
->ht
.ht_supported
= true;
3235 spec
->ht
.ht_supported
= false;
3238 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
3239 IEEE80211_HT_CAP_GRN_FLD
|
3240 IEEE80211_HT_CAP_SGI_20
|
3241 IEEE80211_HT_CAP_SGI_40
;
3243 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) >= 2)
3244 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
3247 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) <<
3248 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
3250 spec
->ht
.ampdu_factor
= 3;
3251 spec
->ht
.ampdu_density
= 4;
3252 spec
->ht
.mcs
.tx_params
=
3253 IEEE80211_HT_MCS_TX_DEFINED
|
3254 IEEE80211_HT_MCS_TX_RX_DIFF
|
3255 ((rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) - 1) <<
3256 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
3258 switch (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
)) {
3260 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
3262 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
3264 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
3265 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
3270 * Create channel information array
3272 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
3276 spec
->channels_info
= info
;
3278 rt2x00_eeprom_read(rt2x00dev
, EEPROM_MAX_TX_POWER
, &eeprom
);
3279 max_power
= rt2x00_get_field16(eeprom
, EEPROM_MAX_TX_POWER_24GHZ
);
3280 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
3281 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
3283 for (i
= 0; i
< 14; i
++) {
3284 info
[i
].max_power
= max_power
;
3285 info
[i
].default_power1
= TXPOWER_G_FROM_DEV(default_power1
[i
]);
3286 info
[i
].default_power2
= TXPOWER_G_FROM_DEV(default_power2
[i
]);
3289 if (spec
->num_channels
> 14) {
3290 max_power
= rt2x00_get_field16(eeprom
, EEPROM_MAX_TX_POWER_5GHZ
);
3291 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
3292 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
3294 for (i
= 14; i
< spec
->num_channels
; i
++) {
3295 info
[i
].max_power
= max_power
;
3296 info
[i
].default_power1
= TXPOWER_A_FROM_DEV(default_power1
[i
]);
3297 info
[i
].default_power2
= TXPOWER_A_FROM_DEV(default_power2
[i
]);
3303 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
3306 * IEEE80211 stack callback functions.
3308 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
3311 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3312 struct mac_iveiv_entry iveiv_entry
;
3315 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
3316 rt2800_register_multiread(rt2x00dev
, offset
,
3317 &iveiv_entry
, sizeof(iveiv_entry
));
3319 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
3320 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
3322 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
3324 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
3326 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3328 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
3330 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
3331 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
3332 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
3334 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
3335 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
3336 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
3338 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
3339 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
3340 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
3342 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
3343 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
3344 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
3346 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
3347 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
3348 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
3350 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
3351 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
3352 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
3354 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
3355 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
3356 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
3360 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
3362 int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
3363 const struct ieee80211_tx_queue_params
*params
)
3365 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3366 struct data_queue
*queue
;
3367 struct rt2x00_field32 field
;
3373 * First pass the configuration through rt2x00lib, that will
3374 * update the queue settings and validate the input. After that
3375 * we are free to update the registers based on the value
3376 * in the queue parameter.
3378 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
3383 * We only need to perform additional register initialization
3389 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
3391 /* Update WMM TXOP register */
3392 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
3393 field
.bit_offset
= (queue_idx
& 1) * 16;
3394 field
.bit_mask
= 0xffff << field
.bit_offset
;
3396 rt2800_register_read(rt2x00dev
, offset
, ®
);
3397 rt2x00_set_field32(®
, field
, queue
->txop
);
3398 rt2800_register_write(rt2x00dev
, offset
, reg
);
3400 /* Update WMM registers */
3401 field
.bit_offset
= queue_idx
* 4;
3402 field
.bit_mask
= 0xf << field
.bit_offset
;
3404 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
3405 rt2x00_set_field32(®
, field
, queue
->aifs
);
3406 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
3408 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
3409 rt2x00_set_field32(®
, field
, queue
->cw_min
);
3410 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
3412 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
3413 rt2x00_set_field32(®
, field
, queue
->cw_max
);
3414 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
3416 /* Update EDCA registers */
3417 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
3419 rt2800_register_read(rt2x00dev
, offset
, ®
);
3420 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
3421 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
3422 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
3423 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
3424 rt2800_register_write(rt2x00dev
, offset
, reg
);
3428 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
3430 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
3432 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
3436 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
3437 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
3438 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
3439 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
3443 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
3445 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
3446 enum ieee80211_ampdu_mlme_action action
,
3447 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
)
3452 case IEEE80211_AMPDU_RX_START
:
3453 case IEEE80211_AMPDU_RX_STOP
:
3454 /* we don't support RX aggregation yet */
3457 case IEEE80211_AMPDU_TX_START
:
3458 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
3460 case IEEE80211_AMPDU_TX_STOP
:
3461 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
3463 case IEEE80211_AMPDU_TX_OPERATIONAL
:
3466 WARNING((struct rt2x00_dev
*)hw
->priv
, "Unknown AMPDU action\n");
3471 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
3473 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
3474 MODULE_VERSION(DRV_VERSION
);
3475 MODULE_DESCRIPTION("Ralink RT2800 library");
3476 MODULE_LICENSE("GPL");