2 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
4 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6 Based on the original rt2800pci.c and rt2800usb.c.
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 Abstract: rt2800 generic device routines.
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/slab.h>
41 #include "rt2800lib.h"
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60 #define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64 #define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
68 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev
) ||
72 !rt2x00_rt(rt2x00dev
, RT2872
))
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
77 rt2x00_rf(rt2x00dev
, RF3021
) ||
78 rt2x00_rf(rt2x00dev
, RF3022
))
81 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
85 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
86 const unsigned int word
, const u8 value
)
90 mutex_lock(&rt2x00dev
->csr_mutex
);
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
96 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
98 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
99 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
100 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
102 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
103 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
105 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
108 mutex_unlock(&rt2x00dev
->csr_mutex
);
111 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
112 const unsigned int word
, u8
*value
)
116 mutex_lock(&rt2x00dev
->csr_mutex
);
119 * Wait until the BBP becomes available, afterwards we
120 * can safely write the read request into the register.
121 * After the data has been written, we wait until hardware
122 * returns the correct value, if at any time the register
123 * doesn't become available in time, reg will be 0xffffffff
124 * which means we return 0xff to the caller.
126 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
128 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
129 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
131 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
225 const u8 command
, const u8 token
,
226 const u8 arg0
, const u8 arg1
)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev
))
236 mutex_lock(&rt2x00dev
->csr_mutex
);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
243 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
244 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
245 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
246 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
247 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
250 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
251 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
254 mutex_unlock(&rt2x00dev
->csr_mutex
);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
258 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
263 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
264 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
265 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
266 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
272 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
275 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
277 void rt2800_write_txwi(__le32
*txwi
, struct txentry_desc
*txdesc
)
282 * Initialize TX Info descriptor
284 rt2x00_desc_read(txwi
, 0, &word
);
285 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
286 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
287 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
, 0);
288 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
289 rt2x00_set_field32(&word
, TXWI_W0_TS
,
290 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
291 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
292 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
293 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
, txdesc
->mpdu_density
);
294 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->txop
);
295 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->mcs
);
296 rt2x00_set_field32(&word
, TXWI_W0_BW
,
297 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
298 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
299 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
300 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->stbc
);
301 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
302 rt2x00_desc_write(txwi
, 0, word
);
304 rt2x00_desc_read(txwi
, 1, &word
);
305 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
306 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
307 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
308 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
309 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->ba_size
);
310 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
311 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
312 txdesc
->key_idx
: 0xff);
313 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
315 rt2x00_set_field32(&word
, TXWI_W1_PACKETID
, txdesc
->queue
+ 1);
316 rt2x00_desc_write(txwi
, 1, word
);
319 * Always write 0 to IV/EIV fields, hardware will insert the IV
320 * from the IVEIV register when TXD_W3_WIV is set to 0.
321 * When TXD_W3_WIV is set to 1 it will use the IV data
322 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
323 * crypto entry in the registers should be used to encrypt the frame.
325 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
326 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
328 EXPORT_SYMBOL_GPL(rt2800_write_txwi
);
330 void rt2800_process_rxwi(struct sk_buff
*skb
, struct rxdone_entry_desc
*rxdesc
)
332 __le32
*rxwi
= (__le32
*) skb
->data
;
335 rt2x00_desc_read(rxwi
, 0, &word
);
337 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
338 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
340 rt2x00_desc_read(rxwi
, 1, &word
);
342 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
343 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
345 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
346 rxdesc
->flags
|= RX_FLAG_40MHZ
;
349 * Detect RX rate, always use MCS as signal type.
351 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
352 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
353 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
356 * Mask of 0x8 bit to remove the short preamble flag.
358 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
359 rxdesc
->signal
&= ~0x8;
361 rt2x00_desc_read(rxwi
, 2, &word
);
364 (rt2x00_get_field32(word
, RXWI_W2_RSSI0
) +
365 rt2x00_get_field32(word
, RXWI_W2_RSSI1
)) / 2;
368 * Remove RXWI descriptor from start of buffer.
370 skb_pull(skb
, RXWI_DESC_SIZE
);
372 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
374 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
376 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
377 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
378 unsigned int beacon_base
;
382 * Disable beaconing while we are reloading the beacon data,
383 * otherwise we might be sending out invalid data.
385 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
386 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
387 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
390 * Add space for the TXWI in front of the skb.
392 skb_push(entry
->skb
, TXWI_DESC_SIZE
);
393 memset(entry
->skb
, 0, TXWI_DESC_SIZE
);
396 * Register descriptor details in skb frame descriptor.
398 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
399 skbdesc
->desc
= entry
->skb
->data
;
400 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
403 * Add the TXWI for the beacon to the skb.
405 rt2800_write_txwi((__le32
*)entry
->skb
->data
, txdesc
);
408 * Dump beacon to userspace through debugfs.
410 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
413 * Write entire beacon with TXWI to register.
415 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
416 rt2800_register_multiwrite(rt2x00dev
, beacon_base
,
417 entry
->skb
->data
, entry
->skb
->len
);
420 * Enable beaconing again.
422 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
423 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 1);
424 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
425 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
428 * Clean up beacon skb.
430 dev_kfree_skb_any(entry
->skb
);
433 EXPORT_SYMBOL(rt2800_write_beacon
);
435 static void inline rt2800_clear_beacon(struct rt2x00_dev
*rt2x00dev
,
436 unsigned int beacon_base
)
441 * For the Beacon base registers we only need to clear
442 * the whole TXWI which (when set to 0) will invalidate
445 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
446 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
449 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
450 const struct rt2x00debug rt2800_rt2x00debug
= {
451 .owner
= THIS_MODULE
,
453 .read
= rt2800_register_read
,
454 .write
= rt2800_register_write
,
455 .flags
= RT2X00DEBUGFS_OFFSET
,
456 .word_base
= CSR_REG_BASE
,
457 .word_size
= sizeof(u32
),
458 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
461 .read
= rt2x00_eeprom_read
,
462 .write
= rt2x00_eeprom_write
,
463 .word_base
= EEPROM_BASE
,
464 .word_size
= sizeof(u16
),
465 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
468 .read
= rt2800_bbp_read
,
469 .write
= rt2800_bbp_write
,
470 .word_base
= BBP_BASE
,
471 .word_size
= sizeof(u8
),
472 .word_count
= BBP_SIZE
/ sizeof(u8
),
475 .read
= rt2x00_rf_read
,
476 .write
= rt2800_rf_write
,
477 .word_base
= RF_BASE
,
478 .word_size
= sizeof(u32
),
479 .word_count
= RF_SIZE
/ sizeof(u32
),
482 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
483 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
485 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
489 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
490 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
492 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
494 #ifdef CONFIG_RT2X00_LIB_LEDS
495 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
496 enum led_brightness brightness
)
498 struct rt2x00_led
*led
=
499 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
500 unsigned int enabled
= brightness
!= LED_OFF
;
501 unsigned int bg_mode
=
502 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
503 unsigned int polarity
=
504 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
505 EEPROM_FREQ_LED_POLARITY
);
506 unsigned int ledmode
=
507 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
508 EEPROM_FREQ_LED_MODE
);
510 if (led
->type
== LED_TYPE_RADIO
) {
511 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
513 } else if (led
->type
== LED_TYPE_ASSOC
) {
514 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
515 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
516 } else if (led
->type
== LED_TYPE_QUALITY
) {
518 * The brightness is divided into 6 levels (0 - 5),
519 * The specs tell us the following levels:
521 * to determine the level in a simple way we can simply
522 * work with bitshifting:
525 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
526 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
531 static int rt2800_blink_set(struct led_classdev
*led_cdev
,
532 unsigned long *delay_on
, unsigned long *delay_off
)
534 struct rt2x00_led
*led
=
535 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
538 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
539 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, *delay_on
);
540 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, *delay_off
);
541 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
546 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
547 struct rt2x00_led
*led
, enum led_type type
)
549 led
->rt2x00dev
= rt2x00dev
;
551 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
552 led
->led_dev
.blink_set
= rt2800_blink_set
;
553 led
->flags
= LED_INITIALIZED
;
555 #endif /* CONFIG_RT2X00_LIB_LEDS */
558 * Configuration handlers.
560 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
561 struct rt2x00lib_crypto
*crypto
,
562 struct ieee80211_key_conf
*key
)
564 struct mac_wcid_entry wcid_entry
;
565 struct mac_iveiv_entry iveiv_entry
;
569 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
571 if (crypto
->cmd
== SET_KEY
) {
572 rt2800_register_read(rt2x00dev
, offset
, ®
);
573 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
574 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
576 * Both the cipher as the BSS Idx numbers are split in a main
577 * value of 3 bits, and a extended field for adding one additional
580 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
581 (crypto
->cipher
& 0x7));
582 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
583 (crypto
->cipher
& 0x8) >> 3);
584 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
585 (crypto
->bssidx
& 0x7));
586 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
587 (crypto
->bssidx
& 0x8) >> 3);
588 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
589 rt2800_register_write(rt2x00dev
, offset
, reg
);
591 rt2800_register_write(rt2x00dev
, offset
, 0);
594 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
596 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
597 if ((crypto
->cipher
== CIPHER_TKIP
) ||
598 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
599 (crypto
->cipher
== CIPHER_AES
))
600 iveiv_entry
.iv
[3] |= 0x20;
601 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
602 rt2800_register_multiwrite(rt2x00dev
, offset
,
603 &iveiv_entry
, sizeof(iveiv_entry
));
605 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
607 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
608 if (crypto
->cmd
== SET_KEY
)
609 memcpy(&wcid_entry
, crypto
->address
, ETH_ALEN
);
610 rt2800_register_multiwrite(rt2x00dev
, offset
,
611 &wcid_entry
, sizeof(wcid_entry
));
614 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
615 struct rt2x00lib_crypto
*crypto
,
616 struct ieee80211_key_conf
*key
)
618 struct hw_key_entry key_entry
;
619 struct rt2x00_field32 field
;
623 if (crypto
->cmd
== SET_KEY
) {
624 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
626 memcpy(key_entry
.key
, crypto
->key
,
627 sizeof(key_entry
.key
));
628 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
629 sizeof(key_entry
.tx_mic
));
630 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
631 sizeof(key_entry
.rx_mic
));
633 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
634 rt2800_register_multiwrite(rt2x00dev
, offset
,
635 &key_entry
, sizeof(key_entry
));
639 * The cipher types are stored over multiple registers
640 * starting with SHARED_KEY_MODE_BASE each word will have
641 * 32 bits and contains the cipher types for 2 bssidx each.
642 * Using the correct defines correctly will cause overhead,
643 * so just calculate the correct offset.
645 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
646 field
.bit_mask
= 0x7 << field
.bit_offset
;
648 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
650 rt2800_register_read(rt2x00dev
, offset
, ®
);
651 rt2x00_set_field32(®
, field
,
652 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
653 rt2800_register_write(rt2x00dev
, offset
, reg
);
656 * Update WCID information
658 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
662 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
664 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
665 struct rt2x00lib_crypto
*crypto
,
666 struct ieee80211_key_conf
*key
)
668 struct hw_key_entry key_entry
;
671 if (crypto
->cmd
== SET_KEY
) {
673 * 1 pairwise key is possible per AID, this means that the AID
674 * equals our hw_key_idx. Make sure the WCID starts _after_ the
675 * last possible shared key entry.
677 if (crypto
->aid
> (256 - 32))
680 key
->hw_key_idx
= 32 + crypto
->aid
;
682 memcpy(key_entry
.key
, crypto
->key
,
683 sizeof(key_entry
.key
));
684 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
685 sizeof(key_entry
.tx_mic
));
686 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
687 sizeof(key_entry
.rx_mic
));
689 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
690 rt2800_register_multiwrite(rt2x00dev
, offset
,
691 &key_entry
, sizeof(key_entry
));
695 * Update WCID information
697 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
701 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
703 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
704 const unsigned int filter_flags
)
709 * Start configuration steps.
710 * Note that the version error will always be dropped
711 * and broadcast frames will always be accepted since
712 * there is no filter for it at this time.
714 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
715 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
716 !(filter_flags
& FIF_FCSFAIL
));
717 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
718 !(filter_flags
& FIF_PLCPFAIL
));
719 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
720 !(filter_flags
& FIF_PROMISC_IN_BSS
));
721 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
722 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
723 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
724 !(filter_flags
& FIF_ALLMULTI
));
725 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
726 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
727 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
728 !(filter_flags
& FIF_CONTROL
));
729 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
730 !(filter_flags
& FIF_CONTROL
));
731 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
732 !(filter_flags
& FIF_CONTROL
));
733 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
734 !(filter_flags
& FIF_CONTROL
));
735 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
736 !(filter_flags
& FIF_CONTROL
));
737 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
738 !(filter_flags
& FIF_PSPOLL
));
739 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
740 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
741 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
742 !(filter_flags
& FIF_CONTROL
));
743 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
745 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
747 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
748 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
752 if (flags
& CONFIG_UPDATE_TYPE
) {
754 * Clear current synchronisation setup.
756 rt2800_clear_beacon(rt2x00dev
,
757 HW_BEACON_OFFSET(intf
->beacon
->entry_idx
));
759 * Enable synchronisation.
761 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
762 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
763 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
764 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
,
765 (conf
->sync
== TSF_SYNC_BEACON
));
766 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
769 if (flags
& CONFIG_UPDATE_MAC
) {
770 reg
= le32_to_cpu(conf
->mac
[1]);
771 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
772 conf
->mac
[1] = cpu_to_le32(reg
);
774 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
775 conf
->mac
, sizeof(conf
->mac
));
778 if (flags
& CONFIG_UPDATE_BSSID
) {
779 reg
= le32_to_cpu(conf
->bssid
[1]);
780 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
781 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
782 conf
->bssid
[1] = cpu_to_le32(reg
);
784 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
785 conf
->bssid
, sizeof(conf
->bssid
));
788 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
790 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
)
794 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
795 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
796 !!erp
->short_preamble
);
797 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
798 !!erp
->short_preamble
);
799 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
801 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
802 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
803 erp
->cts_protection
? 2 : 0);
804 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
806 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
808 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
810 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
811 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, erp
->slot_time
);
812 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
814 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
815 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
816 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
818 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
819 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
820 erp
->beacon_int
* 16);
821 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
823 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
825 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
830 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
831 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
834 * Configure the TX antenna.
836 switch ((int)ant
->tx
) {
838 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
839 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
840 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
843 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
851 * Configure the RX antenna.
853 switch ((int)ant
->rx
) {
855 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
858 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
861 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
865 rt2800_bbp_write(rt2x00dev
, 3, r3
);
866 rt2800_bbp_write(rt2x00dev
, 1, r1
);
868 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
870 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
871 struct rt2x00lib_conf
*libconf
)
876 if (libconf
->rf
.channel
<= 14) {
877 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
878 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
879 } else if (libconf
->rf
.channel
<= 64) {
880 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
881 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
882 } else if (libconf
->rf
.channel
<= 128) {
883 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
884 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
886 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
887 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
890 rt2x00dev
->lna_gain
= lna_gain
;
893 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
894 struct ieee80211_conf
*conf
,
895 struct rf_channel
*rf
,
896 struct channel_info
*info
)
898 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
900 if (rt2x00dev
->default_ant
.tx
== 1)
901 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
903 if (rt2x00dev
->default_ant
.rx
== 1) {
904 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
905 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
906 } else if (rt2x00dev
->default_ant
.rx
== 2)
907 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
909 if (rf
->channel
> 14) {
911 * When TX power is below 0, we should increase it by 7 to
912 * make it a positive value (Minumum value is -7).
913 * However this means that values between 0 and 7 have
914 * double meaning, and we should set a 7DBm boost flag.
916 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
917 (info
->tx_power1
>= 0));
919 if (info
->tx_power1
< 0)
920 info
->tx_power1
+= 7;
922 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
,
923 TXPOWER_A_TO_DEV(info
->tx_power1
));
925 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
926 (info
->tx_power2
>= 0));
928 if (info
->tx_power2
< 0)
929 info
->tx_power2
+= 7;
931 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
,
932 TXPOWER_A_TO_DEV(info
->tx_power2
));
934 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
,
935 TXPOWER_G_TO_DEV(info
->tx_power1
));
936 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
,
937 TXPOWER_G_TO_DEV(info
->tx_power2
));
940 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
942 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
943 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
944 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
945 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
949 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
950 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
951 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
952 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
956 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
957 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
958 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
959 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
962 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
963 struct ieee80211_conf
*conf
,
964 struct rf_channel
*rf
,
965 struct channel_info
*info
)
969 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
970 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
972 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
973 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
974 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
976 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
977 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
978 TXPOWER_G_TO_DEV(info
->tx_power1
));
979 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
981 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
982 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
983 TXPOWER_G_TO_DEV(info
->tx_power2
));
984 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
986 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
987 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
988 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
990 rt2800_rfcsr_write(rt2x00dev
, 24,
991 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
993 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
994 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
995 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
998 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
999 struct ieee80211_conf
*conf
,
1000 struct rf_channel
*rf
,
1001 struct channel_info
*info
)
1004 unsigned int tx_pin
;
1007 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
1008 rt2x00_rf(rt2x00dev
, RF3020
) ||
1009 rt2x00_rf(rt2x00dev
, RF3021
) ||
1010 rt2x00_rf(rt2x00dev
, RF3022
))
1011 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
1013 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
1016 * Change BBP settings
1018 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
1019 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
1020 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
1021 rt2800_bbp_write(rt2x00dev
, 86, 0);
1023 if (rf
->channel
<= 14) {
1024 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1025 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1026 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1028 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
1029 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1032 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
1034 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
1035 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1037 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1040 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
1041 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
1042 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
1043 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
1044 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
1048 /* Turn on unused PA or LNA when not using 1T or 1R */
1049 if (rt2x00dev
->default_ant
.tx
!= 1) {
1050 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
1051 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
1054 /* Turn on unused PA or LNA when not using 1T or 1R */
1055 if (rt2x00dev
->default_ant
.rx
!= 1) {
1056 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
1057 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
1060 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
1061 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
1062 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
1063 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
1064 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, rf
->channel
<= 14);
1065 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
1067 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
1069 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1070 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
1071 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1073 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
1074 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
1075 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
1077 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1078 if (conf_is_ht40(conf
)) {
1079 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
1080 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1081 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
1083 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1084 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
1085 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
1092 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
1096 u32 value
= TXPOWER_G_TO_DEV(txpower
);
1099 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1100 rt2x00_set_field8(&r1
, BBP1_TX_POWER
, 0);
1101 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1103 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
1104 rt2x00_set_field32(®
, TX_PWR_CFG_0_1MBS
, value
);
1105 rt2x00_set_field32(®
, TX_PWR_CFG_0_2MBS
, value
);
1106 rt2x00_set_field32(®
, TX_PWR_CFG_0_55MBS
, value
);
1107 rt2x00_set_field32(®
, TX_PWR_CFG_0_11MBS
, value
);
1108 rt2x00_set_field32(®
, TX_PWR_CFG_0_6MBS
, value
);
1109 rt2x00_set_field32(®
, TX_PWR_CFG_0_9MBS
, value
);
1110 rt2x00_set_field32(®
, TX_PWR_CFG_0_12MBS
, value
);
1111 rt2x00_set_field32(®
, TX_PWR_CFG_0_18MBS
, value
);
1112 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0
, reg
);
1114 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_1
, ®
);
1115 rt2x00_set_field32(®
, TX_PWR_CFG_1_24MBS
, value
);
1116 rt2x00_set_field32(®
, TX_PWR_CFG_1_36MBS
, value
);
1117 rt2x00_set_field32(®
, TX_PWR_CFG_1_48MBS
, value
);
1118 rt2x00_set_field32(®
, TX_PWR_CFG_1_54MBS
, value
);
1119 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS0
, value
);
1120 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS1
, value
);
1121 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS2
, value
);
1122 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS3
, value
);
1123 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1
, reg
);
1125 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_2
, ®
);
1126 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS4
, value
);
1127 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS5
, value
);
1128 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS6
, value
);
1129 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS7
, value
);
1130 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS8
, value
);
1131 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS9
, value
);
1132 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS10
, value
);
1133 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS11
, value
);
1134 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2
, reg
);
1136 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_3
, ®
);
1137 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS12
, value
);
1138 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS13
, value
);
1139 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS14
, value
);
1140 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS15
, value
);
1141 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN1
, value
);
1142 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN2
, value
);
1143 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN3
, value
);
1144 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN4
, value
);
1145 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3
, reg
);
1147 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_4
, ®
);
1148 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN5
, value
);
1149 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN6
, value
);
1150 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN7
, value
);
1151 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN8
, value
);
1152 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4
, reg
);
1155 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
1156 struct rt2x00lib_conf
*libconf
)
1160 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1161 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
1162 libconf
->conf
->short_frame_max_tx_count
);
1163 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
1164 libconf
->conf
->long_frame_max_tx_count
);
1165 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1168 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
1169 struct rt2x00lib_conf
*libconf
)
1171 enum dev_state state
=
1172 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
1173 STATE_SLEEP
: STATE_AWAKE
;
1176 if (state
== STATE_SLEEP
) {
1177 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
1179 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1180 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
1181 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
1182 libconf
->conf
->listen_interval
- 1);
1183 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
1184 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1186 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1188 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1189 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
1190 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
1191 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
1192 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1194 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1198 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
1199 struct rt2x00lib_conf
*libconf
,
1200 const unsigned int flags
)
1202 /* Always recalculate LNA gain before changing configuration */
1203 rt2800_config_lna_gain(rt2x00dev
, libconf
);
1205 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
1206 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
1207 &libconf
->rf
, &libconf
->channel
);
1208 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
1209 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1210 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1211 rt2800_config_retry_limit(rt2x00dev
, libconf
);
1212 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1213 rt2800_config_ps(rt2x00dev
, libconf
);
1215 EXPORT_SYMBOL_GPL(rt2800_config
);
1220 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1225 * Update FCS error count from register.
1227 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1228 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
1230 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
1232 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
1234 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
1235 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1236 rt2x00_rt(rt2x00dev
, RT3071
) ||
1237 rt2x00_rt(rt2x00dev
, RT3090
) ||
1238 rt2x00_rt(rt2x00dev
, RT3390
))
1239 return 0x1c + (2 * rt2x00dev
->lna_gain
);
1241 return 0x2e + rt2x00dev
->lna_gain
;
1244 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
1245 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
1247 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
1250 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1251 struct link_qual
*qual
, u8 vgc_level
)
1253 if (qual
->vgc_level
!= vgc_level
) {
1254 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
1255 qual
->vgc_level
= vgc_level
;
1256 qual
->vgc_level_reg
= vgc_level
;
1260 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1262 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
1264 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
1266 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
1269 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
1273 * When RSSI is better then -80 increase VGC level with 0x10
1275 rt2800_set_vgc(rt2x00dev
, qual
,
1276 rt2800_get_default_vgc(rt2x00dev
) +
1277 ((qual
->rssi
> -80) * 0x10));
1279 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
1282 * Initialization functions.
1284 int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
1291 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1292 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1293 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1294 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1295 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1296 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
1297 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1299 ret
= rt2800_drv_init_registers(rt2x00dev
);
1303 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
1304 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
1305 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
1306 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
1307 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
1308 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
1310 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
1311 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
1312 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
1313 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
1314 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
1315 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
1317 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
1318 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1320 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1322 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1323 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 0);
1324 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
1325 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
1326 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
1327 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1328 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
1329 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1331 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
1333 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1334 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
1335 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
1336 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1338 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1339 rt2x00_rt(rt2x00dev
, RT3090
) ||
1340 rt2x00_rt(rt2x00dev
, RT3390
)) {
1341 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1342 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1343 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1344 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1345 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
1346 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1347 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
1348 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1351 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1354 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1356 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1357 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1359 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1360 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1361 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
1363 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1364 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1366 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
1367 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1368 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1369 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000001f);
1371 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
1372 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1375 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
1376 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
1377 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
1378 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
1379 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
1380 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
1381 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
1382 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
1383 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
1384 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
1386 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
1387 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
1388 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
1389 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
1390 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
1392 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
1393 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
1394 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
1395 rt2x00_rt(rt2x00dev
, RT2883
) ||
1396 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
1397 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
1399 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
1400 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
1401 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
1402 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
1404 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1405 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
1406 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
1407 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
1408 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
1409 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
1410 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
1411 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
1412 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1414 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
1416 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1417 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
1418 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
1419 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
1420 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
1421 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
1422 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
1423 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1425 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1426 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
1427 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
1428 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
1429 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
1430 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
1431 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
1432 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
1433 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1435 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
1436 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
1437 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
1438 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV
, 1);
1439 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1440 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1441 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1442 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1443 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1444 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1445 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
1446 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
1448 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1449 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
1450 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
1451 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV
, 1);
1452 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1453 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1454 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1455 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1456 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1457 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1458 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
1459 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1461 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1462 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
1463 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
1464 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV
, 1);
1465 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1466 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1467 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1468 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1469 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1470 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1471 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
1472 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1474 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1475 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
1476 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
,
1477 !rt2x00_is_usb(rt2x00dev
));
1478 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV
, 1);
1479 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1480 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1481 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1482 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1483 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1484 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1485 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
1486 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1488 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1489 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
1490 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
1491 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV
, 1);
1492 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1493 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1494 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1495 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1496 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1497 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1498 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
1499 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1501 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1502 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
1503 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
1504 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV
, 1);
1505 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1506 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1507 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1508 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1509 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1510 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1511 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
1512 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1514 if (rt2x00_is_usb(rt2x00dev
)) {
1515 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
1517 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1518 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1519 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1520 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1521 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1522 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
1523 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
1524 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
1525 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
1526 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
1527 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1530 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, 0x0000583f);
1531 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
1533 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
1534 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
1535 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
1536 IEEE80211_MAX_RTS_THRESHOLD
);
1537 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
1538 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
1540 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
1543 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1544 * time should be set to 16. However, the original Ralink driver uses
1545 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1546 * connection problems with 11g + CTS protection. Hence, use the same
1547 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1549 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1550 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
1551 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
1552 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
1553 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
1554 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
1555 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1557 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
1560 * ASIC will keep garbage value after boot, clear encryption keys.
1562 for (i
= 0; i
< 4; i
++)
1563 rt2800_register_write(rt2x00dev
,
1564 SHARED_KEY_MODE_ENTRY(i
), 0);
1566 for (i
= 0; i
< 256; i
++) {
1567 u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
1568 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
1569 wcid
, sizeof(wcid
));
1571 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 1);
1572 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
1578 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE0
);
1579 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE1
);
1580 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE2
);
1581 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE3
);
1582 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE4
);
1583 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE5
);
1584 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE6
);
1585 rt2800_clear_beacon(rt2x00dev
, HW_BEACON_BASE7
);
1587 if (rt2x00_is_usb(rt2x00dev
)) {
1588 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
1589 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
1590 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
1593 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
1594 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
1595 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
1596 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
1597 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
1598 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
1599 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
1600 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
1601 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
1602 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
1604 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
1605 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
1606 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
1607 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
1608 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
1609 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
1610 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
1611 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
1612 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
1613 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
1615 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
1616 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
1617 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
1618 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
1619 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
1620 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
1621 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
1622 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
1623 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
1624 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
1626 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
1627 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
1628 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
1629 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
1630 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
1631 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
1634 * We must clear the error counters.
1635 * These registers are cleared on read,
1636 * so we may pass a useless variable to store the value.
1638 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1639 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
1640 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
1641 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
1642 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
1643 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
1647 EXPORT_SYMBOL_GPL(rt2800_init_registers
);
1649 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
1654 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1655 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
1656 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
1659 udelay(REGISTER_BUSY_DELAY
);
1662 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
1666 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1672 * BBP was enabled after firmware was loaded,
1673 * but we need to reactivate it now.
1675 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
1676 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1679 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1680 rt2800_bbp_read(rt2x00dev
, 0, &value
);
1681 if ((value
!= 0xff) && (value
!= 0x00))
1683 udelay(REGISTER_BUSY_DELAY
);
1686 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1690 int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1697 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
1698 rt2800_wait_bbp_ready(rt2x00dev
)))
1701 if (rt2800_is_305x_soc(rt2x00dev
))
1702 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
1704 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
1705 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
1707 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1708 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1709 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
1711 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
1712 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
1715 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1717 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1718 rt2x00_rt(rt2x00dev
, RT3071
) ||
1719 rt2x00_rt(rt2x00dev
, RT3090
) ||
1720 rt2x00_rt(rt2x00dev
, RT3390
)) {
1721 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
1722 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
1723 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
1724 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
1725 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
1726 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
1728 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
1731 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1732 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
1734 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
1735 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
1737 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
1739 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
1740 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
1741 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
1743 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
1744 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1745 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1746 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
1747 rt2800_is_305x_soc(rt2x00dev
))
1748 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
1750 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
1752 if (rt2800_is_305x_soc(rt2x00dev
))
1753 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
1755 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
1756 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
1758 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1759 rt2x00_rt(rt2x00dev
, RT3090
) ||
1760 rt2x00_rt(rt2x00dev
, RT3390
)) {
1761 rt2800_bbp_read(rt2x00dev
, 138, &value
);
1763 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1764 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
1766 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
1769 rt2800_bbp_write(rt2x00dev
, 138, value
);
1773 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1774 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1776 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1777 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1778 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1779 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
1785 EXPORT_SYMBOL_GPL(rt2800_init_bbp
);
1787 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
1788 bool bw40
, u8 rfcsr24
, u8 filter_target
)
1797 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1799 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1800 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
1801 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1803 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
1804 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
1805 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
1808 * Set power & frequency of passband test tone
1810 rt2800_bbp_write(rt2x00dev
, 24, 0);
1812 for (i
= 0; i
< 100; i
++) {
1813 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1816 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
1822 * Set power & frequency of stopband test tone
1824 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
1826 for (i
= 0; i
< 100; i
++) {
1827 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1830 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
1832 if ((passband
- stopband
) <= filter_target
) {
1834 overtuned
+= ((passband
- stopband
) == filter_target
);
1838 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1841 rfcsr24
-= !!overtuned
;
1843 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1847 int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
1854 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
1855 !rt2x00_rt(rt2x00dev
, RT3071
) &&
1856 !rt2x00_rt(rt2x00dev
, RT3090
) &&
1857 !rt2x00_rt(rt2x00dev
, RT3390
) &&
1858 !rt2800_is_305x_soc(rt2x00dev
))
1862 * Init RF calibration.
1864 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1865 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1866 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1868 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1869 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1871 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1872 rt2x00_rt(rt2x00dev
, RT3071
) ||
1873 rt2x00_rt(rt2x00dev
, RT3090
)) {
1874 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1875 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
1876 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
1877 rt2800_rfcsr_write(rt2x00dev
, 7, 0x70);
1878 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
1879 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
1880 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1881 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
1882 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1883 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
1884 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
1885 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
1886 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
1887 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
1888 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
1889 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
1890 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
1891 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1892 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
1893 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1894 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
1895 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
1896 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
1897 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
1898 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1899 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
1900 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
1901 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
1902 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
1903 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1904 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
1905 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1906 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
1907 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
1908 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1909 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1910 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
1911 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
1912 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
1913 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
1914 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
1915 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
1916 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
1917 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
1918 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
1919 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1920 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1921 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1922 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
1923 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
1924 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
1925 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
1926 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
1927 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
1928 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
1929 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
1930 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
1931 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1932 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
1933 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
1934 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
1935 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
1936 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
1937 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
1938 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1939 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
1940 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
1941 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1942 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
1943 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
1944 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
1945 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
1946 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
1947 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
1948 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
1949 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
1950 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
1951 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
1952 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1953 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
1954 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
1955 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
1956 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
1957 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
1958 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
1962 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1963 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
1964 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
1965 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
1966 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
1967 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1968 rt2x00_rt(rt2x00dev
, RT3090
)) {
1969 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1970 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
1971 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1973 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
1975 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
1976 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
1977 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1978 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
1979 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1980 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
1981 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
1983 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
1985 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
1986 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1987 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1988 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
1989 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1993 * Set RX Filter calibration for 20MHz and 40MHz
1995 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1996 rt2x00dev
->calibration
[0] =
1997 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
1998 rt2x00dev
->calibration
[1] =
1999 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
2000 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2001 rt2x00_rt(rt2x00dev
, RT3090
) ||
2002 rt2x00_rt(rt2x00dev
, RT3390
)) {
2003 rt2x00dev
->calibration
[0] =
2004 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
2005 rt2x00dev
->calibration
[1] =
2006 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
2010 * Set back to initial state
2012 rt2800_bbp_write(rt2x00dev
, 24, 0);
2014 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
2015 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
2016 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
2019 * set BBP back to BW20
2021 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2022 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
2023 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2025 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2026 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2027 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2028 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
2029 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
2031 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
2032 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
2033 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
2035 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2036 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
2037 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2038 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2039 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2040 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
2041 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
2043 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
2044 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
2045 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
2046 rt2x00_get_field16(eeprom
,
2047 EEPROM_TXMIXER_GAIN_BG_VAL
));
2048 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2050 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
2051 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
2053 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2054 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
2055 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
2056 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
2057 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
2059 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
2062 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2063 rt2x00_rt(rt2x00dev
, RT3090
) ||
2064 rt2x00_rt(rt2x00dev
, RT3390
)) {
2065 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2066 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2067 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2068 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2069 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2070 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2071 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2073 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
2074 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
2075 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
2077 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
2078 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
2079 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
2081 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
2082 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
2083 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
2086 if (rt2x00_rt(rt2x00dev
, RT3070
) || rt2x00_rt(rt2x00dev
, RT3071
)) {
2087 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
2088 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2089 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
))
2090 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
2092 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
2093 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
2094 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
2095 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
2096 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
2101 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr
);
2103 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
2107 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
2109 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
2111 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
2113 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
2117 mutex_lock(&rt2x00dev
->csr_mutex
);
2119 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
2120 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
2121 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
2122 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
2123 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
2125 /* Wait until the EEPROM has been loaded */
2126 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
2128 /* Apparently the data is read from end to start */
2129 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
2130 (u32
*)&rt2x00dev
->eeprom
[i
]);
2131 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
2132 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
2133 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
2134 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
2135 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
2136 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
2138 mutex_unlock(&rt2x00dev
->csr_mutex
);
2141 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
2145 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
2146 rt2800_efuse_read(rt2x00dev
, i
);
2148 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
2150 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2154 u8 default_lna_gain
;
2157 * Start validation of the data that has been read.
2159 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2160 if (!is_valid_ether_addr(mac
)) {
2161 random_ether_addr(mac
);
2162 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2165 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2166 if (word
== 0xffff) {
2167 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2168 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TXPATH
, 1);
2169 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2820
);
2170 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2171 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2172 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
2173 rt2x00_rt(rt2x00dev
, RT2872
)) {
2175 * There is a max of 2 RX streams for RT28x0 series
2177 if (rt2x00_get_field16(word
, EEPROM_ANTENNA_RXPATH
) > 2)
2178 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2179 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2182 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2183 if (word
== 0xffff) {
2184 rt2x00_set_field16(&word
, EEPROM_NIC_HW_RADIO
, 0);
2185 rt2x00_set_field16(&word
, EEPROM_NIC_DYNAMIC_TX_AGC
, 0);
2186 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2187 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2188 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2189 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_BG
, 0);
2190 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_A
, 0);
2191 rt2x00_set_field16(&word
, EEPROM_NIC_WPS_PBC
, 0);
2192 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_BG
, 0);
2193 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_A
, 0);
2194 rt2x00_set_field16(&word
, EEPROM_NIC_ANT_DIVERSITY
, 0);
2195 rt2x00_set_field16(&word
, EEPROM_NIC_DAC_TEST
, 0);
2196 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2197 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2200 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2201 if ((word
& 0x00ff) == 0x00ff) {
2202 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2203 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2204 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2206 if ((word
& 0xff00) == 0xff00) {
2207 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
2208 LED_MODE_TXRX_ACTIVITY
);
2209 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
2210 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2211 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED1
, 0x5555);
2212 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED2
, 0x2221);
2213 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED3
, 0xa9f8);
2214 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
2218 * During the LNA validation we are going to use
2219 * lna0 as correct value. Note that EEPROM_LNA
2220 * is never validated.
2222 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
2223 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
2225 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
2226 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
2227 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
2228 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
2229 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
2230 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
2232 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
2233 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
2234 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
2235 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
2236 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
2237 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
2239 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
2241 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
2242 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
2243 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
2244 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
2245 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
2246 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
2248 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
2249 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
2250 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
2251 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
2252 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
2253 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
2255 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
2259 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
2261 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2268 * Read EEPROM word for configuration.
2270 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2273 * Identify RF chipset.
2275 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2276 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2278 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2279 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2281 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
2282 !rt2x00_rt(rt2x00dev
, RT2872
) &&
2283 !rt2x00_rt(rt2x00dev
, RT2883
) &&
2284 !rt2x00_rt(rt2x00dev
, RT3070
) &&
2285 !rt2x00_rt(rt2x00dev
, RT3071
) &&
2286 !rt2x00_rt(rt2x00dev
, RT3090
) &&
2287 !rt2x00_rt(rt2x00dev
, RT3390
) &&
2288 !rt2x00_rt(rt2x00dev
, RT3572
)) {
2289 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
2293 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
2294 !rt2x00_rf(rt2x00dev
, RF2850
) &&
2295 !rt2x00_rf(rt2x00dev
, RF2720
) &&
2296 !rt2x00_rf(rt2x00dev
, RF2750
) &&
2297 !rt2x00_rf(rt2x00dev
, RF3020
) &&
2298 !rt2x00_rf(rt2x00dev
, RF2020
) &&
2299 !rt2x00_rf(rt2x00dev
, RF3021
) &&
2300 !rt2x00_rf(rt2x00dev
, RF3022
) &&
2301 !rt2x00_rf(rt2x00dev
, RF3052
)) {
2302 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2307 * Identify default antenna configuration.
2309 rt2x00dev
->default_ant
.tx
=
2310 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
);
2311 rt2x00dev
->default_ant
.rx
=
2312 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
);
2315 * Read frequency offset and RF programming sequence.
2317 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2318 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2321 * Read external LNA informations.
2323 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2325 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2326 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2327 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2328 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2331 * Detect if this device has an hardware controlled radio.
2333 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_HW_RADIO
))
2334 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2337 * Store led settings, for correct led behaviour.
2339 #ifdef CONFIG_RT2X00_LIB_LEDS
2340 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2341 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2342 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
2344 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &rt2x00dev
->led_mcu_reg
);
2345 #endif /* CONFIG_RT2X00_LIB_LEDS */
2349 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
2352 * RF value list for rt28xx
2353 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2355 static const struct rf_channel rf_vals
[] = {
2356 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2357 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2358 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2359 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2360 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2361 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2362 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2363 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2364 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2365 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2366 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2367 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2368 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2369 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2371 /* 802.11 UNI / HyperLan 2 */
2372 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2373 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2374 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2375 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2376 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2377 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2378 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2379 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2380 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2381 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2382 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2383 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2385 /* 802.11 HyperLan 2 */
2386 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2387 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2388 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2389 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2390 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2391 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2392 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2393 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2394 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2395 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2396 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2397 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2398 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2399 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2400 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2401 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2404 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2405 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2406 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2407 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2408 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2409 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2410 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2411 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2412 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2413 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2414 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2417 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2418 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2419 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2420 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2421 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2422 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2423 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2427 * RF value list for rt3xxx
2428 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2430 static const struct rf_channel rf_vals_3x
[] = {
2446 /* 802.11 UNI / HyperLan 2 */
2460 /* 802.11 HyperLan 2 */
2492 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2494 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2495 struct channel_info
*info
;
2502 * Disable powersaving as default on PCI devices.
2504 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
2505 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2508 * Initialize all hw fields.
2510 rt2x00dev
->hw
->flags
=
2511 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2512 IEEE80211_HW_SIGNAL_DBM
|
2513 IEEE80211_HW_SUPPORTS_PS
|
2514 IEEE80211_HW_PS_NULLFUNC_STACK
|
2515 IEEE80211_HW_AMPDU_AGGREGATION
;
2517 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2518 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2519 rt2x00_eeprom_addr(rt2x00dev
,
2520 EEPROM_MAC_ADDR_0
));
2523 * As rt2800 has a global fallback table we cannot specify
2524 * more then one tx rate per frame but since the hw will
2525 * try several rates (based on the fallback table) we should
2526 * still initialize max_rates to the maximum number of rates
2527 * we are going to try. Otherwise mac80211 will truncate our
2528 * reported tx rates and the rc algortihm will end up with
2531 rt2x00dev
->hw
->max_rates
= 7;
2532 rt2x00dev
->hw
->max_rate_tries
= 1;
2534 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2537 * Initialize hw_mode information.
2539 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2540 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2542 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
2543 rt2x00_rf(rt2x00dev
, RF2720
)) {
2544 spec
->num_channels
= 14;
2545 spec
->channels
= rf_vals
;
2546 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
2547 rt2x00_rf(rt2x00dev
, RF2750
)) {
2548 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2549 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
2550 spec
->channels
= rf_vals
;
2551 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
2552 rt2x00_rf(rt2x00dev
, RF2020
) ||
2553 rt2x00_rf(rt2x00dev
, RF3021
) ||
2554 rt2x00_rf(rt2x00dev
, RF3022
)) {
2555 spec
->num_channels
= 14;
2556 spec
->channels
= rf_vals_3x
;
2557 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
2558 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2559 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
2560 spec
->channels
= rf_vals_3x
;
2564 * Initialize HT information.
2566 if (!rt2x00_rf(rt2x00dev
, RF2020
))
2567 spec
->ht
.ht_supported
= true;
2569 spec
->ht
.ht_supported
= false;
2572 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
2573 IEEE80211_HT_CAP_GRN_FLD
|
2574 IEEE80211_HT_CAP_SGI_20
|
2575 IEEE80211_HT_CAP_SGI_40
|
2576 IEEE80211_HT_CAP_RX_STBC
;
2578 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) >= 2)
2579 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
2581 spec
->ht
.ampdu_factor
= 3;
2582 spec
->ht
.ampdu_density
= 4;
2583 spec
->ht
.mcs
.tx_params
=
2584 IEEE80211_HT_MCS_TX_DEFINED
|
2585 IEEE80211_HT_MCS_TX_RX_DIFF
|
2586 ((rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) - 1) <<
2587 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
2589 switch (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
)) {
2591 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
2593 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
2595 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
2596 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
2601 * Create channel information array
2603 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2607 spec
->channels_info
= info
;
2609 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
2610 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
2612 for (i
= 0; i
< 14; i
++) {
2613 info
[i
].tx_power1
= TXPOWER_G_FROM_DEV(tx_power1
[i
]);
2614 info
[i
].tx_power2
= TXPOWER_G_FROM_DEV(tx_power2
[i
]);
2617 if (spec
->num_channels
> 14) {
2618 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
2619 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
2621 for (i
= 14; i
< spec
->num_channels
; i
++) {
2622 info
[i
].tx_power1
= TXPOWER_A_FROM_DEV(tx_power1
[i
]);
2623 info
[i
].tx_power2
= TXPOWER_A_FROM_DEV(tx_power2
[i
]);
2629 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
2632 * IEEE80211 stack callback functions.
2634 static void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
,
2635 u32
*iv32
, u16
*iv16
)
2637 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2638 struct mac_iveiv_entry iveiv_entry
;
2641 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
2642 rt2800_register_multiread(rt2x00dev
, offset
,
2643 &iveiv_entry
, sizeof(iveiv_entry
));
2645 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
2646 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
2649 static int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
2651 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2653 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
2655 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2656 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
2657 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2659 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2660 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
2661 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2663 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2664 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
2665 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2667 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2668 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
2669 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2671 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2672 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
2673 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2675 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2676 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
2677 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2679 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2680 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
2681 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2686 static int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2687 const struct ieee80211_tx_queue_params
*params
)
2689 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2690 struct data_queue
*queue
;
2691 struct rt2x00_field32 field
;
2697 * First pass the configuration through rt2x00lib, that will
2698 * update the queue settings and validate the input. After that
2699 * we are free to update the registers based on the value
2700 * in the queue parameter.
2702 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2707 * We only need to perform additional register initialization
2713 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2715 /* Update WMM TXOP register */
2716 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2717 field
.bit_offset
= (queue_idx
& 1) * 16;
2718 field
.bit_mask
= 0xffff << field
.bit_offset
;
2720 rt2800_register_read(rt2x00dev
, offset
, ®
);
2721 rt2x00_set_field32(®
, field
, queue
->txop
);
2722 rt2800_register_write(rt2x00dev
, offset
, reg
);
2724 /* Update WMM registers */
2725 field
.bit_offset
= queue_idx
* 4;
2726 field
.bit_mask
= 0xf << field
.bit_offset
;
2728 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
2729 rt2x00_set_field32(®
, field
, queue
->aifs
);
2730 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
2732 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
2733 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2734 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
2736 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
2737 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2738 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
2740 /* Update EDCA registers */
2741 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
2743 rt2800_register_read(rt2x00dev
, offset
, ®
);
2744 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
2745 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
2746 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
2747 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
2748 rt2800_register_write(rt2x00dev
, offset
, reg
);
2753 static u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
2755 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2759 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
2760 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
2761 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
2762 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
2767 static int rt2800_ampdu_action(struct ieee80211_hw
*hw
,
2768 struct ieee80211_vif
*vif
,
2769 enum ieee80211_ampdu_mlme_action action
,
2770 struct ieee80211_sta
*sta
,
2773 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2777 case IEEE80211_AMPDU_RX_START
:
2778 case IEEE80211_AMPDU_RX_STOP
:
2779 /* we don't support RX aggregation yet */
2782 case IEEE80211_AMPDU_TX_START
:
2783 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
2785 case IEEE80211_AMPDU_TX_STOP
:
2786 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
2788 case IEEE80211_AMPDU_TX_OPERATIONAL
:
2791 WARNING(rt2x00dev
, "Unknown AMPDU action\n");
2797 const struct ieee80211_ops rt2800_mac80211_ops
= {
2799 .start
= rt2x00mac_start
,
2800 .stop
= rt2x00mac_stop
,
2801 .add_interface
= rt2x00mac_add_interface
,
2802 .remove_interface
= rt2x00mac_remove_interface
,
2803 .config
= rt2x00mac_config
,
2804 .configure_filter
= rt2x00mac_configure_filter
,
2805 .set_tim
= rt2x00mac_set_tim
,
2806 .set_key
= rt2x00mac_set_key
,
2807 .get_stats
= rt2x00mac_get_stats
,
2808 .get_tkip_seq
= rt2800_get_tkip_seq
,
2809 .set_rts_threshold
= rt2800_set_rts_threshold
,
2810 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2811 .conf_tx
= rt2800_conf_tx
,
2812 .get_tsf
= rt2800_get_tsf
,
2813 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2814 .ampdu_action
= rt2800_ampdu_action
,
2816 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops
);
2818 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
2819 MODULE_VERSION(DRV_VERSION
);
2820 MODULE_DESCRIPTION("Ralink RT2800 library");
2821 MODULE_LICENSE("GPL");