2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
41 * Allow hardware encryption to be disabled.
43 static int modparam_nohwcrypt
= 0;
44 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
45 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
58 static u32
rt61pci_bbp_check(struct rt2x00_dev
*rt2x00dev
)
63 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
64 rt2x00pci_register_read(rt2x00dev
, PHY_CSR3
, ®
);
65 if (!rt2x00_get_field32(reg
, PHY_CSR3_BUSY
))
67 udelay(REGISTER_BUSY_DELAY
);
73 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
74 const unsigned int word
, const u8 value
)
79 * Wait until the BBP becomes ready.
81 reg
= rt61pci_bbp_check(rt2x00dev
);
82 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
83 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Write failed.\n");
88 * Write the data into the BBP.
91 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
92 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
93 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
94 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
96 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
99 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
100 const unsigned int word
, u8
*value
)
105 * Wait until the BBP becomes ready.
107 reg
= rt61pci_bbp_check(rt2x00dev
);
108 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
109 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
114 * Write the request into the BBP.
117 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
118 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
119 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
121 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
124 * Wait until the BBP becomes ready.
126 reg
= rt61pci_bbp_check(rt2x00dev
);
127 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
128 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
133 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
136 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
137 const unsigned int word
, const u32 value
)
145 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
146 rt2x00pci_register_read(rt2x00dev
, PHY_CSR4
, ®
);
147 if (!rt2x00_get_field32(reg
, PHY_CSR4_BUSY
))
149 udelay(REGISTER_BUSY_DELAY
);
152 ERROR(rt2x00dev
, "PHY_CSR4 register busy. Write failed.\n");
157 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
158 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
159 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
160 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
162 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
163 rt2x00_rf_write(rt2x00dev
, word
, value
);
166 #ifdef CONFIG_RT61PCI_LEDS
168 * This function is only called from rt61pci_led_brightness()
169 * make gcc happy by placing this function inside the
170 * same ifdef statement as the caller.
172 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
173 const u8 command
, const u8 token
,
174 const u8 arg0
, const u8 arg1
)
178 rt2x00pci_register_read(rt2x00dev
, H2M_MAILBOX_CSR
, ®
);
180 if (rt2x00_get_field32(reg
, H2M_MAILBOX_CSR_OWNER
)) {
181 ERROR(rt2x00dev
, "mcu request error. "
182 "Request 0x%02x failed for token 0x%02x.\n",
187 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
188 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
189 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
190 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
191 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
193 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
194 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
195 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
196 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
198 #endif /* CONFIG_RT61PCI_LEDS */
200 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
202 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
205 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
207 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
208 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
209 eeprom
->reg_data_clock
=
210 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
211 eeprom
->reg_chip_select
=
212 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
215 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
217 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
220 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
221 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
222 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
223 !!eeprom
->reg_data_clock
);
224 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
225 !!eeprom
->reg_chip_select
);
227 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
230 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
231 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
233 static void rt61pci_read_csr(struct rt2x00_dev
*rt2x00dev
,
234 const unsigned int word
, u32
*data
)
236 rt2x00pci_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
239 static void rt61pci_write_csr(struct rt2x00_dev
*rt2x00dev
,
240 const unsigned int word
, u32 data
)
242 rt2x00pci_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
245 static const struct rt2x00debug rt61pci_rt2x00debug
= {
246 .owner
= THIS_MODULE
,
248 .read
= rt61pci_read_csr
,
249 .write
= rt61pci_write_csr
,
250 .word_size
= sizeof(u32
),
251 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
254 .read
= rt2x00_eeprom_read
,
255 .write
= rt2x00_eeprom_write
,
256 .word_size
= sizeof(u16
),
257 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
260 .read
= rt61pci_bbp_read
,
261 .write
= rt61pci_bbp_write
,
262 .word_size
= sizeof(u8
),
263 .word_count
= BBP_SIZE
/ sizeof(u8
),
266 .read
= rt2x00_rf_read
,
267 .write
= rt61pci_rf_write
,
268 .word_size
= sizeof(u32
),
269 .word_count
= RF_SIZE
/ sizeof(u32
),
272 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
274 #ifdef CONFIG_RT61PCI_RFKILL
275 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
279 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
280 return rt2x00_get_field32(reg
, MAC_CSR13_BIT5
);
283 #define rt61pci_rfkill_poll NULL
284 #endif /* CONFIG_RT61PCI_RFKILL */
286 #ifdef CONFIG_RT61PCI_LEDS
287 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
288 enum led_brightness brightness
)
290 struct rt2x00_led
*led
=
291 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
292 unsigned int enabled
= brightness
!= LED_OFF
;
293 unsigned int a_mode
=
294 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
295 unsigned int bg_mode
=
296 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
298 if (led
->type
== LED_TYPE_RADIO
) {
299 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
300 MCU_LEDCS_RADIO_STATUS
, enabled
);
302 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
303 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
304 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
305 } else if (led
->type
== LED_TYPE_ASSOC
) {
306 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
307 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
308 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
309 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
311 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
312 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
313 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
314 } else if (led
->type
== LED_TYPE_QUALITY
) {
316 * The brightness is divided into 6 levels (0 - 5),
317 * this means we need to convert the brightness
318 * argument into the matching level within that range.
320 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
321 brightness
/ (LED_FULL
/ 6), 0);
325 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
326 unsigned long *delay_on
,
327 unsigned long *delay_off
)
329 struct rt2x00_led
*led
=
330 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
333 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
334 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
335 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
336 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
341 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
342 struct rt2x00_led
*led
,
345 led
->rt2x00dev
= rt2x00dev
;
347 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
348 led
->led_dev
.blink_set
= rt61pci_blink_set
;
349 led
->flags
= LED_INITIALIZED
;
351 #endif /* CONFIG_RT61PCI_LEDS */
354 * Configuration handlers.
356 static int rt61pci_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
357 struct rt2x00lib_crypto
*crypto
,
358 struct ieee80211_key_conf
*key
)
360 struct hw_key_entry key_entry
;
361 struct rt2x00_field32 field
;
365 if (crypto
->cmd
== SET_KEY
) {
367 * rt2x00lib can't determine the correct free
368 * key_idx for shared keys. We have 1 register
369 * with key valid bits. The goal is simple, read
370 * the register, if that is full we have no slots
372 * Note that each BSS is allowed to have up to 4
373 * shared keys, so put a mask over the allowed
376 mask
= (0xf << crypto
->bssidx
);
378 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
381 if (reg
&& reg
== mask
)
384 key
->hw_key_idx
+= reg
? (ffz(reg
) - 1) : 0;
387 * Upload key to hardware
389 memcpy(key_entry
.key
, crypto
->key
,
390 sizeof(key_entry
.key
));
391 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
392 sizeof(key_entry
.tx_mic
));
393 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
394 sizeof(key_entry
.rx_mic
));
396 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
397 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
398 &key_entry
, sizeof(key_entry
));
401 * The cipher types are stored over 2 registers.
402 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
403 * bssidx 1 and 2 keys are stored in SEC_CSR5.
404 * Using the correct defines correctly will cause overhead,
405 * so just calculate the correct offset.
407 if (key
->hw_key_idx
< 8) {
408 field
.bit_offset
= (3 * key
->hw_key_idx
);
409 field
.bit_mask
= 0x7 << field
.bit_offset
;
411 rt2x00pci_register_read(rt2x00dev
, SEC_CSR1
, ®
);
412 rt2x00_set_field32(®
, field
, crypto
->cipher
);
413 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, reg
);
415 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
416 field
.bit_mask
= 0x7 << field
.bit_offset
;
418 rt2x00pci_register_read(rt2x00dev
, SEC_CSR5
, ®
);
419 rt2x00_set_field32(®
, field
, crypto
->cipher
);
420 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, reg
);
424 * The driver does not support the IV/EIV generation
425 * in hardware. However it doesn't support the IV/EIV
426 * inside the ieee80211 frame either, but requires it
427 * to be provided seperately for the descriptor.
428 * rt2x00lib will cut the IV/EIV data out of all frames
429 * given to us by mac80211, but we must tell mac80211
430 * to generate the IV/EIV data.
432 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
436 * SEC_CSR0 contains only single-bit fields to indicate
437 * a particular key is valid. Because using the FIELD32()
438 * defines directly will cause a lot of overhead we use
439 * a calculation to determine the correct bit directly.
441 mask
= 1 << key
->hw_key_idx
;
443 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
444 if (crypto
->cmd
== SET_KEY
)
446 else if (crypto
->cmd
== DISABLE_KEY
)
448 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, reg
);
453 static int rt61pci_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
454 struct rt2x00lib_crypto
*crypto
,
455 struct ieee80211_key_conf
*key
)
457 struct hw_pairwise_ta_entry addr_entry
;
458 struct hw_key_entry key_entry
;
462 if (crypto
->cmd
== SET_KEY
) {
464 * rt2x00lib can't determine the correct free
465 * key_idx for pairwise keys. We have 2 registers
466 * with key valid bits. The goal is simple, read
467 * the first register, if that is full move to
469 * When both registers are full, we drop the key,
470 * otherwise we use the first invalid entry.
472 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
473 if (reg
&& reg
== ~0) {
474 key
->hw_key_idx
= 32;
475 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
476 if (reg
&& reg
== ~0)
480 key
->hw_key_idx
+= reg
? (ffz(reg
) - 1) : 0;
483 * Upload key to hardware
485 memcpy(key_entry
.key
, crypto
->key
,
486 sizeof(key_entry
.key
));
487 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
488 sizeof(key_entry
.tx_mic
));
489 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
490 sizeof(key_entry
.rx_mic
));
492 memset(&addr_entry
, 0, sizeof(addr_entry
));
493 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
494 addr_entry
.cipher
= crypto
->cipher
;
496 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
497 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
498 &key_entry
, sizeof(key_entry
));
500 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
501 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
502 &addr_entry
, sizeof(addr_entry
));
505 * Enable pairwise lookup table for given BSS idx,
506 * without this received frames will not be decrypted
509 rt2x00pci_register_read(rt2x00dev
, SEC_CSR4
, ®
);
510 reg
|= (1 << crypto
->bssidx
);
511 rt2x00pci_register_write(rt2x00dev
, SEC_CSR4
, reg
);
514 * The driver does not support the IV/EIV generation
515 * in hardware. However it doesn't support the IV/EIV
516 * inside the ieee80211 frame either, but requires it
517 * to be provided seperately for the descriptor.
518 * rt2x00lib will cut the IV/EIV data out of all frames
519 * given to us by mac80211, but we must tell mac80211
520 * to generate the IV/EIV data.
522 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
526 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
527 * a particular key is valid. Because using the FIELD32()
528 * defines directly will cause a lot of overhead we use
529 * a calculation to determine the correct bit directly.
531 if (key
->hw_key_idx
< 32) {
532 mask
= 1 << key
->hw_key_idx
;
534 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
535 if (crypto
->cmd
== SET_KEY
)
537 else if (crypto
->cmd
== DISABLE_KEY
)
539 rt2x00pci_register_write(rt2x00dev
, SEC_CSR2
, reg
);
541 mask
= 1 << (key
->hw_key_idx
- 32);
543 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
544 if (crypto
->cmd
== SET_KEY
)
546 else if (crypto
->cmd
== DISABLE_KEY
)
548 rt2x00pci_register_write(rt2x00dev
, SEC_CSR3
, reg
);
554 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
555 const unsigned int filter_flags
)
560 * Start configuration steps.
561 * Note that the version error will always be dropped
562 * and broadcast frames will always be accepted since
563 * there is no filter for it at this time.
565 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
566 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
567 !(filter_flags
& FIF_FCSFAIL
));
568 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
569 !(filter_flags
& FIF_PLCPFAIL
));
570 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
571 !(filter_flags
& FIF_CONTROL
));
572 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
573 !(filter_flags
& FIF_PROMISC_IN_BSS
));
574 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
575 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
576 !rt2x00dev
->intf_ap_count
);
577 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
578 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
579 !(filter_flags
& FIF_ALLMULTI
));
580 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
581 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
582 !(filter_flags
& FIF_CONTROL
));
583 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
586 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
587 struct rt2x00_intf
*intf
,
588 struct rt2x00intf_conf
*conf
,
589 const unsigned int flags
)
591 unsigned int beacon_base
;
594 if (flags
& CONFIG_UPDATE_TYPE
) {
596 * Clear current synchronisation setup.
597 * For the Beacon base registers we only need to clear
598 * the first byte since that byte contains the VALID and OWNER
599 * bits which (when set to 0) will invalidate the entire beacon.
601 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
602 rt2x00pci_register_write(rt2x00dev
, beacon_base
, 0);
605 * Enable synchronisation.
607 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
608 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
609 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
610 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
611 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
614 if (flags
& CONFIG_UPDATE_MAC
) {
615 reg
= le32_to_cpu(conf
->mac
[1]);
616 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
617 conf
->mac
[1] = cpu_to_le32(reg
);
619 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
620 conf
->mac
, sizeof(conf
->mac
));
623 if (flags
& CONFIG_UPDATE_BSSID
) {
624 reg
= le32_to_cpu(conf
->bssid
[1]);
625 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
626 conf
->bssid
[1] = cpu_to_le32(reg
);
628 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
629 conf
->bssid
, sizeof(conf
->bssid
));
633 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
634 struct rt2x00lib_erp
*erp
)
638 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
639 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, erp
->ack_timeout
);
640 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
642 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
643 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
644 !!erp
->short_preamble
);
645 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
649 static void rt61pci_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
650 struct rt2x00lib_conf
*libconf
)
655 if (libconf
->band
== IEEE80211_BAND_2GHZ
) {
656 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
659 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
660 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
662 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
665 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
666 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
669 rt2x00dev
->lna_gain
= lna_gain
;
672 static void rt61pci_config_phymode(struct rt2x00_dev
*rt2x00dev
,
673 const int basic_rate_mask
)
675 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
, basic_rate_mask
);
678 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
679 struct rf_channel
*rf
, const int txpower
)
685 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
686 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
688 smart
= !(rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
689 rt2x00_rf(&rt2x00dev
->chip
, RF2527
));
691 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
692 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
693 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
696 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
697 r94
+= txpower
- MAX_TXPOWER
;
698 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
700 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
702 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
703 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
704 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
705 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
709 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
710 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
711 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
712 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
716 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
717 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
718 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
719 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
724 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
727 struct rf_channel rf
;
729 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
730 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
731 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
732 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
734 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
737 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
738 struct antenna_setup
*ant
)
744 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
745 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
746 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
748 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
749 rt2x00_rf(&rt2x00dev
->chip
, RF5325
));
752 * Configure the RX antenna.
755 case ANTENNA_HW_DIVERSITY
:
756 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
757 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
758 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
761 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
762 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
763 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
764 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
766 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
770 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
771 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
772 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
773 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
775 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
779 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
780 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
781 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
784 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
785 struct antenna_setup
*ant
)
791 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
792 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
793 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
795 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
796 rt2x00_rf(&rt2x00dev
->chip
, RF2529
));
797 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
798 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
801 * Configure the RX antenna.
804 case ANTENNA_HW_DIVERSITY
:
805 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
808 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
809 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
813 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
814 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
818 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
819 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
820 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
823 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
824 const int p1
, const int p2
)
828 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
830 rt2x00_set_field32(®
, MAC_CSR13_BIT4
, p1
);
831 rt2x00_set_field32(®
, MAC_CSR13_BIT12
, 0);
833 rt2x00_set_field32(®
, MAC_CSR13_BIT3
, !p2
);
834 rt2x00_set_field32(®
, MAC_CSR13_BIT11
, 0);
836 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
839 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
840 struct antenna_setup
*ant
)
846 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
847 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
848 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
851 * Configure the RX antenna.
855 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
856 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
857 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
859 case ANTENNA_HW_DIVERSITY
:
861 * FIXME: Antenna selection for the rf 2529 is very confusing
862 * in the legacy driver. Just default to antenna B until the
863 * legacy code can be properly translated into rt2x00 code.
867 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
868 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
869 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
873 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
874 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
875 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
881 * value[0] -> non-LNA
887 static const struct antenna_sel antenna_sel_a
[] = {
888 { 96, { 0x58, 0x78 } },
889 { 104, { 0x38, 0x48 } },
890 { 75, { 0xfe, 0x80 } },
891 { 86, { 0xfe, 0x80 } },
892 { 88, { 0xfe, 0x80 } },
893 { 35, { 0x60, 0x60 } },
894 { 97, { 0x58, 0x58 } },
895 { 98, { 0x58, 0x58 } },
898 static const struct antenna_sel antenna_sel_bg
[] = {
899 { 96, { 0x48, 0x68 } },
900 { 104, { 0x2c, 0x3c } },
901 { 75, { 0xfe, 0x80 } },
902 { 86, { 0xfe, 0x80 } },
903 { 88, { 0xfe, 0x80 } },
904 { 35, { 0x50, 0x50 } },
905 { 97, { 0x48, 0x48 } },
906 { 98, { 0x48, 0x48 } },
909 static void rt61pci_config_antenna(struct rt2x00_dev
*rt2x00dev
,
910 struct antenna_setup
*ant
)
912 const struct antenna_sel
*sel
;
918 * We should never come here because rt2x00lib is supposed
919 * to catch this and send us the correct antenna explicitely.
921 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
922 ant
->tx
== ANTENNA_SW_DIVERSITY
);
924 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
926 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
928 sel
= antenna_sel_bg
;
929 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
932 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
933 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
935 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
937 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
938 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
939 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
940 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
942 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
944 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
945 rt2x00_rf(&rt2x00dev
->chip
, RF5325
))
946 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
947 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
948 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
949 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
950 if (test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
))
951 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
953 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
957 static void rt61pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
958 struct rt2x00lib_conf
*libconf
)
962 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
963 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, libconf
->slot_time
);
964 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
966 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
967 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, libconf
->sifs
);
968 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
969 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, libconf
->eifs
);
970 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
972 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
973 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
974 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
976 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
977 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
978 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
980 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
981 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
982 libconf
->conf
->beacon_int
* 16);
983 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
986 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
987 struct rt2x00lib_conf
*libconf
,
988 const unsigned int flags
)
990 /* Always recalculate LNA gain before changing configuration */
991 rt61pci_config_lna_gain(rt2x00dev
, libconf
);
993 if (flags
& CONFIG_UPDATE_PHYMODE
)
994 rt61pci_config_phymode(rt2x00dev
, libconf
->basic_rates
);
995 if (flags
& CONFIG_UPDATE_CHANNEL
)
996 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
997 libconf
->conf
->power_level
);
998 if ((flags
& CONFIG_UPDATE_TXPOWER
) && !(flags
& CONFIG_UPDATE_CHANNEL
))
999 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1000 if (flags
& CONFIG_UPDATE_ANTENNA
)
1001 rt61pci_config_antenna(rt2x00dev
, &libconf
->ant
);
1002 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
1003 rt61pci_config_duration(rt2x00dev
, libconf
);
1009 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
1010 struct link_qual
*qual
)
1015 * Update FCS error count from register.
1017 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1018 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
1021 * Update False CCA count from register.
1023 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1024 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
1027 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
1029 rt61pci_bbp_write(rt2x00dev
, 17, 0x20);
1030 rt2x00dev
->link
.vgc_level
= 0x20;
1033 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
)
1035 int rssi
= rt2x00_get_link_rssi(&rt2x00dev
->link
);
1040 rt61pci_bbp_read(rt2x00dev
, 17, &r17
);
1043 * Determine r17 bounds.
1045 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1048 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1055 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1062 * If we are not associated, we should go straight to the
1063 * dynamic CCA tuning.
1065 if (!rt2x00dev
->intf_associated
)
1066 goto dynamic_cca_tune
;
1069 * Special big-R17 for very short distance
1073 rt61pci_bbp_write(rt2x00dev
, 17, 0x60);
1078 * Special big-R17 for short distance
1081 if (r17
!= up_bound
)
1082 rt61pci_bbp_write(rt2x00dev
, 17, up_bound
);
1087 * Special big-R17 for middle-short distance
1091 if (r17
!= low_bound
)
1092 rt61pci_bbp_write(rt2x00dev
, 17, low_bound
);
1097 * Special mid-R17 for middle distance
1101 if (r17
!= low_bound
)
1102 rt61pci_bbp_write(rt2x00dev
, 17, low_bound
);
1107 * Special case: Change up_bound based on the rssi.
1108 * Lower up_bound when rssi is weaker then -74 dBm.
1110 up_bound
-= 2 * (-74 - rssi
);
1111 if (low_bound
> up_bound
)
1112 up_bound
= low_bound
;
1114 if (r17
> up_bound
) {
1115 rt61pci_bbp_write(rt2x00dev
, 17, up_bound
);
1122 * r17 does not yet exceed upper limit, continue and base
1123 * the r17 tuning on the false CCA count.
1125 if (rt2x00dev
->link
.qual
.false_cca
> 512 && r17
< up_bound
) {
1126 if (++r17
> up_bound
)
1128 rt61pci_bbp_write(rt2x00dev
, 17, r17
);
1129 } else if (rt2x00dev
->link
.qual
.false_cca
< 100 && r17
> low_bound
) {
1130 if (--r17
< low_bound
)
1132 rt61pci_bbp_write(rt2x00dev
, 17, r17
);
1137 * Firmware functions
1139 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1143 switch (rt2x00dev
->chip
.rt
) {
1145 fw_name
= FIRMWARE_RT2561
;
1148 fw_name
= FIRMWARE_RT2561s
;
1151 fw_name
= FIRMWARE_RT2661
;
1161 static u16
rt61pci_get_firmware_crc(const void *data
, const size_t len
)
1166 * Use the crc itu-t algorithm.
1167 * The last 2 bytes in the firmware array are the crc checksum itself,
1168 * this means that we should never pass those 2 bytes to the crc
1171 crc
= crc_itu_t(0, data
, len
- 2);
1172 crc
= crc_itu_t_byte(crc
, 0);
1173 crc
= crc_itu_t_byte(crc
, 0);
1178 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
, const void *data
,
1185 * Wait for stable hardware.
1187 for (i
= 0; i
< 100; i
++) {
1188 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1195 ERROR(rt2x00dev
, "Unstable hardware.\n");
1200 * Prepare MCU and mailbox for firmware loading.
1203 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1204 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1205 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1206 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1207 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
1210 * Write firmware to device.
1213 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1214 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
1215 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1217 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
1220 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
1221 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1223 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
1224 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1226 for (i
= 0; i
< 100; i
++) {
1227 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
1228 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1234 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1239 * Hardware needs another millisecond before it is ready.
1244 * Reset MAC and BBP registers.
1247 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1248 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1249 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1251 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1252 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1253 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1254 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1256 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1257 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1258 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1264 * Initialization functions.
1266 static void rt61pci_init_rxentry(struct rt2x00_dev
*rt2x00dev
,
1267 struct queue_entry
*entry
)
1269 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1270 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1273 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1274 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1276 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1278 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1279 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1280 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1283 static void rt61pci_init_txentry(struct rt2x00_dev
*rt2x00dev
,
1284 struct queue_entry
*entry
)
1286 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1289 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1290 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1291 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1292 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1295 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1297 struct queue_entry_priv_pci
*entry_priv
;
1301 * Initialize registers.
1303 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1304 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1305 rt2x00dev
->tx
[0].limit
);
1306 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1307 rt2x00dev
->tx
[1].limit
);
1308 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1309 rt2x00dev
->tx
[2].limit
);
1310 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1311 rt2x00dev
->tx
[3].limit
);
1312 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1314 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1315 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1316 rt2x00dev
->tx
[0].desc_size
/ 4);
1317 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1319 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1320 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1321 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1322 entry_priv
->desc_dma
);
1323 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1325 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1326 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1327 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1328 entry_priv
->desc_dma
);
1329 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1331 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1332 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1333 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1334 entry_priv
->desc_dma
);
1335 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1337 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1338 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1339 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1340 entry_priv
->desc_dma
);
1341 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1343 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1344 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1345 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1346 rt2x00dev
->rx
->desc_size
/ 4);
1347 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1348 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1350 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1351 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1352 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1353 entry_priv
->desc_dma
);
1354 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1356 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1357 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1358 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1359 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1360 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1361 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1363 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1364 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1365 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1366 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1367 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1368 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1370 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1371 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1372 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1377 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1381 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1382 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1383 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1384 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1385 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1387 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1388 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1389 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1390 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1391 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1392 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1393 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1394 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1395 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1396 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1399 * CCK TXD BBP registers
1401 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1402 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1403 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1404 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1405 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1406 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1407 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1408 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1409 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1410 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1413 * OFDM TXD BBP registers
1415 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1416 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1417 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1418 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1419 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1420 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1421 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1422 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1424 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1425 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1426 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1427 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1428 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1429 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1431 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1432 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1433 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1434 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1435 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1436 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1438 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1439 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1440 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1441 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1442 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1443 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1444 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1445 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1447 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1449 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1451 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1452 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1453 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1455 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1457 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1460 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1463 * Invalidate all Shared Keys (SEC_CSR0),
1464 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1466 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1467 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1468 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1470 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1471 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1472 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1473 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1475 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1477 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1479 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1483 * For the Beacon base registers we only need to clear
1484 * the first byte since that byte contains the VALID and OWNER
1485 * bits which (when set to 0) will invalidate the entire beacon.
1487 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1488 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1489 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1490 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1493 * We must clear the error counters.
1494 * These registers are cleared on read,
1495 * so we may pass a useless variable to store the value.
1497 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1498 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1499 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1502 * Reset MAC and BBP registers.
1504 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1505 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1506 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1507 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1509 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1510 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1511 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1512 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1514 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1515 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1516 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1521 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1526 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1527 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1528 if ((value
!= 0xff) && (value
!= 0x00))
1530 udelay(REGISTER_BUSY_DELAY
);
1533 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1537 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1544 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1547 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1548 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1549 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1550 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1551 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1552 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1553 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1554 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1555 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1556 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1557 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1558 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1559 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1560 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1561 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1562 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1563 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1564 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1565 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1566 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1567 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1568 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1569 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1570 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1572 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1573 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1575 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1576 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1577 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1578 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1586 * Device state switch handlers.
1588 static void rt61pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1589 enum dev_state state
)
1593 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1594 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1595 (state
== STATE_RADIO_RX_OFF
) ||
1596 (state
== STATE_RADIO_RX_OFF_LINK
));
1597 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1600 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1601 enum dev_state state
)
1603 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1607 * When interrupts are being enabled, the interrupt registers
1608 * should clear the register to assure a clean state.
1610 if (state
== STATE_RADIO_IRQ_ON
) {
1611 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1612 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1614 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1615 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1619 * Only toggle the interrupts bits we are going to use.
1620 * Non-checked interrupt bits are disabled by default.
1622 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1623 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1624 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1625 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1626 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1627 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1629 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1630 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1631 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1632 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1633 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1634 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1635 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1636 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1637 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1638 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1641 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1646 * Initialize all registers.
1648 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1649 rt61pci_init_registers(rt2x00dev
) ||
1650 rt61pci_init_bbp(rt2x00dev
)))
1656 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1657 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1658 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1663 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1667 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1670 * Disable synchronisation.
1672 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1677 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1678 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, 1);
1679 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, 1);
1680 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, 1);
1681 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, 1);
1682 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1685 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1691 put_to_sleep
= (state
!= STATE_AWAKE
);
1693 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1694 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1695 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1696 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1699 * Device is not guaranteed to be in the requested state yet.
1700 * We must wait until the register indicates that the
1701 * device has entered the correct state.
1703 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1704 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1705 state
= rt2x00_get_field32(reg
, MAC_CSR12_BBP_CURRENT_STATE
);
1706 if (state
== !put_to_sleep
)
1714 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1715 enum dev_state state
)
1720 case STATE_RADIO_ON
:
1721 retval
= rt61pci_enable_radio(rt2x00dev
);
1723 case STATE_RADIO_OFF
:
1724 rt61pci_disable_radio(rt2x00dev
);
1726 case STATE_RADIO_RX_ON
:
1727 case STATE_RADIO_RX_ON_LINK
:
1728 case STATE_RADIO_RX_OFF
:
1729 case STATE_RADIO_RX_OFF_LINK
:
1730 rt61pci_toggle_rx(rt2x00dev
, state
);
1732 case STATE_RADIO_IRQ_ON
:
1733 case STATE_RADIO_IRQ_OFF
:
1734 rt61pci_toggle_irq(rt2x00dev
, state
);
1736 case STATE_DEEP_SLEEP
:
1740 retval
= rt61pci_set_state(rt2x00dev
, state
);
1747 if (unlikely(retval
))
1748 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1755 * TX descriptor initialization
1757 static void rt61pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1758 struct sk_buff
*skb
,
1759 struct txentry_desc
*txdesc
)
1761 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1762 __le32
*txd
= skbdesc
->desc
;
1766 * Start writing the descriptor words.
1768 rt2x00_desc_read(txd
, 1, &word
);
1769 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1770 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1771 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1772 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1773 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1774 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1775 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1776 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1777 rt2x00_desc_write(txd
, 1, word
);
1779 rt2x00_desc_read(txd
, 2, &word
);
1780 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1781 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1782 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1783 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1784 rt2x00_desc_write(txd
, 2, word
);
1786 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1787 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
);
1788 _rt2x00_desc_write(txd
, 4, skbdesc
->eiv
);
1791 rt2x00_desc_read(txd
, 5, &word
);
1792 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, skbdesc
->entry
->queue
->qid
);
1793 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1794 skbdesc
->entry
->entry_idx
);
1795 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1796 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1797 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1798 rt2x00_desc_write(txd
, 5, word
);
1800 rt2x00_desc_read(txd
, 6, &word
);
1801 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1803 rt2x00_desc_write(txd
, 6, word
);
1805 if (skbdesc
->desc_len
> TXINFO_SIZE
) {
1806 rt2x00_desc_read(txd
, 11, &word
);
1807 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
, skb
->len
);
1808 rt2x00_desc_write(txd
, 11, word
);
1811 rt2x00_desc_read(txd
, 0, &word
);
1812 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1813 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1814 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1815 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1816 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1817 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1818 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1819 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1820 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1821 test_bit(ENTRY_TXD_OFDM_RATE
, &txdesc
->flags
));
1822 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1823 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1824 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1825 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1826 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1827 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1828 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1829 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1830 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skb
->len
);
1831 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1832 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1833 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1834 rt2x00_desc_write(txd
, 0, word
);
1838 * TX data initialization
1840 static void rt61pci_write_beacon(struct queue_entry
*entry
)
1842 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1843 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1844 unsigned int beacon_base
;
1848 * Disable beaconing while we are reloading the beacon data,
1849 * otherwise we might be sending out invalid data.
1851 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1852 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1853 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1854 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1855 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1858 * Write entire beacon with descriptor to register.
1860 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1861 rt2x00pci_register_multiwrite(rt2x00dev
,
1863 skbdesc
->desc
, skbdesc
->desc_len
);
1864 rt2x00pci_register_multiwrite(rt2x00dev
,
1865 beacon_base
+ skbdesc
->desc_len
,
1866 entry
->skb
->data
, entry
->skb
->len
);
1869 * Clean up beacon skb.
1871 dev_kfree_skb_any(entry
->skb
);
1875 static void rt61pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1876 const enum data_queue_qid queue
)
1880 if (queue
== QID_BEACON
) {
1882 * For Wi-Fi faily generated beacons between participating
1883 * stations. Set TBTT phase adaptive adjustment step to 8us.
1885 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1887 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1888 if (!rt2x00_get_field32(reg
, TXRX_CSR9_BEACON_GEN
)) {
1889 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1890 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1891 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1892 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1897 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1898 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, (queue
== QID_AC_BE
));
1899 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, (queue
== QID_AC_BK
));
1900 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, (queue
== QID_AC_VI
));
1901 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, (queue
== QID_AC_VO
));
1902 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1906 * RX control handlers
1908 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1910 u8 offset
= rt2x00dev
->lna_gain
;
1913 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1928 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1929 if (lna
== 3 || lna
== 2)
1933 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1936 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
1937 struct rxdone_entry_desc
*rxdesc
)
1939 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1940 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1944 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1945 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
1947 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1948 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1950 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
)) {
1952 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
1953 rxdesc
->cipher_status
=
1954 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
1957 if (rxdesc
->cipher
!= CIPHER_NONE
) {
1958 _rt2x00_desc_read(entry_priv
->desc
, 2, &rxdesc
->iv
);
1959 _rt2x00_desc_read(entry_priv
->desc
, 3, &rxdesc
->eiv
);
1960 _rt2x00_desc_read(entry_priv
->desc
, 4, &rxdesc
->icv
);
1963 * Hardware has stripped IV/EIV data from 802.11 frame during
1964 * decryption. It has provided the data seperately but rt2x00lib
1965 * should decide if it should be reinserted.
1967 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
1970 * FIXME: Legacy driver indicates that the frame does
1971 * contain the Michael Mic. Unfortunately, in rt2x00
1972 * the MIC seems to be missing completely...
1974 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
1976 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
1977 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
1978 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
1979 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
1983 * Obtain the status about this packet.
1984 * When frame was received with an OFDM bitrate,
1985 * the signal is the PLCP value. If it was received with
1986 * a CCK bitrate the signal is the rate in 100kbit/s.
1988 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
1989 rxdesc
->rssi
= rt61pci_agc_to_rssi(rt2x00dev
, word1
);
1990 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1992 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
1993 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
1994 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1995 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1999 * Interrupt functions.
2001 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
2003 struct data_queue
*queue
;
2004 struct queue_entry
*entry
;
2005 struct queue_entry
*entry_done
;
2006 struct queue_entry_priv_pci
*entry_priv
;
2007 struct txdone_entry_desc txdesc
;
2015 * During each loop we will compare the freshly read
2016 * STA_CSR4 register value with the value read from
2017 * the previous loop. If the 2 values are equal then
2018 * we should stop processing because the chance it
2019 * quite big that the device has been unplugged and
2020 * we risk going into an endless loop.
2025 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
2026 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
2034 * Skip this entry when it contains an invalid
2035 * queue identication number.
2037 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
2038 queue
= rt2x00queue_get_queue(rt2x00dev
, type
);
2039 if (unlikely(!queue
))
2043 * Skip this entry when it contains an invalid
2046 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
2047 if (unlikely(index
>= queue
->limit
))
2050 entry
= &queue
->entries
[index
];
2051 entry_priv
= entry
->priv_data
;
2052 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
2054 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
2055 !rt2x00_get_field32(word
, TXD_W0_VALID
))
2058 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2059 while (entry
!= entry_done
) {
2061 * Just report any entries we missed as failed.
2064 "TX status report missed for entry %d\n",
2065 entry_done
->entry_idx
);
2068 __set_bit(TXDONE_UNKNOWN
, &txdesc
.flags
);
2071 rt2x00lib_txdone(entry_done
, &txdesc
);
2072 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2076 * Obtain the status about this packet.
2079 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
2080 case 0: /* Success, maybe with retry */
2081 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
2083 case 6: /* Failure, excessive retries */
2084 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
2085 /* Don't break, this is a failed frame! */
2086 default: /* Failure */
2087 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
2089 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
2091 rt2x00lib_txdone(entry
, &txdesc
);
2095 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
2097 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2102 * Get the interrupt sources & saved to local variable.
2103 * Write register value back to clear pending interrupts.
2105 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
2106 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
2108 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
2109 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
2111 if (!reg
&& !reg_mcu
)
2114 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2118 * Handle interrupts, walk through all bits
2119 * and run the tasks, the bits are checked in order of
2124 * 1 - Rx ring done interrupt.
2126 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
2127 rt2x00pci_rxdone(rt2x00dev
);
2130 * 2 - Tx ring done interrupt.
2132 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
2133 rt61pci_txdone(rt2x00dev
);
2136 * 3 - Handle MCU command done.
2139 rt2x00pci_register_write(rt2x00dev
,
2140 M2H_CMD_DONE_CSR
, 0xffffffff);
2146 * Device probe functions.
2148 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2150 struct eeprom_93cx6 eeprom
;
2156 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
2158 eeprom
.data
= rt2x00dev
;
2159 eeprom
.register_read
= rt61pci_eepromregister_read
;
2160 eeprom
.register_write
= rt61pci_eepromregister_write
;
2161 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
2162 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
2163 eeprom
.reg_data_in
= 0;
2164 eeprom
.reg_data_out
= 0;
2165 eeprom
.reg_data_clock
= 0;
2166 eeprom
.reg_chip_select
= 0;
2168 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
2169 EEPROM_SIZE
/ sizeof(u16
));
2172 * Start validation of the data that has been read.
2174 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2175 if (!is_valid_ether_addr(mac
)) {
2176 DECLARE_MAC_BUF(macbuf
);
2178 random_ether_addr(mac
);
2179 EEPROM(rt2x00dev
, "MAC: %s\n", print_mac(macbuf
, mac
));
2182 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2183 if (word
== 0xffff) {
2184 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
2185 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
2187 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
2189 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
2190 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
2191 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
2192 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
2193 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2194 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2197 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2198 if (word
== 0xffff) {
2199 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
2200 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
2201 rt2x00_set_field16(&word
, EEPROM_NIC_TX_RX_FIXED
, 0);
2202 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2203 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2204 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2205 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2206 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2209 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
2210 if (word
== 0xffff) {
2211 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
2213 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
2214 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
2217 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2218 if (word
== 0xffff) {
2219 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2220 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
2221 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2222 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2225 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
2226 if (word
== 0xffff) {
2227 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2228 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2229 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2230 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
2232 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
2233 if (value
< -10 || value
> 10)
2234 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2235 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
2236 if (value
< -10 || value
> 10)
2237 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2238 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2241 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
2242 if (word
== 0xffff) {
2243 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2244 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2245 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2246 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
2248 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
2249 if (value
< -10 || value
> 10)
2250 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2251 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
2252 if (value
< -10 || value
> 10)
2253 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2254 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2260 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2268 * Read EEPROM word for configuration.
2270 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2273 * Identify RF chipset.
2274 * To determine the RT chip we have to read the
2275 * PCI header of the device.
2277 pci_read_config_word(to_pci_dev(rt2x00dev
->dev
),
2278 PCI_CONFIG_HEADER_DEVICE
, &device
);
2279 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2280 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2281 rt2x00_set_chip(rt2x00dev
, device
, value
, reg
);
2283 if (!rt2x00_rf(&rt2x00dev
->chip
, RF5225
) &&
2284 !rt2x00_rf(&rt2x00dev
->chip
, RF5325
) &&
2285 !rt2x00_rf(&rt2x00dev
->chip
, RF2527
) &&
2286 !rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
2287 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2292 * Determine number of antenna's.
2294 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2295 __set_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
);
2298 * Identify default antenna configuration.
2300 rt2x00dev
->default_ant
.tx
=
2301 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2302 rt2x00dev
->default_ant
.rx
=
2303 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2306 * Read the Frame type.
2308 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2309 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
2312 * Detect if this device has an hardware controlled radio.
2314 #ifdef CONFIG_RT61PCI_RFKILL
2315 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2316 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2317 #endif /* CONFIG_RT61PCI_RFKILL */
2320 * Read frequency offset and RF programming sequence.
2322 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2323 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2324 __set_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
);
2326 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2329 * Read external LNA informations.
2331 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2333 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2334 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2335 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2336 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2339 * When working with a RF2529 chip without double antenna
2340 * the antenna settings should be gathered from the NIC
2343 if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
) &&
2344 !test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
)) {
2345 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_RX_FIXED
)) {
2347 rt2x00dev
->default_ant
.tx
= ANTENNA_B
;
2348 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
2351 rt2x00dev
->default_ant
.tx
= ANTENNA_B
;
2352 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
2355 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
2356 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
2359 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
2360 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
2364 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2365 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2366 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2367 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2371 * Store led settings, for correct led behaviour.
2372 * If the eeprom value is invalid,
2373 * switch to default led mode.
2375 #ifdef CONFIG_RT61PCI_LEDS
2376 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2377 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2379 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2380 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2381 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2382 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2385 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2386 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2387 rt2x00_get_field16(eeprom
,
2388 EEPROM_LED_POLARITY_GPIO_0
));
2389 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2390 rt2x00_get_field16(eeprom
,
2391 EEPROM_LED_POLARITY_GPIO_1
));
2392 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2393 rt2x00_get_field16(eeprom
,
2394 EEPROM_LED_POLARITY_GPIO_2
));
2395 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2396 rt2x00_get_field16(eeprom
,
2397 EEPROM_LED_POLARITY_GPIO_3
));
2398 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2399 rt2x00_get_field16(eeprom
,
2400 EEPROM_LED_POLARITY_GPIO_4
));
2401 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2402 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2403 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2404 rt2x00_get_field16(eeprom
,
2405 EEPROM_LED_POLARITY_RDY_G
));
2406 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2407 rt2x00_get_field16(eeprom
,
2408 EEPROM_LED_POLARITY_RDY_A
));
2409 #endif /* CONFIG_RT61PCI_LEDS */
2415 * RF value list for RF5225 & RF5325
2416 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2418 static const struct rf_channel rf_vals_noseq
[] = {
2419 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2420 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2421 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2422 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2423 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2424 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2425 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2426 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2427 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2428 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2429 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2430 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2431 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2432 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2434 /* 802.11 UNI / HyperLan 2 */
2435 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2436 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2437 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2438 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2439 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2440 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2441 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2442 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2444 /* 802.11 HyperLan 2 */
2445 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2446 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2447 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2448 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2449 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2450 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2451 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2452 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2453 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2454 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2457 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2458 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2459 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2460 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2461 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2462 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2464 /* MMAC(Japan)J52 ch 34,38,42,46 */
2465 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2466 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2467 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2468 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2472 * RF value list for RF5225 & RF5325
2473 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2475 static const struct rf_channel rf_vals_seq
[] = {
2476 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2477 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2478 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2479 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2480 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2481 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2482 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2483 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2484 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2485 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2486 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2487 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2488 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2489 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2491 /* 802.11 UNI / HyperLan 2 */
2492 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2493 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2494 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2495 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2496 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2497 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2498 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2499 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2501 /* 802.11 HyperLan 2 */
2502 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2503 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2504 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2505 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2506 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2507 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2508 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2509 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2510 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2511 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2514 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2515 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2516 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2517 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2518 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2519 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2521 /* MMAC(Japan)J52 ch 34,38,42,46 */
2522 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2523 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2524 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2525 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2528 static int rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2530 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2531 struct channel_info
*info
;
2536 * Initialize all hw fields.
2538 rt2x00dev
->hw
->flags
=
2539 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2540 IEEE80211_HW_SIGNAL_DBM
;
2541 rt2x00dev
->hw
->extra_tx_headroom
= 0;
2543 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2544 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2545 rt2x00_eeprom_addr(rt2x00dev
,
2546 EEPROM_MAC_ADDR_0
));
2549 * Initialize hw_mode information.
2551 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2552 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2554 if (!test_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
)) {
2555 spec
->num_channels
= 14;
2556 spec
->channels
= rf_vals_noseq
;
2558 spec
->num_channels
= 14;
2559 spec
->channels
= rf_vals_seq
;
2562 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
2563 rt2x00_rf(&rt2x00dev
->chip
, RF5325
)) {
2564 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2565 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2569 * Create channel information array
2571 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2575 spec
->channels_info
= info
;
2577 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2578 for (i
= 0; i
< 14; i
++)
2579 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2581 if (spec
->num_channels
> 14) {
2582 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2583 for (i
= 14; i
< spec
->num_channels
; i
++)
2584 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2590 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2595 * Allocate eeprom data.
2597 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2601 retval
= rt61pci_init_eeprom(rt2x00dev
);
2606 * Initialize hw specifications.
2608 retval
= rt61pci_probe_hw_mode(rt2x00dev
);
2613 * This device requires firmware and DMA mapped skbs.
2615 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2616 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
2617 if (!modparam_nohwcrypt
)
2618 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
2621 * Set the rssi offset.
2623 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2629 * IEEE80211 stack callback functions.
2631 static int rt61pci_set_retry_limit(struct ieee80211_hw
*hw
,
2632 u32 short_retry
, u32 long_retry
)
2634 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2637 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
2638 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
, long_retry
);
2639 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
, short_retry
);
2640 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
2645 static int rt61pci_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2646 const struct ieee80211_tx_queue_params
*params
)
2648 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2649 struct data_queue
*queue
;
2650 struct rt2x00_field32 field
;
2655 * First pass the configuration through rt2x00lib, that will
2656 * update the queue settings and validate the input. After that
2657 * we are free to update the registers based on the value
2658 * in the queue parameter.
2660 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2664 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2666 /* Update WMM TXOP register */
2667 if (queue_idx
< 2) {
2668 field
.bit_offset
= queue_idx
* 16;
2669 field
.bit_mask
= 0xffff << field
.bit_offset
;
2671 rt2x00pci_register_read(rt2x00dev
, AC_TXOP_CSR0
, ®
);
2672 rt2x00_set_field32(®
, field
, queue
->txop
);
2673 rt2x00pci_register_write(rt2x00dev
, AC_TXOP_CSR0
, reg
);
2674 } else if (queue_idx
< 4) {
2675 field
.bit_offset
= (queue_idx
- 2) * 16;
2676 field
.bit_mask
= 0xffff << field
.bit_offset
;
2678 rt2x00pci_register_read(rt2x00dev
, AC_TXOP_CSR1
, ®
);
2679 rt2x00_set_field32(®
, field
, queue
->txop
);
2680 rt2x00pci_register_write(rt2x00dev
, AC_TXOP_CSR1
, reg
);
2683 /* Update WMM registers */
2684 field
.bit_offset
= queue_idx
* 4;
2685 field
.bit_mask
= 0xf << field
.bit_offset
;
2687 rt2x00pci_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2688 rt2x00_set_field32(®
, field
, queue
->aifs
);
2689 rt2x00pci_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2691 rt2x00pci_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2692 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2693 rt2x00pci_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2695 rt2x00pci_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2696 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2697 rt2x00pci_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2702 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
)
2704 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2708 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2709 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2710 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2711 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2716 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2718 .start
= rt2x00mac_start
,
2719 .stop
= rt2x00mac_stop
,
2720 .add_interface
= rt2x00mac_add_interface
,
2721 .remove_interface
= rt2x00mac_remove_interface
,
2722 .config
= rt2x00mac_config
,
2723 .config_interface
= rt2x00mac_config_interface
,
2724 .configure_filter
= rt2x00mac_configure_filter
,
2725 .set_key
= rt2x00mac_set_key
,
2726 .get_stats
= rt2x00mac_get_stats
,
2727 .set_retry_limit
= rt61pci_set_retry_limit
,
2728 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2729 .conf_tx
= rt61pci_conf_tx
,
2730 .get_tx_stats
= rt2x00mac_get_tx_stats
,
2731 .get_tsf
= rt61pci_get_tsf
,
2734 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2735 .irq_handler
= rt61pci_interrupt
,
2736 .probe_hw
= rt61pci_probe_hw
,
2737 .get_firmware_name
= rt61pci_get_firmware_name
,
2738 .get_firmware_crc
= rt61pci_get_firmware_crc
,
2739 .load_firmware
= rt61pci_load_firmware
,
2740 .initialize
= rt2x00pci_initialize
,
2741 .uninitialize
= rt2x00pci_uninitialize
,
2742 .init_rxentry
= rt61pci_init_rxentry
,
2743 .init_txentry
= rt61pci_init_txentry
,
2744 .set_device_state
= rt61pci_set_device_state
,
2745 .rfkill_poll
= rt61pci_rfkill_poll
,
2746 .link_stats
= rt61pci_link_stats
,
2747 .reset_tuner
= rt61pci_reset_tuner
,
2748 .link_tuner
= rt61pci_link_tuner
,
2749 .write_tx_desc
= rt61pci_write_tx_desc
,
2750 .write_tx_data
= rt2x00pci_write_tx_data
,
2751 .write_beacon
= rt61pci_write_beacon
,
2752 .kick_tx_queue
= rt61pci_kick_tx_queue
,
2753 .fill_rxdone
= rt61pci_fill_rxdone
,
2754 .config_shared_key
= rt61pci_config_shared_key
,
2755 .config_pairwise_key
= rt61pci_config_pairwise_key
,
2756 .config_filter
= rt61pci_config_filter
,
2757 .config_intf
= rt61pci_config_intf
,
2758 .config_erp
= rt61pci_config_erp
,
2759 .config
= rt61pci_config
,
2762 static const struct data_queue_desc rt61pci_queue_rx
= {
2763 .entry_num
= RX_ENTRIES
,
2764 .data_size
= DATA_FRAME_SIZE
,
2765 .desc_size
= RXD_DESC_SIZE
,
2766 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2769 static const struct data_queue_desc rt61pci_queue_tx
= {
2770 .entry_num
= TX_ENTRIES
,
2771 .data_size
= DATA_FRAME_SIZE
,
2772 .desc_size
= TXD_DESC_SIZE
,
2773 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2776 static const struct data_queue_desc rt61pci_queue_bcn
= {
2777 .entry_num
= 4 * BEACON_ENTRIES
,
2778 .data_size
= 0, /* No DMA required for beacons */
2779 .desc_size
= TXINFO_SIZE
,
2780 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2783 static const struct rt2x00_ops rt61pci_ops
= {
2784 .name
= KBUILD_MODNAME
,
2787 .eeprom_size
= EEPROM_SIZE
,
2789 .tx_queues
= NUM_TX_QUEUES
,
2790 .rx
= &rt61pci_queue_rx
,
2791 .tx
= &rt61pci_queue_tx
,
2792 .bcn
= &rt61pci_queue_bcn
,
2793 .lib
= &rt61pci_rt2x00_ops
,
2794 .hw
= &rt61pci_mac80211_ops
,
2795 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2796 .debugfs
= &rt61pci_rt2x00debug
,
2797 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2801 * RT61pci module information.
2803 static struct pci_device_id rt61pci_device_table
[] = {
2805 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops
) },
2807 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops
) },
2809 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops
) },
2813 MODULE_AUTHOR(DRV_PROJECT
);
2814 MODULE_VERSION(DRV_VERSION
);
2815 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2816 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2817 "PCI & PCMCIA chipset based cards");
2818 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
2819 MODULE_FIRMWARE(FIRMWARE_RT2561
);
2820 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
2821 MODULE_FIRMWARE(FIRMWARE_RT2661
);
2822 MODULE_LICENSE("GPL");
2824 static struct pci_driver rt61pci_driver
= {
2825 .name
= KBUILD_MODNAME
,
2826 .id_table
= rt61pci_device_table
,
2827 .probe
= rt2x00pci_probe
,
2828 .remove
= __devexit_p(rt2x00pci_remove
),
2829 .suspend
= rt2x00pci_suspend
,
2830 .resume
= rt2x00pci_resume
,
2833 static int __init
rt61pci_init(void)
2835 return pci_register_driver(&rt61pci_driver
);
2838 static void __exit
rt61pci_exit(void)
2840 pci_unregister_driver(&rt61pci_driver
);
2843 module_init(rt61pci_init
);
2844 module_exit(rt61pci_exit
);