2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/eeprom_93cx6.h>
38 #include "rt2x00mmio.h"
39 #include "rt2x00pci.h"
43 * Allow hardware encryption to be disabled.
45 static bool modparam_nohwcrypt
= false;
46 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
47 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
51 * BBP and RF register require indirect register access,
52 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
53 * These indirect registers work with busy bits,
54 * and we will try maximal REGISTER_BUSY_COUNT times to access
55 * the register while taking a REGISTER_BUSY_DELAY us delay
56 * between each attempt. When the busy bit is still set at that time,
57 * the access attempt is considered to have failed,
58 * and we will print an error.
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64 #define WAIT_FOR_MCU(__dev, __reg) \
65 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
68 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
69 const unsigned int word
, const u8 value
)
73 mutex_lock(&rt2x00dev
->csr_mutex
);
76 * Wait until the BBP becomes available, afterwards we
77 * can safely write the new data into the register.
79 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
81 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
82 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
83 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
84 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
86 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
89 mutex_unlock(&rt2x00dev
->csr_mutex
);
92 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
93 const unsigned int word
, u8
*value
)
97 mutex_lock(&rt2x00dev
->csr_mutex
);
100 * Wait until the BBP becomes available, afterwards we
101 * can safely write the read request into the register.
102 * After the data has been written, we wait until hardware
103 * returns the correct value, if at any time the register
104 * doesn't become available in time, reg will be 0xffffffff
105 * which means we return 0xff to the caller.
107 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
109 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
110 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
111 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
113 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
115 WAIT_FOR_BBP(rt2x00dev
, ®
);
118 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
120 mutex_unlock(&rt2x00dev
->csr_mutex
);
123 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
124 const unsigned int word
, const u32 value
)
128 mutex_lock(&rt2x00dev
->csr_mutex
);
131 * Wait until the RF becomes available, afterwards we
132 * can safely write the new data into the register.
134 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
136 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
137 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
138 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
139 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
141 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
142 rt2x00_rf_write(rt2x00dev
, word
, value
);
145 mutex_unlock(&rt2x00dev
->csr_mutex
);
148 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
149 const u8 command
, const u8 token
,
150 const u8 arg0
, const u8 arg1
)
154 mutex_lock(&rt2x00dev
->csr_mutex
);
157 * Wait until the MCU becomes available, afterwards we
158 * can safely write the new data into the register.
160 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
161 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
162 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
163 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
164 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
165 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
167 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
168 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
169 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
170 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
173 mutex_unlock(&rt2x00dev
->csr_mutex
);
177 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
179 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
182 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
184 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
185 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
186 eeprom
->reg_data_clock
=
187 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
188 eeprom
->reg_chip_select
=
189 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
192 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
194 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
197 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
198 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
199 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
200 !!eeprom
->reg_data_clock
);
201 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
202 !!eeprom
->reg_chip_select
);
204 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
207 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
208 static const struct rt2x00debug rt61pci_rt2x00debug
= {
209 .owner
= THIS_MODULE
,
211 .read
= rt2x00pci_register_read
,
212 .write
= rt2x00pci_register_write
,
213 .flags
= RT2X00DEBUGFS_OFFSET
,
214 .word_base
= CSR_REG_BASE
,
215 .word_size
= sizeof(u32
),
216 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
219 .read
= rt2x00_eeprom_read
,
220 .write
= rt2x00_eeprom_write
,
221 .word_base
= EEPROM_BASE
,
222 .word_size
= sizeof(u16
),
223 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
226 .read
= rt61pci_bbp_read
,
227 .write
= rt61pci_bbp_write
,
228 .word_base
= BBP_BASE
,
229 .word_size
= sizeof(u8
),
230 .word_count
= BBP_SIZE
/ sizeof(u8
),
233 .read
= rt2x00_rf_read
,
234 .write
= rt61pci_rf_write
,
235 .word_base
= RF_BASE
,
236 .word_size
= sizeof(u32
),
237 .word_count
= RF_SIZE
/ sizeof(u32
),
240 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
242 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
246 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
247 return rt2x00_get_field32(reg
, MAC_CSR13_VAL5
);
250 #ifdef CONFIG_RT2X00_LIB_LEDS
251 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
252 enum led_brightness brightness
)
254 struct rt2x00_led
*led
=
255 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
256 unsigned int enabled
= brightness
!= LED_OFF
;
257 unsigned int a_mode
=
258 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
259 unsigned int bg_mode
=
260 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
262 if (led
->type
== LED_TYPE_RADIO
) {
263 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
264 MCU_LEDCS_RADIO_STATUS
, enabled
);
266 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
267 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
268 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
269 } else if (led
->type
== LED_TYPE_ASSOC
) {
270 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
271 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
272 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
273 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
275 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
276 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
277 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
278 } else if (led
->type
== LED_TYPE_QUALITY
) {
280 * The brightness is divided into 6 levels (0 - 5),
281 * this means we need to convert the brightness
282 * argument into the matching level within that range.
284 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
285 brightness
/ (LED_FULL
/ 6), 0);
289 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
290 unsigned long *delay_on
,
291 unsigned long *delay_off
)
293 struct rt2x00_led
*led
=
294 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
297 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
298 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
299 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
300 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
305 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
306 struct rt2x00_led
*led
,
309 led
->rt2x00dev
= rt2x00dev
;
311 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
312 led
->led_dev
.blink_set
= rt61pci_blink_set
;
313 led
->flags
= LED_INITIALIZED
;
315 #endif /* CONFIG_RT2X00_LIB_LEDS */
318 * Configuration handlers.
320 static int rt61pci_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
321 struct rt2x00lib_crypto
*crypto
,
322 struct ieee80211_key_conf
*key
)
324 struct hw_key_entry key_entry
;
325 struct rt2x00_field32 field
;
329 if (crypto
->cmd
== SET_KEY
) {
331 * rt2x00lib can't determine the correct free
332 * key_idx for shared keys. We have 1 register
333 * with key valid bits. The goal is simple, read
334 * the register, if that is full we have no slots
336 * Note that each BSS is allowed to have up to 4
337 * shared keys, so put a mask over the allowed
340 mask
= (0xf << crypto
->bssidx
);
342 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
345 if (reg
&& reg
== mask
)
348 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
351 * Upload key to hardware
353 memcpy(key_entry
.key
, crypto
->key
,
354 sizeof(key_entry
.key
));
355 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
356 sizeof(key_entry
.tx_mic
));
357 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
358 sizeof(key_entry
.rx_mic
));
360 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
361 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
362 &key_entry
, sizeof(key_entry
));
365 * The cipher types are stored over 2 registers.
366 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
367 * bssidx 1 and 2 keys are stored in SEC_CSR5.
368 * Using the correct defines correctly will cause overhead,
369 * so just calculate the correct offset.
371 if (key
->hw_key_idx
< 8) {
372 field
.bit_offset
= (3 * key
->hw_key_idx
);
373 field
.bit_mask
= 0x7 << field
.bit_offset
;
375 rt2x00pci_register_read(rt2x00dev
, SEC_CSR1
, ®
);
376 rt2x00_set_field32(®
, field
, crypto
->cipher
);
377 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, reg
);
379 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
380 field
.bit_mask
= 0x7 << field
.bit_offset
;
382 rt2x00pci_register_read(rt2x00dev
, SEC_CSR5
, ®
);
383 rt2x00_set_field32(®
, field
, crypto
->cipher
);
384 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, reg
);
388 * The driver does not support the IV/EIV generation
389 * in hardware. However it doesn't support the IV/EIV
390 * inside the ieee80211 frame either, but requires it
391 * to be provided separately for the descriptor.
392 * rt2x00lib will cut the IV/EIV data out of all frames
393 * given to us by mac80211, but we must tell mac80211
394 * to generate the IV/EIV data.
396 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
400 * SEC_CSR0 contains only single-bit fields to indicate
401 * a particular key is valid. Because using the FIELD32()
402 * defines directly will cause a lot of overhead, we use
403 * a calculation to determine the correct bit directly.
405 mask
= 1 << key
->hw_key_idx
;
407 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
408 if (crypto
->cmd
== SET_KEY
)
410 else if (crypto
->cmd
== DISABLE_KEY
)
412 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, reg
);
417 static int rt61pci_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
418 struct rt2x00lib_crypto
*crypto
,
419 struct ieee80211_key_conf
*key
)
421 struct hw_pairwise_ta_entry addr_entry
;
422 struct hw_key_entry key_entry
;
426 if (crypto
->cmd
== SET_KEY
) {
428 * rt2x00lib can't determine the correct free
429 * key_idx for pairwise keys. We have 2 registers
430 * with key valid bits. The goal is simple: read
431 * the first register. If that is full, move to
433 * When both registers are full, we drop the key.
434 * Otherwise, we use the first invalid entry.
436 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
437 if (reg
&& reg
== ~0) {
438 key
->hw_key_idx
= 32;
439 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
440 if (reg
&& reg
== ~0)
444 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
447 * Upload key to hardware
449 memcpy(key_entry
.key
, crypto
->key
,
450 sizeof(key_entry
.key
));
451 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
452 sizeof(key_entry
.tx_mic
));
453 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
454 sizeof(key_entry
.rx_mic
));
456 memset(&addr_entry
, 0, sizeof(addr_entry
));
457 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
458 addr_entry
.cipher
= crypto
->cipher
;
460 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
461 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
462 &key_entry
, sizeof(key_entry
));
464 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
465 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
466 &addr_entry
, sizeof(addr_entry
));
469 * Enable pairwise lookup table for given BSS idx.
470 * Without this, received frames will not be decrypted
473 rt2x00pci_register_read(rt2x00dev
, SEC_CSR4
, ®
);
474 reg
|= (1 << crypto
->bssidx
);
475 rt2x00pci_register_write(rt2x00dev
, SEC_CSR4
, reg
);
478 * The driver does not support the IV/EIV generation
479 * in hardware. However it doesn't support the IV/EIV
480 * inside the ieee80211 frame either, but requires it
481 * to be provided separately for the descriptor.
482 * rt2x00lib will cut the IV/EIV data out of all frames
483 * given to us by mac80211, but we must tell mac80211
484 * to generate the IV/EIV data.
486 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
490 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
491 * a particular key is valid. Because using the FIELD32()
492 * defines directly will cause a lot of overhead, we use
493 * a calculation to determine the correct bit directly.
495 if (key
->hw_key_idx
< 32) {
496 mask
= 1 << key
->hw_key_idx
;
498 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
499 if (crypto
->cmd
== SET_KEY
)
501 else if (crypto
->cmd
== DISABLE_KEY
)
503 rt2x00pci_register_write(rt2x00dev
, SEC_CSR2
, reg
);
505 mask
= 1 << (key
->hw_key_idx
- 32);
507 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
508 if (crypto
->cmd
== SET_KEY
)
510 else if (crypto
->cmd
== DISABLE_KEY
)
512 rt2x00pci_register_write(rt2x00dev
, SEC_CSR3
, reg
);
518 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
519 const unsigned int filter_flags
)
524 * Start configuration steps.
525 * Note that the version error will always be dropped
526 * and broadcast frames will always be accepted since
527 * there is no filter for it at this time.
529 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
530 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
531 !(filter_flags
& FIF_FCSFAIL
));
532 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
533 !(filter_flags
& FIF_PLCPFAIL
));
534 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
535 !(filter_flags
& (FIF_CONTROL
| FIF_PSPOLL
)));
536 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
537 !(filter_flags
& FIF_PROMISC_IN_BSS
));
538 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
539 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
540 !rt2x00dev
->intf_ap_count
);
541 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
542 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
543 !(filter_flags
& FIF_ALLMULTI
));
544 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
545 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
546 !(filter_flags
& FIF_CONTROL
));
547 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
550 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
551 struct rt2x00_intf
*intf
,
552 struct rt2x00intf_conf
*conf
,
553 const unsigned int flags
)
557 if (flags
& CONFIG_UPDATE_TYPE
) {
559 * Enable synchronisation.
561 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
562 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
563 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
566 if (flags
& CONFIG_UPDATE_MAC
) {
567 reg
= le32_to_cpu(conf
->mac
[1]);
568 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
569 conf
->mac
[1] = cpu_to_le32(reg
);
571 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
572 conf
->mac
, sizeof(conf
->mac
));
575 if (flags
& CONFIG_UPDATE_BSSID
) {
576 reg
= le32_to_cpu(conf
->bssid
[1]);
577 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
578 conf
->bssid
[1] = cpu_to_le32(reg
);
580 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
581 conf
->bssid
, sizeof(conf
->bssid
));
585 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
586 struct rt2x00lib_erp
*erp
,
591 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
592 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, 0x32);
593 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
594 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
596 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
597 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
598 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
599 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
600 !!erp
->short_preamble
);
601 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
604 if (changed
& BSS_CHANGED_BASIC_RATES
)
605 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
,
608 if (changed
& BSS_CHANGED_BEACON_INT
) {
609 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
610 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
611 erp
->beacon_int
* 16);
612 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
615 if (changed
& BSS_CHANGED_ERP_SLOT
) {
616 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
617 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, erp
->slot_time
);
618 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
620 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
621 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, erp
->sifs
);
622 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
623 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, erp
->eifs
);
624 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
628 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
629 struct antenna_setup
*ant
)
635 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
636 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
637 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
639 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF5325
));
642 * Configure the RX antenna.
645 case ANTENNA_HW_DIVERSITY
:
646 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
647 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
648 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
651 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
652 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
653 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
654 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
656 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
660 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
661 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
662 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
663 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
665 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
669 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
670 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
671 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
674 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
675 struct antenna_setup
*ant
)
681 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
682 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
683 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
685 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF2529
));
686 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
687 !test_bit(CAPABILITY_FRAME_TYPE
, &rt2x00dev
->cap_flags
));
690 * Configure the RX antenna.
693 case ANTENNA_HW_DIVERSITY
:
694 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
697 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
698 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
702 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
703 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
707 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
708 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
709 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
712 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
713 const int p1
, const int p2
)
717 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
719 rt2x00_set_field32(®
, MAC_CSR13_DIR4
, 0);
720 rt2x00_set_field32(®
, MAC_CSR13_VAL4
, p1
);
722 rt2x00_set_field32(®
, MAC_CSR13_DIR3
, 0);
723 rt2x00_set_field32(®
, MAC_CSR13_VAL3
, !p2
);
725 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
728 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
729 struct antenna_setup
*ant
)
735 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
736 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
737 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
740 * Configure the RX antenna.
744 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
745 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
746 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
748 case ANTENNA_HW_DIVERSITY
:
750 * FIXME: Antenna selection for the rf 2529 is very confusing
751 * in the legacy driver. Just default to antenna B until the
752 * legacy code can be properly translated into rt2x00 code.
756 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
757 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
758 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
762 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
763 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
764 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
770 * value[0] -> non-LNA
776 static const struct antenna_sel antenna_sel_a
[] = {
777 { 96, { 0x58, 0x78 } },
778 { 104, { 0x38, 0x48 } },
779 { 75, { 0xfe, 0x80 } },
780 { 86, { 0xfe, 0x80 } },
781 { 88, { 0xfe, 0x80 } },
782 { 35, { 0x60, 0x60 } },
783 { 97, { 0x58, 0x58 } },
784 { 98, { 0x58, 0x58 } },
787 static const struct antenna_sel antenna_sel_bg
[] = {
788 { 96, { 0x48, 0x68 } },
789 { 104, { 0x2c, 0x3c } },
790 { 75, { 0xfe, 0x80 } },
791 { 86, { 0xfe, 0x80 } },
792 { 88, { 0xfe, 0x80 } },
793 { 35, { 0x50, 0x50 } },
794 { 97, { 0x48, 0x48 } },
795 { 98, { 0x48, 0x48 } },
798 static void rt61pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
799 struct antenna_setup
*ant
)
801 const struct antenna_sel
*sel
;
807 * We should never come here because rt2x00lib is supposed
808 * to catch this and send us the correct antenna explicitely.
810 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
811 ant
->tx
== ANTENNA_SW_DIVERSITY
);
813 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
815 lna
= test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
817 sel
= antenna_sel_bg
;
818 lna
= test_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
821 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
822 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
824 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
826 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
827 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
828 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
829 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
831 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
833 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
))
834 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
835 else if (rt2x00_rf(rt2x00dev
, RF2527
))
836 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
837 else if (rt2x00_rf(rt2x00dev
, RF2529
)) {
838 if (test_bit(CAPABILITY_DOUBLE_ANTENNA
, &rt2x00dev
->cap_flags
))
839 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
841 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
845 static void rt61pci_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
846 struct rt2x00lib_conf
*libconf
)
851 if (libconf
->conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
852 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
))
855 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
856 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
858 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
861 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
862 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
865 rt2x00dev
->lna_gain
= lna_gain
;
868 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
869 struct rf_channel
*rf
, const int txpower
)
875 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
876 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
878 smart
= !(rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF2527
));
880 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
881 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
882 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
885 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
886 r94
+= txpower
- MAX_TXPOWER
;
887 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
889 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
891 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
892 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
893 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
894 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
898 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
899 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
900 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
901 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
905 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
906 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
907 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
908 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
913 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
916 struct rf_channel rf
;
918 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
919 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
920 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
921 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
923 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
926 static void rt61pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
927 struct rt2x00lib_conf
*libconf
)
931 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
932 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_RATE_DOWN
, 1);
933 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_RATE_STEP
, 0);
934 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_FALLBACK_CCK
, 0);
935 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
,
936 libconf
->conf
->long_frame_max_tx_count
);
937 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
,
938 libconf
->conf
->short_frame_max_tx_count
);
939 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
942 static void rt61pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
943 struct rt2x00lib_conf
*libconf
)
945 enum dev_state state
=
946 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
947 STATE_SLEEP
: STATE_AWAKE
;
950 if (state
== STATE_SLEEP
) {
951 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
952 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
,
953 rt2x00dev
->beacon_int
- 10);
954 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
,
955 libconf
->conf
->listen_interval
- 1);
956 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 5);
958 /* We must first disable autowake before it can be enabled */
959 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
960 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
962 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 1);
963 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
965 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000005);
966 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x0000001c);
967 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000060);
969 rt61pci_mcu_request(rt2x00dev
, MCU_SLEEP
, 0xff, 0, 0);
971 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
972 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
, 0);
973 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
, 0);
974 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
975 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 0);
976 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
978 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
979 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x00000018);
980 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000020);
982 rt61pci_mcu_request(rt2x00dev
, MCU_WAKEUP
, 0xff, 0, 0);
986 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
987 struct rt2x00lib_conf
*libconf
,
988 const unsigned int flags
)
990 /* Always recalculate LNA gain before changing configuration */
991 rt61pci_config_lna_gain(rt2x00dev
, libconf
);
993 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
994 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
995 libconf
->conf
->power_level
);
996 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
997 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
998 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
999 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1000 rt61pci_config_retry_limit(rt2x00dev
, libconf
);
1001 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1002 rt61pci_config_ps(rt2x00dev
, libconf
);
1008 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
1009 struct link_qual
*qual
)
1014 * Update FCS error count from register.
1016 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1017 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
1020 * Update False CCA count from register.
1022 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1023 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
1026 static inline void rt61pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1027 struct link_qual
*qual
, u8 vgc_level
)
1029 if (qual
->vgc_level
!= vgc_level
) {
1030 rt61pci_bbp_write(rt2x00dev
, 17, vgc_level
);
1031 qual
->vgc_level
= vgc_level
;
1032 qual
->vgc_level_reg
= vgc_level
;
1036 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
1037 struct link_qual
*qual
)
1039 rt61pci_set_vgc(rt2x00dev
, qual
, 0x20);
1042 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
1043 struct link_qual
*qual
, const u32 count
)
1049 * Determine r17 bounds.
1051 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1054 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
)) {
1061 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
)) {
1068 * If we are not associated, we should go straight to the
1069 * dynamic CCA tuning.
1071 if (!rt2x00dev
->intf_associated
)
1072 goto dynamic_cca_tune
;
1075 * Special big-R17 for very short distance
1077 if (qual
->rssi
>= -35) {
1078 rt61pci_set_vgc(rt2x00dev
, qual
, 0x60);
1083 * Special big-R17 for short distance
1085 if (qual
->rssi
>= -58) {
1086 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1091 * Special big-R17 for middle-short distance
1093 if (qual
->rssi
>= -66) {
1094 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x10);
1099 * Special mid-R17 for middle distance
1101 if (qual
->rssi
>= -74) {
1102 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x08);
1107 * Special case: Change up_bound based on the rssi.
1108 * Lower up_bound when rssi is weaker then -74 dBm.
1110 up_bound
-= 2 * (-74 - qual
->rssi
);
1111 if (low_bound
> up_bound
)
1112 up_bound
= low_bound
;
1114 if (qual
->vgc_level
> up_bound
) {
1115 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1122 * r17 does not yet exceed upper limit, continue and base
1123 * the r17 tuning on the false CCA count.
1125 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< up_bound
))
1126 rt61pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level
);
1127 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> low_bound
))
1128 rt61pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level
);
1134 static void rt61pci_start_queue(struct data_queue
*queue
)
1136 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
1139 switch (queue
->qid
) {
1141 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1142 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1143 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1146 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1147 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1148 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1149 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1150 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1157 static void rt61pci_kick_queue(struct data_queue
*queue
)
1159 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
1162 switch (queue
->qid
) {
1164 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1165 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, 1);
1166 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1169 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1170 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, 1);
1171 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1174 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1175 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, 1);
1176 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1179 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1180 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, 1);
1181 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1188 static void rt61pci_stop_queue(struct data_queue
*queue
)
1190 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
1193 switch (queue
->qid
) {
1195 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1196 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, 1);
1197 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1200 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1201 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, 1);
1202 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1205 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1206 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, 1);
1207 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1210 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1211 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, 1);
1212 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1215 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1216 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 1);
1217 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1220 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1221 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1222 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1223 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1224 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1227 * Wait for possibly running tbtt tasklets.
1229 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
1237 * Firmware functions
1239 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1244 pci_read_config_word(to_pci_dev(rt2x00dev
->dev
), PCI_DEVICE_ID
, &chip
);
1247 fw_name
= FIRMWARE_RT2561
;
1249 case RT2561s_PCI_ID
:
1250 fw_name
= FIRMWARE_RT2561s
;
1253 fw_name
= FIRMWARE_RT2661
;
1263 static int rt61pci_check_firmware(struct rt2x00_dev
*rt2x00dev
,
1264 const u8
*data
, const size_t len
)
1270 * Only support 8kb firmware files.
1273 return FW_BAD_LENGTH
;
1276 * The last 2 bytes in the firmware array are the crc checksum itself.
1277 * This means that we should never pass those 2 bytes to the crc
1280 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
1283 * Use the crc itu-t algorithm.
1285 crc
= crc_itu_t(0, data
, len
- 2);
1286 crc
= crc_itu_t_byte(crc
, 0);
1287 crc
= crc_itu_t_byte(crc
, 0);
1289 return (fw_crc
== crc
) ? FW_OK
: FW_BAD_CRC
;
1292 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
,
1293 const u8
*data
, const size_t len
)
1299 * Wait for stable hardware.
1301 for (i
= 0; i
< 100; i
++) {
1302 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1309 ERROR(rt2x00dev
, "Unstable hardware.\n");
1314 * Prepare MCU and mailbox for firmware loading.
1317 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1318 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1319 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1320 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1321 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
1324 * Write firmware to device.
1327 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1328 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
1329 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1331 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
1334 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
1335 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1337 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
1338 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1340 for (i
= 0; i
< 100; i
++) {
1341 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
1342 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1348 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1353 * Hardware needs another millisecond before it is ready.
1358 * Reset MAC and BBP registers.
1361 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1362 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1363 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1365 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1366 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1367 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1368 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1370 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1371 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1372 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1378 * Initialization functions.
1380 static bool rt61pci_get_entry_state(struct queue_entry
*entry
)
1382 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1385 if (entry
->queue
->qid
== QID_RX
) {
1386 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1388 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
1390 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1392 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1393 rt2x00_get_field32(word
, TXD_W0_VALID
));
1397 static void rt61pci_clear_entry(struct queue_entry
*entry
)
1399 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1400 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1403 if (entry
->queue
->qid
== QID_RX
) {
1404 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1405 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1407 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1409 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1410 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1411 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1413 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1414 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1415 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1416 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1420 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1422 struct queue_entry_priv_pci
*entry_priv
;
1426 * Initialize registers.
1428 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1429 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1430 rt2x00dev
->tx
[0].limit
);
1431 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1432 rt2x00dev
->tx
[1].limit
);
1433 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1434 rt2x00dev
->tx
[2].limit
);
1435 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1436 rt2x00dev
->tx
[3].limit
);
1437 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1439 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1440 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1441 rt2x00dev
->tx
[0].desc_size
/ 4);
1442 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1444 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1445 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1446 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1447 entry_priv
->desc_dma
);
1448 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1450 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1451 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1452 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1453 entry_priv
->desc_dma
);
1454 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1456 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1457 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1458 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1459 entry_priv
->desc_dma
);
1460 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1462 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1463 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1464 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1465 entry_priv
->desc_dma
);
1466 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1468 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1469 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1470 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1471 rt2x00dev
->rx
->desc_size
/ 4);
1472 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1473 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1475 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1476 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1477 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1478 entry_priv
->desc_dma
);
1479 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1481 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1482 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1483 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1484 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1485 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1486 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1488 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1489 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1490 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1491 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1492 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1493 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1495 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1496 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1497 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1502 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1506 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1507 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1508 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1509 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1510 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1512 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1513 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1514 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1515 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1516 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1517 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1518 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1519 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1520 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1521 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1524 * CCK TXD BBP registers
1526 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1527 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1528 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1529 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1530 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1531 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1532 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1533 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1534 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1535 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1538 * OFDM TXD BBP registers
1540 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1541 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1542 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1543 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1544 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1545 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1546 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1547 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1549 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1550 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1551 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1552 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1553 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1554 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1556 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1557 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1558 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1559 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1560 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1561 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1563 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1564 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1565 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1566 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1567 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1568 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1569 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1570 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1572 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1574 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1576 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1577 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1578 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1580 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1582 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1585 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1588 * Invalidate all Shared Keys (SEC_CSR0),
1589 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1591 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1592 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1593 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1595 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1596 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1597 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1598 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1600 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1602 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1604 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1608 * For the Beacon base registers we only need to clear
1609 * the first byte since that byte contains the VALID and OWNER
1610 * bits which (when set to 0) will invalidate the entire beacon.
1612 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1613 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1614 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1615 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1618 * We must clear the error counters.
1619 * These registers are cleared on read,
1620 * so we may pass a useless variable to store the value.
1622 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1623 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1624 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1627 * Reset MAC and BBP registers.
1629 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1630 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1631 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1632 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1634 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1635 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1636 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1637 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1639 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1640 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1641 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1646 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1651 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1652 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1653 if ((value
!= 0xff) && (value
!= 0x00))
1655 udelay(REGISTER_BUSY_DELAY
);
1658 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1662 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1669 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1672 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1673 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1674 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1675 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1676 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1677 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1678 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1679 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1680 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1681 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1682 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1683 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1684 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1685 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1686 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1687 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1688 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1689 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1690 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1691 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1692 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1693 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1694 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1695 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1697 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1698 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1700 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1701 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1702 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1703 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1711 * Device state switch handlers.
1713 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1714 enum dev_state state
)
1716 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1718 unsigned long flags
;
1721 * When interrupts are being enabled, the interrupt registers
1722 * should clear the register to assure a clean state.
1724 if (state
== STATE_RADIO_IRQ_ON
) {
1725 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1726 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1728 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1729 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1733 * Only toggle the interrupts bits we are going to use.
1734 * Non-checked interrupt bits are disabled by default.
1736 spin_lock_irqsave(&rt2x00dev
->irqmask_lock
, flags
);
1738 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1739 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1740 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1741 rt2x00_set_field32(®
, INT_MASK_CSR_BEACON_DONE
, mask
);
1742 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1743 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1744 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1746 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1747 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1748 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1749 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1750 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1751 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1752 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1753 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1754 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1755 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_TWAKEUP
, mask
);
1756 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1758 spin_unlock_irqrestore(&rt2x00dev
->irqmask_lock
, flags
);
1760 if (state
== STATE_RADIO_IRQ_OFF
) {
1762 * Ensure that all tasklets are finished.
1764 tasklet_kill(&rt2x00dev
->txstatus_tasklet
);
1765 tasklet_kill(&rt2x00dev
->rxdone_tasklet
);
1766 tasklet_kill(&rt2x00dev
->autowake_tasklet
);
1767 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
1771 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1776 * Initialize all registers.
1778 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1779 rt61pci_init_registers(rt2x00dev
) ||
1780 rt61pci_init_bbp(rt2x00dev
)))
1786 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1787 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1788 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1793 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1798 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1801 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1807 put_to_sleep
= (state
!= STATE_AWAKE
);
1809 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1810 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1811 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1812 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1815 * Device is not guaranteed to be in the requested state yet.
1816 * We must wait until the register indicates that the
1817 * device has entered the correct state.
1819 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1820 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®2
);
1821 state
= rt2x00_get_field32(reg2
, MAC_CSR12_BBP_CURRENT_STATE
);
1822 if (state
== !put_to_sleep
)
1824 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1831 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1832 enum dev_state state
)
1837 case STATE_RADIO_ON
:
1838 retval
= rt61pci_enable_radio(rt2x00dev
);
1840 case STATE_RADIO_OFF
:
1841 rt61pci_disable_radio(rt2x00dev
);
1843 case STATE_RADIO_IRQ_ON
:
1844 case STATE_RADIO_IRQ_OFF
:
1845 rt61pci_toggle_irq(rt2x00dev
, state
);
1847 case STATE_DEEP_SLEEP
:
1851 retval
= rt61pci_set_state(rt2x00dev
, state
);
1858 if (unlikely(retval
))
1859 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1866 * TX descriptor initialization
1868 static void rt61pci_write_tx_desc(struct queue_entry
*entry
,
1869 struct txentry_desc
*txdesc
)
1871 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1872 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1873 __le32
*txd
= entry_priv
->desc
;
1877 * Start writing the descriptor words.
1879 rt2x00_desc_read(txd
, 1, &word
);
1880 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, entry
->queue
->qid
);
1881 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, entry
->queue
->aifs
);
1882 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, entry
->queue
->cw_min
);
1883 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, entry
->queue
->cw_max
);
1884 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1885 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1886 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1887 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1888 rt2x00_desc_write(txd
, 1, word
);
1890 rt2x00_desc_read(txd
, 2, &word
);
1891 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->u
.plcp
.signal
);
1892 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->u
.plcp
.service
);
1893 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
,
1894 txdesc
->u
.plcp
.length_low
);
1895 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
,
1896 txdesc
->u
.plcp
.length_high
);
1897 rt2x00_desc_write(txd
, 2, word
);
1899 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1900 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
[0]);
1901 _rt2x00_desc_write(txd
, 4, skbdesc
->iv
[1]);
1904 rt2x00_desc_read(txd
, 5, &word
);
1905 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, entry
->queue
->qid
);
1906 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1907 skbdesc
->entry
->entry_idx
);
1908 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1909 TXPOWER_TO_DEV(entry
->queue
->rt2x00dev
->tx_power
));
1910 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1911 rt2x00_desc_write(txd
, 5, word
);
1913 if (entry
->queue
->qid
!= QID_BEACON
) {
1914 rt2x00_desc_read(txd
, 6, &word
);
1915 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1917 rt2x00_desc_write(txd
, 6, word
);
1919 rt2x00_desc_read(txd
, 11, &word
);
1920 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
,
1922 rt2x00_desc_write(txd
, 11, word
);
1926 * Writing TXD word 0 must the last to prevent a race condition with
1927 * the device, whereby the device may take hold of the TXD before we
1928 * finished updating it.
1930 rt2x00_desc_read(txd
, 0, &word
);
1931 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1932 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1933 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1934 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1935 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1936 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1937 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1938 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1939 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1940 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1941 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->u
.plcp
.ifs
);
1942 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1943 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1944 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1945 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1946 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1947 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1948 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1949 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, txdesc
->length
);
1950 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1951 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1952 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1953 rt2x00_desc_write(txd
, 0, word
);
1956 * Register descriptor details in skb frame descriptor.
1958 skbdesc
->desc
= txd
;
1959 skbdesc
->desc_len
= (entry
->queue
->qid
== QID_BEACON
) ? TXINFO_SIZE
:
1964 * TX data initialization
1966 static void rt61pci_write_beacon(struct queue_entry
*entry
,
1967 struct txentry_desc
*txdesc
)
1969 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1970 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1971 unsigned int beacon_base
;
1972 unsigned int padding_len
;
1976 * Disable beaconing while we are reloading the beacon data,
1977 * otherwise we might be sending out invalid data.
1979 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1981 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1982 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1985 * Write the TX descriptor for the beacon.
1987 rt61pci_write_tx_desc(entry
, txdesc
);
1990 * Dump beacon to userspace through debugfs.
1992 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
1995 * Write entire beacon with descriptor and padding to register.
1997 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
1998 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
1999 ERROR(rt2x00dev
, "Failure padding beacon, aborting\n");
2000 /* skb freed by skb_pad() on failure */
2002 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, orig_reg
);
2006 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
2007 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
,
2008 entry_priv
->desc
, TXINFO_SIZE
);
2009 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
+ TXINFO_SIZE
,
2011 entry
->skb
->len
+ padding_len
);
2014 * Enable beaconing again.
2016 * For Wi-Fi faily generated beacons between participating
2017 * stations. Set TBTT phase adaptive adjustment step to 8us.
2019 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
2021 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
2022 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
2025 * Clean up beacon skb.
2027 dev_kfree_skb_any(entry
->skb
);
2031 static void rt61pci_clear_beacon(struct queue_entry
*entry
)
2033 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
2037 * Disable beaconing while we are reloading the beacon data,
2038 * otherwise we might be sending out invalid data.
2040 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
2041 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
2042 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
2047 rt2x00pci_register_write(rt2x00dev
,
2048 HW_BEACON_OFFSET(entry
->entry_idx
), 0);
2051 * Enable beaconing again.
2053 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
2054 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
2058 * RX control handlers
2060 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
2062 u8 offset
= rt2x00dev
->lna_gain
;
2065 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
2080 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
2081 if (lna
== 3 || lna
== 2)
2085 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
2088 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
2089 struct rxdone_entry_desc
*rxdesc
)
2091 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
2092 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
2096 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
2097 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
2099 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
2100 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
2102 rxdesc
->cipher
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
2103 rxdesc
->cipher_status
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
2105 if (rxdesc
->cipher
!= CIPHER_NONE
) {
2106 _rt2x00_desc_read(entry_priv
->desc
, 2, &rxdesc
->iv
[0]);
2107 _rt2x00_desc_read(entry_priv
->desc
, 3, &rxdesc
->iv
[1]);
2108 rxdesc
->dev_flags
|= RXDONE_CRYPTO_IV
;
2110 _rt2x00_desc_read(entry_priv
->desc
, 4, &rxdesc
->icv
);
2111 rxdesc
->dev_flags
|= RXDONE_CRYPTO_ICV
;
2114 * Hardware has stripped IV/EIV data from 802.11 frame during
2115 * decryption. It has provided the data separately but rt2x00lib
2116 * should decide if it should be reinserted.
2118 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
2121 * The hardware has already checked the Michael Mic and has
2122 * stripped it from the frame. Signal this to mac80211.
2124 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
2126 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
2127 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
2128 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
2129 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
2133 * Obtain the status about this packet.
2134 * When frame was received with an OFDM bitrate,
2135 * the signal is the PLCP value. If it was received with
2136 * a CCK bitrate the signal is the rate in 100kbit/s.
2138 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
2139 rxdesc
->rssi
= rt61pci_agc_to_rssi(rt2x00dev
, word1
);
2140 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
2142 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
2143 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
2145 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
2146 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
2147 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
2151 * Interrupt functions.
2153 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
2155 struct data_queue
*queue
;
2156 struct queue_entry
*entry
;
2157 struct queue_entry
*entry_done
;
2158 struct queue_entry_priv_pci
*entry_priv
;
2159 struct txdone_entry_desc txdesc
;
2167 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2168 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2169 * flag is not set anymore.
2171 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2172 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2173 * tx ring size for now.
2175 for (i
= 0; i
< rt2x00dev
->ops
->tx
->entry_num
; i
++) {
2176 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
2177 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
2181 * Skip this entry when it contains an invalid
2182 * queue identication number.
2184 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
2185 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, type
);
2186 if (unlikely(!queue
))
2190 * Skip this entry when it contains an invalid
2193 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
2194 if (unlikely(index
>= queue
->limit
))
2197 entry
= &queue
->entries
[index
];
2198 entry_priv
= entry
->priv_data
;
2199 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
2201 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
2202 !rt2x00_get_field32(word
, TXD_W0_VALID
))
2205 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2206 while (entry
!= entry_done
) {
2208 * Just report any entries we missed as failed.
2211 "TX status report missed for entry %d\n",
2212 entry_done
->entry_idx
);
2214 rt2x00lib_txdone_noinfo(entry_done
, TXDONE_UNKNOWN
);
2215 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2219 * Obtain the status about this packet.
2222 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
2223 case 0: /* Success, maybe with retry */
2224 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
2226 case 6: /* Failure, excessive retries */
2227 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
2228 /* Don't break, this is a failed frame! */
2229 default: /* Failure */
2230 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
2232 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
2235 * the frame was retried at least once
2236 * -> hw used fallback rates
2239 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
2241 rt2x00lib_txdone(entry
, &txdesc
);
2245 static void rt61pci_wakeup(struct rt2x00_dev
*rt2x00dev
)
2247 struct rt2x00lib_conf libconf
= { .conf
= &rt2x00dev
->hw
->conf
};
2249 rt61pci_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
2252 static inline void rt61pci_enable_interrupt(struct rt2x00_dev
*rt2x00dev
,
2253 struct rt2x00_field32 irq_field
)
2258 * Enable a single interrupt. The interrupt mask register
2259 * access needs locking.
2261 spin_lock_irq(&rt2x00dev
->irqmask_lock
);
2263 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
2264 rt2x00_set_field32(®
, irq_field
, 0);
2265 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
2267 spin_unlock_irq(&rt2x00dev
->irqmask_lock
);
2270 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev
*rt2x00dev
,
2271 struct rt2x00_field32 irq_field
)
2276 * Enable a single MCU interrupt. The interrupt mask register
2277 * access needs locking.
2279 spin_lock_irq(&rt2x00dev
->irqmask_lock
);
2281 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
2282 rt2x00_set_field32(®
, irq_field
, 0);
2283 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
2285 spin_unlock_irq(&rt2x00dev
->irqmask_lock
);
2288 static void rt61pci_txstatus_tasklet(unsigned long data
)
2290 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
2291 rt61pci_txdone(rt2x00dev
);
2292 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2293 rt61pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_TXDONE
);
2296 static void rt61pci_tbtt_tasklet(unsigned long data
)
2298 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
2299 rt2x00lib_beacondone(rt2x00dev
);
2300 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2301 rt61pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_BEACON_DONE
);
2304 static void rt61pci_rxdone_tasklet(unsigned long data
)
2306 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
2307 if (rt2x00pci_rxdone(rt2x00dev
))
2308 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
2309 else if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2310 rt61pci_enable_interrupt(rt2x00dev
, INT_MASK_CSR_RXDONE
);
2313 static void rt61pci_autowake_tasklet(unsigned long data
)
2315 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
2316 rt61pci_wakeup(rt2x00dev
);
2317 rt2x00pci_register_write(rt2x00dev
,
2318 M2H_CMD_DONE_CSR
, 0xffffffff);
2319 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2320 rt61pci_enable_mcu_interrupt(rt2x00dev
, MCU_INT_MASK_CSR_TWAKEUP
);
2323 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
2325 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2326 u32 reg_mcu
, mask_mcu
;
2330 * Get the interrupt sources & saved to local variable.
2331 * Write register value back to clear pending interrupts.
2333 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
2334 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
2336 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
2337 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
2339 if (!reg
&& !reg_mcu
)
2342 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2346 * Schedule tasklets for interrupt handling.
2348 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
2349 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
2351 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
2352 tasklet_schedule(&rt2x00dev
->txstatus_tasklet
);
2354 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_BEACON_DONE
))
2355 tasklet_hi_schedule(&rt2x00dev
->tbtt_tasklet
);
2357 if (rt2x00_get_field32(reg_mcu
, MCU_INT_SOURCE_CSR_TWAKEUP
))
2358 tasklet_schedule(&rt2x00dev
->autowake_tasklet
);
2361 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2362 * for interrupts and interrupt masks we can just use the value of
2363 * INT_SOURCE_CSR to create the interrupt mask.
2369 * Disable all interrupts for which a tasklet was scheduled right now,
2370 * the tasklet will reenable the appropriate interrupts.
2372 spin_lock(&rt2x00dev
->irqmask_lock
);
2374 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
2376 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
2378 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
2380 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
2382 spin_unlock(&rt2x00dev
->irqmask_lock
);
2388 * Device probe functions.
2390 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2392 struct eeprom_93cx6 eeprom
;
2398 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
2400 eeprom
.data
= rt2x00dev
;
2401 eeprom
.register_read
= rt61pci_eepromregister_read
;
2402 eeprom
.register_write
= rt61pci_eepromregister_write
;
2403 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
2404 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
2405 eeprom
.reg_data_in
= 0;
2406 eeprom
.reg_data_out
= 0;
2407 eeprom
.reg_data_clock
= 0;
2408 eeprom
.reg_chip_select
= 0;
2410 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
2411 EEPROM_SIZE
/ sizeof(u16
));
2414 * Start validation of the data that has been read.
2416 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2417 if (!is_valid_ether_addr(mac
)) {
2418 eth_random_addr(mac
);
2419 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2422 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2423 if (word
== 0xffff) {
2424 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
2425 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
2427 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
2429 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
2430 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
2431 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
2432 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
2433 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2434 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2437 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2438 if (word
== 0xffff) {
2439 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
2440 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
2441 rt2x00_set_field16(&word
, EEPROM_NIC_RX_FIXED
, 0);
2442 rt2x00_set_field16(&word
, EEPROM_NIC_TX_FIXED
, 0);
2443 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2444 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2445 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2446 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2447 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2450 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
2451 if (word
== 0xffff) {
2452 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
2454 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
2455 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
2458 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2459 if (word
== 0xffff) {
2460 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2461 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
2462 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2463 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2466 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
2467 if (word
== 0xffff) {
2468 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2469 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2470 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2471 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
2473 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
2474 if (value
< -10 || value
> 10)
2475 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2476 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
2477 if (value
< -10 || value
> 10)
2478 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2479 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2482 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
2483 if (word
== 0xffff) {
2484 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2485 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2486 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2487 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
2489 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
2490 if (value
< -10 || value
> 10)
2491 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2492 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
2493 if (value
< -10 || value
> 10)
2494 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2495 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2501 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2508 * Read EEPROM word for configuration.
2510 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2513 * Identify RF chipset.
2515 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2516 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2517 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2518 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2520 if (!rt2x00_rf(rt2x00dev
, RF5225
) &&
2521 !rt2x00_rf(rt2x00dev
, RF5325
) &&
2522 !rt2x00_rf(rt2x00dev
, RF2527
) &&
2523 !rt2x00_rf(rt2x00dev
, RF2529
)) {
2524 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2529 * Determine number of antennas.
2531 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2532 __set_bit(CAPABILITY_DOUBLE_ANTENNA
, &rt2x00dev
->cap_flags
);
2535 * Identify default antenna configuration.
2537 rt2x00dev
->default_ant
.tx
=
2538 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2539 rt2x00dev
->default_ant
.rx
=
2540 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2543 * Read the Frame type.
2545 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2546 __set_bit(CAPABILITY_FRAME_TYPE
, &rt2x00dev
->cap_flags
);
2549 * Detect if this device has a hardware controlled radio.
2551 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2552 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
2555 * Read frequency offset and RF programming sequence.
2557 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2558 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2559 __set_bit(CAPABILITY_RF_SEQUENCE
, &rt2x00dev
->cap_flags
);
2561 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2564 * Read external LNA informations.
2566 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2568 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2569 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
2570 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2571 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
2574 * When working with a RF2529 chip without double antenna,
2575 * the antenna settings should be gathered from the NIC
2578 if (rt2x00_rf(rt2x00dev
, RF2529
) &&
2579 !test_bit(CAPABILITY_DOUBLE_ANTENNA
, &rt2x00dev
->cap_flags
)) {
2580 rt2x00dev
->default_ant
.rx
=
2581 ANTENNA_A
+ rt2x00_get_field16(eeprom
, EEPROM_NIC_RX_FIXED
);
2582 rt2x00dev
->default_ant
.tx
=
2583 ANTENNA_B
- rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_FIXED
);
2585 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2586 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2587 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2588 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2592 * Store led settings, for correct led behaviour.
2593 * If the eeprom value is invalid,
2594 * switch to default led mode.
2596 #ifdef CONFIG_RT2X00_LIB_LEDS
2597 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2598 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2600 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2601 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2602 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2603 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2606 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2607 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2608 rt2x00_get_field16(eeprom
,
2609 EEPROM_LED_POLARITY_GPIO_0
));
2610 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2611 rt2x00_get_field16(eeprom
,
2612 EEPROM_LED_POLARITY_GPIO_1
));
2613 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2614 rt2x00_get_field16(eeprom
,
2615 EEPROM_LED_POLARITY_GPIO_2
));
2616 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2617 rt2x00_get_field16(eeprom
,
2618 EEPROM_LED_POLARITY_GPIO_3
));
2619 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2620 rt2x00_get_field16(eeprom
,
2621 EEPROM_LED_POLARITY_GPIO_4
));
2622 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2623 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2624 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2625 rt2x00_get_field16(eeprom
,
2626 EEPROM_LED_POLARITY_RDY_G
));
2627 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2628 rt2x00_get_field16(eeprom
,
2629 EEPROM_LED_POLARITY_RDY_A
));
2630 #endif /* CONFIG_RT2X00_LIB_LEDS */
2636 * RF value list for RF5225 & RF5325
2637 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2639 static const struct rf_channel rf_vals_noseq
[] = {
2640 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2641 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2642 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2643 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2644 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2645 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2646 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2647 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2648 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2649 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2650 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2651 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2652 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2653 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2655 /* 802.11 UNI / HyperLan 2 */
2656 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2657 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2658 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2659 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2660 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2661 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2662 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2663 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2665 /* 802.11 HyperLan 2 */
2666 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2667 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2668 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2669 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2670 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2671 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2672 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2673 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2674 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2675 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2678 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2679 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2680 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2681 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2682 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2683 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2685 /* MMAC(Japan)J52 ch 34,38,42,46 */
2686 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2687 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2688 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2689 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2693 * RF value list for RF5225 & RF5325
2694 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2696 static const struct rf_channel rf_vals_seq
[] = {
2697 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2698 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2699 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2700 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2701 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2702 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2703 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2704 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2705 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2706 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2707 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2708 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2709 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2710 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2712 /* 802.11 UNI / HyperLan 2 */
2713 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2714 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2715 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2716 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2717 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2718 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2719 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2720 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2722 /* 802.11 HyperLan 2 */
2723 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2724 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2725 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2726 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2727 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2728 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2729 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2730 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2731 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2732 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2735 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2736 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2737 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2738 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2739 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2740 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2742 /* MMAC(Japan)J52 ch 34,38,42,46 */
2743 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2744 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2745 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2746 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2749 static int rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2751 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2752 struct channel_info
*info
;
2757 * Disable powersaving as default.
2759 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2762 * Initialize all hw fields.
2764 rt2x00dev
->hw
->flags
=
2765 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2766 IEEE80211_HW_SIGNAL_DBM
|
2767 IEEE80211_HW_SUPPORTS_PS
|
2768 IEEE80211_HW_PS_NULLFUNC_STACK
;
2770 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2771 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2772 rt2x00_eeprom_addr(rt2x00dev
,
2773 EEPROM_MAC_ADDR_0
));
2776 * As rt61 has a global fallback table we cannot specify
2777 * more then one tx rate per frame but since the hw will
2778 * try several rates (based on the fallback table) we should
2779 * initialize max_report_rates to the maximum number of rates
2780 * we are going to try. Otherwise mac80211 will truncate our
2781 * reported tx rates and the rc algortihm will end up with
2784 rt2x00dev
->hw
->max_rates
= 1;
2785 rt2x00dev
->hw
->max_report_rates
= 7;
2786 rt2x00dev
->hw
->max_rate_tries
= 1;
2789 * Initialize hw_mode information.
2791 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2792 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2794 if (!test_bit(CAPABILITY_RF_SEQUENCE
, &rt2x00dev
->cap_flags
)) {
2795 spec
->num_channels
= 14;
2796 spec
->channels
= rf_vals_noseq
;
2798 spec
->num_channels
= 14;
2799 spec
->channels
= rf_vals_seq
;
2802 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
)) {
2803 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2804 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2808 * Create channel information array
2810 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
2814 spec
->channels_info
= info
;
2816 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2817 for (i
= 0; i
< 14; i
++) {
2818 info
[i
].max_power
= MAX_TXPOWER
;
2819 info
[i
].default_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2822 if (spec
->num_channels
> 14) {
2823 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2824 for (i
= 14; i
< spec
->num_channels
; i
++) {
2825 info
[i
].max_power
= MAX_TXPOWER
;
2826 info
[i
].default_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2833 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2839 * Disable power saving.
2841 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
2844 * Allocate eeprom data.
2846 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2850 retval
= rt61pci_init_eeprom(rt2x00dev
);
2855 * Enable rfkill polling by setting GPIO direction of the
2856 * rfkill switch GPIO pin correctly.
2858 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
2859 rt2x00_set_field32(®
, MAC_CSR13_DIR5
, 1);
2860 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
2863 * Initialize hw specifications.
2865 retval
= rt61pci_probe_hw_mode(rt2x00dev
);
2870 * This device has multiple filters for control frames,
2871 * but has no a separate filter for PS Poll frames.
2873 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
2876 * This device requires firmware and DMA mapped skbs.
2878 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
2879 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
2880 if (!modparam_nohwcrypt
)
2881 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
2882 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
2885 * Set the rssi offset.
2887 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2893 * IEEE80211 stack callback functions.
2895 static int rt61pci_conf_tx(struct ieee80211_hw
*hw
,
2896 struct ieee80211_vif
*vif
, u16 queue_idx
,
2897 const struct ieee80211_tx_queue_params
*params
)
2899 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2900 struct data_queue
*queue
;
2901 struct rt2x00_field32 field
;
2907 * First pass the configuration through rt2x00lib, that will
2908 * update the queue settings and validate the input. After that
2909 * we are free to update the registers based on the value
2910 * in the queue parameter.
2912 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
2917 * We only need to perform additional register initialization
2923 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
2925 /* Update WMM TXOP register */
2926 offset
= AC_TXOP_CSR0
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2927 field
.bit_offset
= (queue_idx
& 1) * 16;
2928 field
.bit_mask
= 0xffff << field
.bit_offset
;
2930 rt2x00pci_register_read(rt2x00dev
, offset
, ®
);
2931 rt2x00_set_field32(®
, field
, queue
->txop
);
2932 rt2x00pci_register_write(rt2x00dev
, offset
, reg
);
2934 /* Update WMM registers */
2935 field
.bit_offset
= queue_idx
* 4;
2936 field
.bit_mask
= 0xf << field
.bit_offset
;
2938 rt2x00pci_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2939 rt2x00_set_field32(®
, field
, queue
->aifs
);
2940 rt2x00pci_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2942 rt2x00pci_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2943 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2944 rt2x00pci_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2946 rt2x00pci_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2947 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2948 rt2x00pci_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2953 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
2955 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2959 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2960 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2961 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2962 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2967 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2969 .start
= rt2x00mac_start
,
2970 .stop
= rt2x00mac_stop
,
2971 .add_interface
= rt2x00mac_add_interface
,
2972 .remove_interface
= rt2x00mac_remove_interface
,
2973 .config
= rt2x00mac_config
,
2974 .configure_filter
= rt2x00mac_configure_filter
,
2975 .set_key
= rt2x00mac_set_key
,
2976 .sw_scan_start
= rt2x00mac_sw_scan_start
,
2977 .sw_scan_complete
= rt2x00mac_sw_scan_complete
,
2978 .get_stats
= rt2x00mac_get_stats
,
2979 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2980 .conf_tx
= rt61pci_conf_tx
,
2981 .get_tsf
= rt61pci_get_tsf
,
2982 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2983 .flush
= rt2x00mac_flush
,
2984 .set_antenna
= rt2x00mac_set_antenna
,
2985 .get_antenna
= rt2x00mac_get_antenna
,
2986 .get_ringparam
= rt2x00mac_get_ringparam
,
2987 .tx_frames_pending
= rt2x00mac_tx_frames_pending
,
2990 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2991 .irq_handler
= rt61pci_interrupt
,
2992 .txstatus_tasklet
= rt61pci_txstatus_tasklet
,
2993 .tbtt_tasklet
= rt61pci_tbtt_tasklet
,
2994 .rxdone_tasklet
= rt61pci_rxdone_tasklet
,
2995 .autowake_tasklet
= rt61pci_autowake_tasklet
,
2996 .probe_hw
= rt61pci_probe_hw
,
2997 .get_firmware_name
= rt61pci_get_firmware_name
,
2998 .check_firmware
= rt61pci_check_firmware
,
2999 .load_firmware
= rt61pci_load_firmware
,
3000 .initialize
= rt2x00pci_initialize
,
3001 .uninitialize
= rt2x00pci_uninitialize
,
3002 .get_entry_state
= rt61pci_get_entry_state
,
3003 .clear_entry
= rt61pci_clear_entry
,
3004 .set_device_state
= rt61pci_set_device_state
,
3005 .rfkill_poll
= rt61pci_rfkill_poll
,
3006 .link_stats
= rt61pci_link_stats
,
3007 .reset_tuner
= rt61pci_reset_tuner
,
3008 .link_tuner
= rt61pci_link_tuner
,
3009 .start_queue
= rt61pci_start_queue
,
3010 .kick_queue
= rt61pci_kick_queue
,
3011 .stop_queue
= rt61pci_stop_queue
,
3012 .flush_queue
= rt2x00pci_flush_queue
,
3013 .write_tx_desc
= rt61pci_write_tx_desc
,
3014 .write_beacon
= rt61pci_write_beacon
,
3015 .clear_beacon
= rt61pci_clear_beacon
,
3016 .fill_rxdone
= rt61pci_fill_rxdone
,
3017 .config_shared_key
= rt61pci_config_shared_key
,
3018 .config_pairwise_key
= rt61pci_config_pairwise_key
,
3019 .config_filter
= rt61pci_config_filter
,
3020 .config_intf
= rt61pci_config_intf
,
3021 .config_erp
= rt61pci_config_erp
,
3022 .config_ant
= rt61pci_config_ant
,
3023 .config
= rt61pci_config
,
3026 static const struct data_queue_desc rt61pci_queue_rx
= {
3028 .data_size
= DATA_FRAME_SIZE
,
3029 .desc_size
= RXD_DESC_SIZE
,
3030 .priv_size
= sizeof(struct queue_entry_priv_pci
),
3033 static const struct data_queue_desc rt61pci_queue_tx
= {
3035 .data_size
= DATA_FRAME_SIZE
,
3036 .desc_size
= TXD_DESC_SIZE
,
3037 .priv_size
= sizeof(struct queue_entry_priv_pci
),
3040 static const struct data_queue_desc rt61pci_queue_bcn
= {
3042 .data_size
= 0, /* No DMA required for beacons */
3043 .desc_size
= TXINFO_SIZE
,
3044 .priv_size
= sizeof(struct queue_entry_priv_pci
),
3047 static const struct rt2x00_ops rt61pci_ops
= {
3048 .name
= KBUILD_MODNAME
,
3050 .eeprom_size
= EEPROM_SIZE
,
3052 .tx_queues
= NUM_TX_QUEUES
,
3053 .extra_tx_headroom
= 0,
3054 .rx
= &rt61pci_queue_rx
,
3055 .tx
= &rt61pci_queue_tx
,
3056 .bcn
= &rt61pci_queue_bcn
,
3057 .lib
= &rt61pci_rt2x00_ops
,
3058 .hw
= &rt61pci_mac80211_ops
,
3059 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
3060 .debugfs
= &rt61pci_rt2x00debug
,
3061 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3065 * RT61pci module information.
3067 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table
) = {
3069 { PCI_DEVICE(0x1814, 0x0301) },
3071 { PCI_DEVICE(0x1814, 0x0302) },
3073 { PCI_DEVICE(0x1814, 0x0401) },
3077 MODULE_AUTHOR(DRV_PROJECT
);
3078 MODULE_VERSION(DRV_VERSION
);
3079 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
3080 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
3081 "PCI & PCMCIA chipset based cards");
3082 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
3083 MODULE_FIRMWARE(FIRMWARE_RT2561
);
3084 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
3085 MODULE_FIRMWARE(FIRMWARE_RT2661
);
3086 MODULE_LICENSE("GPL");
3088 static int rt61pci_probe(struct pci_dev
*pci_dev
,
3089 const struct pci_device_id
*id
)
3091 return rt2x00pci_probe(pci_dev
, &rt61pci_ops
);
3094 static struct pci_driver rt61pci_driver
= {
3095 .name
= KBUILD_MODNAME
,
3096 .id_table
= rt61pci_device_table
,
3097 .probe
= rt61pci_probe
,
3098 .remove
= rt2x00pci_remove
,
3099 .suspend
= rt2x00pci_suspend
,
3100 .resume
= rt2x00pci_resume
,
3103 module_pci_driver(rt61pci_driver
);