drivers/net/wireless/rt2x00/rt61pci.h

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: Data structures and registers for the rt61pci module.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #ifndef RT61PCI_H
  28 #define RT61PCI_H
  29
  30 /*
  31  * RT chip PCI IDs.
  32  */
  33 #define RT2561s_PCI_ID                  0x0301
  34 #define RT2561_PCI_ID                   0x0302
  35 #define RT2661_PCI_ID                   0x0401
  36
  37 /*
  38  * RF chip defines.
  39  */
  40 #define RF5225                          0x0001
  41 #define RF5325                          0x0002
  42 #define RF2527                          0x0003
  43 #define RF2529                          0x0004
  44
  45 /*
  46  * Signal information.
  47  * Default offset is required for RSSI <-> dBm conversion.
  48  */
  49 #define DEFAULT_RSSI_OFFSET             120
  50
  51 /*
  52  * Register layout information.
  53  */
  54 #define CSR_REG_BASE                    0x3000
  55 #define CSR_REG_SIZE                    0x04b0
  56 #define EEPROM_BASE                     0x0000
  57 #define EEPROM_SIZE                     0x0100
  58 #define BBP_BASE                        0x0000
  59 #define BBP_SIZE                        0x0080
  60 #define RF_BASE                         0x0004
  61 #define RF_SIZE                         0x0010
  62
  63 /*
  64  * Number of TX queues.
  65  */
  66 #define NUM_TX_QUEUES                   4
  67
  68 /*
  69  * PCI registers.
  70  */
  71
  72 /*
  73  * HOST_CMD_CSR: For HOST to interrupt embedded processor
  74  */
  75 #define HOST_CMD_CSR                    0x0008
  76 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x0000007f)
  77 #define HOST_CMD_CSR_INTERRUPT_MCU      FIELD32(0x00000080)
  78
  79 /*
  80  * MCU_CNTL_CSR
  81  * SELECT_BANK: Select 8051 program bank.
  82  * RESET: Enable 8051 reset state.
  83  * READY: Ready state for 8051.
  84  */
  85 #define MCU_CNTL_CSR                    0x000c
  86 #define MCU_CNTL_CSR_SELECT_BANK        FIELD32(0x00000001)
  87 #define MCU_CNTL_CSR_RESET              FIELD32(0x00000002)
  88 #define MCU_CNTL_CSR_READY              FIELD32(0x00000004)
  89
  90 /*
  91  * SOFT_RESET_CSR
  92  * FORCE_CLOCK_ON: Host force MAC clock ON
  93  */
  94 #define SOFT_RESET_CSR                  0x0010
  95 #define SOFT_RESET_CSR_FORCE_CLOCK_ON   FIELD32(0x00000002)
  96
  97 /*
  98  * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
  99  */
 100 #define MCU_INT_SOURCE_CSR              0x0014
 101 #define MCU_INT_SOURCE_CSR_0            FIELD32(0x00000001)
 102 #define MCU_INT_SOURCE_CSR_1            FIELD32(0x00000002)
 103 #define MCU_INT_SOURCE_CSR_2            FIELD32(0x00000004)
 104 #define MCU_INT_SOURCE_CSR_3            FIELD32(0x00000008)
 105 #define MCU_INT_SOURCE_CSR_4            FIELD32(0x00000010)
 106 #define MCU_INT_SOURCE_CSR_5            FIELD32(0x00000020)
 107 #define MCU_INT_SOURCE_CSR_6            FIELD32(0x00000040)
 108 #define MCU_INT_SOURCE_CSR_7            FIELD32(0x00000080)
 109 #define MCU_INT_SOURCE_CSR_TWAKEUP      FIELD32(0x00000100)
 110 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE  FIELD32(0x00000200)
 111
 112 /*
 113  * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
 114  */
 115 #define MCU_INT_MASK_CSR                0x0018
 116 #define MCU_INT_MASK_CSR_0              FIELD32(0x00000001)
 117 #define MCU_INT_MASK_CSR_1              FIELD32(0x00000002)
 118 #define MCU_INT_MASK_CSR_2              FIELD32(0x00000004)
 119 #define MCU_INT_MASK_CSR_3              FIELD32(0x00000008)
 120 #define MCU_INT_MASK_CSR_4              FIELD32(0x00000010)
 121 #define MCU_INT_MASK_CSR_5              FIELD32(0x00000020)
 122 #define MCU_INT_MASK_CSR_6              FIELD32(0x00000040)
 123 #define MCU_INT_MASK_CSR_7              FIELD32(0x00000080)
 124 #define MCU_INT_MASK_CSR_TWAKEUP        FIELD32(0x00000100)
 125 #define MCU_INT_MASK_CSR_TBTT_EXPIRE    FIELD32(0x00000200)
 126
 127 /*
 128  * PCI_USEC_CSR
 129  */
 130 #define PCI_USEC_CSR                    0x001c
 131
 132 /*
 133  * Security key table memory.
 134  * 16 entries 32-byte for shared key table
 135  * 64 entries 32-byte for pairwise key table
 136  * 64 entries 8-byte for pairwise ta key table
 137  */
 138 #define SHARED_KEY_TABLE_BASE           0x1000
 139 #define PAIRWISE_KEY_TABLE_BASE         0x1200
 140 #define PAIRWISE_TA_TABLE_BASE          0x1a00
 141
 142 #define SHARED_KEY_ENTRY(__idx) \
 143         ( SHARED_KEY_TABLE_BASE + \
 144                 ((__idx) * sizeof(struct hw_key_entry)) )
 145 #define PAIRWISE_KEY_ENTRY(__idx) \
 146         ( PAIRWISE_KEY_TABLE_BASE + \
 147                 ((__idx) * sizeof(struct hw_key_entry)) )
 148 #define PAIRWISE_TA_ENTRY(__idx) \
 149         ( PAIRWISE_TA_TABLE_BASE + \
 150                 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
 151
 152 struct hw_key_entry {
 153         u8 key[16];
 154         u8 tx_mic[8];
 155         u8 rx_mic[8];
 156 } __packed;
 157
 158 struct hw_pairwise_ta_entry {
 159         u8 address[6];
 160         u8 cipher;
 161         u8 reserved;
 162 } __packed;
 163
 164 /*
 165  * Other on-chip shared memory space.
 166  */
 167 #define HW_CIS_BASE                     0x2000
 168 #define HW_NULL_BASE                    0x2b00
 169
 170 /*
 171  * Since NULL frame won't be that long (256 byte),
 172  * We steal 16 tail bytes to save debugging settings.
 173  */
 174 #define HW_DEBUG_SETTING_BASE           0x2bf0
 175
 176 /*
 177  * On-chip BEACON frame space.
 178  */
 179 #define HW_BEACON_BASE0                 0x2c00
 180 #define HW_BEACON_BASE1                 0x2d00
 181 #define HW_BEACON_BASE2                 0x2e00
 182 #define HW_BEACON_BASE3                 0x2f00
 183
 184 #define HW_BEACON_OFFSET(__index) \
 185         ( HW_BEACON_BASE0 + (__index * 0x0100) )
 186
 187 /*
 188  * HOST-MCU shared memory.
 189  */
 190
 191 /*
 192  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
 193  */
 194 #define H2M_MAILBOX_CSR                 0x2100
 195 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
 196 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
 197 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
 198 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
 199
 200 /*
 201  * MCU_LEDCS: LED control for MCU Mailbox.
 202  */
 203 #define MCU_LEDCS_LED_MODE              FIELD16(0x001f)
 204 #define MCU_LEDCS_RADIO_STATUS          FIELD16(0x0020)
 205 #define MCU_LEDCS_LINK_BG_STATUS        FIELD16(0x0040)
 206 #define MCU_LEDCS_LINK_A_STATUS         FIELD16(0x0080)
 207 #define MCU_LEDCS_POLARITY_GPIO_0       FIELD16(0x0100)
 208 #define MCU_LEDCS_POLARITY_GPIO_1       FIELD16(0x0200)
 209 #define MCU_LEDCS_POLARITY_GPIO_2       FIELD16(0x0400)
 210 #define MCU_LEDCS_POLARITY_GPIO_3       FIELD16(0x0800)
 211 #define MCU_LEDCS_POLARITY_GPIO_4       FIELD16(0x1000)
 212 #define MCU_LEDCS_POLARITY_ACT          FIELD16(0x2000)
 213 #define MCU_LEDCS_POLARITY_READY_BG     FIELD16(0x4000)
 214 #define MCU_LEDCS_POLARITY_READY_A      FIELD16(0x8000)
 215
 216 /*
 217  * M2H_CMD_DONE_CSR.
 218  */
 219 #define M2H_CMD_DONE_CSR                0x2104
 220
 221 /*
 222  * MCU_TXOP_ARRAY_BASE.
 223  */
 224 #define MCU_TXOP_ARRAY_BASE             0x2110
 225
 226 /*
 227  * MAC Control/Status Registers(CSR).
 228  * Some values are set in TU, whereas 1 TU == 1024 us.
 229  */
 230
 231 /*
 232  * MAC_CSR0: ASIC revision number.
 233  */
 234 #define MAC_CSR0                        0x3000
 235 #define MAC_CSR0_REVISION               FIELD32(0x0000000f)
 236 #define MAC_CSR0_CHIPSET                FIELD32(0x000ffff0)
 237
 238 /*
 239  * MAC_CSR1: System control register.
 240  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
 241  * BBP_RESET: Hardware reset BBP.
 242  * HOST_READY: Host is ready after initialization, 1: ready.
 243  */
 244 #define MAC_CSR1                        0x3004
 245 #define MAC_CSR1_SOFT_RESET             FIELD32(0x00000001)
 246 #define MAC_CSR1_BBP_RESET              FIELD32(0x00000002)
 247 #define MAC_CSR1_HOST_READY             FIELD32(0x00000004)
 248
 249 /*
 250  * MAC_CSR2: STA MAC register 0.
 251  */
 252 #define MAC_CSR2                        0x3008
 253 #define MAC_CSR2_BYTE0                  FIELD32(0x000000ff)
 254 #define MAC_CSR2_BYTE1                  FIELD32(0x0000ff00)
 255 #define MAC_CSR2_BYTE2                  FIELD32(0x00ff0000)
 256 #define MAC_CSR2_BYTE3                  FIELD32(0xff000000)
 257
 258 /*
 259  * MAC_CSR3: STA MAC register 1.
 260  * UNICAST_TO_ME_MASK:
 261  *      Used to mask off bits from byte 5 of the MAC address
 262  *      to determine the UNICAST_TO_ME bit for RX frames.
 263  *      The full mask is complemented by BSS_ID_MASK:
 264  *              MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 265  */
 266 #define MAC_CSR3                        0x300c
 267 #define MAC_CSR3_BYTE4                  FIELD32(0x000000ff)
 268 #define MAC_CSR3_BYTE5                  FIELD32(0x0000ff00)
 269 #define MAC_CSR3_UNICAST_TO_ME_MASK     FIELD32(0x00ff0000)
 270
 271 /*
 272  * MAC_CSR4: BSSID register 0.
 273  */
 274 #define MAC_CSR4                        0x3010
 275 #define MAC_CSR4_BYTE0                  FIELD32(0x000000ff)
 276 #define MAC_CSR4_BYTE1                  FIELD32(0x0000ff00)
 277 #define MAC_CSR4_BYTE2                  FIELD32(0x00ff0000)
 278 #define MAC_CSR4_BYTE3                  FIELD32(0xff000000)
 279
 280 /*
 281  * MAC_CSR5: BSSID register 1.
 282  * BSS_ID_MASK:
 283  *      This mask is used to mask off bits 0 and 1 of byte 5 of the
 284  *      BSSID. This will make sure that those bits will be ignored
 285  *      when determining the MY_BSS of RX frames.
 286  *              0: 1-BSSID mode (BSS index = 0)
 287  *              1: 2-BSSID mode (BSS index: Byte5, bit 0)
 288  *              2: 2-BSSID mode (BSS index: byte5, bit 1)
 289  *              3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 290  */
 291 #define MAC_CSR5                        0x3014
 292 #define MAC_CSR5_BYTE4                  FIELD32(0x000000ff)
 293 #define MAC_CSR5_BYTE5                  FIELD32(0x0000ff00)
 294 #define MAC_CSR5_BSS_ID_MASK            FIELD32(0x00ff0000)
 295
 296 /*
 297  * MAC_CSR6: Maximum frame length register.
 298  */
 299 #define MAC_CSR6                        0x3018
 300 #define MAC_CSR6_MAX_FRAME_UNIT         FIELD32(0x00000fff)
 301
 302 /*
 303  * MAC_CSR7: Reserved
 304  */
 305 #define MAC_CSR7                        0x301c
 306
 307 /*
 308  * MAC_CSR8: SIFS/EIFS register.
 309  * All units are in US.
 310  */
 311 #define MAC_CSR8                        0x3020
 312 #define MAC_CSR8_SIFS                   FIELD32(0x000000ff)
 313 #define MAC_CSR8_SIFS_AFTER_RX_OFDM     FIELD32(0x0000ff00)
 314 #define MAC_CSR8_EIFS                   FIELD32(0xffff0000)
 315
 316 /*
 317  * MAC_CSR9: Back-Off control register.
 318  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
 319  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
 320  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
 321  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
 322  */
 323 #define MAC_CSR9                        0x3024
 324 #define MAC_CSR9_SLOT_TIME              FIELD32(0x000000ff)
 325 #define MAC_CSR9_CWMIN                  FIELD32(0x00000f00)
 326 #define MAC_CSR9_CWMAX                  FIELD32(0x0000f000)
 327 #define MAC_CSR9_CW_SELECT              FIELD32(0x00010000)
 328
 329 /*
 330  * MAC_CSR10: Power state configuration.
 331  */
 332 #define MAC_CSR10                       0x3028
 333
 334 /*
 335  * MAC_CSR11: Power saving transition time register.
 336  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
 337  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 338  * WAKEUP_LATENCY: In unit of TU.
 339  */
 340 #define MAC_CSR11                       0x302c
 341 #define MAC_CSR11_DELAY_AFTER_TBCN      FIELD32(0x000000ff)
 342 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
 343 #define MAC_CSR11_AUTOWAKE              FIELD32(0x00008000)
 344 #define MAC_CSR11_WAKEUP_LATENCY        FIELD32(0x000f0000)
 345
 346 /*
 347  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
 348  * CURRENT_STATE: 0:sleep, 1:awake.
 349  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
 350  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
 351  */
 352 #define MAC_CSR12                       0x3030
 353 #define MAC_CSR12_CURRENT_STATE         FIELD32(0x00000001)
 354 #define MAC_CSR12_PUT_TO_SLEEP          FIELD32(0x00000002)
 355 #define MAC_CSR12_FORCE_WAKEUP          FIELD32(0x00000004)
 356 #define MAC_CSR12_BBP_CURRENT_STATE     FIELD32(0x00000008)
 357
 358 /*
 359  * MAC_CSR13: GPIO.
 360  */
 361 #define MAC_CSR13                       0x3034
 362 #define MAC_CSR13_BIT0                  FIELD32(0x00000001)
 363 #define MAC_CSR13_BIT1                  FIELD32(0x00000002)
 364 #define MAC_CSR13_BIT2                  FIELD32(0x00000004)
 365 #define MAC_CSR13_BIT3                  FIELD32(0x00000008)
 366 #define MAC_CSR13_BIT4                  FIELD32(0x00000010)
 367 #define MAC_CSR13_BIT5                  FIELD32(0x00000020)
 368 #define MAC_CSR13_BIT6                  FIELD32(0x00000040)
 369 #define MAC_CSR13_BIT7                  FIELD32(0x00000080)
 370 #define MAC_CSR13_BIT8                  FIELD32(0x00000100)
 371 #define MAC_CSR13_BIT9                  FIELD32(0x00000200)
 372 #define MAC_CSR13_BIT10                 FIELD32(0x00000400)
 373 #define MAC_CSR13_BIT11                 FIELD32(0x00000800)
 374 #define MAC_CSR13_BIT12                 FIELD32(0x00001000)
 375
 376 /*
 377  * MAC_CSR14: LED control register.
 378  * ON_PERIOD: On period, default 70ms.
 379  * OFF_PERIOD: Off period, default 30ms.
 380  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
 381  * SW_LED: s/w LED, 1: ON, 0: OFF.
 382  * HW_LED_POLARITY: 0: active low, 1: active high.
 383  */
 384 #define MAC_CSR14                       0x3038
 385 #define MAC_CSR14_ON_PERIOD             FIELD32(0x000000ff)
 386 #define MAC_CSR14_OFF_PERIOD            FIELD32(0x0000ff00)
 387 #define MAC_CSR14_HW_LED                FIELD32(0x00010000)
 388 #define MAC_CSR14_SW_LED                FIELD32(0x00020000)
 389 #define MAC_CSR14_HW_LED_POLARITY       FIELD32(0x00040000)
 390 #define MAC_CSR14_SW_LED2               FIELD32(0x00080000)
 391
 392 /*
 393  * MAC_CSR15: NAV control.
 394  */
 395 #define MAC_CSR15                       0x303c
 396
 397 /*
 398  * TXRX control registers.
 399  * Some values are set in TU, whereas 1 TU == 1024 us.
 400  */
 401
 402 /*
 403  * TXRX_CSR0: TX/RX configuration register.
 404  * TSF_OFFSET: Default is 24.
 405  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
 406  * DISABLE_RX: Disable Rx engine.
 407  * DROP_CRC: Drop CRC error.
 408  * DROP_PHYSICAL: Drop physical error.
 409  * DROP_CONTROL: Drop control frame.
 410  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 411  * DROP_TO_DS: Drop fram ToDs bit is true.
 412  * DROP_VERSION_ERROR: Drop version error frame.
 413  * DROP_MULTICAST: Drop multicast frames.
 414  * DROP_BORADCAST: Drop broadcast frames.
 415  * DROP_ACK_CTS: Drop received ACK and CTS.
 416  */
 417 #define TXRX_CSR0                       0x3040
 418 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
 419 #define TXRX_CSR0_TSF_OFFSET            FIELD32(0x00007e00)
 420 #define TXRX_CSR0_AUTO_TX_SEQ           FIELD32(0x00008000)
 421 #define TXRX_CSR0_DISABLE_RX            FIELD32(0x00010000)
 422 #define TXRX_CSR0_DROP_CRC              FIELD32(0x00020000)
 423 #define TXRX_CSR0_DROP_PHYSICAL         FIELD32(0x00040000)
 424 #define TXRX_CSR0_DROP_CONTROL          FIELD32(0x00080000)
 425 #define TXRX_CSR0_DROP_NOT_TO_ME        FIELD32(0x00100000)
 426 #define TXRX_CSR0_DROP_TO_DS            FIELD32(0x00200000)
 427 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
 428 #define TXRX_CSR0_DROP_MULTICAST        FIELD32(0x00800000)
 429 #define TXRX_CSR0_DROP_BROADCAST        FIELD32(0x01000000)
 430 #define TXRX_CSR0_DROP_ACK_CTS          FIELD32(0x02000000)
 431 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
 432
 433 /*
 434  * TXRX_CSR1
 435  */
 436 #define TXRX_CSR1                       0x3044
 437 #define TXRX_CSR1_BBP_ID0               FIELD32(0x0000007f)
 438 #define TXRX_CSR1_BBP_ID0_VALID         FIELD32(0x00000080)
 439 #define TXRX_CSR1_BBP_ID1               FIELD32(0x00007f00)
 440 #define TXRX_CSR1_BBP_ID1_VALID         FIELD32(0x00008000)
 441 #define TXRX_CSR1_BBP_ID2               FIELD32(0x007f0000)
 442 #define TXRX_CSR1_BBP_ID2_VALID         FIELD32(0x00800000)
 443 #define TXRX_CSR1_BBP_ID3               FIELD32(0x7f000000)
 444 #define TXRX_CSR1_BBP_ID3_VALID         FIELD32(0x80000000)
 445
 446 /*
 447  * TXRX_CSR2
 448  */
 449 #define TXRX_CSR2                       0x3048
 450 #define TXRX_CSR2_BBP_ID0               FIELD32(0x0000007f)
 451 #define TXRX_CSR2_BBP_ID0_VALID         FIELD32(0x00000080)
 452 #define TXRX_CSR2_BBP_ID1               FIELD32(0x00007f00)
 453 #define TXRX_CSR2_BBP_ID1_VALID         FIELD32(0x00008000)
 454 #define TXRX_CSR2_BBP_ID2               FIELD32(0x007f0000)
 455 #define TXRX_CSR2_BBP_ID2_VALID         FIELD32(0x00800000)
 456 #define TXRX_CSR2_BBP_ID3               FIELD32(0x7f000000)
 457 #define TXRX_CSR2_BBP_ID3_VALID         FIELD32(0x80000000)
 458
 459 /*
 460  * TXRX_CSR3
 461  */
 462 #define TXRX_CSR3                       0x304c
 463 #define TXRX_CSR3_BBP_ID0               FIELD32(0x0000007f)
 464 #define TXRX_CSR3_BBP_ID0_VALID         FIELD32(0x00000080)
 465 #define TXRX_CSR3_BBP_ID1               FIELD32(0x00007f00)
 466 #define TXRX_CSR3_BBP_ID1_VALID         FIELD32(0x00008000)
 467 #define TXRX_CSR3_BBP_ID2               FIELD32(0x007f0000)
 468 #define TXRX_CSR3_BBP_ID2_VALID         FIELD32(0x00800000)
 469 #define TXRX_CSR3_BBP_ID3               FIELD32(0x7f000000)
 470 #define TXRX_CSR3_BBP_ID3_VALID         FIELD32(0x80000000)
 471
 472 /*
 473  * TXRX_CSR4: Auto-Responder/Tx-retry register.
 474  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
 475  * OFDM_TX_RATE_DOWN: 1:enable.
 476  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
 477  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
 478  */
 479 #define TXRX_CSR4                       0x3050
 480 #define TXRX_CSR4_TX_ACK_TIMEOUT        FIELD32(0x000000ff)
 481 #define TXRX_CSR4_CNTL_ACK_POLICY       FIELD32(0x00000700)
 482 #define TXRX_CSR4_ACK_CTS_PSM           FIELD32(0x00010000)
 483 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
 484 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
 485 #define TXRX_CSR4_OFDM_TX_RATE_DOWN     FIELD32(0x00080000)
 486 #define TXRX_CSR4_OFDM_TX_RATE_STEP     FIELD32(0x00300000)
 487 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
 488 #define TXRX_CSR4_LONG_RETRY_LIMIT      FIELD32(0x0f000000)
 489 #define TXRX_CSR4_SHORT_RETRY_LIMIT     FIELD32(0xf0000000)
 490
 491 /*
 492  * TXRX_CSR5
 493  */
 494 #define TXRX_CSR5                       0x3054
 495
 496 /*
 497  * TXRX_CSR6: ACK/CTS payload consumed time
 498  */
 499 #define TXRX_CSR6                       0x3058
 500
 501 /*
 502  * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
 503  */
 504 #define TXRX_CSR7                       0x305c
 505 #define TXRX_CSR7_ACK_CTS_6MBS          FIELD32(0x000000ff)
 506 #define TXRX_CSR7_ACK_CTS_9MBS          FIELD32(0x0000ff00)
 507 #define TXRX_CSR7_ACK_CTS_12MBS         FIELD32(0x00ff0000)
 508 #define TXRX_CSR7_ACK_CTS_18MBS         FIELD32(0xff000000)
 509
 510 /*
 511  * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
 512  */
 513 #define TXRX_CSR8                       0x3060
 514 #define TXRX_CSR8_ACK_CTS_24MBS         FIELD32(0x000000ff)
 515 #define TXRX_CSR8_ACK_CTS_36MBS         FIELD32(0x0000ff00)
 516 #define TXRX_CSR8_ACK_CTS_48MBS         FIELD32(0x00ff0000)
 517 #define TXRX_CSR8_ACK_CTS_54MBS         FIELD32(0xff000000)
 518
 519 /*
 520  * TXRX_CSR9: Synchronization control register.
 521  * BEACON_INTERVAL: In unit of 1/16 TU.
 522  * TSF_TICKING: Enable TSF auto counting.
 523  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 524  * BEACON_GEN: Enable beacon generator.
 525  */
 526 #define TXRX_CSR9                       0x3064
 527 #define TXRX_CSR9_BEACON_INTERVAL       FIELD32(0x0000ffff)
 528 #define TXRX_CSR9_TSF_TICKING           FIELD32(0x00010000)
 529 #define TXRX_CSR9_TSF_SYNC              FIELD32(0x00060000)
 530 #define TXRX_CSR9_TBTT_ENABLE           FIELD32(0x00080000)
 531 #define TXRX_CSR9_BEACON_GEN            FIELD32(0x00100000)
 532 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
 533
 534 /*
 535  * TXRX_CSR10: BEACON alignment.
 536  */
 537 #define TXRX_CSR10                      0x3068
 538
 539 /*
 540  * TXRX_CSR11: AES mask.
 541  */
 542 #define TXRX_CSR11                      0x306c
 543
 544 /*
 545  * TXRX_CSR12: TSF low 32.
 546  */
 547 #define TXRX_CSR12                      0x3070
 548 #define TXRX_CSR12_LOW_TSFTIMER         FIELD32(0xffffffff)
 549
 550 /*
 551  * TXRX_CSR13: TSF high 32.
 552  */
 553 #define TXRX_CSR13                      0x3074
 554 #define TXRX_CSR13_HIGH_TSFTIMER        FIELD32(0xffffffff)
 555
 556 /*
 557  * TXRX_CSR14: TBTT timer.
 558  */
 559 #define TXRX_CSR14                      0x3078
 560
 561 /*
 562  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
 563  */
 564 #define TXRX_CSR15                      0x307c
 565
 566 /*
 567  * PHY control registers.
 568  * Some values are set in TU, whereas 1 TU == 1024 us.
 569  */
 570
 571 /*
 572  * PHY_CSR0: RF/PS control.
 573  */
 574 #define PHY_CSR0                        0x3080
 575 #define PHY_CSR0_PA_PE_BG               FIELD32(0x00010000)
 576 #define PHY_CSR0_PA_PE_A                FIELD32(0x00020000)
 577
 578 /*
 579  * PHY_CSR1
 580  */
 581 #define PHY_CSR1                        0x3084
 582
 583 /*
 584  * PHY_CSR2: Pre-TX BBP control.
 585  */
 586 #define PHY_CSR2                        0x3088
 587
 588 /*
 589  * PHY_CSR3: BBP serial control register.
 590  * VALUE: Register value to program into BBP.
 591  * REG_NUM: Selected BBP register.
 592  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
 593  * BUSY: 1: ASIC is busy execute BBP programming.
 594  */
 595 #define PHY_CSR3                        0x308c
 596 #define PHY_CSR3_VALUE                  FIELD32(0x000000ff)
 597 #define PHY_CSR3_REGNUM                 FIELD32(0x00007f00)
 598 #define PHY_CSR3_READ_CONTROL           FIELD32(0x00008000)
 599 #define PHY_CSR3_BUSY                   FIELD32(0x00010000)
 600
 601 /*
 602  * PHY_CSR4: RF serial control register
 603  * VALUE: Register value (include register id) serial out to RF/IF chip.
 604  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
 605  * IF_SELECT: 1: select IF to program, 0: select RF to program.
 606  * PLL_LD: RF PLL_LD status.
 607  * BUSY: 1: ASIC is busy execute RF programming.
 608  */
 609 #define PHY_CSR4                        0x3090
 610 #define PHY_CSR4_VALUE                  FIELD32(0x00ffffff)
 611 #define PHY_CSR4_NUMBER_OF_BITS         FIELD32(0x1f000000)
 612 #define PHY_CSR4_IF_SELECT              FIELD32(0x20000000)
 613 #define PHY_CSR4_PLL_LD                 FIELD32(0x40000000)
 614 #define PHY_CSR4_BUSY                   FIELD32(0x80000000)
 615
 616 /*
 617  * PHY_CSR5: RX to TX signal switch timing control.
 618  */
 619 #define PHY_CSR5                        0x3094
 620 #define PHY_CSR5_IQ_FLIP                FIELD32(0x00000004)
 621
 622 /*
 623  * PHY_CSR6: TX to RX signal timing control.
 624  */
 625 #define PHY_CSR6                        0x3098
 626 #define PHY_CSR6_IQ_FLIP                FIELD32(0x00000004)
 627
 628 /*
 629  * PHY_CSR7: TX DAC switching timing control.
 630  */
 631 #define PHY_CSR7                        0x309c
 632
 633 /*
 634  * Security control register.
 635  */
 636
 637 /*
 638  * SEC_CSR0: Shared key table control.
 639  */
 640 #define SEC_CSR0                        0x30a0
 641 #define SEC_CSR0_BSS0_KEY0_VALID        FIELD32(0x00000001)
 642 #define SEC_CSR0_BSS0_KEY1_VALID        FIELD32(0x00000002)
 643 #define SEC_CSR0_BSS0_KEY2_VALID        FIELD32(0x00000004)
 644 #define SEC_CSR0_BSS0_KEY3_VALID        FIELD32(0x00000008)
 645 #define SEC_CSR0_BSS1_KEY0_VALID        FIELD32(0x00000010)
 646 #define SEC_CSR0_BSS1_KEY1_VALID        FIELD32(0x00000020)
 647 #define SEC_CSR0_BSS1_KEY2_VALID        FIELD32(0x00000040)
 648 #define SEC_CSR0_BSS1_KEY3_VALID        FIELD32(0x00000080)
 649 #define SEC_CSR0_BSS2_KEY0_VALID        FIELD32(0x00000100)
 650 #define SEC_CSR0_BSS2_KEY1_VALID        FIELD32(0x00000200)
 651 #define SEC_CSR0_BSS2_KEY2_VALID        FIELD32(0x00000400)
 652 #define SEC_CSR0_BSS2_KEY3_VALID        FIELD32(0x00000800)
 653 #define SEC_CSR0_BSS3_KEY0_VALID        FIELD32(0x00001000)
 654 #define SEC_CSR0_BSS3_KEY1_VALID        FIELD32(0x00002000)
 655 #define SEC_CSR0_BSS3_KEY2_VALID        FIELD32(0x00004000)
 656 #define SEC_CSR0_BSS3_KEY3_VALID        FIELD32(0x00008000)
 657
 658 /*
 659  * SEC_CSR1: Shared key table security mode register.
 660  */
 661 #define SEC_CSR1                        0x30a4
 662 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 663 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 664 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 665 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 666 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 667 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 668 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 669 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 670
 671 /*
 672  * Pairwise key table valid bitmap registers.
 673  * SEC_CSR2: pairwise key table valid bitmap 0.
 674  * SEC_CSR3: pairwise key table valid bitmap 1.
 675  */
 676 #define SEC_CSR2                        0x30a8
 677 #define SEC_CSR3                        0x30ac
 678
 679 /*
 680  * SEC_CSR4: Pairwise key table lookup control.
 681  */
 682 #define SEC_CSR4                        0x30b0
 683 #define SEC_CSR4_ENABLE_BSS0            FIELD32(0x00000001)
 684 #define SEC_CSR4_ENABLE_BSS1            FIELD32(0x00000002)
 685 #define SEC_CSR4_ENABLE_BSS2            FIELD32(0x00000004)
 686 #define SEC_CSR4_ENABLE_BSS3            FIELD32(0x00000008)
 687
 688 /*
 689  * SEC_CSR5: shared key table security mode register.
 690  */
 691 #define SEC_CSR5                        0x30b4
 692 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 693 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 694 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 695 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 696 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 697 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 698 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 699 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 700
 701 /*
 702  * STA control registers.
 703  */
 704
 705 /*
 706  * STA_CSR0: RX PLCP error count & RX FCS error count.
 707  */
 708 #define STA_CSR0                        0x30c0
 709 #define STA_CSR0_FCS_ERROR              FIELD32(0x0000ffff)
 710 #define STA_CSR0_PLCP_ERROR             FIELD32(0xffff0000)
 711
 712 /*
 713  * STA_CSR1: RX False CCA count & RX LONG frame count.
 714  */
 715 #define STA_CSR1                        0x30c4
 716 #define STA_CSR1_PHYSICAL_ERROR         FIELD32(0x0000ffff)
 717 #define STA_CSR1_FALSE_CCA_ERROR        FIELD32(0xffff0000)
 718
 719 /*
 720  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
 721  */
 722 #define STA_CSR2                        0x30c8
 723 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
 724 #define STA_CSR2_RX_OVERFLOW_COUNT      FIELD32(0xffff0000)
 725
 726 /*
 727  * STA_CSR3: TX Beacon count.
 728  */
 729 #define STA_CSR3                        0x30cc
 730 #define STA_CSR3_TX_BEACON_COUNT        FIELD32(0x0000ffff)
 731
 732 /*
 733  * STA_CSR4: TX Result status register.
 734  * VALID: 1:This register contains a valid TX result.
 735  */
 736 #define STA_CSR4                        0x30d0
 737 #define STA_CSR4_VALID                  FIELD32(0x00000001)
 738 #define STA_CSR4_TX_RESULT              FIELD32(0x0000000e)
 739 #define STA_CSR4_RETRY_COUNT            FIELD32(0x000000f0)
 740 #define STA_CSR4_PID_SUBTYPE            FIELD32(0x00001f00)
 741 #define STA_CSR4_PID_TYPE               FIELD32(0x0000e000)
 742 #define STA_CSR4_TXRATE                 FIELD32(0x000f0000)
 743
 744 /*
 745  * QOS control registers.
 746  */
 747
 748 /*
 749  * QOS_CSR0: TXOP holder MAC address register.
 750  */
 751 #define QOS_CSR0                        0x30e0
 752 #define QOS_CSR0_BYTE0                  FIELD32(0x000000ff)
 753 #define QOS_CSR0_BYTE1                  FIELD32(0x0000ff00)
 754 #define QOS_CSR0_BYTE2                  FIELD32(0x00ff0000)
 755 #define QOS_CSR0_BYTE3                  FIELD32(0xff000000)
 756
 757 /*
 758  * QOS_CSR1: TXOP holder MAC address register.
 759  */
 760 #define QOS_CSR1                        0x30e4
 761 #define QOS_CSR1_BYTE4                  FIELD32(0x000000ff)
 762 #define QOS_CSR1_BYTE5                  FIELD32(0x0000ff00)
 763
 764 /*
 765  * QOS_CSR2: TXOP holder timeout register.
 766  */
 767 #define QOS_CSR2                        0x30e8
 768
 769 /*
 770  * RX QOS-CFPOLL MAC address register.
 771  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
 772  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
 773  */
 774 #define QOS_CSR3                        0x30ec
 775 #define QOS_CSR4                        0x30f0
 776
 777 /*
 778  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
 779  */
 780 #define QOS_CSR5                        0x30f4
 781
 782 /*
 783  * Host DMA registers.
 784  */
 785
 786 /*
 787  * AC0_BASE_CSR: AC_BK base address.
 788  */
 789 #define AC0_BASE_CSR                    0x3400
 790 #define AC0_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 791
 792 /*
 793  * AC1_BASE_CSR: AC_BE base address.
 794  */
 795 #define AC1_BASE_CSR                    0x3404
 796 #define AC1_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 797
 798 /*
 799  * AC2_BASE_CSR: AC_VI base address.
 800  */
 801 #define AC2_BASE_CSR                    0x3408
 802 #define AC2_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 803
 804 /*
 805  * AC3_BASE_CSR: AC_VO base address.
 806  */
 807 #define AC3_BASE_CSR                    0x340c
 808 #define AC3_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 809
 810 /*
 811  * MGMT_BASE_CSR: MGMT ring base address.
 812  */
 813 #define MGMT_BASE_CSR                   0x3410
 814 #define MGMT_BASE_CSR_RING_REGISTER     FIELD32(0xffffffff)
 815
 816 /*
 817  * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
 818  */
 819 #define TX_RING_CSR0                    0x3418
 820 #define TX_RING_CSR0_AC0_RING_SIZE      FIELD32(0x000000ff)
 821 #define TX_RING_CSR0_AC1_RING_SIZE      FIELD32(0x0000ff00)
 822 #define TX_RING_CSR0_AC2_RING_SIZE      FIELD32(0x00ff0000)
 823 #define TX_RING_CSR0_AC3_RING_SIZE      FIELD32(0xff000000)
 824
 825 /*
 826  * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
 827  * TXD_SIZE: In unit of 32-bit.
 828  */
 829 #define TX_RING_CSR1                    0x341c
 830 #define TX_RING_CSR1_MGMT_RING_SIZE     FIELD32(0x000000ff)
 831 #define TX_RING_CSR1_HCCA_RING_SIZE     FIELD32(0x0000ff00)
 832 #define TX_RING_CSR1_TXD_SIZE           FIELD32(0x003f0000)
 833
 834 /*
 835  * AIFSN_CSR: AIFSN for each EDCA AC.
 836  * AIFSN0: For AC_BK.
 837  * AIFSN1: For AC_BE.
 838  * AIFSN2: For AC_VI.
 839  * AIFSN3: For AC_VO.
 840  */
 841 #define AIFSN_CSR                       0x3420
 842 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
 843 #define AIFSN_CSR_AIFSN1                FIELD32(0x000000f0)
 844 #define AIFSN_CSR_AIFSN2                FIELD32(0x00000f00)
 845 #define AIFSN_CSR_AIFSN3                FIELD32(0x0000f000)
 846
 847 /*
 848  * CWMIN_CSR: CWmin for each EDCA AC.
 849  * CWMIN0: For AC_BK.
 850  * CWMIN1: For AC_BE.
 851  * CWMIN2: For AC_VI.
 852  * CWMIN3: For AC_VO.
 853  */
 854 #define CWMIN_CSR                       0x3424
 855 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
 856 #define CWMIN_CSR_CWMIN1                FIELD32(0x000000f0)
 857 #define CWMIN_CSR_CWMIN2                FIELD32(0x00000f00)
 858 #define CWMIN_CSR_CWMIN3                FIELD32(0x0000f000)
 859
 860 /*
 861  * CWMAX_CSR: CWmax for each EDCA AC.
 862  * CWMAX0: For AC_BK.
 863  * CWMAX1: For AC_BE.
 864  * CWMAX2: For AC_VI.
 865  * CWMAX3: For AC_VO.
 866  */
 867 #define CWMAX_CSR                       0x3428
 868 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
 869 #define CWMAX_CSR_CWMAX1                FIELD32(0x000000f0)
 870 #define CWMAX_CSR_CWMAX2                FIELD32(0x00000f00)
 871 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 872
 873 /*
 874  * TX_DMA_DST_CSR: TX DMA destination
 875  * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
 876  */
 877 #define TX_DMA_DST_CSR                  0x342c
 878 #define TX_DMA_DST_CSR_DEST_AC0         FIELD32(0x00000003)
 879 #define TX_DMA_DST_CSR_DEST_AC1         FIELD32(0x0000000c)
 880 #define TX_DMA_DST_CSR_DEST_AC2         FIELD32(0x00000030)
 881 #define TX_DMA_DST_CSR_DEST_AC3         FIELD32(0x000000c0)
 882 #define TX_DMA_DST_CSR_DEST_MGMT        FIELD32(0x00000300)
 883
 884 /*
 885  * TX_CNTL_CSR: KICK/Abort TX.
 886  * KICK_TX_AC0: For AC_BK.
 887  * KICK_TX_AC1: For AC_BE.
 888  * KICK_TX_AC2: For AC_VI.
 889  * KICK_TX_AC3: For AC_VO.
 890  * ABORT_TX_AC0: For AC_BK.
 891  * ABORT_TX_AC1: For AC_BE.
 892  * ABORT_TX_AC2: For AC_VI.
 893  * ABORT_TX_AC3: For AC_VO.
 894  */
 895 #define TX_CNTL_CSR                     0x3430
 896 #define TX_CNTL_CSR_KICK_TX_AC0         FIELD32(0x00000001)
 897 #define TX_CNTL_CSR_KICK_TX_AC1         FIELD32(0x00000002)
 898 #define TX_CNTL_CSR_KICK_TX_AC2         FIELD32(0x00000004)
 899 #define TX_CNTL_CSR_KICK_TX_AC3         FIELD32(0x00000008)
 900 #define TX_CNTL_CSR_KICK_TX_MGMT        FIELD32(0x00000010)
 901 #define TX_CNTL_CSR_ABORT_TX_AC0        FIELD32(0x00010000)
 902 #define TX_CNTL_CSR_ABORT_TX_AC1        FIELD32(0x00020000)
 903 #define TX_CNTL_CSR_ABORT_TX_AC2        FIELD32(0x00040000)
 904 #define TX_CNTL_CSR_ABORT_TX_AC3        FIELD32(0x00080000)
 905 #define TX_CNTL_CSR_ABORT_TX_MGMT       FIELD32(0x00100000)
 906
 907 /*
 908  * LOAD_TX_RING_CSR: Load RX desriptor
 909  */
 910 #define LOAD_TX_RING_CSR                0x3434
 911 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0   FIELD32(0x00000001)
 912 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1   FIELD32(0x00000002)
 913 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2   FIELD32(0x00000004)
 914 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3   FIELD32(0x00000008)
 915 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT  FIELD32(0x00000010)
 916
 917 /*
 918  * Several read-only registers, for debugging.
 919  */
 920 #define AC0_TXPTR_CSR                   0x3438
 921 #define AC1_TXPTR_CSR                   0x343c
 922 #define AC2_TXPTR_CSR                   0x3440
 923 #define AC3_TXPTR_CSR                   0x3444
 924 #define MGMT_TXPTR_CSR                  0x3448
 925
 926 /*
 927  * RX_BASE_CSR
 928  */
 929 #define RX_BASE_CSR                     0x3450
 930 #define RX_BASE_CSR_RING_REGISTER       FIELD32(0xffffffff)
 931
 932 /*
 933  * RX_RING_CSR.
 934  * RXD_SIZE: In unit of 32-bit.
 935  */
 936 #define RX_RING_CSR                     0x3454
 937 #define RX_RING_CSR_RING_SIZE           FIELD32(0x000000ff)
 938 #define RX_RING_CSR_RXD_SIZE            FIELD32(0x00003f00)
 939 #define RX_RING_CSR_RXD_WRITEBACK_SIZE  FIELD32(0x00070000)
 940
 941 /*
 942  * RX_CNTL_CSR
 943  */
 944 #define RX_CNTL_CSR                     0x3458
 945 #define RX_CNTL_CSR_ENABLE_RX_DMA       FIELD32(0x00000001)
 946 #define RX_CNTL_CSR_LOAD_RXD            FIELD32(0x00000002)
 947
 948 /*
 949  * RXPTR_CSR: Read-only, for debugging.
 950  */
 951 #define RXPTR_CSR                       0x345c
 952
 953 /*
 954  * PCI_CFG_CSR
 955  */
 956 #define PCI_CFG_CSR                     0x3460
 957
 958 /*
 959  * BUF_FORMAT_CSR
 960  */
 961 #define BUF_FORMAT_CSR                  0x3464
 962
 963 /*
 964  * INT_SOURCE_CSR: Interrupt source register.
 965  * Write one to clear corresponding bit.
 966  */
 967 #define INT_SOURCE_CSR                  0x3468
 968 #define INT_SOURCE_CSR_TXDONE           FIELD32(0x00000001)
 969 #define INT_SOURCE_CSR_RXDONE           FIELD32(0x00000002)
 970 #define INT_SOURCE_CSR_BEACON_DONE      FIELD32(0x00000004)
 971 #define INT_SOURCE_CSR_TX_ABORT_DONE    FIELD32(0x00000010)
 972 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00010000)
 973 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00020000)
 974 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00040000)
 975 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00080000)
 976 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00100000)
 977 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00200000)
 978
 979 /*
 980  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 981  * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
 982  */
 983 #define INT_MASK_CSR                    0x346c
 984 #define INT_MASK_CSR_TXDONE             FIELD32(0x00000001)
 985 #define INT_MASK_CSR_RXDONE             FIELD32(0x00000002)
 986 #define INT_MASK_CSR_BEACON_DONE        FIELD32(0x00000004)
 987 #define INT_MASK_CSR_TX_ABORT_DONE      FIELD32(0x00000010)
 988 #define INT_MASK_CSR_ENABLE_MITIGATION  FIELD32(0x00000080)
 989 #define INT_MASK_CSR_MITIGATION_PERIOD  FIELD32(0x0000ff00)
 990 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00010000)
 991 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00020000)
 992 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00040000)
 993 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00080000)
 994 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00100000)
 995 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00200000)
 996
 997 /*
 998  * E2PROM_CSR: EEPROM control register.
 999  * RELOAD: Write 1 to reload eeprom content.
1000  * TYPE_93C46: 1: 93c46, 0:93c66.
1001  * LOAD_STATUS: 1:loading, 0:done.
1002  */
1003 #define E2PROM_CSR                      0x3470
1004 #define E2PROM_CSR_RELOAD               FIELD32(0x00000001)
1005 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000002)
1006 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000004)
1007 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000008)
1008 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000010)
1009 #define E2PROM_CSR_TYPE_93C46           FIELD32(0x00000020)
1010 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
1011
1012 /*
1013  * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
1014  * AC0_TX_OP: For AC_BK, in unit of 32us.
1015  * AC1_TX_OP: For AC_BE, in unit of 32us.
1016  */
1017 #define AC_TXOP_CSR0                    0x3474
1018 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
1019 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
1020
1021 /*
1022  * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
1023  * AC2_TX_OP: For AC_VI, in unit of 32us.
1024  * AC3_TX_OP: For AC_VO, in unit of 32us.
1025  */
1026 #define AC_TXOP_CSR1                    0x3478
1027 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
1028 #define AC_TXOP_CSR1_AC3_TX_OP          FIELD32(0xffff0000)
1029
1030 /*
1031  * DMA_STATUS_CSR
1032  */
1033 #define DMA_STATUS_CSR                  0x3480
1034
1035 /*
1036  * TEST_MODE_CSR
1037  */
1038 #define TEST_MODE_CSR                   0x3484
1039
1040 /*
1041  * UART0_TX_CSR
1042  */
1043 #define UART0_TX_CSR                    0x3488
1044
1045 /*
1046  * UART0_RX_CSR
1047  */
1048 #define UART0_RX_CSR                    0x348c
1049
1050 /*
1051  * UART0_FRAME_CSR
1052  */
1053 #define UART0_FRAME_CSR                 0x3490
1054
1055 /*
1056  * UART0_BUFFER_CSR
1057  */
1058 #define UART0_BUFFER_CSR                0x3494
1059
1060 /*
1061  * IO_CNTL_CSR
1062  * RF_PS: Set RF interface value to power save
1063  */
1064 #define IO_CNTL_CSR                     0x3498
1065 #define IO_CNTL_CSR_RF_PS               FIELD32(0x00000004)
1066
1067 /*
1068  * UART_INT_SOURCE_CSR
1069  */
1070 #define UART_INT_SOURCE_CSR             0x34a8
1071
1072 /*
1073  * UART_INT_MASK_CSR
1074  */
1075 #define UART_INT_MASK_CSR               0x34ac
1076
1077 /*
1078  * PBF_QUEUE_CSR
1079  */
1080 #define PBF_QUEUE_CSR                   0x34b0
1081
1082 /*
1083  * Firmware DMA registers.
1084  * Firmware DMA registers are dedicated for MCU usage
1085  * and should not be touched by host driver.
1086  * Therefore we skip the definition of these registers.
1087  */
1088 #define FW_TX_BASE_CSR                  0x34c0
1089 #define FW_TX_START_CSR                 0x34c4
1090 #define FW_TX_LAST_CSR                  0x34c8
1091 #define FW_MODE_CNTL_CSR                0x34cc
1092 #define FW_TXPTR_CSR                    0x34d0
1093
1094 /*
1095  * 8051 firmware image.
1096  */
1097 #define FIRMWARE_RT2561                 "rt2561.bin"
1098 #define FIRMWARE_RT2561s                "rt2561s.bin"
1099 #define FIRMWARE_RT2661                 "rt2661.bin"
1100 #define FIRMWARE_IMAGE_BASE             0x4000
1101
1102 /*
1103  * BBP registers.
1104  * The wordsize of the BBP is 8 bits.
1105  */
1106
1107 /*
1108  * R2
1109  */
1110 #define BBP_R2_BG_MODE                  FIELD8(0x20)
1111
1112 /*
1113  * R3
1114  */
1115 #define BBP_R3_SMART_MODE               FIELD8(0x01)
1116
1117 /*
1118  * R4: RX antenna control
1119  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1120  */
1121
1122 /*
1123  * ANTENNA_CONTROL semantics (guessed):
1124  * 0x1: Software controlled antenna switching (fixed or SW diversity)
1125  * 0x2: Hardware diversity.
1126  */
1127 #define BBP_R4_RX_ANTENNA_CONTROL       FIELD8(0x03)
1128 #define BBP_R4_RX_FRAME_END             FIELD8(0x20)
1129
1130 /*
1131  * R77
1132  */
1133 #define BBP_R77_RX_ANTENNA              FIELD8(0x03)
1134
1135 /*
1136  * RF registers
1137  */
1138
1139 /*
1140  * RF 3
1141  */
1142 #define RF3_TXPOWER                     FIELD32(0x00003e00)
1143
1144 /*
1145  * RF 4
1146  */
1147 #define RF4_FREQ_OFFSET                 FIELD32(0x0003f000)
1148
1149 /*
1150  * EEPROM content.
1151  * The wordsize of the EEPROM is 16 bits.
1152  */
1153
1154 /*
1155  * HW MAC address.
1156  */
1157 #define EEPROM_MAC_ADDR_0               0x0002
1158 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
1159 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
1160 #define EEPROM_MAC_ADDR1                0x0003
1161 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
1162 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
1163 #define EEPROM_MAC_ADDR_2               0x0004
1164 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
1165 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
1166
1167 /*
1168  * EEPROM antenna.
1169  * ANTENNA_NUM: Number of antenna's.
1170  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1171  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1172  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1173  * DYN_TXAGC: Dynamic TX AGC control.
1174  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1175  * RF_TYPE: Rf_type of this adapter.
1176  */
1177 #define EEPROM_ANTENNA                  0x0010
1178 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
1179 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
1180 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
1181 #define EEPROM_ANTENNA_FRAME_TYPE       FIELD16(0x0040)
1182 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
1183 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
1184 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
1185
1186 /*
1187  * EEPROM NIC config.
1188  * ENABLE_DIVERSITY: 1:enable, 0:disable.
1189  * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1190  * CARDBUS_ACCEL: 0:enable, 1:disable.
1191  * EXTERNAL_LNA_A: External LNA enable for 5G.
1192  */
1193 #define EEPROM_NIC                      0x0011
1194 #define EEPROM_NIC_ENABLE_DIVERSITY     FIELD16(0x0001)
1195 #define EEPROM_NIC_TX_DIVERSITY         FIELD16(0x0002)
1196 #define EEPROM_NIC_RX_FIXED             FIELD16(0x0004)
1197 #define EEPROM_NIC_TX_FIXED             FIELD16(0x0008)
1198 #define EEPROM_NIC_EXTERNAL_LNA_BG      FIELD16(0x0010)
1199 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0020)
1200 #define EEPROM_NIC_EXTERNAL_LNA_A       FIELD16(0x0040)
1201
1202 /*
1203  * EEPROM geography.
1204  * GEO_A: Default geographical setting for 5GHz band
1205  * GEO: Default geographical setting.
1206  */
1207 #define EEPROM_GEOGRAPHY                0x0012
1208 #define EEPROM_GEOGRAPHY_GEO_A          FIELD16(0x00ff)
1209 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0xff00)
1210
1211 /*
1212  * EEPROM BBP.
1213  */
1214 #define EEPROM_BBP_START                0x0013
1215 #define EEPROM_BBP_SIZE                 16
1216 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
1217 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
1218
1219 /*
1220  * EEPROM TXPOWER 802.11G
1221  */
1222 #define EEPROM_TXPOWER_G_START          0x0023
1223 #define EEPROM_TXPOWER_G_SIZE           7
1224 #define EEPROM_TXPOWER_G_1              FIELD16(0x00ff)
1225 #define EEPROM_TXPOWER_G_2              FIELD16(0xff00)
1226
1227 /*
1228  * EEPROM Frequency
1229  */
1230 #define EEPROM_FREQ                     0x002f
1231 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
1232 #define EEPROM_FREQ_SEQ_MASK            FIELD16(0xff00)
1233 #define EEPROM_FREQ_SEQ                 FIELD16(0x0300)
1234
1235 /*
1236  * EEPROM LED.
1237  * POLARITY_RDY_G: Polarity RDY_G setting.
1238  * POLARITY_RDY_A: Polarity RDY_A setting.
1239  * POLARITY_ACT: Polarity ACT setting.
1240  * POLARITY_GPIO_0: Polarity GPIO0 setting.
1241  * POLARITY_GPIO_1: Polarity GPIO1 setting.
1242  * POLARITY_GPIO_2: Polarity GPIO2 setting.
1243  * POLARITY_GPIO_3: Polarity GPIO3 setting.
1244  * POLARITY_GPIO_4: Polarity GPIO4 setting.
1245  * LED_MODE: Led mode.
1246  */
1247 #define EEPROM_LED                      0x0030
1248 #define EEPROM_LED_POLARITY_RDY_G       FIELD16(0x0001)
1249 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
1250 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
1251 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
1252 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
1253 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
1254 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
1255 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
1256 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
1257
1258 /*
1259  * EEPROM TXPOWER 802.11A
1260  */
1261 #define EEPROM_TXPOWER_A_START          0x0031
1262 #define EEPROM_TXPOWER_A_SIZE           12
1263 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
1264 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
1265
1266 /*
1267  * EEPROM RSSI offset 802.11BG
1268  */
1269 #define EEPROM_RSSI_OFFSET_BG           0x004d
1270 #define EEPROM_RSSI_OFFSET_BG_1         FIELD16(0x00ff)
1271 #define EEPROM_RSSI_OFFSET_BG_2         FIELD16(0xff00)
1272
1273 /*
1274  * EEPROM RSSI offset 802.11A
1275  */
1276 #define EEPROM_RSSI_OFFSET_A            0x004e
1277 #define EEPROM_RSSI_OFFSET_A_1          FIELD16(0x00ff)
1278 #define EEPROM_RSSI_OFFSET_A_2          FIELD16(0xff00)
1279
1280 /*
1281  * MCU mailbox commands.
1282  */
1283 #define MCU_SLEEP                       0x30
1284 #define MCU_WAKEUP                      0x31
1285 #define MCU_LED                         0x50
1286 #define MCU_LED_STRENGTH                0x52
1287
1288 /*
1289  * DMA descriptor defines.
1290  */
1291 #define TXD_DESC_SIZE                   ( 16 * sizeof(__le32) )
1292 #define TXINFO_SIZE                     ( 6 * sizeof(__le32) )
1293 #define RXD_DESC_SIZE                   ( 16 * sizeof(__le32) )
1294
1295 /*
1296  * TX descriptor format for TX, PRIO and Beacon Ring.
1297  */
1298
1299 /*
1300  * Word0
1301  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1302  * KEY_TABLE: Use per-client pairwise KEY table.
1303  * KEY_INDEX:
1304  * Key index (0~31) to the pairwise KEY table.
1305  * 0~3 to shared KEY table 0 (BSS0).
1306  * 4~7 to shared KEY table 1 (BSS1).
1307  * 8~11 to shared KEY table 2 (BSS2).
1308  * 12~15 to shared KEY table 3 (BSS3).
1309  * BURST: Next frame belongs to same "burst" event.
1310  */
1311 #define TXD_W0_OWNER_NIC                FIELD32(0x00000001)
1312 #define TXD_W0_VALID                    FIELD32(0x00000002)
1313 #define TXD_W0_MORE_FRAG                FIELD32(0x00000004)
1314 #define TXD_W0_ACK                      FIELD32(0x00000008)
1315 #define TXD_W0_TIMESTAMP                FIELD32(0x00000010)
1316 #define TXD_W0_OFDM                     FIELD32(0x00000020)
1317 #define TXD_W0_IFS                      FIELD32(0x00000040)
1318 #define TXD_W0_RETRY_MODE               FIELD32(0x00000080)
1319 #define TXD_W0_TKIP_MIC                 FIELD32(0x00000100)
1320 #define TXD_W0_KEY_TABLE                FIELD32(0x00000200)
1321 #define TXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1322 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1323 #define TXD_W0_BURST                    FIELD32(0x10000000)
1324 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1325
1326 /*
1327  * Word1
1328  * HOST_Q_ID: EDCA/HCCA queue ID.
1329  * HW_SEQUENCE: MAC overwrites the frame sequence number.
1330  * BUFFER_COUNT: Number of buffers in this TXD.
1331  */
1332 #define TXD_W1_HOST_Q_ID                FIELD32(0x0000000f)
1333 #define TXD_W1_AIFSN                    FIELD32(0x000000f0)
1334 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
1335 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
1336 #define TXD_W1_IV_OFFSET                FIELD32(0x003f0000)
1337 #define TXD_W1_PIGGY_BACK               FIELD32(0x01000000)
1338 #define TXD_W1_HW_SEQUENCE              FIELD32(0x10000000)
1339 #define TXD_W1_BUFFER_COUNT             FIELD32(0xe0000000)
1340
1341 /*
1342  * Word2: PLCP information
1343  */
1344 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
1345 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
1346 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
1347 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
1348
1349 /*
1350  * Word3
1351  */
1352 #define TXD_W3_IV                       FIELD32(0xffffffff)
1353
1354 /*
1355  * Word4
1356  */
1357 #define TXD_W4_EIV                      FIELD32(0xffffffff)
1358
1359 /*
1360  * Word5
1361  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1362  * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1363  * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1364  * WAITING_DMA_DONE_INT: TXD been filled with data
1365  * and waiting for TxDoneISR housekeeping.
1366  */
1367 #define TXD_W5_FRAME_OFFSET             FIELD32(0x000000ff)
1368 #define TXD_W5_PID_SUBTYPE              FIELD32(0x00001f00)
1369 #define TXD_W5_PID_TYPE                 FIELD32(0x0000e000)
1370 #define TXD_W5_TX_POWER                 FIELD32(0x00ff0000)
1371 #define TXD_W5_WAITING_DMA_DONE_INT     FIELD32(0x01000000)
1372
1373 /*
1374  * the above 24-byte is called TXINFO and will be DMAed to MAC block
1375  * through TXFIFO. MAC block use this TXINFO to control the transmission
1376  * behavior of this frame.
1377  * The following fields are not used by MAC block.
1378  * They are used by DMA block and HOST driver only.
1379  * Once a frame has been DMA to ASIC, all the following fields are useless
1380  * to ASIC.
1381  */
1382
1383 /*
1384  * Word6-10: Buffer physical address
1385  */
1386 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1387 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1388 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1389 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1390 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1391
1392 /*
1393  * Word11-13: Buffer length
1394  */
1395 #define TXD_W11_BUFFER_LENGTH0          FIELD32(0x00000fff)
1396 #define TXD_W11_BUFFER_LENGTH1          FIELD32(0x0fff0000)
1397 #define TXD_W12_BUFFER_LENGTH2          FIELD32(0x00000fff)
1398 #define TXD_W12_BUFFER_LENGTH3          FIELD32(0x0fff0000)
1399 #define TXD_W13_BUFFER_LENGTH4          FIELD32(0x00000fff)
1400
1401 /*
1402  * Word14
1403  */
1404 #define TXD_W14_SK_BUFFER               FIELD32(0xffffffff)
1405
1406 /*
1407  * Word15
1408  */
1409 #define TXD_W15_NEXT_SK_BUFFER          FIELD32(0xffffffff)
1410
1411 /*
1412  * RX descriptor format for RX Ring.
1413  */
1414
1415 /*
1416  * Word0
1417  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1418  * KEY_INDEX: Decryption key actually used.
1419  */
1420 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
1421 #define RXD_W0_DROP                     FIELD32(0x00000002)
1422 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000004)
1423 #define RXD_W0_MULTICAST                FIELD32(0x00000008)
1424 #define RXD_W0_BROADCAST                FIELD32(0x00000010)
1425 #define RXD_W0_MY_BSS                   FIELD32(0x00000020)
1426 #define RXD_W0_CRC_ERROR                FIELD32(0x00000040)
1427 #define RXD_W0_OFDM                     FIELD32(0x00000080)
1428 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000300)
1429 #define RXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1430 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1431 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1432
1433 /*
1434  * Word1
1435  * SIGNAL: RX raw data rate reported by BBP.
1436  */
1437 #define RXD_W1_SIGNAL                   FIELD32(0x000000ff)
1438 #define RXD_W1_RSSI_AGC                 FIELD32(0x00001f00)
1439 #define RXD_W1_RSSI_LNA                 FIELD32(0x00006000)
1440 #define RXD_W1_FRAME_OFFSET             FIELD32(0x7f000000)
1441
1442 /*
1443  * Word2
1444  * IV: Received IV of originally encrypted.
1445  */
1446 #define RXD_W2_IV                       FIELD32(0xffffffff)
1447
1448 /*
1449  * Word3
1450  * EIV: Received EIV of originally encrypted.
1451  */
1452 #define RXD_W3_EIV                      FIELD32(0xffffffff)
1453
1454 /*
1455  * Word4
1456  * ICV: Received ICV of originally encrypted.
1457  * NOTE: This is a guess, the official definition is "reserved"
1458  */
1459 #define RXD_W4_ICV                      FIELD32(0xffffffff)
1460
1461 /*
1462  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1463  * and passed to the HOST driver.
1464  * The following fields are for DMA block and HOST usage only.
1465  * Can't be touched by ASIC MAC block.
1466  */
1467
1468 /*
1469  * Word5
1470  */
1471 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1472
1473 /*
1474  * Word6-15: Reserved
1475  */
1476 #define RXD_W6_RESERVED                 FIELD32(0xffffffff)
1477 #define RXD_W7_RESERVED                 FIELD32(0xffffffff)
1478 #define RXD_W8_RESERVED                 FIELD32(0xffffffff)
1479 #define RXD_W9_RESERVED                 FIELD32(0xffffffff)
1480 #define RXD_W10_RESERVED                FIELD32(0xffffffff)
1481 #define RXD_W11_RESERVED                FIELD32(0xffffffff)
1482 #define RXD_W12_RESERVED                FIELD32(0xffffffff)
1483 #define RXD_W13_RESERVED                FIELD32(0xffffffff)
1484 #define RXD_W14_RESERVED                FIELD32(0xffffffff)
1485 #define RXD_W15_RESERVED                FIELD32(0xffffffff)
1486
1487 /*
1488  * Macros for converting txpower from EEPROM to mac80211 value
1489  * and from mac80211 value to register value.
1490  */
1491 #define MIN_TXPOWER     0
1492 #define MAX_TXPOWER     31
1493 #define DEFAULT_TXPOWER 24
1494
1495 #define TXPOWER_FROM_DEV(__txpower) \
1496         (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1497
1498 #define TXPOWER_TO_DEV(__txpower) \
1499         clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1500
1501 #endif /* RT61PCI_H */