drivers/net/wireless/rt2x00/rt61pci.h

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: Data structures and registers for the rt61pci module.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #ifndef RT61PCI_H
  28 #define RT61PCI_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF5225                          0x0001
  34 #define RF5325                          0x0002
  35 #define RF2527                          0x0003
  36 #define RF2529                          0x0004
  37
  38 /*
  39  * Signal information.
  40  * Defaul offset is required for RSSI <-> dBm conversion.
  41  */
  42 #define DEFAULT_RSSI_OFFSET             120
  43
  44 /*
  45  * Register layout information.
  46  */
  47 #define CSR_REG_BASE                    0x3000
  48 #define CSR_REG_SIZE                    0x04b0
  49 #define EEPROM_BASE                     0x0000
  50 #define EEPROM_SIZE                     0x0100
  51 #define BBP_BASE                        0x0000
  52 #define BBP_SIZE                        0x0080
  53 #define RF_BASE                         0x0004
  54 #define RF_SIZE                         0x0010
  55
  56 /*
  57  * Number of TX queues.
  58  */
  59 #define NUM_TX_QUEUES                   4
  60
  61 /*
  62  * PCI registers.
  63  */
  64
  65 /*
  66  * HOST_CMD_CSR: For HOST to interrupt embedded processor
  67  */
  68 #define HOST_CMD_CSR                    0x0008
  69 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x0000007f)
  70 #define HOST_CMD_CSR_INTERRUPT_MCU      FIELD32(0x00000080)
  71
  72 /*
  73  * MCU_CNTL_CSR
  74  * SELECT_BANK: Select 8051 program bank.
  75  * RESET: Enable 8051 reset state.
  76  * READY: Ready state for 8051.
  77  */
  78 #define MCU_CNTL_CSR                    0x000c
  79 #define MCU_CNTL_CSR_SELECT_BANK        FIELD32(0x00000001)
  80 #define MCU_CNTL_CSR_RESET              FIELD32(0x00000002)
  81 #define MCU_CNTL_CSR_READY              FIELD32(0x00000004)
  82
  83 /*
  84  * SOFT_RESET_CSR
  85  * FORCE_CLOCK_ON: Host force MAC clock ON
  86  */
  87 #define SOFT_RESET_CSR                  0x0010
  88 #define SOFT_RESET_CSR_FORCE_CLOCK_ON   FIELD32(0x00000002)
  89
  90 /*
  91  * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
  92  */
  93 #define MCU_INT_SOURCE_CSR              0x0014
  94 #define MCU_INT_SOURCE_CSR_0            FIELD32(0x00000001)
  95 #define MCU_INT_SOURCE_CSR_1            FIELD32(0x00000002)
  96 #define MCU_INT_SOURCE_CSR_2            FIELD32(0x00000004)
  97 #define MCU_INT_SOURCE_CSR_3            FIELD32(0x00000008)
  98 #define MCU_INT_SOURCE_CSR_4            FIELD32(0x00000010)
  99 #define MCU_INT_SOURCE_CSR_5            FIELD32(0x00000020)
 100 #define MCU_INT_SOURCE_CSR_6            FIELD32(0x00000040)
 101 #define MCU_INT_SOURCE_CSR_7            FIELD32(0x00000080)
 102 #define MCU_INT_SOURCE_CSR_TWAKEUP      FIELD32(0x00000100)
 103 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE  FIELD32(0x00000200)
 104
 105 /*
 106  * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
 107  */
 108 #define MCU_INT_MASK_CSR                0x0018
 109 #define MCU_INT_MASK_CSR_0              FIELD32(0x00000001)
 110 #define MCU_INT_MASK_CSR_1              FIELD32(0x00000002)
 111 #define MCU_INT_MASK_CSR_2              FIELD32(0x00000004)
 112 #define MCU_INT_MASK_CSR_3              FIELD32(0x00000008)
 113 #define MCU_INT_MASK_CSR_4              FIELD32(0x00000010)
 114 #define MCU_INT_MASK_CSR_5              FIELD32(0x00000020)
 115 #define MCU_INT_MASK_CSR_6              FIELD32(0x00000040)
 116 #define MCU_INT_MASK_CSR_7              FIELD32(0x00000080)
 117 #define MCU_INT_MASK_CSR_TWAKEUP        FIELD32(0x00000100)
 118 #define MCU_INT_MASK_CSR_TBTT_EXPIRE    FIELD32(0x00000200)
 119
 120 /*
 121  * PCI_USEC_CSR
 122  */
 123 #define PCI_USEC_CSR                    0x001c
 124
 125 /*
 126  * Security key table memory.
 127  * 16 entries 32-byte for shared key table
 128  * 64 entries 32-byte for pairwise key table
 129  * 64 entries 8-byte for pairwise ta key table
 130  */
 131 #define SHARED_KEY_TABLE_BASE           0x1000
 132 #define PAIRWISE_KEY_TABLE_BASE         0x1200
 133 #define PAIRWISE_TA_TABLE_BASE          0x1a00
 134
 135 #define SHARED_KEY_ENTRY(__idx) \
 136         ( SHARED_KEY_TABLE_BASE + \
 137                 ((__idx) * sizeof(struct hw_key_entry)) )
 138 #define PAIRWISE_KEY_ENTRY(__idx) \
 139         ( PAIRWISE_KEY_TABLE_BASE + \
 140                 ((__idx) * sizeof(struct hw_key_entry)) )
 141 #define PAIRWISE_TA_ENTRY(__idx) \
 142         ( PAIRWISE_TA_TABLE_BASE + \
 143                 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
 144
 145 struct hw_key_entry {
 146         u8 key[16];
 147         u8 tx_mic[8];
 148         u8 rx_mic[8];
 149 } __attribute__ ((packed));
 150
 151 struct hw_pairwise_ta_entry {
 152         u8 address[6];
 153         u8 cipher;
 154         u8 reserved;
 155 } __attribute__ ((packed));
 156
 157 /*
 158  * Other on-chip shared memory space.
 159  */
 160 #define HW_CIS_BASE                     0x2000
 161 #define HW_NULL_BASE                    0x2b00
 162
 163 /*
 164  * Since NULL frame won't be that long (256 byte),
 165  * We steal 16 tail bytes to save debugging settings.
 166  */
 167 #define HW_DEBUG_SETTING_BASE           0x2bf0
 168
 169 /*
 170  * On-chip BEACON frame space.
 171  */
 172 #define HW_BEACON_BASE0                 0x2c00
 173 #define HW_BEACON_BASE1                 0x2d00
 174 #define HW_BEACON_BASE2                 0x2e00
 175 #define HW_BEACON_BASE3                 0x2f00
 176
 177 #define HW_BEACON_OFFSET(__index) \
 178         ( HW_BEACON_BASE0 + (__index * 0x0100) )
 179
 180 /*
 181  * HOST-MCU shared memory.
 182  */
 183
 184 /*
 185  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
 186  */
 187 #define H2M_MAILBOX_CSR                 0x2100
 188 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
 189 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
 190 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
 191 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
 192
 193 /*
 194  * MCU_LEDCS: LED control for MCU Mailbox.
 195  */
 196 #define MCU_LEDCS_LED_MODE              FIELD16(0x001f)
 197 #define MCU_LEDCS_RADIO_STATUS          FIELD16(0x0020)
 198 #define MCU_LEDCS_LINK_BG_STATUS        FIELD16(0x0040)
 199 #define MCU_LEDCS_LINK_A_STATUS         FIELD16(0x0080)
 200 #define MCU_LEDCS_POLARITY_GPIO_0       FIELD16(0x0100)
 201 #define MCU_LEDCS_POLARITY_GPIO_1       FIELD16(0x0200)
 202 #define MCU_LEDCS_POLARITY_GPIO_2       FIELD16(0x0400)
 203 #define MCU_LEDCS_POLARITY_GPIO_3       FIELD16(0x0800)
 204 #define MCU_LEDCS_POLARITY_GPIO_4       FIELD16(0x1000)
 205 #define MCU_LEDCS_POLARITY_ACT          FIELD16(0x2000)
 206 #define MCU_LEDCS_POLARITY_READY_BG     FIELD16(0x4000)
 207 #define MCU_LEDCS_POLARITY_READY_A      FIELD16(0x8000)
 208
 209 /*
 210  * M2H_CMD_DONE_CSR.
 211  */
 212 #define M2H_CMD_DONE_CSR                0x2104
 213
 214 /*
 215  * MCU_TXOP_ARRAY_BASE.
 216  */
 217 #define MCU_TXOP_ARRAY_BASE             0x2110
 218
 219 /*
 220  * MAC Control/Status Registers(CSR).
 221  * Some values are set in TU, whereas 1 TU == 1024 us.
 222  */
 223
 224 /*
 225  * MAC_CSR0: ASIC revision number.
 226  */
 227 #define MAC_CSR0                        0x3000
 228
 229 /*
 230  * MAC_CSR1: System control register.
 231  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
 232  * BBP_RESET: Hardware reset BBP.
 233  * HOST_READY: Host is ready after initialization, 1: ready.
 234  */
 235 #define MAC_CSR1                        0x3004
 236 #define MAC_CSR1_SOFT_RESET             FIELD32(0x00000001)
 237 #define MAC_CSR1_BBP_RESET              FIELD32(0x00000002)
 238 #define MAC_CSR1_HOST_READY             FIELD32(0x00000004)
 239
 240 /*
 241  * MAC_CSR2: STA MAC register 0.
 242  */
 243 #define MAC_CSR2                        0x3008
 244 #define MAC_CSR2_BYTE0                  FIELD32(0x000000ff)
 245 #define MAC_CSR2_BYTE1                  FIELD32(0x0000ff00)
 246 #define MAC_CSR2_BYTE2                  FIELD32(0x00ff0000)
 247 #define MAC_CSR2_BYTE3                  FIELD32(0xff000000)
 248
 249 /*
 250  * MAC_CSR3: STA MAC register 1.
 251  * UNICAST_TO_ME_MASK:
 252  *      Used to mask off bits from byte 5 of the MAC address
 253  *      to determine the UNICAST_TO_ME bit for RX frames.
 254  *      The full mask is complemented by BSS_ID_MASK:
 255  *              MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 256  */
 257 #define MAC_CSR3                        0x300c
 258 #define MAC_CSR3_BYTE4                  FIELD32(0x000000ff)
 259 #define MAC_CSR3_BYTE5                  FIELD32(0x0000ff00)
 260 #define MAC_CSR3_UNICAST_TO_ME_MASK     FIELD32(0x00ff0000)
 261
 262 /*
 263  * MAC_CSR4: BSSID register 0.
 264  */
 265 #define MAC_CSR4                        0x3010
 266 #define MAC_CSR4_BYTE0                  FIELD32(0x000000ff)
 267 #define MAC_CSR4_BYTE1                  FIELD32(0x0000ff00)
 268 #define MAC_CSR4_BYTE2                  FIELD32(0x00ff0000)
 269 #define MAC_CSR4_BYTE3                  FIELD32(0xff000000)
 270
 271 /*
 272  * MAC_CSR5: BSSID register 1.
 273  * BSS_ID_MASK:
 274  *      This mask is used to mask off bits 0 and 1 of byte 5 of the
 275  *      BSSID. This will make sure that those bits will be ignored
 276  *      when determining the MY_BSS of RX frames.
 277  *              0: 1-BSSID mode (BSS index = 0)
 278  *              1: 2-BSSID mode (BSS index: Byte5, bit 0)
 279  *              2: 2-BSSID mode (BSS index: byte5, bit 1)
 280  *              3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 281  */
 282 #define MAC_CSR5                        0x3014
 283 #define MAC_CSR5_BYTE4                  FIELD32(0x000000ff)
 284 #define MAC_CSR5_BYTE5                  FIELD32(0x0000ff00)
 285 #define MAC_CSR5_BSS_ID_MASK            FIELD32(0x00ff0000)
 286
 287 /*
 288  * MAC_CSR6: Maximum frame length register.
 289  */
 290 #define MAC_CSR6                        0x3018
 291 #define MAC_CSR6_MAX_FRAME_UNIT         FIELD32(0x00000fff)
 292
 293 /*
 294  * MAC_CSR7: Reserved
 295  */
 296 #define MAC_CSR7                        0x301c
 297
 298 /*
 299  * MAC_CSR8: SIFS/EIFS register.
 300  * All units are in US.
 301  */
 302 #define MAC_CSR8                        0x3020
 303 #define MAC_CSR8_SIFS                   FIELD32(0x000000ff)
 304 #define MAC_CSR8_SIFS_AFTER_RX_OFDM     FIELD32(0x0000ff00)
 305 #define MAC_CSR8_EIFS                   FIELD32(0xffff0000)
 306
 307 /*
 308  * MAC_CSR9: Back-Off control register.
 309  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
 310  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
 311  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
 312  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
 313  */
 314 #define MAC_CSR9                        0x3024
 315 #define MAC_CSR9_SLOT_TIME              FIELD32(0x000000ff)
 316 #define MAC_CSR9_CWMIN                  FIELD32(0x00000f00)
 317 #define MAC_CSR9_CWMAX                  FIELD32(0x0000f000)
 318 #define MAC_CSR9_CW_SELECT              FIELD32(0x00010000)
 319
 320 /*
 321  * MAC_CSR10: Power state configuration.
 322  */
 323 #define MAC_CSR10                       0x3028
 324
 325 /*
 326  * MAC_CSR11: Power saving transition time register.
 327  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
 328  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 329  * WAKEUP_LATENCY: In unit of TU.
 330  */
 331 #define MAC_CSR11                       0x302c
 332 #define MAC_CSR11_DELAY_AFTER_TBCN      FIELD32(0x000000ff)
 333 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
 334 #define MAC_CSR11_AUTOWAKE              FIELD32(0x00008000)
 335 #define MAC_CSR11_WAKEUP_LATENCY        FIELD32(0x000f0000)
 336
 337 /*
 338  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
 339  * CURRENT_STATE: 0:sleep, 1:awake.
 340  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
 341  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
 342  */
 343 #define MAC_CSR12                       0x3030
 344 #define MAC_CSR12_CURRENT_STATE         FIELD32(0x00000001)
 345 #define MAC_CSR12_PUT_TO_SLEEP          FIELD32(0x00000002)
 346 #define MAC_CSR12_FORCE_WAKEUP          FIELD32(0x00000004)
 347 #define MAC_CSR12_BBP_CURRENT_STATE     FIELD32(0x00000008)
 348
 349 /*
 350  * MAC_CSR13: GPIO.
 351  */
 352 #define MAC_CSR13                       0x3034
 353 #define MAC_CSR13_BIT0                  FIELD32(0x00000001)
 354 #define MAC_CSR13_BIT1                  FIELD32(0x00000002)
 355 #define MAC_CSR13_BIT2                  FIELD32(0x00000004)
 356 #define MAC_CSR13_BIT3                  FIELD32(0x00000008)
 357 #define MAC_CSR13_BIT4                  FIELD32(0x00000010)
 358 #define MAC_CSR13_BIT5                  FIELD32(0x00000020)
 359 #define MAC_CSR13_BIT6                  FIELD32(0x00000040)
 360 #define MAC_CSR13_BIT7                  FIELD32(0x00000080)
 361 #define MAC_CSR13_BIT8                  FIELD32(0x00000100)
 362 #define MAC_CSR13_BIT9                  FIELD32(0x00000200)
 363 #define MAC_CSR13_BIT10                 FIELD32(0x00000400)
 364 #define MAC_CSR13_BIT11                 FIELD32(0x00000800)
 365 #define MAC_CSR13_BIT12                 FIELD32(0x00001000)
 366
 367 /*
 368  * MAC_CSR14: LED control register.
 369  * ON_PERIOD: On period, default 70ms.
 370  * OFF_PERIOD: Off period, default 30ms.
 371  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
 372  * SW_LED: s/w LED, 1: ON, 0: OFF.
 373  * HW_LED_POLARITY: 0: active low, 1: active high.
 374  */
 375 #define MAC_CSR14                       0x3038
 376 #define MAC_CSR14_ON_PERIOD             FIELD32(0x000000ff)
 377 #define MAC_CSR14_OFF_PERIOD            FIELD32(0x0000ff00)
 378 #define MAC_CSR14_HW_LED                FIELD32(0x00010000)
 379 #define MAC_CSR14_SW_LED                FIELD32(0x00020000)
 380 #define MAC_CSR14_HW_LED_POLARITY       FIELD32(0x00040000)
 381 #define MAC_CSR14_SW_LED2               FIELD32(0x00080000)
 382
 383 /*
 384  * MAC_CSR15: NAV control.
 385  */
 386 #define MAC_CSR15                       0x303c
 387
 388 /*
 389  * TXRX control registers.
 390  * Some values are set in TU, whereas 1 TU == 1024 us.
 391  */
 392
 393 /*
 394  * TXRX_CSR0: TX/RX configuration register.
 395  * TSF_OFFSET: Default is 24.
 396  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
 397  * DISABLE_RX: Disable Rx engine.
 398  * DROP_CRC: Drop CRC error.
 399  * DROP_PHYSICAL: Drop physical error.
 400  * DROP_CONTROL: Drop control frame.
 401  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 402  * DROP_TO_DS: Drop fram ToDs bit is true.
 403  * DROP_VERSION_ERROR: Drop version error frame.
 404  * DROP_MULTICAST: Drop multicast frames.
 405  * DROP_BORADCAST: Drop broadcast frames.
 406  * ROP_ACK_CTS: Drop received ACK and CTS.
 407  */
 408 #define TXRX_CSR0                       0x3040
 409 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
 410 #define TXRX_CSR0_TSF_OFFSET            FIELD32(0x00007e00)
 411 #define TXRX_CSR0_AUTO_TX_SEQ           FIELD32(0x00008000)
 412 #define TXRX_CSR0_DISABLE_RX            FIELD32(0x00010000)
 413 #define TXRX_CSR0_DROP_CRC              FIELD32(0x00020000)
 414 #define TXRX_CSR0_DROP_PHYSICAL         FIELD32(0x00040000)
 415 #define TXRX_CSR0_DROP_CONTROL          FIELD32(0x00080000)
 416 #define TXRX_CSR0_DROP_NOT_TO_ME        FIELD32(0x00100000)
 417 #define TXRX_CSR0_DROP_TO_DS            FIELD32(0x00200000)
 418 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
 419 #define TXRX_CSR0_DROP_MULTICAST        FIELD32(0x00800000)
 420 #define TXRX_CSR0_DROP_BROADCAST        FIELD32(0x01000000)
 421 #define TXRX_CSR0_DROP_ACK_CTS          FIELD32(0x02000000)
 422 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
 423
 424 /*
 425  * TXRX_CSR1
 426  */
 427 #define TXRX_CSR1                       0x3044
 428 #define TXRX_CSR1_BBP_ID0               FIELD32(0x0000007f)
 429 #define TXRX_CSR1_BBP_ID0_VALID         FIELD32(0x00000080)
 430 #define TXRX_CSR1_BBP_ID1               FIELD32(0x00007f00)
 431 #define TXRX_CSR1_BBP_ID1_VALID         FIELD32(0x00008000)
 432 #define TXRX_CSR1_BBP_ID2               FIELD32(0x007f0000)
 433 #define TXRX_CSR1_BBP_ID2_VALID         FIELD32(0x00800000)
 434 #define TXRX_CSR1_BBP_ID3               FIELD32(0x7f000000)
 435 #define TXRX_CSR1_BBP_ID3_VALID         FIELD32(0x80000000)
 436
 437 /*
 438  * TXRX_CSR2
 439  */
 440 #define TXRX_CSR2                       0x3048
 441 #define TXRX_CSR2_BBP_ID0               FIELD32(0x0000007f)
 442 #define TXRX_CSR2_BBP_ID0_VALID         FIELD32(0x00000080)
 443 #define TXRX_CSR2_BBP_ID1               FIELD32(0x00007f00)
 444 #define TXRX_CSR2_BBP_ID1_VALID         FIELD32(0x00008000)
 445 #define TXRX_CSR2_BBP_ID2               FIELD32(0x007f0000)
 446 #define TXRX_CSR2_BBP_ID2_VALID         FIELD32(0x00800000)
 447 #define TXRX_CSR2_BBP_ID3               FIELD32(0x7f000000)
 448 #define TXRX_CSR2_BBP_ID3_VALID         FIELD32(0x80000000)
 449
 450 /*
 451  * TXRX_CSR3
 452  */
 453 #define TXRX_CSR3                       0x304c
 454 #define TXRX_CSR3_BBP_ID0               FIELD32(0x0000007f)
 455 #define TXRX_CSR3_BBP_ID0_VALID         FIELD32(0x00000080)
 456 #define TXRX_CSR3_BBP_ID1               FIELD32(0x00007f00)
 457 #define TXRX_CSR3_BBP_ID1_VALID         FIELD32(0x00008000)
 458 #define TXRX_CSR3_BBP_ID2               FIELD32(0x007f0000)
 459 #define TXRX_CSR3_BBP_ID2_VALID         FIELD32(0x00800000)
 460 #define TXRX_CSR3_BBP_ID3               FIELD32(0x7f000000)
 461 #define TXRX_CSR3_BBP_ID3_VALID         FIELD32(0x80000000)
 462
 463 /*
 464  * TXRX_CSR4: Auto-Responder/Tx-retry register.
 465  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
 466  * OFDM_TX_RATE_DOWN: 1:enable.
 467  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
 468  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
 469  */
 470 #define TXRX_CSR4                       0x3050
 471 #define TXRX_CSR4_TX_ACK_TIMEOUT        FIELD32(0x000000ff)
 472 #define TXRX_CSR4_CNTL_ACK_POLICY       FIELD32(0x00000700)
 473 #define TXRX_CSR4_ACK_CTS_PSM           FIELD32(0x00010000)
 474 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
 475 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
 476 #define TXRX_CSR4_OFDM_TX_RATE_DOWN     FIELD32(0x00080000)
 477 #define TXRX_CSR4_OFDM_TX_RATE_STEP     FIELD32(0x00300000)
 478 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
 479 #define TXRX_CSR4_LONG_RETRY_LIMIT      FIELD32(0x0f000000)
 480 #define TXRX_CSR4_SHORT_RETRY_LIMIT     FIELD32(0xf0000000)
 481
 482 /*
 483  * TXRX_CSR5
 484  */
 485 #define TXRX_CSR5                       0x3054
 486
 487 /*
 488  * TXRX_CSR6: ACK/CTS payload consumed time
 489  */
 490 #define TXRX_CSR6                       0x3058
 491
 492 /*
 493  * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
 494  */
 495 #define TXRX_CSR7                       0x305c
 496 #define TXRX_CSR7_ACK_CTS_6MBS          FIELD32(0x000000ff)
 497 #define TXRX_CSR7_ACK_CTS_9MBS          FIELD32(0x0000ff00)
 498 #define TXRX_CSR7_ACK_CTS_12MBS         FIELD32(0x00ff0000)
 499 #define TXRX_CSR7_ACK_CTS_18MBS         FIELD32(0xff000000)
 500
 501 /*
 502  * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
 503  */
 504 #define TXRX_CSR8                       0x3060
 505 #define TXRX_CSR8_ACK_CTS_24MBS         FIELD32(0x000000ff)
 506 #define TXRX_CSR8_ACK_CTS_36MBS         FIELD32(0x0000ff00)
 507 #define TXRX_CSR8_ACK_CTS_48MBS         FIELD32(0x00ff0000)
 508 #define TXRX_CSR8_ACK_CTS_54MBS         FIELD32(0xff000000)
 509
 510 /*
 511  * TXRX_CSR9: Synchronization control register.
 512  * BEACON_INTERVAL: In unit of 1/16 TU.
 513  * TSF_TICKING: Enable TSF auto counting.
 514  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 515  * BEACON_GEN: Enable beacon generator.
 516  */
 517 #define TXRX_CSR9                       0x3064
 518 #define TXRX_CSR9_BEACON_INTERVAL       FIELD32(0x0000ffff)
 519 #define TXRX_CSR9_TSF_TICKING           FIELD32(0x00010000)
 520 #define TXRX_CSR9_TSF_SYNC              FIELD32(0x00060000)
 521 #define TXRX_CSR9_TBTT_ENABLE           FIELD32(0x00080000)
 522 #define TXRX_CSR9_BEACON_GEN            FIELD32(0x00100000)
 523 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
 524
 525 /*
 526  * TXRX_CSR10: BEACON alignment.
 527  */
 528 #define TXRX_CSR10                      0x3068
 529
 530 /*
 531  * TXRX_CSR11: AES mask.
 532  */
 533 #define TXRX_CSR11                      0x306c
 534
 535 /*
 536  * TXRX_CSR12: TSF low 32.
 537  */
 538 #define TXRX_CSR12                      0x3070
 539 #define TXRX_CSR12_LOW_TSFTIMER         FIELD32(0xffffffff)
 540
 541 /*
 542  * TXRX_CSR13: TSF high 32.
 543  */
 544 #define TXRX_CSR13                      0x3074
 545 #define TXRX_CSR13_HIGH_TSFTIMER        FIELD32(0xffffffff)
 546
 547 /*
 548  * TXRX_CSR14: TBTT timer.
 549  */
 550 #define TXRX_CSR14                      0x3078
 551
 552 /*
 553  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
 554  */
 555 #define TXRX_CSR15                      0x307c
 556
 557 /*
 558  * PHY control registers.
 559  * Some values are set in TU, whereas 1 TU == 1024 us.
 560  */
 561
 562 /*
 563  * PHY_CSR0: RF/PS control.
 564  */
 565 #define PHY_CSR0                        0x3080
 566 #define PHY_CSR0_PA_PE_BG               FIELD32(0x00010000)
 567 #define PHY_CSR0_PA_PE_A                FIELD32(0x00020000)
 568
 569 /*
 570  * PHY_CSR1
 571  */
 572 #define PHY_CSR1                        0x3084
 573
 574 /*
 575  * PHY_CSR2: Pre-TX BBP control.
 576  */
 577 #define PHY_CSR2                        0x3088
 578
 579 /*
 580  * PHY_CSR3: BBP serial control register.
 581  * VALUE: Register value to program into BBP.
 582  * REG_NUM: Selected BBP register.
 583  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
 584  * BUSY: 1: ASIC is busy execute BBP programming.
 585  */
 586 #define PHY_CSR3                        0x308c
 587 #define PHY_CSR3_VALUE                  FIELD32(0x000000ff)
 588 #define PHY_CSR3_REGNUM                 FIELD32(0x00007f00)
 589 #define PHY_CSR3_READ_CONTROL           FIELD32(0x00008000)
 590 #define PHY_CSR3_BUSY                   FIELD32(0x00010000)
 591
 592 /*
 593  * PHY_CSR4: RF serial control register
 594  * VALUE: Register value (include register id) serial out to RF/IF chip.
 595  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
 596  * IF_SELECT: 1: select IF to program, 0: select RF to program.
 597  * PLL_LD: RF PLL_LD status.
 598  * BUSY: 1: ASIC is busy execute RF programming.
 599  */
 600 #define PHY_CSR4                        0x3090
 601 #define PHY_CSR4_VALUE                  FIELD32(0x00ffffff)
 602 #define PHY_CSR4_NUMBER_OF_BITS         FIELD32(0x1f000000)
 603 #define PHY_CSR4_IF_SELECT              FIELD32(0x20000000)
 604 #define PHY_CSR4_PLL_LD                 FIELD32(0x40000000)
 605 #define PHY_CSR4_BUSY                   FIELD32(0x80000000)
 606
 607 /*
 608  * PHY_CSR5: RX to TX signal switch timing control.
 609  */
 610 #define PHY_CSR5                        0x3094
 611 #define PHY_CSR5_IQ_FLIP                FIELD32(0x00000004)
 612
 613 /*
 614  * PHY_CSR6: TX to RX signal timing control.
 615  */
 616 #define PHY_CSR6                        0x3098
 617 #define PHY_CSR6_IQ_FLIP                FIELD32(0x00000004)
 618
 619 /*
 620  * PHY_CSR7: TX DAC switching timing control.
 621  */
 622 #define PHY_CSR7                        0x309c
 623
 624 /*
 625  * Security control register.
 626  */
 627
 628 /*
 629  * SEC_CSR0: Shared key table control.
 630  */
 631 #define SEC_CSR0                        0x30a0
 632 #define SEC_CSR0_BSS0_KEY0_VALID        FIELD32(0x00000001)
 633 #define SEC_CSR0_BSS0_KEY1_VALID        FIELD32(0x00000002)
 634 #define SEC_CSR0_BSS0_KEY2_VALID        FIELD32(0x00000004)
 635 #define SEC_CSR0_BSS0_KEY3_VALID        FIELD32(0x00000008)
 636 #define SEC_CSR0_BSS1_KEY0_VALID        FIELD32(0x00000010)
 637 #define SEC_CSR0_BSS1_KEY1_VALID        FIELD32(0x00000020)
 638 #define SEC_CSR0_BSS1_KEY2_VALID        FIELD32(0x00000040)
 639 #define SEC_CSR0_BSS1_KEY3_VALID        FIELD32(0x00000080)
 640 #define SEC_CSR0_BSS2_KEY0_VALID        FIELD32(0x00000100)
 641 #define SEC_CSR0_BSS2_KEY1_VALID        FIELD32(0x00000200)
 642 #define SEC_CSR0_BSS2_KEY2_VALID        FIELD32(0x00000400)
 643 #define SEC_CSR0_BSS2_KEY3_VALID        FIELD32(0x00000800)
 644 #define SEC_CSR0_BSS3_KEY0_VALID        FIELD32(0x00001000)
 645 #define SEC_CSR0_BSS3_KEY1_VALID        FIELD32(0x00002000)
 646 #define SEC_CSR0_BSS3_KEY2_VALID        FIELD32(0x00004000)
 647 #define SEC_CSR0_BSS3_KEY3_VALID        FIELD32(0x00008000)
 648
 649 /*
 650  * SEC_CSR1: Shared key table security mode register.
 651  */
 652 #define SEC_CSR1                        0x30a4
 653 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 654 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 655 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 656 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 657 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 658 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 659 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 660 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 661
 662 /*
 663  * Pairwise key table valid bitmap registers.
 664  * SEC_CSR2: pairwise key table valid bitmap 0.
 665  * SEC_CSR3: pairwise key table valid bitmap 1.
 666  */
 667 #define SEC_CSR2                        0x30a8
 668 #define SEC_CSR3                        0x30ac
 669
 670 /*
 671  * SEC_CSR4: Pairwise key table lookup control.
 672  */
 673 #define SEC_CSR4                        0x30b0
 674 #define SEC_CSR4_ENABLE_BSS0            FIELD32(0x00000001)
 675 #define SEC_CSR4_ENABLE_BSS1            FIELD32(0x00000002)
 676 #define SEC_CSR4_ENABLE_BSS2            FIELD32(0x00000004)
 677 #define SEC_CSR4_ENABLE_BSS3            FIELD32(0x00000008)
 678
 679 /*
 680  * SEC_CSR5: shared key table security mode register.
 681  */
 682 #define SEC_CSR5                        0x30b4
 683 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 684 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 685 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 686 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 687 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 688 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 689 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 690 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 691
 692 /*
 693  * STA control registers.
 694  */
 695
 696 /*
 697  * STA_CSR0: RX PLCP error count & RX FCS error count.
 698  */
 699 #define STA_CSR0                        0x30c0
 700 #define STA_CSR0_FCS_ERROR              FIELD32(0x0000ffff)
 701 #define STA_CSR0_PLCP_ERROR             FIELD32(0xffff0000)
 702
 703 /*
 704  * STA_CSR1: RX False CCA count & RX LONG frame count.
 705  */
 706 #define STA_CSR1                        0x30c4
 707 #define STA_CSR1_PHYSICAL_ERROR         FIELD32(0x0000ffff)
 708 #define STA_CSR1_FALSE_CCA_ERROR        FIELD32(0xffff0000)
 709
 710 /*
 711  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
 712  */
 713 #define STA_CSR2                        0x30c8
 714 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
 715 #define STA_CSR2_RX_OVERFLOW_COUNT      FIELD32(0xffff0000)
 716
 717 /*
 718  * STA_CSR3: TX Beacon count.
 719  */
 720 #define STA_CSR3                        0x30cc
 721 #define STA_CSR3_TX_BEACON_COUNT        FIELD32(0x0000ffff)
 722
 723 /*
 724  * STA_CSR4: TX Result status register.
 725  * VALID: 1:This register contains a valid TX result.
 726  */
 727 #define STA_CSR4                        0x30d0
 728 #define STA_CSR4_VALID                  FIELD32(0x00000001)
 729 #define STA_CSR4_TX_RESULT              FIELD32(0x0000000e)
 730 #define STA_CSR4_RETRY_COUNT            FIELD32(0x000000f0)
 731 #define STA_CSR4_PID_SUBTYPE            FIELD32(0x00001f00)
 732 #define STA_CSR4_PID_TYPE               FIELD32(0x0000e000)
 733 #define STA_CSR4_TXRATE                 FIELD32(0x000f0000)
 734
 735 /*
 736  * QOS control registers.
 737  */
 738
 739 /*
 740  * QOS_CSR0: TXOP holder MAC address register.
 741  */
 742 #define QOS_CSR0                        0x30e0
 743 #define QOS_CSR0_BYTE0                  FIELD32(0x000000ff)
 744 #define QOS_CSR0_BYTE1                  FIELD32(0x0000ff00)
 745 #define QOS_CSR0_BYTE2                  FIELD32(0x00ff0000)
 746 #define QOS_CSR0_BYTE3                  FIELD32(0xff000000)
 747
 748 /*
 749  * QOS_CSR1: TXOP holder MAC address register.
 750  */
 751 #define QOS_CSR1                        0x30e4
 752 #define QOS_CSR1_BYTE4                  FIELD32(0x000000ff)
 753 #define QOS_CSR1_BYTE5                  FIELD32(0x0000ff00)
 754
 755 /*
 756  * QOS_CSR2: TXOP holder timeout register.
 757  */
 758 #define QOS_CSR2                        0x30e8
 759
 760 /*
 761  * RX QOS-CFPOLL MAC address register.
 762  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
 763  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
 764  */
 765 #define QOS_CSR3                        0x30ec
 766 #define QOS_CSR4                        0x30f0
 767
 768 /*
 769  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
 770  */
 771 #define QOS_CSR5                        0x30f4
 772
 773 /*
 774  * Host DMA registers.
 775  */
 776
 777 /*
 778  * AC0_BASE_CSR: AC_BK base address.
 779  */
 780 #define AC0_BASE_CSR                    0x3400
 781 #define AC0_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 782
 783 /*
 784  * AC1_BASE_CSR: AC_BE base address.
 785  */
 786 #define AC1_BASE_CSR                    0x3404
 787 #define AC1_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 788
 789 /*
 790  * AC2_BASE_CSR: AC_VI base address.
 791  */
 792 #define AC2_BASE_CSR                    0x3408
 793 #define AC2_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 794
 795 /*
 796  * AC3_BASE_CSR: AC_VO base address.
 797  */
 798 #define AC3_BASE_CSR                    0x340c
 799 #define AC3_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 800
 801 /*
 802  * MGMT_BASE_CSR: MGMT ring base address.
 803  */
 804 #define MGMT_BASE_CSR                   0x3410
 805 #define MGMT_BASE_CSR_RING_REGISTER     FIELD32(0xffffffff)
 806
 807 /*
 808  * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
 809  */
 810 #define TX_RING_CSR0                    0x3418
 811 #define TX_RING_CSR0_AC0_RING_SIZE      FIELD32(0x000000ff)
 812 #define TX_RING_CSR0_AC1_RING_SIZE      FIELD32(0x0000ff00)
 813 #define TX_RING_CSR0_AC2_RING_SIZE      FIELD32(0x00ff0000)
 814 #define TX_RING_CSR0_AC3_RING_SIZE      FIELD32(0xff000000)
 815
 816 /*
 817  * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
 818  * TXD_SIZE: In unit of 32-bit.
 819  */
 820 #define TX_RING_CSR1                    0x341c
 821 #define TX_RING_CSR1_MGMT_RING_SIZE     FIELD32(0x000000ff)
 822 #define TX_RING_CSR1_HCCA_RING_SIZE     FIELD32(0x0000ff00)
 823 #define TX_RING_CSR1_TXD_SIZE           FIELD32(0x003f0000)
 824
 825 /*
 826  * AIFSN_CSR: AIFSN for each EDCA AC.
 827  * AIFSN0: For AC_BK.
 828  * AIFSN1: For AC_BE.
 829  * AIFSN2: For AC_VI.
 830  * AIFSN3: For AC_VO.
 831  */
 832 #define AIFSN_CSR                       0x3420
 833 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
 834 #define AIFSN_CSR_AIFSN1                FIELD32(0x000000f0)
 835 #define AIFSN_CSR_AIFSN2                FIELD32(0x00000f00)
 836 #define AIFSN_CSR_AIFSN3                FIELD32(0x0000f000)
 837
 838 /*
 839  * CWMIN_CSR: CWmin for each EDCA AC.
 840  * CWMIN0: For AC_BK.
 841  * CWMIN1: For AC_BE.
 842  * CWMIN2: For AC_VI.
 843  * CWMIN3: For AC_VO.
 844  */
 845 #define CWMIN_CSR                       0x3424
 846 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
 847 #define CWMIN_CSR_CWMIN1                FIELD32(0x000000f0)
 848 #define CWMIN_CSR_CWMIN2                FIELD32(0x00000f00)
 849 #define CWMIN_CSR_CWMIN3                FIELD32(0x0000f000)
 850
 851 /*
 852  * CWMAX_CSR: CWmax for each EDCA AC.
 853  * CWMAX0: For AC_BK.
 854  * CWMAX1: For AC_BE.
 855  * CWMAX2: For AC_VI.
 856  * CWMAX3: For AC_VO.
 857  */
 858 #define CWMAX_CSR                       0x3428
 859 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
 860 #define CWMAX_CSR_CWMAX1                FIELD32(0x000000f0)
 861 #define CWMAX_CSR_CWMAX2                FIELD32(0x00000f00)
 862 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 863
 864 /*
 865  * TX_DMA_DST_CSR: TX DMA destination
 866  * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
 867  */
 868 #define TX_DMA_DST_CSR                  0x342c
 869 #define TX_DMA_DST_CSR_DEST_AC0         FIELD32(0x00000003)
 870 #define TX_DMA_DST_CSR_DEST_AC1         FIELD32(0x0000000c)
 871 #define TX_DMA_DST_CSR_DEST_AC2         FIELD32(0x00000030)
 872 #define TX_DMA_DST_CSR_DEST_AC3         FIELD32(0x000000c0)
 873 #define TX_DMA_DST_CSR_DEST_MGMT        FIELD32(0x00000300)
 874
 875 /*
 876  * TX_CNTL_CSR: KICK/Abort TX.
 877  * KICK_TX_AC0: For AC_BK.
 878  * KICK_TX_AC1: For AC_BE.
 879  * KICK_TX_AC2: For AC_VI.
 880  * KICK_TX_AC3: For AC_VO.
 881  * ABORT_TX_AC0: For AC_BK.
 882  * ABORT_TX_AC1: For AC_BE.
 883  * ABORT_TX_AC2: For AC_VI.
 884  * ABORT_TX_AC3: For AC_VO.
 885  */
 886 #define TX_CNTL_CSR                     0x3430
 887 #define TX_CNTL_CSR_KICK_TX_AC0         FIELD32(0x00000001)
 888 #define TX_CNTL_CSR_KICK_TX_AC1         FIELD32(0x00000002)
 889 #define TX_CNTL_CSR_KICK_TX_AC2         FIELD32(0x00000004)
 890 #define TX_CNTL_CSR_KICK_TX_AC3         FIELD32(0x00000008)
 891 #define TX_CNTL_CSR_KICK_TX_MGMT        FIELD32(0x00000010)
 892 #define TX_CNTL_CSR_ABORT_TX_AC0        FIELD32(0x00010000)
 893 #define TX_CNTL_CSR_ABORT_TX_AC1        FIELD32(0x00020000)
 894 #define TX_CNTL_CSR_ABORT_TX_AC2        FIELD32(0x00040000)
 895 #define TX_CNTL_CSR_ABORT_TX_AC3        FIELD32(0x00080000)
 896 #define TX_CNTL_CSR_ABORT_TX_MGMT       FIELD32(0x00100000)
 897
 898 /*
 899  * LOAD_TX_RING_CSR: Load RX desriptor
 900  */
 901 #define LOAD_TX_RING_CSR                0x3434
 902 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0   FIELD32(0x00000001)
 903 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1   FIELD32(0x00000002)
 904 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2   FIELD32(0x00000004)
 905 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3   FIELD32(0x00000008)
 906 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT  FIELD32(0x00000010)
 907
 908 /*
 909  * Several read-only registers, for debugging.
 910  */
 911 #define AC0_TXPTR_CSR                   0x3438
 912 #define AC1_TXPTR_CSR                   0x343c
 913 #define AC2_TXPTR_CSR                   0x3440
 914 #define AC3_TXPTR_CSR                   0x3444
 915 #define MGMT_TXPTR_CSR                  0x3448
 916
 917 /*
 918  * RX_BASE_CSR
 919  */
 920 #define RX_BASE_CSR                     0x3450
 921 #define RX_BASE_CSR_RING_REGISTER       FIELD32(0xffffffff)
 922
 923 /*
 924  * RX_RING_CSR.
 925  * RXD_SIZE: In unit of 32-bit.
 926  */
 927 #define RX_RING_CSR                     0x3454
 928 #define RX_RING_CSR_RING_SIZE           FIELD32(0x000000ff)
 929 #define RX_RING_CSR_RXD_SIZE            FIELD32(0x00003f00)
 930 #define RX_RING_CSR_RXD_WRITEBACK_SIZE  FIELD32(0x00070000)
 931
 932 /*
 933  * RX_CNTL_CSR
 934  */
 935 #define RX_CNTL_CSR                     0x3458
 936 #define RX_CNTL_CSR_ENABLE_RX_DMA       FIELD32(0x00000001)
 937 #define RX_CNTL_CSR_LOAD_RXD            FIELD32(0x00000002)
 938
 939 /*
 940  * RXPTR_CSR: Read-only, for debugging.
 941  */
 942 #define RXPTR_CSR                       0x345c
 943
 944 /*
 945  * PCI_CFG_CSR
 946  */
 947 #define PCI_CFG_CSR                     0x3460
 948
 949 /*
 950  * BUF_FORMAT_CSR
 951  */
 952 #define BUF_FORMAT_CSR                  0x3464
 953
 954 /*
 955  * INT_SOURCE_CSR: Interrupt source register.
 956  * Write one to clear corresponding bit.
 957  */
 958 #define INT_SOURCE_CSR                  0x3468
 959 #define INT_SOURCE_CSR_TXDONE           FIELD32(0x00000001)
 960 #define INT_SOURCE_CSR_RXDONE           FIELD32(0x00000002)
 961 #define INT_SOURCE_CSR_BEACON_DONE      FIELD32(0x00000004)
 962 #define INT_SOURCE_CSR_TX_ABORT_DONE    FIELD32(0x00000010)
 963 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00010000)
 964 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00020000)
 965 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00040000)
 966 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00080000)
 967 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00100000)
 968 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00200000)
 969
 970 /*
 971  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 972  * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
 973  */
 974 #define INT_MASK_CSR                    0x346c
 975 #define INT_MASK_CSR_TXDONE             FIELD32(0x00000001)
 976 #define INT_MASK_CSR_RXDONE             FIELD32(0x00000002)
 977 #define INT_MASK_CSR_BEACON_DONE        FIELD32(0x00000004)
 978 #define INT_MASK_CSR_TX_ABORT_DONE      FIELD32(0x00000010)
 979 #define INT_MASK_CSR_ENABLE_MITIGATION  FIELD32(0x00000080)
 980 #define INT_MASK_CSR_MITIGATION_PERIOD  FIELD32(0x0000ff00)
 981 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00010000)
 982 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00020000)
 983 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00040000)
 984 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00080000)
 985 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00100000)
 986 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00200000)
 987
 988 /*
 989  * E2PROM_CSR: EEPROM control register.
 990  * RELOAD: Write 1 to reload eeprom content.
 991  * TYPE_93C46: 1: 93c46, 0:93c66.
 992  * LOAD_STATUS: 1:loading, 0:done.
 993  */
 994 #define E2PROM_CSR                      0x3470
 995 #define E2PROM_CSR_RELOAD               FIELD32(0x00000001)
 996 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000002)
 997 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000004)
 998 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000008)
 999 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000010)
1000 #define E2PROM_CSR_TYPE_93C46           FIELD32(0x00000020)
1001 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
1002
1003 /*
1004  * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
1005  * AC0_TX_OP: For AC_BK, in unit of 32us.
1006  * AC1_TX_OP: For AC_BE, in unit of 32us.
1007  */
1008 #define AC_TXOP_CSR0                    0x3474
1009 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
1010 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
1011
1012 /*
1013  * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
1014  * AC2_TX_OP: For AC_VI, in unit of 32us.
1015  * AC3_TX_OP: For AC_VO, in unit of 32us.
1016  */
1017 #define AC_TXOP_CSR1                    0x3478
1018 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
1019 #define AC_TXOP_CSR1_AC3_TX_OP          FIELD32(0xffff0000)
1020
1021 /*
1022  * DMA_STATUS_CSR
1023  */
1024 #define DMA_STATUS_CSR                  0x3480
1025
1026 /*
1027  * TEST_MODE_CSR
1028  */
1029 #define TEST_MODE_CSR                   0x3484
1030
1031 /*
1032  * UART0_TX_CSR
1033  */
1034 #define UART0_TX_CSR                    0x3488
1035
1036 /*
1037  * UART0_RX_CSR
1038  */
1039 #define UART0_RX_CSR                    0x348c
1040
1041 /*
1042  * UART0_FRAME_CSR
1043  */
1044 #define UART0_FRAME_CSR                 0x3490
1045
1046 /*
1047  * UART0_BUFFER_CSR
1048  */
1049 #define UART0_BUFFER_CSR                0x3494
1050
1051 /*
1052  * IO_CNTL_CSR
1053  * RF_PS: Set RF interface value to power save
1054  */
1055 #define IO_CNTL_CSR                     0x3498
1056 #define IO_CNTL_CSR_RF_PS               FIELD32(0x00000004)
1057
1058 /*
1059  * UART_INT_SOURCE_CSR
1060  */
1061 #define UART_INT_SOURCE_CSR             0x34a8
1062
1063 /*
1064  * UART_INT_MASK_CSR
1065  */
1066 #define UART_INT_MASK_CSR               0x34ac
1067
1068 /*
1069  * PBF_QUEUE_CSR
1070  */
1071 #define PBF_QUEUE_CSR                   0x34b0
1072
1073 /*
1074  * Firmware DMA registers.
1075  * Firmware DMA registers are dedicated for MCU usage
1076  * and should not be touched by host driver.
1077  * Therefore we skip the definition of these registers.
1078  */
1079 #define FW_TX_BASE_CSR                  0x34c0
1080 #define FW_TX_START_CSR                 0x34c4
1081 #define FW_TX_LAST_CSR                  0x34c8
1082 #define FW_MODE_CNTL_CSR                0x34cc
1083 #define FW_TXPTR_CSR                    0x34d0
1084
1085 /*
1086  * 8051 firmware image.
1087  */
1088 #define FIRMWARE_RT2561                 "rt2561.bin"
1089 #define FIRMWARE_RT2561s                "rt2561s.bin"
1090 #define FIRMWARE_RT2661                 "rt2661.bin"
1091 #define FIRMWARE_IMAGE_BASE             0x4000
1092
1093 /*
1094  * BBP registers.
1095  * The wordsize of the BBP is 8 bits.
1096  */
1097
1098 /*
1099  * R2
1100  */
1101 #define BBP_R2_BG_MODE                  FIELD8(0x20)
1102
1103 /*
1104  * R3
1105  */
1106 #define BBP_R3_SMART_MODE               FIELD8(0x01)
1107
1108 /*
1109  * R4: RX antenna control
1110  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1111  */
1112
1113 /*
1114  * ANTENNA_CONTROL semantics (guessed):
1115  * 0x1: Software controlled antenna switching (fixed or SW diversity)
1116  * 0x2: Hardware diversity.
1117  */
1118 #define BBP_R4_RX_ANTENNA_CONTROL       FIELD8(0x03)
1119 #define BBP_R4_RX_FRAME_END             FIELD8(0x20)
1120
1121 /*
1122  * R77
1123  */
1124 #define BBP_R77_RX_ANTENNA              FIELD8(0x03)
1125
1126 /*
1127  * RF registers
1128  */
1129
1130 /*
1131  * RF 3
1132  */
1133 #define RF3_TXPOWER                     FIELD32(0x00003e00)
1134
1135 /*
1136  * RF 4
1137  */
1138 #define RF4_FREQ_OFFSET                 FIELD32(0x0003f000)
1139
1140 /*
1141  * EEPROM content.
1142  * The wordsize of the EEPROM is 16 bits.
1143  */
1144
1145 /*
1146  * HW MAC address.
1147  */
1148 #define EEPROM_MAC_ADDR_0               0x0002
1149 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
1150 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
1151 #define EEPROM_MAC_ADDR1                0x0003
1152 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
1153 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
1154 #define EEPROM_MAC_ADDR_2               0x0004
1155 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
1156 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
1157
1158 /*
1159  * EEPROM antenna.
1160  * ANTENNA_NUM: Number of antenna's.
1161  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1162  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1163  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1164  * DYN_TXAGC: Dynamic TX AGC control.
1165  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1166  * RF_TYPE: Rf_type of this adapter.
1167  */
1168 #define EEPROM_ANTENNA                  0x0010
1169 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
1170 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
1171 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
1172 #define EEPROM_ANTENNA_FRAME_TYPE       FIELD16(0x0040)
1173 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
1174 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
1175 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
1176
1177 /*
1178  * EEPROM NIC config.
1179  * ENABLE_DIVERSITY: 1:enable, 0:disable.
1180  * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1181  * CARDBUS_ACCEL: 0:enable, 1:disable.
1182  * EXTERNAL_LNA_A: External LNA enable for 5G.
1183  */
1184 #define EEPROM_NIC                      0x0011
1185 #define EEPROM_NIC_ENABLE_DIVERSITY     FIELD16(0x0001)
1186 #define EEPROM_NIC_TX_DIVERSITY         FIELD16(0x0002)
1187 #define EEPROM_NIC_RX_FIXED             FIELD16(0x0004)
1188 #define EEPROM_NIC_TX_FIXED             FIELD16(0x0008)
1189 #define EEPROM_NIC_EXTERNAL_LNA_BG      FIELD16(0x0010)
1190 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0020)
1191 #define EEPROM_NIC_EXTERNAL_LNA_A       FIELD16(0x0040)
1192
1193 /*
1194  * EEPROM geography.
1195  * GEO_A: Default geographical setting for 5GHz band
1196  * GEO: Default geographical setting.
1197  */
1198 #define EEPROM_GEOGRAPHY                0x0012
1199 #define EEPROM_GEOGRAPHY_GEO_A          FIELD16(0x00ff)
1200 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0xff00)
1201
1202 /*
1203  * EEPROM BBP.
1204  */
1205 #define EEPROM_BBP_START                0x0013
1206 #define EEPROM_BBP_SIZE                 16
1207 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
1208 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
1209
1210 /*
1211  * EEPROM TXPOWER 802.11G
1212  */
1213 #define EEPROM_TXPOWER_G_START          0x0023
1214 #define EEPROM_TXPOWER_G_SIZE           7
1215 #define EEPROM_TXPOWER_G_1              FIELD16(0x00ff)
1216 #define EEPROM_TXPOWER_G_2              FIELD16(0xff00)
1217
1218 /*
1219  * EEPROM Frequency
1220  */
1221 #define EEPROM_FREQ                     0x002f
1222 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
1223 #define EEPROM_FREQ_SEQ_MASK            FIELD16(0xff00)
1224 #define EEPROM_FREQ_SEQ                 FIELD16(0x0300)
1225
1226 /*
1227  * EEPROM LED.
1228  * POLARITY_RDY_G: Polarity RDY_G setting.
1229  * POLARITY_RDY_A: Polarity RDY_A setting.
1230  * POLARITY_ACT: Polarity ACT setting.
1231  * POLARITY_GPIO_0: Polarity GPIO0 setting.
1232  * POLARITY_GPIO_1: Polarity GPIO1 setting.
1233  * POLARITY_GPIO_2: Polarity GPIO2 setting.
1234  * POLARITY_GPIO_3: Polarity GPIO3 setting.
1235  * POLARITY_GPIO_4: Polarity GPIO4 setting.
1236  * LED_MODE: Led mode.
1237  */
1238 #define EEPROM_LED                      0x0030
1239 #define EEPROM_LED_POLARITY_RDY_G       FIELD16(0x0001)
1240 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
1241 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
1242 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
1243 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
1244 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
1245 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
1246 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
1247 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
1248
1249 /*
1250  * EEPROM TXPOWER 802.11A
1251  */
1252 #define EEPROM_TXPOWER_A_START          0x0031
1253 #define EEPROM_TXPOWER_A_SIZE           12
1254 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
1255 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
1256
1257 /*
1258  * EEPROM RSSI offset 802.11BG
1259  */
1260 #define EEPROM_RSSI_OFFSET_BG           0x004d
1261 #define EEPROM_RSSI_OFFSET_BG_1         FIELD16(0x00ff)
1262 #define EEPROM_RSSI_OFFSET_BG_2         FIELD16(0xff00)
1263
1264 /*
1265  * EEPROM RSSI offset 802.11A
1266  */
1267 #define EEPROM_RSSI_OFFSET_A            0x004e
1268 #define EEPROM_RSSI_OFFSET_A_1          FIELD16(0x00ff)
1269 #define EEPROM_RSSI_OFFSET_A_2          FIELD16(0xff00)
1270
1271 /*
1272  * MCU mailbox commands.
1273  */
1274 #define MCU_SLEEP                       0x30
1275 #define MCU_WAKEUP                      0x31
1276 #define MCU_LED                         0x50
1277 #define MCU_LED_STRENGTH                0x52
1278
1279 /*
1280  * DMA descriptor defines.
1281  */
1282 #define TXD_DESC_SIZE                   ( 16 * sizeof(__le32) )
1283 #define TXINFO_SIZE                     ( 6 * sizeof(__le32) )
1284 #define RXD_DESC_SIZE                   ( 16 * sizeof(__le32) )
1285
1286 /*
1287  * TX descriptor format for TX, PRIO and Beacon Ring.
1288  */
1289
1290 /*
1291  * Word0
1292  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1293  * KEY_TABLE: Use per-client pairwise KEY table.
1294  * KEY_INDEX:
1295  * Key index (0~31) to the pairwise KEY table.
1296  * 0~3 to shared KEY table 0 (BSS0).
1297  * 4~7 to shared KEY table 1 (BSS1).
1298  * 8~11 to shared KEY table 2 (BSS2).
1299  * 12~15 to shared KEY table 3 (BSS3).
1300  * BURST: Next frame belongs to same "burst" event.
1301  */
1302 #define TXD_W0_OWNER_NIC                FIELD32(0x00000001)
1303 #define TXD_W0_VALID                    FIELD32(0x00000002)
1304 #define TXD_W0_MORE_FRAG                FIELD32(0x00000004)
1305 #define TXD_W0_ACK                      FIELD32(0x00000008)
1306 #define TXD_W0_TIMESTAMP                FIELD32(0x00000010)
1307 #define TXD_W0_OFDM                     FIELD32(0x00000020)
1308 #define TXD_W0_IFS                      FIELD32(0x00000040)
1309 #define TXD_W0_RETRY_MODE               FIELD32(0x00000080)
1310 #define TXD_W0_TKIP_MIC                 FIELD32(0x00000100)
1311 #define TXD_W0_KEY_TABLE                FIELD32(0x00000200)
1312 #define TXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1313 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1314 #define TXD_W0_BURST                    FIELD32(0x10000000)
1315 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1316
1317 /*
1318  * Word1
1319  * HOST_Q_ID: EDCA/HCCA queue ID.
1320  * HW_SEQUENCE: MAC overwrites the frame sequence number.
1321  * BUFFER_COUNT: Number of buffers in this TXD.
1322  */
1323 #define TXD_W1_HOST_Q_ID                FIELD32(0x0000000f)
1324 #define TXD_W1_AIFSN                    FIELD32(0x000000f0)
1325 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
1326 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
1327 #define TXD_W1_IV_OFFSET                FIELD32(0x003f0000)
1328 #define TXD_W1_PIGGY_BACK               FIELD32(0x01000000)
1329 #define TXD_W1_HW_SEQUENCE              FIELD32(0x10000000)
1330 #define TXD_W1_BUFFER_COUNT             FIELD32(0xe0000000)
1331
1332 /*
1333  * Word2: PLCP information
1334  */
1335 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
1336 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
1337 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
1338 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
1339
1340 /*
1341  * Word3
1342  */
1343 #define TXD_W3_IV                       FIELD32(0xffffffff)
1344
1345 /*
1346  * Word4
1347  */
1348 #define TXD_W4_EIV                      FIELD32(0xffffffff)
1349
1350 /*
1351  * Word5
1352  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1353  * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1354  * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1355  * WAITING_DMA_DONE_INT: TXD been filled with data
1356  * and waiting for TxDoneISR housekeeping.
1357  */
1358 #define TXD_W5_FRAME_OFFSET             FIELD32(0x000000ff)
1359 #define TXD_W5_PID_SUBTYPE              FIELD32(0x00001f00)
1360 #define TXD_W5_PID_TYPE                 FIELD32(0x0000e000)
1361 #define TXD_W5_TX_POWER                 FIELD32(0x00ff0000)
1362 #define TXD_W5_WAITING_DMA_DONE_INT     FIELD32(0x01000000)
1363
1364 /*
1365  * the above 24-byte is called TXINFO and will be DMAed to MAC block
1366  * through TXFIFO. MAC block use this TXINFO to control the transmission
1367  * behavior of this frame.
1368  * The following fields are not used by MAC block.
1369  * They are used by DMA block and HOST driver only.
1370  * Once a frame has been DMA to ASIC, all the following fields are useless
1371  * to ASIC.
1372  */
1373
1374 /*
1375  * Word6-10: Buffer physical address
1376  */
1377 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1378 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1379 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1380 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1381 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1382
1383 /*
1384  * Word11-13: Buffer length
1385  */
1386 #define TXD_W11_BUFFER_LENGTH0          FIELD32(0x00000fff)
1387 #define TXD_W11_BUFFER_LENGTH1          FIELD32(0x0fff0000)
1388 #define TXD_W12_BUFFER_LENGTH2          FIELD32(0x00000fff)
1389 #define TXD_W12_BUFFER_LENGTH3          FIELD32(0x0fff0000)
1390 #define TXD_W13_BUFFER_LENGTH4          FIELD32(0x00000fff)
1391
1392 /*
1393  * Word14
1394  */
1395 #define TXD_W14_SK_BUFFER               FIELD32(0xffffffff)
1396
1397 /*
1398  * Word15
1399  */
1400 #define TXD_W15_NEXT_SK_BUFFER          FIELD32(0xffffffff)
1401
1402 /*
1403  * RX descriptor format for RX Ring.
1404  */
1405
1406 /*
1407  * Word0
1408  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1409  * KEY_INDEX: Decryption key actually used.
1410  */
1411 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
1412 #define RXD_W0_DROP                     FIELD32(0x00000002)
1413 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000004)
1414 #define RXD_W0_MULTICAST                FIELD32(0x00000008)
1415 #define RXD_W0_BROADCAST                FIELD32(0x00000010)
1416 #define RXD_W0_MY_BSS                   FIELD32(0x00000020)
1417 #define RXD_W0_CRC_ERROR                FIELD32(0x00000040)
1418 #define RXD_W0_OFDM                     FIELD32(0x00000080)
1419 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000300)
1420 #define RXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1421 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1422 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1423
1424 /*
1425  * Word1
1426  * SIGNAL: RX raw data rate reported by BBP.
1427  */
1428 #define RXD_W1_SIGNAL                   FIELD32(0x000000ff)
1429 #define RXD_W1_RSSI_AGC                 FIELD32(0x00001f00)
1430 #define RXD_W1_RSSI_LNA                 FIELD32(0x00006000)
1431 #define RXD_W1_FRAME_OFFSET             FIELD32(0x7f000000)
1432
1433 /*
1434  * Word2
1435  * IV: Received IV of originally encrypted.
1436  */
1437 #define RXD_W2_IV                       FIELD32(0xffffffff)
1438
1439 /*
1440  * Word3
1441  * EIV: Received EIV of originally encrypted.
1442  */
1443 #define RXD_W3_EIV                      FIELD32(0xffffffff)
1444
1445 /*
1446  * Word4
1447  * ICV: Received ICV of originally encrypted.
1448  * NOTE: This is a guess, the official definition is "reserved"
1449  */
1450 #define RXD_W4_ICV                      FIELD32(0xffffffff)
1451
1452 /*
1453  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1454  * and passed to the HOST driver.
1455  * The following fields are for DMA block and HOST usage only.
1456  * Can't be touched by ASIC MAC block.
1457  */
1458
1459 /*
1460  * Word5
1461  */
1462 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1463
1464 /*
1465  * Word6-15: Reserved
1466  */
1467 #define RXD_W6_RESERVED                 FIELD32(0xffffffff)
1468 #define RXD_W7_RESERVED                 FIELD32(0xffffffff)
1469 #define RXD_W8_RESERVED                 FIELD32(0xffffffff)
1470 #define RXD_W9_RESERVED                 FIELD32(0xffffffff)
1471 #define RXD_W10_RESERVED                FIELD32(0xffffffff)
1472 #define RXD_W11_RESERVED                FIELD32(0xffffffff)
1473 #define RXD_W12_RESERVED                FIELD32(0xffffffff)
1474 #define RXD_W13_RESERVED                FIELD32(0xffffffff)
1475 #define RXD_W14_RESERVED                FIELD32(0xffffffff)
1476 #define RXD_W15_RESERVED                FIELD32(0xffffffff)
1477
1478 /*
1479  * Macros for converting txpower from EEPROM to mac80211 value
1480  * and from mac80211 value to register value.
1481  */
1482 #define MIN_TXPOWER     0
1483 #define MAX_TXPOWER     31
1484 #define DEFAULT_TXPOWER 24
1485
1486 #define TXPOWER_FROM_DEV(__txpower) \
1487         (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1488
1489 #define TXPOWER_TO_DEV(__txpower) \
1490         clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1491
1492 #endif /* RT61PCI_H */