2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
28 * Set enviroment defines for rt2x00.h
30 #define DRV_NAME "rt73usb"
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/usb.h>
40 #include "rt2x00usb.h"
45 * All access to the CSR registers will go through the methods
46 * rt73usb_register_read and rt73usb_register_write.
47 * BBP and RF register require indirect register access,
48 * and use the CSR registers BBPCSR and RFCSR to achieve this.
49 * These indirect registers work with busy bits,
50 * and we will try maximal REGISTER_BUSY_COUNT times to access
51 * the register while taking a REGISTER_BUSY_DELAY us delay
52 * between each attampt. When the busy bit is still set at that time,
53 * the access attempt is considered to have failed,
54 * and we will print an error.
56 static inline void rt73usb_register_read(const struct rt2x00_dev
*rt2x00dev
,
57 const unsigned int offset
, u32
*value
)
60 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_READ
,
61 USB_VENDOR_REQUEST_IN
, offset
,
62 ®
, sizeof(u32
), REGISTER_TIMEOUT
);
63 *value
= le32_to_cpu(reg
);
66 static inline void rt73usb_register_multiread(const struct rt2x00_dev
68 const unsigned int offset
,
69 void *value
, const u32 length
)
71 int timeout
= REGISTER_TIMEOUT
* (length
/ sizeof(u32
));
72 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_READ
,
73 USB_VENDOR_REQUEST_IN
, offset
,
74 value
, length
, timeout
);
77 static inline void rt73usb_register_write(const struct rt2x00_dev
*rt2x00dev
,
78 const unsigned int offset
, u32 value
)
80 __le32 reg
= cpu_to_le32(value
);
81 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_WRITE
,
82 USB_VENDOR_REQUEST_OUT
, offset
,
83 ®
, sizeof(u32
), REGISTER_TIMEOUT
);
86 static inline void rt73usb_register_multiwrite(const struct rt2x00_dev
88 const unsigned int offset
,
89 void *value
, const u32 length
)
91 int timeout
= REGISTER_TIMEOUT
* (length
/ sizeof(u32
));
92 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_WRITE
,
93 USB_VENDOR_REQUEST_OUT
, offset
,
94 value
, length
, timeout
);
97 static u32
rt73usb_bbp_check(const struct rt2x00_dev
*rt2x00dev
)
102 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
103 rt73usb_register_read(rt2x00dev
, PHY_CSR3
, ®
);
104 if (!rt2x00_get_field32(reg
, PHY_CSR3_BUSY
))
106 udelay(REGISTER_BUSY_DELAY
);
112 static void rt73usb_bbp_write(const struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, const u8 value
)
118 * Wait until the BBP becomes ready.
120 reg
= rt73usb_bbp_check(rt2x00dev
);
121 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
122 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Write failed.\n");
127 * Write the data into the BBP.
130 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
131 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
132 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
133 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
135 rt73usb_register_write(rt2x00dev
, PHY_CSR3
, reg
);
138 static void rt73usb_bbp_read(const struct rt2x00_dev
*rt2x00dev
,
139 const unsigned int word
, u8
*value
)
144 * Wait until the BBP becomes ready.
146 reg
= rt73usb_bbp_check(rt2x00dev
);
147 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
148 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
153 * Write the request into the BBP.
156 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
157 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
158 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
160 rt73usb_register_write(rt2x00dev
, PHY_CSR3
, reg
);
163 * Wait until the BBP becomes ready.
165 reg
= rt73usb_bbp_check(rt2x00dev
);
166 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
167 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
172 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
175 static void rt73usb_rf_write(const struct rt2x00_dev
*rt2x00dev
,
176 const unsigned int word
, const u32 value
)
184 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
185 rt73usb_register_read(rt2x00dev
, PHY_CSR4
, ®
);
186 if (!rt2x00_get_field32(reg
, PHY_CSR4_BUSY
))
188 udelay(REGISTER_BUSY_DELAY
);
191 ERROR(rt2x00dev
, "PHY_CSR4 register busy. Write failed.\n");
196 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
198 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
199 rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
200 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
202 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 20);
204 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
205 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
207 rt73usb_register_write(rt2x00dev
, PHY_CSR4
, reg
);
208 rt2x00_rf_write(rt2x00dev
, word
, value
);
211 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
212 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
214 static void rt73usb_read_csr(const struct rt2x00_dev
*rt2x00dev
,
215 const unsigned int word
, u32
*data
)
217 rt73usb_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
220 static void rt73usb_write_csr(const struct rt2x00_dev
*rt2x00dev
,
221 const unsigned int word
, u32 data
)
223 rt73usb_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
226 static const struct rt2x00debug rt73usb_rt2x00debug
= {
227 .owner
= THIS_MODULE
,
229 .read
= rt73usb_read_csr
,
230 .write
= rt73usb_write_csr
,
231 .word_size
= sizeof(u32
),
232 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
235 .read
= rt2x00_eeprom_read
,
236 .write
= rt2x00_eeprom_write
,
237 .word_size
= sizeof(u16
),
238 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
241 .read
= rt73usb_bbp_read
,
242 .write
= rt73usb_bbp_write
,
243 .word_size
= sizeof(u8
),
244 .word_count
= BBP_SIZE
/ sizeof(u8
),
247 .read
= rt2x00_rf_read
,
248 .write
= rt73usb_rf_write
,
249 .word_size
= sizeof(u32
),
250 .word_count
= RF_SIZE
/ sizeof(u32
),
253 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
256 * Configuration handlers.
258 static void rt73usb_config_mac_addr(struct rt2x00_dev
*rt2x00dev
, u8
*addr
)
263 memset(®
, 0, sizeof(reg
));
264 memcpy(®
, addr
, ETH_ALEN
);
266 tmp
= le32_to_cpu(reg
[1]);
267 rt2x00_set_field32(&tmp
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
268 reg
[1] = cpu_to_le32(tmp
);
271 * The MAC address is passed to us as an array of bytes,
272 * that array is little endian, so no need for byte ordering.
274 rt73usb_register_multiwrite(rt2x00dev
, MAC_CSR2
, ®
, sizeof(reg
));
277 static void rt73usb_config_bssid(struct rt2x00_dev
*rt2x00dev
, u8
*bssid
)
282 memset(®
, 0, sizeof(reg
));
283 memcpy(®
, bssid
, ETH_ALEN
);
285 tmp
= le32_to_cpu(reg
[1]);
286 rt2x00_set_field32(&tmp
, MAC_CSR5_BSS_ID_MASK
, 3);
287 reg
[1] = cpu_to_le32(tmp
);
290 * The BSSID is passed to us as an array of bytes,
291 * that array is little endian, so no need for byte ordering.
293 rt73usb_register_multiwrite(rt2x00dev
, MAC_CSR4
, ®
, sizeof(reg
));
296 static void rt73usb_config_packet_filter(struct rt2x00_dev
*rt2x00dev
,
297 const unsigned int filter
)
299 int promisc
= !!(filter
& IFF_PROMISC
);
300 int multicast
= !!(filter
& IFF_MULTICAST
);
301 int broadcast
= !!(filter
& IFF_BROADCAST
);
304 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
305 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
, !promisc
);
306 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
, !multicast
);
307 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BORADCAST
, !broadcast
);
308 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
311 static void rt73usb_config_type(struct rt2x00_dev
*rt2x00dev
, const int type
)
316 * Clear current synchronisation setup.
317 * For the Beacon base registers we only need to clear
318 * the first byte since that byte contains the VALID and OWNER
319 * bits which (when set to 0) will invalidate the entire beacon.
321 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, 0);
322 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
323 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
324 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
325 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
328 * Apply hardware packet filter.
330 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
332 if (!is_monitor_present(&rt2x00dev
->interface
) &&
333 (type
== IEEE80211_IF_TYPE_IBSS
|| type
== IEEE80211_IF_TYPE_STA
))
334 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
, 1);
336 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
, 0);
339 * If there is a non-monitor interface present
340 * the packet should be strict (even if a monitor interface is present!).
341 * When there is only 1 interface present which is in monitor mode
342 * we should start accepting _all_ frames.
344 if (is_interface_present(&rt2x00dev
->interface
)) {
345 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
, 1);
346 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
, 1);
347 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
, 1);
348 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
349 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
, 1);
350 } else if (is_monitor_present(&rt2x00dev
->interface
)) {
351 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
, 0);
352 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
, 0);
353 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
, 0);
354 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 0);
355 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
, 0);
358 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
361 * Enable synchronisation.
363 rt73usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
364 if (is_interface_present(&rt2x00dev
->interface
)) {
365 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
366 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
369 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
370 if (type
== IEEE80211_IF_TYPE_IBSS
|| type
== IEEE80211_IF_TYPE_AP
)
371 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 2);
372 else if (type
== IEEE80211_IF_TYPE_STA
)
373 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 1);
374 else if (is_monitor_present(&rt2x00dev
->interface
) &&
375 !is_interface_present(&rt2x00dev
->interface
))
376 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
378 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
381 static void rt73usb_config_rate(struct rt2x00_dev
*rt2x00dev
, const int rate
)
383 struct ieee80211_conf
*conf
= &rt2x00dev
->hw
->conf
;
388 if (DEVICE_GET_RATE_FIELD(rate
, PREAMBLE
))
389 preamble
= SHORT_PREAMBLE
;
393 reg
= DEVICE_GET_RATE_FIELD(rate
, RATEMASK
) & DEV_BASIC_RATEMASK
;
395 rt73usb_register_write(rt2x00dev
, TXRX_CSR5
, reg
);
397 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
398 value
= ((conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
) ?
400 PLCP
+ preamble
+ get_duration(ACK_SIZE
, 10);
401 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, value
);
402 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
404 rt73usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
405 if (preamble
== SHORT_PREAMBLE
)
406 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
, 1);
408 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
, 0);
409 rt73usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
412 static void rt73usb_config_phymode(struct rt2x00_dev
*rt2x00dev
,
415 struct ieee80211_hw_mode
*mode
;
416 struct ieee80211_rate
*rate
;
418 if (phymode
== MODE_IEEE80211A
)
419 rt2x00dev
->curr_hwmode
= HWMODE_A
;
420 else if (phymode
== MODE_IEEE80211B
)
421 rt2x00dev
->curr_hwmode
= HWMODE_B
;
423 rt2x00dev
->curr_hwmode
= HWMODE_G
;
425 mode
= &rt2x00dev
->hwmodes
[rt2x00dev
->curr_hwmode
];
426 rate
= &mode
->rates
[mode
->num_rates
- 1];
428 rt73usb_config_rate(rt2x00dev
, rate
->val2
);
431 static void rt73usb_config_lock_channel(struct rt2x00_dev
*rt2x00dev
,
432 struct rf_channel
*rf
,
439 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
440 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
442 smart
= !(rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
443 rt2x00_rf(&rt2x00dev
->chip
, RF2527
));
445 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
446 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
447 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
450 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
451 r94
+= txpower
- MAX_TXPOWER
;
452 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
454 rt73usb_bbp_write(rt2x00dev
, 94, r94
);
456 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
457 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
458 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
459 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
461 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
462 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
463 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
464 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
466 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
467 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
468 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
469 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
474 static void rt73usb_config_channel(struct rt2x00_dev
*rt2x00dev
,
475 const int index
, const int channel
,
478 struct rf_channel rf
;
481 * Fill rf_reg structure.
483 memcpy(&rf
, &rt2x00dev
->spec
.channels
[index
], sizeof(rf
));
485 rt73usb_config_lock_channel(rt2x00dev
, &rf
, txpower
);
488 static void rt73usb_config_txpower(struct rt2x00_dev
*rt2x00dev
,
491 struct rf_channel rf
;
493 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
494 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
495 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
496 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
498 rt73usb_config_lock_channel(rt2x00dev
, &rf
, txpower
);
501 static void rt73usb_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
502 const int antenna_tx
,
503 const int antenna_rx
)
509 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
510 rt73usb_bbp_read(rt2x00dev
, 4, &r4
);
511 rt73usb_bbp_read(rt2x00dev
, 77, &r77
);
513 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, 0);
515 switch (antenna_rx
) {
516 case ANTENNA_SW_DIVERSITY
:
517 case ANTENNA_HW_DIVERSITY
:
518 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 2);
519 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
520 !!(rt2x00dev
->curr_hwmode
!= HWMODE_A
));
523 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 1);
524 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
526 if (rt2x00dev
->curr_hwmode
== HWMODE_A
)
527 rt2x00_set_field8(&r77
, BBP_R77_PAIR
, 0);
529 rt2x00_set_field8(&r77
, BBP_R77_PAIR
, 3);
532 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 1);
533 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
535 if (rt2x00dev
->curr_hwmode
== HWMODE_A
)
536 rt2x00_set_field8(&r77
, BBP_R77_PAIR
, 3);
538 rt2x00_set_field8(&r77
, BBP_R77_PAIR
, 0);
542 rt73usb_bbp_write(rt2x00dev
, 77, r77
);
543 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
544 rt73usb_bbp_write(rt2x00dev
, 4, r4
);
547 static void rt73usb_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
548 const int antenna_tx
,
549 const int antenna_rx
)
555 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
556 rt73usb_bbp_read(rt2x00dev
, 4, &r4
);
557 rt73usb_bbp_read(rt2x00dev
, 77, &r77
);
559 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, 0);
560 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
561 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
563 switch (antenna_rx
) {
564 case ANTENNA_SW_DIVERSITY
:
565 case ANTENNA_HW_DIVERSITY
:
566 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 2);
569 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 1);
570 rt2x00_set_field8(&r77
, BBP_R77_PAIR
, 3);
573 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 1);
574 rt2x00_set_field8(&r77
, BBP_R77_PAIR
, 0);
578 rt73usb_bbp_write(rt2x00dev
, 77, r77
);
579 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
580 rt73usb_bbp_write(rt2x00dev
, 4, r4
);
586 * value[0] -> non-LNA
592 static const struct antenna_sel antenna_sel_a
[] = {
593 { 96, { 0x58, 0x78 } },
594 { 104, { 0x38, 0x48 } },
595 { 75, { 0xfe, 0x80 } },
596 { 86, { 0xfe, 0x80 } },
597 { 88, { 0xfe, 0x80 } },
598 { 35, { 0x60, 0x60 } },
599 { 97, { 0x58, 0x58 } },
600 { 98, { 0x58, 0x58 } },
603 static const struct antenna_sel antenna_sel_bg
[] = {
604 { 96, { 0x48, 0x68 } },
605 { 104, { 0x2c, 0x3c } },
606 { 75, { 0xfe, 0x80 } },
607 { 86, { 0xfe, 0x80 } },
608 { 88, { 0xfe, 0x80 } },
609 { 35, { 0x50, 0x50 } },
610 { 97, { 0x48, 0x48 } },
611 { 98, { 0x48, 0x48 } },
614 static void rt73usb_config_antenna(struct rt2x00_dev
*rt2x00dev
,
615 const int antenna_tx
, const int antenna_rx
)
617 const struct antenna_sel
*sel
;
622 rt73usb_register_read(rt2x00dev
, PHY_CSR0
, ®
);
624 if (rt2x00dev
->curr_hwmode
== HWMODE_A
) {
626 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
628 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
, 0);
629 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
, 1);
631 sel
= antenna_sel_bg
;
632 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
634 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
, 1);
635 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
, 0);
638 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
639 rt73usb_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
641 rt73usb_register_write(rt2x00dev
, PHY_CSR0
, reg
);
643 if (rt2x00_rf(&rt2x00dev
->chip
, RF5226
) ||
644 rt2x00_rf(&rt2x00dev
->chip
, RF5225
))
645 rt73usb_config_antenna_5x(rt2x00dev
, antenna_tx
, antenna_rx
);
646 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2528
) ||
647 rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
648 rt73usb_config_antenna_2x(rt2x00dev
, antenna_tx
, antenna_rx
);
651 static void rt73usb_config_duration(struct rt2x00_dev
*rt2x00dev
,
652 const int short_slot_time
,
653 const int beacon_int
)
657 rt73usb_register_read(rt2x00dev
, MAC_CSR9
, ®
);
658 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
,
659 short_slot_time
? SHORT_SLOT_TIME
: SLOT_TIME
);
660 rt73usb_register_write(rt2x00dev
, MAC_CSR9
, reg
);
662 rt73usb_register_read(rt2x00dev
, MAC_CSR8
, ®
);
663 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, SIFS
);
664 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
665 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, EIFS
);
666 rt73usb_register_write(rt2x00dev
, MAC_CSR8
, reg
);
668 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
669 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
670 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
672 rt73usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
673 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
674 rt73usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
676 rt73usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
677 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, beacon_int
* 16);
678 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
681 static void rt73usb_config(struct rt2x00_dev
*rt2x00dev
,
682 const unsigned int flags
,
683 struct ieee80211_conf
*conf
)
685 int short_slot_time
= conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
;
687 if (flags
& CONFIG_UPDATE_PHYMODE
)
688 rt73usb_config_phymode(rt2x00dev
, conf
->phymode
);
689 if (flags
& CONFIG_UPDATE_CHANNEL
)
690 rt73usb_config_channel(rt2x00dev
, conf
->channel_val
,
691 conf
->channel
, conf
->power_level
);
692 if ((flags
& CONFIG_UPDATE_TXPOWER
) && !(flags
& CONFIG_UPDATE_CHANNEL
))
693 rt73usb_config_txpower(rt2x00dev
, conf
->power_level
);
694 if (flags
& CONFIG_UPDATE_ANTENNA
)
695 rt73usb_config_antenna(rt2x00dev
, conf
->antenna_sel_tx
,
696 conf
->antenna_sel_rx
);
697 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
698 rt73usb_config_duration(rt2x00dev
, short_slot_time
,
705 static void rt73usb_enable_led(struct rt2x00_dev
*rt2x00dev
)
709 rt73usb_register_read(rt2x00dev
, MAC_CSR14
, ®
);
710 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, 70);
711 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, 30);
712 rt73usb_register_write(rt2x00dev
, MAC_CSR14
, reg
);
714 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_RADIO_STATUS
, 1);
715 if (rt2x00dev
->rx_status
.phymode
== MODE_IEEE80211A
)
716 rt2x00_set_field16(&rt2x00dev
->led_reg
,
717 MCU_LEDCS_LINK_A_STATUS
, 1);
719 rt2x00_set_field16(&rt2x00dev
->led_reg
,
720 MCU_LEDCS_LINK_BG_STATUS
, 1);
722 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_LED_CONTROL
, 0x0000,
723 rt2x00dev
->led_reg
, REGISTER_TIMEOUT
);
726 static void rt73usb_disable_led(struct rt2x00_dev
*rt2x00dev
)
728 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_RADIO_STATUS
, 0);
729 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_LINK_BG_STATUS
, 0);
730 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_LINK_A_STATUS
, 0);
732 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_LED_CONTROL
, 0x0000,
733 rt2x00dev
->led_reg
, REGISTER_TIMEOUT
);
736 static void rt73usb_activity_led(struct rt2x00_dev
*rt2x00dev
, int rssi
)
740 if (rt2x00dev
->led_mode
!= LED_MODE_SIGNAL_STRENGTH
)
744 * Led handling requires a positive value for the rssi,
745 * to do that correctly we need to add the correction.
747 rssi
+= rt2x00dev
->rssi_offset
;
762 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_LED_CONTROL
, led
,
763 rt2x00dev
->led_reg
, REGISTER_TIMEOUT
);
769 static void rt73usb_link_stats(struct rt2x00_dev
*rt2x00dev
)
774 * Update FCS error count from register.
776 rt73usb_register_read(rt2x00dev
, STA_CSR0
, ®
);
777 rt2x00dev
->link
.rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
780 * Update False CCA count from register.
782 rt73usb_register_read(rt2x00dev
, STA_CSR1
, ®
);
783 reg
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
784 rt2x00dev
->link
.false_cca
=
785 rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
788 static void rt73usb_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
790 rt73usb_bbp_write(rt2x00dev
, 17, 0x20);
791 rt2x00dev
->link
.vgc_level
= 0x20;
794 static void rt73usb_link_tuner(struct rt2x00_dev
*rt2x00dev
)
796 int rssi
= rt2x00_get_link_rssi(&rt2x00dev
->link
);
802 * Update Led strength
804 rt73usb_activity_led(rt2x00dev
, rssi
);
806 rt73usb_bbp_read(rt2x00dev
, 17, &r17
);
809 * Determine r17 bounds.
811 if (rt2x00dev
->rx_status
.phymode
== MODE_IEEE80211A
) {
815 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
823 } else if (rssi
> -84) {
831 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
838 * Special big-R17 for very short distance
842 rt73usb_bbp_write(rt2x00dev
, 17, 0x60);
847 * Special big-R17 for short distance
851 rt73usb_bbp_write(rt2x00dev
, 17, up_bound
);
856 * Special big-R17 for middle-short distance
860 if (r17
!= low_bound
)
861 rt73usb_bbp_write(rt2x00dev
, 17, low_bound
);
866 * Special mid-R17 for middle distance
869 if (r17
!= (low_bound
+ 0x10))
870 rt73usb_bbp_write(rt2x00dev
, 17, low_bound
+ 0x08);
875 * Special case: Change up_bound based on the rssi.
876 * Lower up_bound when rssi is weaker then -74 dBm.
878 up_bound
-= 2 * (-74 - rssi
);
879 if (low_bound
> up_bound
)
880 up_bound
= low_bound
;
882 if (r17
> up_bound
) {
883 rt73usb_bbp_write(rt2x00dev
, 17, up_bound
);
888 * r17 does not yet exceed upper limit, continue and base
889 * the r17 tuning on the false CCA count.
891 if (rt2x00dev
->link
.false_cca
> 512 && r17
< up_bound
) {
895 rt73usb_bbp_write(rt2x00dev
, 17, r17
);
896 } else if (rt2x00dev
->link
.false_cca
< 100 && r17
> low_bound
) {
900 rt73usb_bbp_write(rt2x00dev
, 17, r17
);
905 * Firmware name function.
907 static char *rt73usb_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
909 return FIRMWARE_RT2571
;
913 * Initialization functions.
915 static int rt73usb_load_firmware(struct rt2x00_dev
*rt2x00dev
, void *data
,
927 * Wait for stable hardware.
929 for (i
= 0; i
< 100; i
++) {
930 rt73usb_register_read(rt2x00dev
, MAC_CSR0
, ®
);
937 ERROR(rt2x00dev
, "Unstable hardware.\n");
942 * Write firmware to device.
943 * We setup a seperate cache for this action,
944 * since we are going to write larger chunks of data
945 * then normally used cache size.
947 cache
= kmalloc(CSR_CACHE_SIZE_FIRMWARE
, GFP_KERNEL
);
949 ERROR(rt2x00dev
, "Failed to allocate firmware cache.\n");
953 for (i
= 0; i
< len
; i
+= CSR_CACHE_SIZE_FIRMWARE
) {
954 buflen
= min_t(int, len
- i
, CSR_CACHE_SIZE_FIRMWARE
);
955 timeout
= REGISTER_TIMEOUT
* (buflen
/ sizeof(u32
));
957 memcpy(cache
, ptr
, buflen
);
959 rt2x00usb_vendor_request(rt2x00dev
, USB_MULTI_WRITE
,
960 USB_VENDOR_REQUEST_OUT
,
961 FIRMWARE_IMAGE_BASE
+ i
, 0x0000,
962 cache
, buflen
, timeout
);
970 * Send firmware request to device to load firmware,
971 * we need to specify a long timeout time.
973 status
= rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
,
974 0x0000, USB_MODE_FIRMWARE
,
975 REGISTER_TIMEOUT_FIRMWARE
);
977 ERROR(rt2x00dev
, "Failed to write Firmware to device.\n");
981 rt73usb_disable_led(rt2x00dev
);
986 static int rt73usb_init_registers(struct rt2x00_dev
*rt2x00dev
)
990 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
991 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
992 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
993 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
994 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
996 rt73usb_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
997 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
998 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
999 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1000 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1001 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1002 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1003 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1004 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1005 rt73usb_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1008 * CCK TXD BBP registers
1010 rt73usb_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1011 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1012 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1013 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1014 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1015 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1016 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1017 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1018 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1019 rt73usb_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1022 * OFDM TXD BBP registers
1024 rt73usb_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1025 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1026 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1027 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1028 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1029 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1030 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1031 rt73usb_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1033 rt73usb_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1034 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1035 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1036 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1037 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1038 rt73usb_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1040 rt73usb_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1041 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1042 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1043 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1044 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1045 rt73usb_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1047 rt73usb_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1049 rt73usb_register_read(rt2x00dev
, MAC_CSR6
, ®
);
1050 rt2x00_set_field32(®
, MAC_CSR6_MAX_FRAME_UNIT
, 0xfff);
1051 rt73usb_register_write(rt2x00dev
, MAC_CSR6
, reg
);
1053 rt73usb_register_write(rt2x00dev
, MAC_CSR10
, 0x00000718);
1055 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1058 rt73usb_register_write(rt2x00dev
, MAC_CSR13
, 0x00007f00);
1061 * Invalidate all Shared Keys (SEC_CSR0),
1062 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1064 rt73usb_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1065 rt73usb_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1066 rt73usb_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1069 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
1070 rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
1071 rt2x00_set_field32(®
, PHY_CSR1_RF_RPI
, 1);
1072 rt73usb_register_write(rt2x00dev
, PHY_CSR1
, reg
);
1074 rt73usb_register_write(rt2x00dev
, PHY_CSR5
, 0x00040a06);
1075 rt73usb_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1076 rt73usb_register_write(rt2x00dev
, PHY_CSR7
, 0x00000408);
1078 rt73usb_register_read(rt2x00dev
, AC_TXOP_CSR0
, ®
);
1079 rt2x00_set_field32(®
, AC_TXOP_CSR0_AC0_TX_OP
, 0);
1080 rt2x00_set_field32(®
, AC_TXOP_CSR0_AC1_TX_OP
, 0);
1081 rt73usb_register_write(rt2x00dev
, AC_TXOP_CSR0
, reg
);
1083 rt73usb_register_read(rt2x00dev
, AC_TXOP_CSR1
, ®
);
1084 rt2x00_set_field32(®
, AC_TXOP_CSR1_AC2_TX_OP
, 192);
1085 rt2x00_set_field32(®
, AC_TXOP_CSR1_AC3_TX_OP
, 48);
1086 rt73usb_register_write(rt2x00dev
, AC_TXOP_CSR1
, reg
);
1088 rt73usb_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1089 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1090 rt73usb_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1093 * We must clear the error counters.
1094 * These registers are cleared on read,
1095 * so we may pass a useless variable to store the value.
1097 rt73usb_register_read(rt2x00dev
, STA_CSR0
, ®
);
1098 rt73usb_register_read(rt2x00dev
, STA_CSR1
, ®
);
1099 rt73usb_register_read(rt2x00dev
, STA_CSR2
, ®
);
1102 * Reset MAC and BBP registers.
1104 rt73usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1105 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1106 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1107 rt73usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1109 rt73usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1110 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1111 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1112 rt73usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1114 rt73usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1115 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1116 rt73usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1121 static int rt73usb_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1128 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1129 rt73usb_bbp_read(rt2x00dev
, 0, &value
);
1130 if ((value
!= 0xff) && (value
!= 0x00))
1131 goto continue_csr_init
;
1132 NOTICE(rt2x00dev
, "Waiting for BBP register.\n");
1133 udelay(REGISTER_BUSY_DELAY
);
1136 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1140 rt73usb_bbp_write(rt2x00dev
, 3, 0x80);
1141 rt73usb_bbp_write(rt2x00dev
, 15, 0x30);
1142 rt73usb_bbp_write(rt2x00dev
, 21, 0xc8);
1143 rt73usb_bbp_write(rt2x00dev
, 22, 0x38);
1144 rt73usb_bbp_write(rt2x00dev
, 23, 0x06);
1145 rt73usb_bbp_write(rt2x00dev
, 24, 0xfe);
1146 rt73usb_bbp_write(rt2x00dev
, 25, 0x0a);
1147 rt73usb_bbp_write(rt2x00dev
, 26, 0x0d);
1148 rt73usb_bbp_write(rt2x00dev
, 32, 0x0b);
1149 rt73usb_bbp_write(rt2x00dev
, 34, 0x12);
1150 rt73usb_bbp_write(rt2x00dev
, 37, 0x07);
1151 rt73usb_bbp_write(rt2x00dev
, 39, 0xf8);
1152 rt73usb_bbp_write(rt2x00dev
, 41, 0x60);
1153 rt73usb_bbp_write(rt2x00dev
, 53, 0x10);
1154 rt73usb_bbp_write(rt2x00dev
, 54, 0x18);
1155 rt73usb_bbp_write(rt2x00dev
, 60, 0x10);
1156 rt73usb_bbp_write(rt2x00dev
, 61, 0x04);
1157 rt73usb_bbp_write(rt2x00dev
, 62, 0x04);
1158 rt73usb_bbp_write(rt2x00dev
, 75, 0xfe);
1159 rt73usb_bbp_write(rt2x00dev
, 86, 0xfe);
1160 rt73usb_bbp_write(rt2x00dev
, 88, 0xfe);
1161 rt73usb_bbp_write(rt2x00dev
, 90, 0x0f);
1162 rt73usb_bbp_write(rt2x00dev
, 99, 0x00);
1163 rt73usb_bbp_write(rt2x00dev
, 102, 0x16);
1164 rt73usb_bbp_write(rt2x00dev
, 107, 0x04);
1166 DEBUG(rt2x00dev
, "Start initialization from EEPROM...\n");
1167 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1168 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1170 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1171 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1172 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1173 DEBUG(rt2x00dev
, "BBP: 0x%02x, value: 0x%02x.\n",
1175 rt73usb_bbp_write(rt2x00dev
, reg_id
, value
);
1178 DEBUG(rt2x00dev
, "...End initialization from EEPROM.\n");
1184 * Device state switch handlers.
1186 static void rt73usb_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1187 enum dev_state state
)
1191 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1192 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1193 state
== STATE_RADIO_RX_OFF
);
1194 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1197 static int rt73usb_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1200 * Initialize all registers.
1202 if (rt73usb_init_registers(rt2x00dev
) ||
1203 rt73usb_init_bbp(rt2x00dev
)) {
1204 ERROR(rt2x00dev
, "Register initialization failed.\n");
1208 rt2x00usb_enable_radio(rt2x00dev
);
1213 rt73usb_enable_led(rt2x00dev
);
1218 static void rt73usb_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1223 rt73usb_disable_led(rt2x00dev
);
1225 rt73usb_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1228 * Disable synchronisation.
1230 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1232 rt2x00usb_disable_radio(rt2x00dev
);
1235 static int rt73usb_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1242 put_to_sleep
= (state
!= STATE_AWAKE
);
1244 rt73usb_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1245 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1246 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1247 rt73usb_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1250 * Device is not guaranteed to be in the requested state yet.
1251 * We must wait until the register indicates that the
1252 * device has entered the correct state.
1254 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1255 rt73usb_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1257 rt2x00_get_field32(reg
, MAC_CSR12_BBP_CURRENT_STATE
);
1258 if (current_state
== !put_to_sleep
)
1263 NOTICE(rt2x00dev
, "Device failed to enter state %d, "
1264 "current device state %d.\n", !put_to_sleep
, current_state
);
1269 static int rt73usb_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1270 enum dev_state state
)
1275 case STATE_RADIO_ON
:
1276 retval
= rt73usb_enable_radio(rt2x00dev
);
1278 case STATE_RADIO_OFF
:
1279 rt73usb_disable_radio(rt2x00dev
);
1281 case STATE_RADIO_RX_ON
:
1282 case STATE_RADIO_RX_OFF
:
1283 rt73usb_toggle_rx(rt2x00dev
, state
);
1285 case STATE_DEEP_SLEEP
:
1289 retval
= rt73usb_set_state(rt2x00dev
, state
);
1300 * TX descriptor initialization
1302 static void rt73usb_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1303 struct data_desc
*txd
,
1304 struct data_entry_desc
*desc
,
1305 struct ieee80211_hdr
*ieee80211hdr
,
1306 unsigned int length
,
1307 struct ieee80211_tx_control
*control
)
1312 * Start writing the descriptor words.
1314 rt2x00_desc_read(txd
, 1, &word
);
1315 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, desc
->queue
);
1316 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, desc
->aifs
);
1317 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, desc
->cw_min
);
1318 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, desc
->cw_max
);
1319 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, IEEE80211_HEADER
);
1320 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
, 1);
1321 rt2x00_desc_write(txd
, 1, word
);
1323 rt2x00_desc_read(txd
, 2, &word
);
1324 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, desc
->signal
);
1325 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, desc
->service
);
1326 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, desc
->length_low
);
1327 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, desc
->length_high
);
1328 rt2x00_desc_write(txd
, 2, word
);
1330 rt2x00_desc_read(txd
, 5, &word
);
1331 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1332 TXPOWER_TO_DEV(control
->power_level
));
1333 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1334 rt2x00_desc_write(txd
, 5, word
);
1336 rt2x00_desc_read(txd
, 0, &word
);
1337 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1338 test_bit(ENTRY_TXD_BURST
, &desc
->flags
));
1339 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1340 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1341 test_bit(ENTRY_TXD_MORE_FRAG
, &desc
->flags
));
1342 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1343 !(control
->flags
& IEEE80211_TXCTL_NO_ACK
));
1344 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1345 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &desc
->flags
));
1346 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1347 test_bit(ENTRY_TXD_OFDM_RATE
, &desc
->flags
));
1348 rt2x00_set_field32(&word
, TXD_W0_IFS
, desc
->ifs
);
1349 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1351 IEEE80211_TXCTL_LONG_RETRY_LIMIT
));
1352 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
, 0);
1353 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, length
);
1354 rt2x00_set_field32(&word
, TXD_W0_BURST2
,
1355 test_bit(ENTRY_TXD_BURST
, &desc
->flags
));
1356 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, CIPHER_NONE
);
1357 rt2x00_desc_write(txd
, 0, word
);
1361 * TX data initialization
1363 static void rt73usb_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1368 if (queue
!= IEEE80211_TX_QUEUE_BEACON
)
1372 * For Wi-Fi faily generated beacons between participating stations.
1373 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1375 rt73usb_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1377 rt73usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1378 if (!rt2x00_get_field32(reg
, TXRX_CSR9_BEACON_GEN
)) {
1379 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1380 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1385 * RX control handlers
1387 static int rt73usb_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1393 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1408 if (rt2x00dev
->rx_status
.phymode
== MODE_IEEE80211A
) {
1409 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1410 if (lna
== 3 || lna
== 2)
1419 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
1420 offset
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
1422 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
1425 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
1426 offset
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
1429 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1432 static int rt73usb_fill_rxdone(struct data_entry
*entry
,
1433 int *signal
, int *rssi
, int *ofdm
, int *size
)
1435 struct data_desc
*rxd
= (struct data_desc
*)entry
->skb
->data
;
1439 rt2x00_desc_read(rxd
, 0, &word0
);
1440 rt2x00_desc_read(rxd
, 1, &word1
);
1442 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
) ||
1443 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
))
1447 * Obtain the status about this packet.
1449 *signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
1450 *rssi
= rt73usb_agc_to_rssi(entry
->ring
->rt2x00dev
, word1
);
1451 *ofdm
= rt2x00_get_field32(word0
, RXD_W0_OFDM
);
1452 *size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1455 * Pull the skb to clear the descriptor area.
1457 skb_pull(entry
->skb
, entry
->ring
->desc_size
);
1463 * Device probe functions.
1465 static int rt73usb_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1471 rt2x00usb_eeprom_read(rt2x00dev
, rt2x00dev
->eeprom
, EEPROM_SIZE
);
1474 * Start validation of the data that has been read.
1476 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1477 if (!is_valid_ether_addr(mac
)) {
1478 DECLARE_MAC_BUF(macbuf
);
1480 random_ether_addr(mac
);
1481 EEPROM(rt2x00dev
, "MAC: %s\n", print_mac(macbuf
, mac
));
1484 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1485 if (word
== 0xffff) {
1486 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1487 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
, 2);
1488 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
, 2);
1489 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
1490 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1491 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1492 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5226
);
1493 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1494 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1497 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1498 if (word
== 0xffff) {
1499 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA
, 0);
1500 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1501 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1504 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
1505 if (word
== 0xffff) {
1506 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_RDY_G
, 0);
1507 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_RDY_A
, 0);
1508 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_ACT
, 0);
1509 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_0
, 0);
1510 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_1
, 0);
1511 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_2
, 0);
1512 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_3
, 0);
1513 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_4
, 0);
1514 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
1516 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
1517 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
1520 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
1521 if (word
== 0xffff) {
1522 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
1523 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
1524 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
1525 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
1528 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
1529 if (word
== 0xffff) {
1530 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1531 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1532 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1533 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
1535 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
1536 if (value
< -10 || value
> 10)
1537 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1538 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
1539 if (value
< -10 || value
> 10)
1540 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1541 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1544 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
1545 if (word
== 0xffff) {
1546 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1547 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1548 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
1549 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
1551 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
1552 if (value
< -10 || value
> 10)
1553 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1554 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
1555 if (value
< -10 || value
> 10)
1556 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1557 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
1563 static int rt73usb_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1570 * Read EEPROM word for configuration.
1572 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1575 * Identify RF chipset.
1577 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1578 rt73usb_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1579 rt2x00_set_chip(rt2x00dev
, RT2571
, value
, reg
);
1581 if (!rt2x00_rev(&rt2x00dev
->chip
, 0x25730)) {
1582 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
1586 if (!rt2x00_rf(&rt2x00dev
->chip
, RF5226
) &&
1587 !rt2x00_rf(&rt2x00dev
->chip
, RF2528
) &&
1588 !rt2x00_rf(&rt2x00dev
->chip
, RF5225
) &&
1589 !rt2x00_rf(&rt2x00dev
->chip
, RF2527
)) {
1590 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1595 * Identify default antenna configuration.
1597 rt2x00dev
->hw
->conf
.antenna_sel_tx
=
1598 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1599 rt2x00dev
->hw
->conf
.antenna_sel_rx
=
1600 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1603 * Read the Frame type.
1605 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
1606 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
1609 * Read frequency offset.
1611 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1612 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
1615 * Read external LNA informations.
1617 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1619 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA
)) {
1620 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
1621 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
1625 * Store led settings, for correct led behaviour.
1627 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
1629 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_LED_MODE
,
1630 rt2x00dev
->led_mode
);
1631 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
1632 rt2x00_get_field16(eeprom
,
1633 EEPROM_LED_POLARITY_GPIO_0
));
1634 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
1635 rt2x00_get_field16(eeprom
,
1636 EEPROM_LED_POLARITY_GPIO_1
));
1637 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
1638 rt2x00_get_field16(eeprom
,
1639 EEPROM_LED_POLARITY_GPIO_2
));
1640 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
1641 rt2x00_get_field16(eeprom
,
1642 EEPROM_LED_POLARITY_GPIO_3
));
1643 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
1644 rt2x00_get_field16(eeprom
,
1645 EEPROM_LED_POLARITY_GPIO_4
));
1646 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_ACT
,
1647 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
1648 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_READY_BG
,
1649 rt2x00_get_field16(eeprom
,
1650 EEPROM_LED_POLARITY_RDY_G
));
1651 rt2x00_set_field16(&rt2x00dev
->led_reg
, MCU_LEDCS_POLARITY_READY_A
,
1652 rt2x00_get_field16(eeprom
,
1653 EEPROM_LED_POLARITY_RDY_A
));
1659 * RF value list for RF2528
1662 static const struct rf_channel rf_vals_bg_2528
[] = {
1663 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1664 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1665 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1666 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1667 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1668 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1669 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1670 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1671 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1672 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1673 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1674 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1675 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1676 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1680 * RF value list for RF5226
1681 * Supports: 2.4 GHz & 5.2 GHz
1683 static const struct rf_channel rf_vals_5226
[] = {
1684 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1685 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1686 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1687 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1688 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1689 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1690 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1691 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1692 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1693 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1694 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1695 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1696 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1697 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1699 /* 802.11 UNI / HyperLan 2 */
1700 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1701 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1702 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1703 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1704 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1705 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1706 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1707 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1709 /* 802.11 HyperLan 2 */
1710 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1711 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1712 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1713 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1714 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1715 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1716 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1717 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1718 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1719 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1722 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1723 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1724 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1725 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1726 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1727 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1729 /* MMAC(Japan)J52 ch 34,38,42,46 */
1730 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1731 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1732 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1733 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1737 * RF value list for RF5225 & RF2527
1738 * Supports: 2.4 GHz & 5.2 GHz
1740 static const struct rf_channel rf_vals_5225_2527
[] = {
1741 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1742 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1743 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1744 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1745 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1746 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1747 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1748 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1749 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1750 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1751 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1752 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1753 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1754 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1756 /* 802.11 UNI / HyperLan 2 */
1757 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1758 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1759 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1760 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1761 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1762 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1763 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1764 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1766 /* 802.11 HyperLan 2 */
1767 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1768 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1769 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1770 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1771 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1772 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1773 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1774 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1775 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1776 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1779 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1780 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1781 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1782 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1783 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1784 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1786 /* MMAC(Japan)J52 ch 34,38,42,46 */
1787 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1788 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1789 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1790 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1794 static void rt73usb_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1796 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1801 * Initialize all hw fields.
1803 rt2x00dev
->hw
->flags
=
1804 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
1805 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1806 IEEE80211_HW_MONITOR_DURING_OPER
|
1807 IEEE80211_HW_NO_PROBE_FILTERING
;
1808 rt2x00dev
->hw
->extra_tx_headroom
= TXD_DESC_SIZE
;
1809 rt2x00dev
->hw
->max_signal
= MAX_SIGNAL
;
1810 rt2x00dev
->hw
->max_rssi
= MAX_RX_SSI
;
1811 rt2x00dev
->hw
->queues
= 5;
1813 SET_IEEE80211_DEV(rt2x00dev
->hw
, &rt2x00dev_usb(rt2x00dev
)->dev
);
1814 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1815 rt2x00_eeprom_addr(rt2x00dev
,
1816 EEPROM_MAC_ADDR_0
));
1819 * Convert tx_power array in eeprom.
1821 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
1822 for (i
= 0; i
< 14; i
++)
1823 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1826 * Initialize hw_mode information.
1828 spec
->num_modes
= 2;
1829 spec
->num_rates
= 12;
1830 spec
->tx_power_a
= NULL
;
1831 spec
->tx_power_bg
= txpower
;
1832 spec
->tx_power_default
= DEFAULT_TXPOWER
;
1834 if (rt2x00_rf(&rt2x00dev
->chip
, RF2528
)) {
1835 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2528
);
1836 spec
->channels
= rf_vals_bg_2528
;
1837 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5226
)) {
1838 spec
->num_channels
= ARRAY_SIZE(rf_vals_5226
);
1839 spec
->channels
= rf_vals_5226
;
1840 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2527
)) {
1841 spec
->num_channels
= 14;
1842 spec
->channels
= rf_vals_5225_2527
;
1843 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
)) {
1844 spec
->num_channels
= ARRAY_SIZE(rf_vals_5225_2527
);
1845 spec
->channels
= rf_vals_5225_2527
;
1848 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
1849 rt2x00_rf(&rt2x00dev
->chip
, RF5226
)) {
1850 spec
->num_modes
= 3;
1852 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
1853 for (i
= 0; i
< 14; i
++)
1854 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1856 spec
->tx_power_a
= txpower
;
1860 static int rt73usb_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1865 * Allocate eeprom data.
1867 retval
= rt73usb_validate_eeprom(rt2x00dev
);
1871 retval
= rt73usb_init_eeprom(rt2x00dev
);
1876 * Initialize hw specifications.
1878 rt73usb_probe_hw_mode(rt2x00dev
);
1881 * USB devices require scheduled packet filter toggling
1882 * This device requires firmware
1884 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
1885 __set_bit(PACKET_FILTER_SCHEDULED
, &rt2x00dev
->flags
);
1888 * Set the rssi offset.
1890 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1896 * IEEE80211 stack callback functions.
1898 static int rt73usb_set_retry_limit(struct ieee80211_hw
*hw
,
1899 u32 short_retry
, u32 long_retry
)
1901 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1904 rt73usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
1905 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
, long_retry
);
1906 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
, short_retry
);
1907 rt73usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
1914 * Mac80211 demands get_tsf must be atomic.
1915 * This is not possible for rt73usb since all register access
1916 * functions require sleeping. Untill mac80211 no longer needs
1917 * get_tsf to be atomic, this function should be disabled.
1919 static u64
rt73usb_get_tsf(struct ieee80211_hw
*hw
)
1921 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1925 rt73usb_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
1926 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
1927 rt73usb_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
1928 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
1934 static void rt73usb_reset_tsf(struct ieee80211_hw
*hw
)
1936 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1938 rt73usb_register_write(rt2x00dev
, TXRX_CSR12
, 0);
1939 rt73usb_register_write(rt2x00dev
, TXRX_CSR13
, 0);
1942 int rt73usb_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1943 struct ieee80211_tx_control
*control
)
1945 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1949 * Just in case the ieee80211 doesn't set this,
1950 * but we need this queue set for the descriptor
1953 control
->queue
= IEEE80211_TX_QUEUE_BEACON
;
1956 * First we create the beacon.
1958 skb_push(skb
, TXD_DESC_SIZE
);
1959 rt2x00lib_write_tx_desc(rt2x00dev
, (struct data_desc
*)skb
->data
,
1960 (struct ieee80211_hdr
*)(skb
->data
+
1962 skb
->len
- TXD_DESC_SIZE
, control
);
1965 * Write entire beacon with descriptor to register,
1966 * and kick the beacon generator.
1968 timeout
= REGISTER_TIMEOUT
* (skb
->len
/ sizeof(u32
));
1969 rt2x00usb_vendor_request(rt2x00dev
, USB_MULTI_WRITE
,
1970 USB_VENDOR_REQUEST_OUT
,
1971 HW_BEACON_BASE0
, 0x0000,
1972 skb
->data
, skb
->len
, timeout
);
1973 rt73usb_kick_tx_queue(rt2x00dev
, IEEE80211_TX_QUEUE_BEACON
);
1978 static const struct ieee80211_ops rt73usb_mac80211_ops
= {
1980 .add_interface
= rt2x00mac_add_interface
,
1981 .remove_interface
= rt2x00mac_remove_interface
,
1982 .config
= rt2x00mac_config
,
1983 .config_interface
= rt2x00mac_config_interface
,
1984 .set_multicast_list
= rt2x00mac_set_multicast_list
,
1985 .get_stats
= rt2x00mac_get_stats
,
1986 .set_retry_limit
= rt73usb_set_retry_limit
,
1987 .conf_tx
= rt2x00mac_conf_tx
,
1988 .get_tx_stats
= rt2x00mac_get_tx_stats
,
1991 * See comment at the rt73usb_get_tsf function.
1993 .get_tsf
= rt73usb_get_tsf
,
1995 .reset_tsf
= rt73usb_reset_tsf
,
1996 .beacon_update
= rt73usb_beacon_update
,
1999 static const struct rt2x00lib_ops rt73usb_rt2x00_ops
= {
2000 .probe_hw
= rt73usb_probe_hw
,
2001 .get_firmware_name
= rt73usb_get_firmware_name
,
2002 .load_firmware
= rt73usb_load_firmware
,
2003 .initialize
= rt2x00usb_initialize
,
2004 .uninitialize
= rt2x00usb_uninitialize
,
2005 .set_device_state
= rt73usb_set_device_state
,
2006 .link_stats
= rt73usb_link_stats
,
2007 .reset_tuner
= rt73usb_reset_tuner
,
2008 .link_tuner
= rt73usb_link_tuner
,
2009 .write_tx_desc
= rt73usb_write_tx_desc
,
2010 .write_tx_data
= rt2x00usb_write_tx_data
,
2011 .kick_tx_queue
= rt73usb_kick_tx_queue
,
2012 .fill_rxdone
= rt73usb_fill_rxdone
,
2013 .config_mac_addr
= rt73usb_config_mac_addr
,
2014 .config_bssid
= rt73usb_config_bssid
,
2015 .config_packet_filter
= rt73usb_config_packet_filter
,
2016 .config_type
= rt73usb_config_type
,
2017 .config
= rt73usb_config
,
2020 static const struct rt2x00_ops rt73usb_ops
= {
2022 .rxd_size
= RXD_DESC_SIZE
,
2023 .txd_size
= TXD_DESC_SIZE
,
2024 .eeprom_size
= EEPROM_SIZE
,
2026 .lib
= &rt73usb_rt2x00_ops
,
2027 .hw
= &rt73usb_mac80211_ops
,
2028 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2029 .debugfs
= &rt73usb_rt2x00debug
,
2030 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2034 * rt73usb module information.
2036 static struct usb_device_id rt73usb_device_table
[] = {
2038 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops
) },
2040 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops
) },
2042 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops
) },
2043 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops
) },
2045 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops
) },
2046 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops
) },
2047 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops
) },
2049 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops
) },
2051 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops
) },
2053 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops
) },
2054 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops
) },
2056 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops
) },
2058 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops
) },
2059 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops
) },
2061 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops
) },
2063 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops
) },
2064 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops
) },
2066 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops
) },
2068 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops
) },
2069 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops
) },
2071 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops
) },
2072 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops
) },
2074 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops
) },
2075 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops
) },
2076 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops
) },
2077 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops
) },
2079 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops
) },
2080 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops
) },
2082 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops
) },
2083 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops
) },
2084 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops
) },
2086 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops
) },
2088 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops
) },
2089 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops
) },
2091 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops
) },
2093 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops
) },
2094 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops
) },
2098 MODULE_AUTHOR(DRV_PROJECT
);
2099 MODULE_VERSION(DRV_VERSION
);
2100 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2101 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2102 MODULE_DEVICE_TABLE(usb
, rt73usb_device_table
);
2103 MODULE_FIRMWARE(FIRMWARE_RT2571
);
2104 MODULE_LICENSE("GPL");
2106 static struct usb_driver rt73usb_driver
= {
2108 .id_table
= rt73usb_device_table
,
2109 .probe
= rt2x00usb_probe
,
2110 .disconnect
= rt2x00usb_disconnect
,
2111 .suspend
= rt2x00usb_suspend
,
2112 .resume
= rt2x00usb_resume
,
2115 static int __init
rt73usb_init(void)
2117 return usb_register(&rt73usb_driver
);
2120 static void __exit
rt73usb_exit(void)
2122 usb_deregister(&rt73usb_driver
);
2125 module_init(rt73usb_init
);
2126 module_exit(rt73usb_exit
);