2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
36 #include "rt2x00usb.h"
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 * The _lock versions must be used if you already hold the usb_cache_mutex
53 static inline void rt73usb_register_read(struct rt2x00_dev
*rt2x00dev
,
54 const unsigned int offset
, u32
*value
)
57 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_READ
,
58 USB_VENDOR_REQUEST_IN
, offset
,
59 ®
, sizeof(u32
), REGISTER_TIMEOUT
);
60 *value
= le32_to_cpu(reg
);
63 static inline void rt73usb_register_read_lock(struct rt2x00_dev
*rt2x00dev
,
64 const unsigned int offset
, u32
*value
)
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev
, USB_MULTI_READ
,
68 USB_VENDOR_REQUEST_IN
, offset
,
69 ®
, sizeof(u32
), REGISTER_TIMEOUT
);
70 *value
= le32_to_cpu(reg
);
73 static inline void rt73usb_register_multiread(struct rt2x00_dev
*rt2x00dev
,
74 const unsigned int offset
,
75 void *value
, const u32 length
)
77 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_READ
,
78 USB_VENDOR_REQUEST_IN
, offset
,
80 REGISTER_TIMEOUT32(length
));
83 static inline void rt73usb_register_write(struct rt2x00_dev
*rt2x00dev
,
84 const unsigned int offset
, u32 value
)
86 __le32 reg
= cpu_to_le32(value
);
87 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_WRITE
,
88 USB_VENDOR_REQUEST_OUT
, offset
,
89 ®
, sizeof(u32
), REGISTER_TIMEOUT
);
92 static inline void rt73usb_register_write_lock(struct rt2x00_dev
*rt2x00dev
,
93 const unsigned int offset
, u32 value
)
95 __le32 reg
= cpu_to_le32(value
);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev
, USB_MULTI_WRITE
,
97 USB_VENDOR_REQUEST_OUT
, offset
,
98 ®
, sizeof(u32
), REGISTER_TIMEOUT
);
101 static inline void rt73usb_register_multiwrite(struct rt2x00_dev
*rt2x00dev
,
102 const unsigned int offset
,
103 void *value
, const u32 length
)
105 rt2x00usb_vendor_request_buff(rt2x00dev
, USB_MULTI_WRITE
,
106 USB_VENDOR_REQUEST_OUT
, offset
,
108 REGISTER_TIMEOUT32(length
));
111 static u32
rt73usb_bbp_check(struct rt2x00_dev
*rt2x00dev
)
116 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
117 rt73usb_register_read_lock(rt2x00dev
, PHY_CSR3
, ®
);
118 if (!rt2x00_get_field32(reg
, PHY_CSR3_BUSY
))
120 udelay(REGISTER_BUSY_DELAY
);
126 static void rt73usb_bbp_write(struct rt2x00_dev
*rt2x00dev
,
127 const unsigned int word
, const u8 value
)
131 mutex_lock(&rt2x00dev
->usb_cache_mutex
);
134 * Wait until the BBP becomes ready.
136 reg
= rt73usb_bbp_check(rt2x00dev
);
137 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
138 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Write failed.\n");
139 mutex_unlock(&rt2x00dev
->usb_cache_mutex
);
144 * Write the data into the BBP.
147 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
148 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
149 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
150 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
152 rt73usb_register_write_lock(rt2x00dev
, PHY_CSR3
, reg
);
153 mutex_unlock(&rt2x00dev
->usb_cache_mutex
);
156 static void rt73usb_bbp_read(struct rt2x00_dev
*rt2x00dev
,
157 const unsigned int word
, u8
*value
)
161 mutex_lock(&rt2x00dev
->usb_cache_mutex
);
164 * Wait until the BBP becomes ready.
166 reg
= rt73usb_bbp_check(rt2x00dev
);
167 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
168 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
169 mutex_unlock(&rt2x00dev
->usb_cache_mutex
);
174 * Write the request into the BBP.
177 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
178 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
179 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
181 rt73usb_register_write_lock(rt2x00dev
, PHY_CSR3
, reg
);
184 * Wait until the BBP becomes ready.
186 reg
= rt73usb_bbp_check(rt2x00dev
);
187 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
188 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
193 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
194 mutex_unlock(&rt2x00dev
->usb_cache_mutex
);
197 static void rt73usb_rf_write(struct rt2x00_dev
*rt2x00dev
,
198 const unsigned int word
, const u32 value
)
206 mutex_lock(&rt2x00dev
->usb_cache_mutex
);
208 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
209 rt73usb_register_read_lock(rt2x00dev
, PHY_CSR4
, ®
);
210 if (!rt2x00_get_field32(reg
, PHY_CSR4_BUSY
))
212 udelay(REGISTER_BUSY_DELAY
);
215 mutex_unlock(&rt2x00dev
->usb_cache_mutex
);
216 ERROR(rt2x00dev
, "PHY_CSR4 register busy. Write failed.\n");
221 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
224 * RF5225 and RF2527 contain 21 bits per RF register value,
225 * all others contain 20 bits.
227 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
,
228 20 + (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
229 rt2x00_rf(&rt2x00dev
->chip
, RF2527
)));
230 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
231 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
233 rt73usb_register_write_lock(rt2x00dev
, PHY_CSR4
, reg
);
234 rt2x00_rf_write(rt2x00dev
, word
, value
);
235 mutex_unlock(&rt2x00dev
->usb_cache_mutex
);
238 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
239 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
241 static void rt73usb_read_csr(struct rt2x00_dev
*rt2x00dev
,
242 const unsigned int word
, u32
*data
)
244 rt73usb_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
247 static void rt73usb_write_csr(struct rt2x00_dev
*rt2x00dev
,
248 const unsigned int word
, u32 data
)
250 rt73usb_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
253 static const struct rt2x00debug rt73usb_rt2x00debug
= {
254 .owner
= THIS_MODULE
,
256 .read
= rt73usb_read_csr
,
257 .write
= rt73usb_write_csr
,
258 .word_size
= sizeof(u32
),
259 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
262 .read
= rt2x00_eeprom_read
,
263 .write
= rt2x00_eeprom_write
,
264 .word_size
= sizeof(u16
),
265 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
268 .read
= rt73usb_bbp_read
,
269 .write
= rt73usb_bbp_write
,
270 .word_size
= sizeof(u8
),
271 .word_count
= BBP_SIZE
/ sizeof(u8
),
274 .read
= rt2x00_rf_read
,
275 .write
= rt73usb_rf_write
,
276 .word_size
= sizeof(u32
),
277 .word_count
= RF_SIZE
/ sizeof(u32
),
280 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
282 #ifdef CONFIG_RT73USB_LEDS
283 static void rt73usb_brightness_set(struct led_classdev
*led_cdev
,
284 enum led_brightness brightness
)
286 struct rt2x00_led
*led
=
287 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
288 unsigned int enabled
= brightness
!= LED_OFF
;
289 unsigned int a_mode
=
290 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
291 unsigned int bg_mode
=
292 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
294 if (led
->type
== LED_TYPE_RADIO
) {
295 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
296 MCU_LEDCS_RADIO_STATUS
, enabled
);
298 rt2x00usb_vendor_request_sw(led
->rt2x00dev
, USB_LED_CONTROL
,
299 0, led
->rt2x00dev
->led_mcu_reg
,
301 } else if (led
->type
== LED_TYPE_ASSOC
) {
302 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
303 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
304 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
305 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
307 rt2x00usb_vendor_request_sw(led
->rt2x00dev
, USB_LED_CONTROL
,
308 0, led
->rt2x00dev
->led_mcu_reg
,
310 } else if (led
->type
== LED_TYPE_QUALITY
) {
312 * The brightness is divided into 6 levels (0 - 5),
313 * this means we need to convert the brightness
314 * argument into the matching level within that range.
316 rt2x00usb_vendor_request_sw(led
->rt2x00dev
, USB_LED_CONTROL
,
317 brightness
/ (LED_FULL
/ 6),
318 led
->rt2x00dev
->led_mcu_reg
,
323 static int rt73usb_blink_set(struct led_classdev
*led_cdev
,
324 unsigned long *delay_on
,
325 unsigned long *delay_off
)
327 struct rt2x00_led
*led
=
328 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
331 rt73usb_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
332 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
333 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
334 rt73usb_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
338 #endif /* CONFIG_RT73USB_LEDS */
341 * Configuration handlers.
343 static void rt73usb_config_filter(struct rt2x00_dev
*rt2x00dev
,
344 const unsigned int filter_flags
)
349 * Start configuration steps.
350 * Note that the version error will always be dropped
351 * and broadcast frames will always be accepted since
352 * there is no filter for it at this time.
354 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
355 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
356 !(filter_flags
& FIF_FCSFAIL
));
357 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
358 !(filter_flags
& FIF_PLCPFAIL
));
359 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
360 !(filter_flags
& FIF_CONTROL
));
361 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
362 !(filter_flags
& FIF_PROMISC_IN_BSS
));
363 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
364 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
365 !rt2x00dev
->intf_ap_count
);
366 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
367 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
368 !(filter_flags
& FIF_ALLMULTI
));
369 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
370 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
371 !(filter_flags
& FIF_CONTROL
));
372 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
375 static void rt73usb_config_intf(struct rt2x00_dev
*rt2x00dev
,
376 struct rt2x00_intf
*intf
,
377 struct rt2x00intf_conf
*conf
,
378 const unsigned int flags
)
380 unsigned int beacon_base
;
383 if (flags
& CONFIG_UPDATE_TYPE
) {
385 * Clear current synchronisation setup.
386 * For the Beacon base registers we only need to clear
387 * the first byte since that byte contains the VALID and OWNER
388 * bits which (when set to 0) will invalidate the entire beacon.
390 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
391 rt73usb_register_write(rt2x00dev
, beacon_base
, 0);
394 * Enable synchronisation.
396 rt73usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
397 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
398 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
399 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
400 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
403 if (flags
& CONFIG_UPDATE_MAC
) {
404 reg
= le32_to_cpu(conf
->mac
[1]);
405 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
406 conf
->mac
[1] = cpu_to_le32(reg
);
408 rt73usb_register_multiwrite(rt2x00dev
, MAC_CSR2
,
409 conf
->mac
, sizeof(conf
->mac
));
412 if (flags
& CONFIG_UPDATE_BSSID
) {
413 reg
= le32_to_cpu(conf
->bssid
[1]);
414 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
415 conf
->bssid
[1] = cpu_to_le32(reg
);
417 rt73usb_register_multiwrite(rt2x00dev
, MAC_CSR4
,
418 conf
->bssid
, sizeof(conf
->bssid
));
422 static void rt73usb_config_erp(struct rt2x00_dev
*rt2x00dev
,
423 struct rt2x00lib_erp
*erp
)
427 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
428 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, erp
->ack_timeout
);
429 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
431 rt73usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
432 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
433 !!erp
->short_preamble
);
434 rt73usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
437 static void rt73usb_config_phymode(struct rt2x00_dev
*rt2x00dev
,
438 const int basic_rate_mask
)
440 rt73usb_register_write(rt2x00dev
, TXRX_CSR5
, basic_rate_mask
);
443 static void rt73usb_config_channel(struct rt2x00_dev
*rt2x00dev
,
444 struct rf_channel
*rf
, const int txpower
)
450 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
451 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
453 smart
= !(rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
454 rt2x00_rf(&rt2x00dev
->chip
, RF2527
));
456 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
457 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
458 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
461 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
462 r94
+= txpower
- MAX_TXPOWER
;
463 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
465 rt73usb_bbp_write(rt2x00dev
, 94, r94
);
467 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
468 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
469 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
470 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
472 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
473 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
474 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
475 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
477 rt73usb_rf_write(rt2x00dev
, 1, rf
->rf1
);
478 rt73usb_rf_write(rt2x00dev
, 2, rf
->rf2
);
479 rt73usb_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
480 rt73usb_rf_write(rt2x00dev
, 4, rf
->rf4
);
485 static void rt73usb_config_txpower(struct rt2x00_dev
*rt2x00dev
,
488 struct rf_channel rf
;
490 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
491 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
492 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
493 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
495 rt73usb_config_channel(rt2x00dev
, &rf
, txpower
);
498 static void rt73usb_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
499 struct antenna_setup
*ant
)
506 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
507 rt73usb_bbp_read(rt2x00dev
, 4, &r4
);
508 rt73usb_bbp_read(rt2x00dev
, 77, &r77
);
510 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, 0);
513 * Configure the RX antenna.
516 case ANTENNA_HW_DIVERSITY
:
517 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
518 temp
= !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
)
519 && (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
);
520 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, temp
);
523 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
524 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
525 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
526 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
528 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
532 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
533 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
534 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
535 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
537 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
541 rt73usb_bbp_write(rt2x00dev
, 77, r77
);
542 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
543 rt73usb_bbp_write(rt2x00dev
, 4, r4
);
546 static void rt73usb_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
547 struct antenna_setup
*ant
)
553 rt73usb_bbp_read(rt2x00dev
, 3, &r3
);
554 rt73usb_bbp_read(rt2x00dev
, 4, &r4
);
555 rt73usb_bbp_read(rt2x00dev
, 77, &r77
);
557 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, 0);
558 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
559 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
562 * Configure the RX antenna.
565 case ANTENNA_HW_DIVERSITY
:
566 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
569 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
570 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
574 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
575 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
579 rt73usb_bbp_write(rt2x00dev
, 77, r77
);
580 rt73usb_bbp_write(rt2x00dev
, 3, r3
);
581 rt73usb_bbp_write(rt2x00dev
, 4, r4
);
587 * value[0] -> non-LNA
593 static const struct antenna_sel antenna_sel_a
[] = {
594 { 96, { 0x58, 0x78 } },
595 { 104, { 0x38, 0x48 } },
596 { 75, { 0xfe, 0x80 } },
597 { 86, { 0xfe, 0x80 } },
598 { 88, { 0xfe, 0x80 } },
599 { 35, { 0x60, 0x60 } },
600 { 97, { 0x58, 0x58 } },
601 { 98, { 0x58, 0x58 } },
604 static const struct antenna_sel antenna_sel_bg
[] = {
605 { 96, { 0x48, 0x68 } },
606 { 104, { 0x2c, 0x3c } },
607 { 75, { 0xfe, 0x80 } },
608 { 86, { 0xfe, 0x80 } },
609 { 88, { 0xfe, 0x80 } },
610 { 35, { 0x50, 0x50 } },
611 { 97, { 0x48, 0x48 } },
612 { 98, { 0x48, 0x48 } },
615 static void rt73usb_config_antenna(struct rt2x00_dev
*rt2x00dev
,
616 struct antenna_setup
*ant
)
618 const struct antenna_sel
*sel
;
624 * We should never come here because rt2x00lib is supposed
625 * to catch this and send us the correct antenna explicitely.
627 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
628 ant
->tx
== ANTENNA_SW_DIVERSITY
);
630 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
632 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
634 sel
= antenna_sel_bg
;
635 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
638 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
639 rt73usb_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
641 rt73usb_register_read(rt2x00dev
, PHY_CSR0
, ®
);
643 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
644 (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
));
645 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
646 (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
));
648 rt73usb_register_write(rt2x00dev
, PHY_CSR0
, reg
);
650 if (rt2x00_rf(&rt2x00dev
->chip
, RF5226
) ||
651 rt2x00_rf(&rt2x00dev
->chip
, RF5225
))
652 rt73usb_config_antenna_5x(rt2x00dev
, ant
);
653 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2528
) ||
654 rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
655 rt73usb_config_antenna_2x(rt2x00dev
, ant
);
658 static void rt73usb_config_duration(struct rt2x00_dev
*rt2x00dev
,
659 struct rt2x00lib_conf
*libconf
)
663 rt73usb_register_read(rt2x00dev
, MAC_CSR9
, ®
);
664 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, libconf
->slot_time
);
665 rt73usb_register_write(rt2x00dev
, MAC_CSR9
, reg
);
667 rt73usb_register_read(rt2x00dev
, MAC_CSR8
, ®
);
668 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, libconf
->sifs
);
669 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
670 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, libconf
->eifs
);
671 rt73usb_register_write(rt2x00dev
, MAC_CSR8
, reg
);
673 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
674 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
675 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
677 rt73usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
678 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
679 rt73usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
681 rt73usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
682 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
683 libconf
->conf
->beacon_int
* 16);
684 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
687 static void rt73usb_config(struct rt2x00_dev
*rt2x00dev
,
688 struct rt2x00lib_conf
*libconf
,
689 const unsigned int flags
)
691 if (flags
& CONFIG_UPDATE_PHYMODE
)
692 rt73usb_config_phymode(rt2x00dev
, libconf
->basic_rates
);
693 if (flags
& CONFIG_UPDATE_CHANNEL
)
694 rt73usb_config_channel(rt2x00dev
, &libconf
->rf
,
695 libconf
->conf
->power_level
);
696 if ((flags
& CONFIG_UPDATE_TXPOWER
) && !(flags
& CONFIG_UPDATE_CHANNEL
))
697 rt73usb_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
698 if (flags
& CONFIG_UPDATE_ANTENNA
)
699 rt73usb_config_antenna(rt2x00dev
, &libconf
->ant
);
700 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
701 rt73usb_config_duration(rt2x00dev
, libconf
);
707 static void rt73usb_link_stats(struct rt2x00_dev
*rt2x00dev
,
708 struct link_qual
*qual
)
713 * Update FCS error count from register.
715 rt73usb_register_read(rt2x00dev
, STA_CSR0
, ®
);
716 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
719 * Update False CCA count from register.
721 rt73usb_register_read(rt2x00dev
, STA_CSR1
, ®
);
722 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
725 static void rt73usb_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
727 rt73usb_bbp_write(rt2x00dev
, 17, 0x20);
728 rt2x00dev
->link
.vgc_level
= 0x20;
731 static void rt73usb_link_tuner(struct rt2x00_dev
*rt2x00dev
)
733 int rssi
= rt2x00_get_link_rssi(&rt2x00dev
->link
);
738 rt73usb_bbp_read(rt2x00dev
, 17, &r17
);
741 * Determine r17 bounds.
743 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
747 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
755 } else if (rssi
> -84) {
763 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
770 * If we are not associated, we should go straight to the
771 * dynamic CCA tuning.
773 if (!rt2x00dev
->intf_associated
)
774 goto dynamic_cca_tune
;
777 * Special big-R17 for very short distance
781 rt73usb_bbp_write(rt2x00dev
, 17, 0x60);
786 * Special big-R17 for short distance
790 rt73usb_bbp_write(rt2x00dev
, 17, up_bound
);
795 * Special big-R17 for middle-short distance
799 if (r17
!= low_bound
)
800 rt73usb_bbp_write(rt2x00dev
, 17, low_bound
);
805 * Special mid-R17 for middle distance
808 if (r17
!= (low_bound
+ 0x10))
809 rt73usb_bbp_write(rt2x00dev
, 17, low_bound
+ 0x08);
814 * Special case: Change up_bound based on the rssi.
815 * Lower up_bound when rssi is weaker then -74 dBm.
817 up_bound
-= 2 * (-74 - rssi
);
818 if (low_bound
> up_bound
)
819 up_bound
= low_bound
;
821 if (r17
> up_bound
) {
822 rt73usb_bbp_write(rt2x00dev
, 17, up_bound
);
829 * r17 does not yet exceed upper limit, continue and base
830 * the r17 tuning on the false CCA count.
832 if (rt2x00dev
->link
.qual
.false_cca
> 512 && r17
< up_bound
) {
836 rt73usb_bbp_write(rt2x00dev
, 17, r17
);
837 } else if (rt2x00dev
->link
.qual
.false_cca
< 100 && r17
> low_bound
) {
841 rt73usb_bbp_write(rt2x00dev
, 17, r17
);
848 static char *rt73usb_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
850 return FIRMWARE_RT2571
;
853 static u16
rt73usb_get_firmware_crc(void *data
, const size_t len
)
858 * Use the crc itu-t algorithm.
859 * The last 2 bytes in the firmware array are the crc checksum itself,
860 * this means that we should never pass those 2 bytes to the crc
863 crc
= crc_itu_t(0, data
, len
- 2);
864 crc
= crc_itu_t_byte(crc
, 0);
865 crc
= crc_itu_t_byte(crc
, 0);
870 static int rt73usb_load_firmware(struct rt2x00_dev
*rt2x00dev
, void *data
,
881 * Wait for stable hardware.
883 for (i
= 0; i
< 100; i
++) {
884 rt73usb_register_read(rt2x00dev
, MAC_CSR0
, ®
);
891 ERROR(rt2x00dev
, "Unstable hardware.\n");
896 * Write firmware to device.
897 * We setup a seperate cache for this action,
898 * since we are going to write larger chunks of data
899 * then normally used cache size.
901 cache
= kmalloc(CSR_CACHE_SIZE_FIRMWARE
, GFP_KERNEL
);
903 ERROR(rt2x00dev
, "Failed to allocate firmware cache.\n");
907 for (i
= 0; i
< len
; i
+= CSR_CACHE_SIZE_FIRMWARE
) {
908 buflen
= min_t(int, len
- i
, CSR_CACHE_SIZE_FIRMWARE
);
910 memcpy(cache
, ptr
, buflen
);
912 rt2x00usb_vendor_request(rt2x00dev
, USB_MULTI_WRITE
,
913 USB_VENDOR_REQUEST_OUT
,
914 FIRMWARE_IMAGE_BASE
+ i
, 0,
916 REGISTER_TIMEOUT32(buflen
));
924 * Send firmware request to device to load firmware,
925 * we need to specify a long timeout time.
927 status
= rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
,
928 0, USB_MODE_FIRMWARE
,
929 REGISTER_TIMEOUT_FIRMWARE
);
931 ERROR(rt2x00dev
, "Failed to write Firmware to device.\n");
939 * Initialization functions.
941 static int rt73usb_init_registers(struct rt2x00_dev
*rt2x00dev
)
945 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
946 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
947 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
948 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
949 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
951 rt73usb_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
952 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
953 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
954 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
955 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
956 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
957 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
958 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
959 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
960 rt73usb_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
963 * CCK TXD BBP registers
965 rt73usb_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
966 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
967 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
968 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
969 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
970 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
971 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
972 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
973 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
974 rt73usb_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
977 * OFDM TXD BBP registers
979 rt73usb_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
980 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
981 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
982 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
983 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
984 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
985 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
986 rt73usb_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
988 rt73usb_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
989 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
990 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
991 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
992 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
993 rt73usb_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
995 rt73usb_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
996 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
997 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
998 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
999 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1000 rt73usb_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1002 rt73usb_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1004 rt73usb_register_read(rt2x00dev
, MAC_CSR6
, ®
);
1005 rt2x00_set_field32(®
, MAC_CSR6_MAX_FRAME_UNIT
, 0xfff);
1006 rt73usb_register_write(rt2x00dev
, MAC_CSR6
, reg
);
1008 rt73usb_register_write(rt2x00dev
, MAC_CSR10
, 0x00000718);
1010 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1013 rt73usb_register_write(rt2x00dev
, MAC_CSR13
, 0x00007f00);
1016 * Invalidate all Shared Keys (SEC_CSR0),
1017 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1019 rt73usb_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1020 rt73usb_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1021 rt73usb_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1024 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
1025 rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
1026 rt2x00_set_field32(®
, PHY_CSR1_RF_RPI
, 1);
1027 rt73usb_register_write(rt2x00dev
, PHY_CSR1
, reg
);
1029 rt73usb_register_write(rt2x00dev
, PHY_CSR5
, 0x00040a06);
1030 rt73usb_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1031 rt73usb_register_write(rt2x00dev
, PHY_CSR7
, 0x00000408);
1033 rt73usb_register_read(rt2x00dev
, AC_TXOP_CSR0
, ®
);
1034 rt2x00_set_field32(®
, AC_TXOP_CSR0_AC0_TX_OP
, 0);
1035 rt2x00_set_field32(®
, AC_TXOP_CSR0_AC1_TX_OP
, 0);
1036 rt73usb_register_write(rt2x00dev
, AC_TXOP_CSR0
, reg
);
1038 rt73usb_register_read(rt2x00dev
, AC_TXOP_CSR1
, ®
);
1039 rt2x00_set_field32(®
, AC_TXOP_CSR1_AC2_TX_OP
, 192);
1040 rt2x00_set_field32(®
, AC_TXOP_CSR1_AC3_TX_OP
, 48);
1041 rt73usb_register_write(rt2x00dev
, AC_TXOP_CSR1
, reg
);
1043 rt73usb_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1044 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1045 rt73usb_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1049 * For the Beacon base registers we only need to clear
1050 * the first byte since that byte contains the VALID and OWNER
1051 * bits which (when set to 0) will invalidate the entire beacon.
1053 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1054 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1055 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1056 rt73usb_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1059 * We must clear the error counters.
1060 * These registers are cleared on read,
1061 * so we may pass a useless variable to store the value.
1063 rt73usb_register_read(rt2x00dev
, STA_CSR0
, ®
);
1064 rt73usb_register_read(rt2x00dev
, STA_CSR1
, ®
);
1065 rt73usb_register_read(rt2x00dev
, STA_CSR2
, ®
);
1068 * Reset MAC and BBP registers.
1070 rt73usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1071 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1072 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1073 rt73usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1075 rt73usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1076 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1077 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1078 rt73usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1080 rt73usb_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1081 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1082 rt73usb_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1087 static int rt73usb_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1094 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1095 rt73usb_bbp_read(rt2x00dev
, 0, &value
);
1096 if ((value
!= 0xff) && (value
!= 0x00))
1097 goto continue_csr_init
;
1098 NOTICE(rt2x00dev
, "Waiting for BBP register.\n");
1099 udelay(REGISTER_BUSY_DELAY
);
1102 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1106 rt73usb_bbp_write(rt2x00dev
, 3, 0x80);
1107 rt73usb_bbp_write(rt2x00dev
, 15, 0x30);
1108 rt73usb_bbp_write(rt2x00dev
, 21, 0xc8);
1109 rt73usb_bbp_write(rt2x00dev
, 22, 0x38);
1110 rt73usb_bbp_write(rt2x00dev
, 23, 0x06);
1111 rt73usb_bbp_write(rt2x00dev
, 24, 0xfe);
1112 rt73usb_bbp_write(rt2x00dev
, 25, 0x0a);
1113 rt73usb_bbp_write(rt2x00dev
, 26, 0x0d);
1114 rt73usb_bbp_write(rt2x00dev
, 32, 0x0b);
1115 rt73usb_bbp_write(rt2x00dev
, 34, 0x12);
1116 rt73usb_bbp_write(rt2x00dev
, 37, 0x07);
1117 rt73usb_bbp_write(rt2x00dev
, 39, 0xf8);
1118 rt73usb_bbp_write(rt2x00dev
, 41, 0x60);
1119 rt73usb_bbp_write(rt2x00dev
, 53, 0x10);
1120 rt73usb_bbp_write(rt2x00dev
, 54, 0x18);
1121 rt73usb_bbp_write(rt2x00dev
, 60, 0x10);
1122 rt73usb_bbp_write(rt2x00dev
, 61, 0x04);
1123 rt73usb_bbp_write(rt2x00dev
, 62, 0x04);
1124 rt73usb_bbp_write(rt2x00dev
, 75, 0xfe);
1125 rt73usb_bbp_write(rt2x00dev
, 86, 0xfe);
1126 rt73usb_bbp_write(rt2x00dev
, 88, 0xfe);
1127 rt73usb_bbp_write(rt2x00dev
, 90, 0x0f);
1128 rt73usb_bbp_write(rt2x00dev
, 99, 0x00);
1129 rt73usb_bbp_write(rt2x00dev
, 102, 0x16);
1130 rt73usb_bbp_write(rt2x00dev
, 107, 0x04);
1132 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1133 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1135 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1136 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1137 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1138 rt73usb_bbp_write(rt2x00dev
, reg_id
, value
);
1146 * Device state switch handlers.
1148 static void rt73usb_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1149 enum dev_state state
)
1153 rt73usb_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1154 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1155 state
== STATE_RADIO_RX_OFF
);
1156 rt73usb_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1159 static int rt73usb_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1162 * Initialize all registers.
1164 if (rt73usb_init_registers(rt2x00dev
) ||
1165 rt73usb_init_bbp(rt2x00dev
)) {
1166 ERROR(rt2x00dev
, "Register initialization failed.\n");
1173 static void rt73usb_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1175 rt73usb_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1178 * Disable synchronisation.
1180 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1182 rt2x00usb_disable_radio(rt2x00dev
);
1185 static int rt73usb_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1192 put_to_sleep
= (state
!= STATE_AWAKE
);
1194 rt73usb_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1195 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1196 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1197 rt73usb_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1200 * Device is not guaranteed to be in the requested state yet.
1201 * We must wait until the register indicates that the
1202 * device has entered the correct state.
1204 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1205 rt73usb_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1207 rt2x00_get_field32(reg
, MAC_CSR12_BBP_CURRENT_STATE
);
1208 if (current_state
== !put_to_sleep
)
1213 NOTICE(rt2x00dev
, "Device failed to enter state %d, "
1214 "current device state %d.\n", !put_to_sleep
, current_state
);
1219 static int rt73usb_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1220 enum dev_state state
)
1225 case STATE_RADIO_ON
:
1226 retval
= rt73usb_enable_radio(rt2x00dev
);
1228 case STATE_RADIO_OFF
:
1229 rt73usb_disable_radio(rt2x00dev
);
1231 case STATE_RADIO_RX_ON
:
1232 case STATE_RADIO_RX_ON_LINK
:
1233 rt73usb_toggle_rx(rt2x00dev
, STATE_RADIO_RX_ON
);
1235 case STATE_RADIO_RX_OFF
:
1236 case STATE_RADIO_RX_OFF_LINK
:
1237 rt73usb_toggle_rx(rt2x00dev
, STATE_RADIO_RX_OFF
);
1239 case STATE_DEEP_SLEEP
:
1243 retval
= rt73usb_set_state(rt2x00dev
, state
);
1254 * TX descriptor initialization
1256 static void rt73usb_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1257 struct sk_buff
*skb
,
1258 struct txentry_desc
*txdesc
,
1259 struct ieee80211_tx_control
*control
)
1261 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1262 __le32
*txd
= skbdesc
->desc
;
1266 * Start writing the descriptor words.
1268 rt2x00_desc_read(txd
, 1, &word
);
1269 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1270 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1271 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1272 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1273 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, IEEE80211_HEADER
);
1274 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
, 1);
1275 rt2x00_desc_write(txd
, 1, word
);
1277 rt2x00_desc_read(txd
, 2, &word
);
1278 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1279 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1280 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1281 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1282 rt2x00_desc_write(txd
, 2, word
);
1284 rt2x00_desc_read(txd
, 5, &word
);
1285 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1286 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1287 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1288 rt2x00_desc_write(txd
, 5, word
);
1290 rt2x00_desc_read(txd
, 0, &word
);
1291 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1292 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1293 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1294 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1295 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1296 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1297 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1298 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1299 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1300 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1301 test_bit(ENTRY_TXD_OFDM_RATE
, &txdesc
->flags
));
1302 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1303 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1305 IEEE80211_TXCTL_LONG_RETRY_LIMIT
));
1306 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
, 0);
1307 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skbdesc
->data_len
);
1308 rt2x00_set_field32(&word
, TXD_W0_BURST2
,
1309 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1310 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, CIPHER_NONE
);
1311 rt2x00_desc_write(txd
, 0, word
);
1314 static int rt73usb_get_tx_data_len(struct rt2x00_dev
*rt2x00dev
,
1315 struct sk_buff
*skb
)
1320 * The length _must_ be a multiple of 4,
1321 * but it must _not_ be a multiple of the USB packet size.
1323 length
= roundup(skb
->len
, 4);
1324 length
+= (4 * !(length
% rt2x00dev
->usb_maxpacket
));
1330 * TX data initialization
1332 static void rt73usb_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1333 const enum data_queue_qid queue
)
1337 if (queue
!= QID_BEACON
)
1341 * For Wi-Fi faily generated beacons between participating stations.
1342 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1344 rt73usb_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1346 rt73usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1347 if (!rt2x00_get_field32(reg
, TXRX_CSR9_BEACON_GEN
)) {
1348 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1349 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1350 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1351 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1356 * RX control handlers
1358 static int rt73usb_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1364 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1379 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1380 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1381 if (lna
== 3 || lna
== 2)
1390 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
1391 offset
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
1393 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
1396 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
1397 offset
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
1400 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1403 static void rt73usb_fill_rxdone(struct queue_entry
*entry
,
1404 struct rxdone_entry_desc
*rxdesc
)
1406 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1407 __le32
*rxd
= (__le32
*)entry
->skb
->data
;
1408 unsigned int offset
= entry
->queue
->desc_size
+ 2;
1413 * Copy descriptor to the available headroom inside the skbuffer.
1415 skb_push(entry
->skb
, offset
);
1416 memcpy(entry
->skb
->data
, rxd
, entry
->queue
->desc_size
);
1417 rxd
= (__le32
*)entry
->skb
->data
;
1420 * The descriptor is now aligned to 4 bytes and thus it is
1421 * now safe to read it on all architectures.
1423 rt2x00_desc_read(rxd
, 0, &word0
);
1424 rt2x00_desc_read(rxd
, 1, &word1
);
1427 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1428 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1431 * Obtain the status about this packet.
1432 * When frame was received with an OFDM bitrate,
1433 * the signal is the PLCP value. If it was received with
1434 * a CCK bitrate the signal is the rate in 100kbit/s.
1436 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
1437 rxdesc
->rssi
= rt73usb_agc_to_rssi(entry
->queue
->rt2x00dev
, word1
);
1438 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1440 rxdesc
->dev_flags
= 0;
1441 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
1442 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
1443 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1444 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1447 * Adjust the skb memory window to the frame boundaries.
1449 skb_pull(entry
->skb
, offset
+ entry
->queue
->desc_size
);
1450 skb_trim(entry
->skb
, rxdesc
->size
);
1453 * Set descriptor and data pointer.
1455 skbdesc
->data
= entry
->skb
->data
;
1456 skbdesc
->data_len
= rxdesc
->size
;
1457 skbdesc
->desc
= rxd
;
1458 skbdesc
->desc_len
= entry
->queue
->desc_size
;
1462 * Device probe functions.
1464 static int rt73usb_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1470 rt2x00usb_eeprom_read(rt2x00dev
, rt2x00dev
->eeprom
, EEPROM_SIZE
);
1473 * Start validation of the data that has been read.
1475 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1476 if (!is_valid_ether_addr(mac
)) {
1477 DECLARE_MAC_BUF(macbuf
);
1479 random_ether_addr(mac
);
1480 EEPROM(rt2x00dev
, "MAC: %s\n", print_mac(macbuf
, mac
));
1483 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1484 if (word
== 0xffff) {
1485 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1486 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
1488 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
1490 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
1491 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1492 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1493 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5226
);
1494 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1495 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1498 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1499 if (word
== 0xffff) {
1500 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA
, 0);
1501 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1502 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1505 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
1506 if (word
== 0xffff) {
1507 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_RDY_G
, 0);
1508 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_RDY_A
, 0);
1509 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_ACT
, 0);
1510 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_0
, 0);
1511 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_1
, 0);
1512 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_2
, 0);
1513 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_3
, 0);
1514 rt2x00_set_field16(&word
, EEPROM_LED_POLARITY_GPIO_4
, 0);
1515 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
1517 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
1518 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
1521 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
1522 if (word
== 0xffff) {
1523 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
1524 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
1525 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
1526 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
1529 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
1530 if (word
== 0xffff) {
1531 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1532 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1533 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1534 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
1536 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
1537 if (value
< -10 || value
> 10)
1538 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1539 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
1540 if (value
< -10 || value
> 10)
1541 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1542 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1545 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
1546 if (word
== 0xffff) {
1547 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1548 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1549 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
1550 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
1552 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
1553 if (value
< -10 || value
> 10)
1554 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1555 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
1556 if (value
< -10 || value
> 10)
1557 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1558 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
1564 static int rt73usb_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1571 * Read EEPROM word for configuration.
1573 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1576 * Identify RF chipset.
1578 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1579 rt73usb_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1580 rt2x00_set_chip(rt2x00dev
, RT2571
, value
, reg
);
1582 if (!rt2x00_check_rev(&rt2x00dev
->chip
, 0x25730)) {
1583 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
1587 if (!rt2x00_rf(&rt2x00dev
->chip
, RF5226
) &&
1588 !rt2x00_rf(&rt2x00dev
->chip
, RF2528
) &&
1589 !rt2x00_rf(&rt2x00dev
->chip
, RF5225
) &&
1590 !rt2x00_rf(&rt2x00dev
->chip
, RF2527
)) {
1591 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1596 * Identify default antenna configuration.
1598 rt2x00dev
->default_ant
.tx
=
1599 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1600 rt2x00dev
->default_ant
.rx
=
1601 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1604 * Read the Frame type.
1606 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
1607 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
1610 * Read frequency offset.
1612 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1613 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
1616 * Read external LNA informations.
1618 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1620 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA
)) {
1621 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
1622 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
1626 * Store led settings, for correct led behaviour.
1628 #ifdef CONFIG_RT73USB_LEDS
1629 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
1631 rt2x00dev
->led_radio
.rt2x00dev
= rt2x00dev
;
1632 rt2x00dev
->led_radio
.type
= LED_TYPE_RADIO
;
1633 rt2x00dev
->led_radio
.led_dev
.brightness_set
=
1634 rt73usb_brightness_set
;
1635 rt2x00dev
->led_radio
.led_dev
.blink_set
=
1637 rt2x00dev
->led_radio
.flags
= LED_INITIALIZED
;
1639 rt2x00dev
->led_assoc
.rt2x00dev
= rt2x00dev
;
1640 rt2x00dev
->led_assoc
.type
= LED_TYPE_ASSOC
;
1641 rt2x00dev
->led_assoc
.led_dev
.brightness_set
=
1642 rt73usb_brightness_set
;
1643 rt2x00dev
->led_assoc
.led_dev
.blink_set
=
1645 rt2x00dev
->led_assoc
.flags
= LED_INITIALIZED
;
1647 if (value
== LED_MODE_SIGNAL_STRENGTH
) {
1648 rt2x00dev
->led_qual
.rt2x00dev
= rt2x00dev
;
1649 rt2x00dev
->led_qual
.type
= LED_TYPE_QUALITY
;
1650 rt2x00dev
->led_qual
.led_dev
.brightness_set
=
1651 rt73usb_brightness_set
;
1652 rt2x00dev
->led_qual
.led_dev
.blink_set
=
1654 rt2x00dev
->led_qual
.flags
= LED_INITIALIZED
;
1657 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
1658 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
1659 rt2x00_get_field16(eeprom
,
1660 EEPROM_LED_POLARITY_GPIO_0
));
1661 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
1662 rt2x00_get_field16(eeprom
,
1663 EEPROM_LED_POLARITY_GPIO_1
));
1664 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
1665 rt2x00_get_field16(eeprom
,
1666 EEPROM_LED_POLARITY_GPIO_2
));
1667 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
1668 rt2x00_get_field16(eeprom
,
1669 EEPROM_LED_POLARITY_GPIO_3
));
1670 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
1671 rt2x00_get_field16(eeprom
,
1672 EEPROM_LED_POLARITY_GPIO_4
));
1673 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
1674 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
1675 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
1676 rt2x00_get_field16(eeprom
,
1677 EEPROM_LED_POLARITY_RDY_G
));
1678 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
1679 rt2x00_get_field16(eeprom
,
1680 EEPROM_LED_POLARITY_RDY_A
));
1681 #endif /* CONFIG_RT73USB_LEDS */
1687 * RF value list for RF2528
1690 static const struct rf_channel rf_vals_bg_2528
[] = {
1691 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1692 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1693 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1694 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1695 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1696 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1697 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1698 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1699 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1700 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1701 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1702 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1703 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1704 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1708 * RF value list for RF5226
1709 * Supports: 2.4 GHz & 5.2 GHz
1711 static const struct rf_channel rf_vals_5226
[] = {
1712 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1713 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1714 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1715 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1716 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1717 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1718 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1719 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1720 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1721 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1722 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1723 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1724 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1725 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1727 /* 802.11 UNI / HyperLan 2 */
1728 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1729 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1730 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1731 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1732 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1733 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1734 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1735 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1737 /* 802.11 HyperLan 2 */
1738 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1739 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1740 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1741 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1742 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1743 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1744 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1745 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1746 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1747 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1750 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1751 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1752 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1753 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1754 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1755 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1757 /* MMAC(Japan)J52 ch 34,38,42,46 */
1758 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1759 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1760 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1761 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1765 * RF value list for RF5225 & RF2527
1766 * Supports: 2.4 GHz & 5.2 GHz
1768 static const struct rf_channel rf_vals_5225_2527
[] = {
1769 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1770 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1771 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1772 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1773 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1774 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1775 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1776 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1777 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1778 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1779 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1780 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1781 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1782 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1784 /* 802.11 UNI / HyperLan 2 */
1785 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1786 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1787 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1788 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1789 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1790 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1791 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1792 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1794 /* 802.11 HyperLan 2 */
1795 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1796 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1797 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1798 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1799 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1800 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1801 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1802 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1803 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1804 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1807 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1808 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1809 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1810 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1811 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1812 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1814 /* MMAC(Japan)J52 ch 34,38,42,46 */
1815 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1816 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1817 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1818 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1822 static void rt73usb_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1824 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1829 * Initialize all hw fields.
1831 rt2x00dev
->hw
->flags
=
1832 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
1833 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1834 IEEE80211_HW_SIGNAL_DBM
;
1835 rt2x00dev
->hw
->extra_tx_headroom
= TXD_DESC_SIZE
;
1836 rt2x00dev
->hw
->queues
= 4;
1838 SET_IEEE80211_DEV(rt2x00dev
->hw
, &rt2x00dev_usb(rt2x00dev
)->dev
);
1839 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1840 rt2x00_eeprom_addr(rt2x00dev
,
1841 EEPROM_MAC_ADDR_0
));
1844 * Convert tx_power array in eeprom.
1846 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
1847 for (i
= 0; i
< 14; i
++)
1848 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1851 * Initialize hw_mode information.
1853 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
1854 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
1855 spec
->tx_power_a
= NULL
;
1856 spec
->tx_power_bg
= txpower
;
1857 spec
->tx_power_default
= DEFAULT_TXPOWER
;
1859 if (rt2x00_rf(&rt2x00dev
->chip
, RF2528
)) {
1860 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2528
);
1861 spec
->channels
= rf_vals_bg_2528
;
1862 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5226
)) {
1863 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
1864 spec
->num_channels
= ARRAY_SIZE(rf_vals_5226
);
1865 spec
->channels
= rf_vals_5226
;
1866 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2527
)) {
1867 spec
->num_channels
= 14;
1868 spec
->channels
= rf_vals_5225_2527
;
1869 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
)) {
1870 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
1871 spec
->num_channels
= ARRAY_SIZE(rf_vals_5225_2527
);
1872 spec
->channels
= rf_vals_5225_2527
;
1875 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
1876 rt2x00_rf(&rt2x00dev
->chip
, RF5226
)) {
1877 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
1878 for (i
= 0; i
< 14; i
++)
1879 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1881 spec
->tx_power_a
= txpower
;
1885 static int rt73usb_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1890 * Allocate eeprom data.
1892 retval
= rt73usb_validate_eeprom(rt2x00dev
);
1896 retval
= rt73usb_init_eeprom(rt2x00dev
);
1901 * Initialize hw specifications.
1903 rt73usb_probe_hw_mode(rt2x00dev
);
1906 * This device requires firmware.
1908 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
1909 __set_bit(DRIVER_REQUIRE_SCHEDULED
, &rt2x00dev
->flags
);
1912 * Set the rssi offset.
1914 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1920 * IEEE80211 stack callback functions.
1922 static int rt73usb_set_retry_limit(struct ieee80211_hw
*hw
,
1923 u32 short_retry
, u32 long_retry
)
1925 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1928 rt73usb_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
1929 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
, long_retry
);
1930 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
, short_retry
);
1931 rt73usb_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
1938 * Mac80211 demands get_tsf must be atomic.
1939 * This is not possible for rt73usb since all register access
1940 * functions require sleeping. Untill mac80211 no longer needs
1941 * get_tsf to be atomic, this function should be disabled.
1943 static u64
rt73usb_get_tsf(struct ieee80211_hw
*hw
)
1945 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1949 rt73usb_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
1950 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
1951 rt73usb_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
1952 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
1957 #define rt73usb_get_tsf NULL
1960 static int rt73usb_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1961 struct ieee80211_tx_control
*control
)
1963 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1964 struct rt2x00_intf
*intf
= vif_to_intf(control
->vif
);
1965 struct skb_frame_desc
*skbdesc
;
1966 unsigned int beacon_base
;
1969 if (unlikely(!intf
->beacon
))
1973 * Add the descriptor in front of the skb.
1975 skb_push(skb
, intf
->beacon
->queue
->desc_size
);
1976 memset(skb
->data
, 0, intf
->beacon
->queue
->desc_size
);
1979 * Fill in skb descriptor
1981 skbdesc
= get_skb_frame_desc(skb
);
1982 memset(skbdesc
, 0, sizeof(*skbdesc
));
1983 skbdesc
->flags
|= FRAME_DESC_DRIVER_GENERATED
;
1984 skbdesc
->data
= skb
->data
+ intf
->beacon
->queue
->desc_size
;
1985 skbdesc
->data_len
= skb
->len
- intf
->beacon
->queue
->desc_size
;
1986 skbdesc
->desc
= skb
->data
;
1987 skbdesc
->desc_len
= intf
->beacon
->queue
->desc_size
;
1988 skbdesc
->entry
= intf
->beacon
;
1991 * Disable beaconing while we are reloading the beacon data,
1992 * otherwise we might be sending out invalid data.
1994 rt73usb_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1995 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1996 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1997 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1998 rt73usb_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
2001 * Write entire beacon with descriptor to register,
2002 * and kick the beacon generator.
2004 rt2x00lib_write_tx_desc(rt2x00dev
, skb
, control
);
2005 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
2006 rt2x00usb_vendor_request(rt2x00dev
, USB_MULTI_WRITE
,
2007 USB_VENDOR_REQUEST_OUT
, beacon_base
, 0,
2008 skb
->data
, skb
->len
,
2009 REGISTER_TIMEOUT32(skb
->len
));
2010 rt73usb_kick_tx_queue(rt2x00dev
, QID_BEACON
);
2015 static const struct ieee80211_ops rt73usb_mac80211_ops
= {
2017 .start
= rt2x00mac_start
,
2018 .stop
= rt2x00mac_stop
,
2019 .add_interface
= rt2x00mac_add_interface
,
2020 .remove_interface
= rt2x00mac_remove_interface
,
2021 .config
= rt2x00mac_config
,
2022 .config_interface
= rt2x00mac_config_interface
,
2023 .configure_filter
= rt2x00mac_configure_filter
,
2024 .get_stats
= rt2x00mac_get_stats
,
2025 .set_retry_limit
= rt73usb_set_retry_limit
,
2026 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2027 .conf_tx
= rt2x00mac_conf_tx
,
2028 .get_tx_stats
= rt2x00mac_get_tx_stats
,
2029 .get_tsf
= rt73usb_get_tsf
,
2030 .beacon_update
= rt73usb_beacon_update
,
2033 static const struct rt2x00lib_ops rt73usb_rt2x00_ops
= {
2034 .probe_hw
= rt73usb_probe_hw
,
2035 .get_firmware_name
= rt73usb_get_firmware_name
,
2036 .get_firmware_crc
= rt73usb_get_firmware_crc
,
2037 .load_firmware
= rt73usb_load_firmware
,
2038 .initialize
= rt2x00usb_initialize
,
2039 .uninitialize
= rt2x00usb_uninitialize
,
2040 .init_rxentry
= rt2x00usb_init_rxentry
,
2041 .init_txentry
= rt2x00usb_init_txentry
,
2042 .set_device_state
= rt73usb_set_device_state
,
2043 .link_stats
= rt73usb_link_stats
,
2044 .reset_tuner
= rt73usb_reset_tuner
,
2045 .link_tuner
= rt73usb_link_tuner
,
2046 .write_tx_desc
= rt73usb_write_tx_desc
,
2047 .write_tx_data
= rt2x00usb_write_tx_data
,
2048 .get_tx_data_len
= rt73usb_get_tx_data_len
,
2049 .kick_tx_queue
= rt73usb_kick_tx_queue
,
2050 .fill_rxdone
= rt73usb_fill_rxdone
,
2051 .config_filter
= rt73usb_config_filter
,
2052 .config_intf
= rt73usb_config_intf
,
2053 .config_erp
= rt73usb_config_erp
,
2054 .config
= rt73usb_config
,
2057 static const struct data_queue_desc rt73usb_queue_rx
= {
2058 .entry_num
= RX_ENTRIES
,
2059 .data_size
= DATA_FRAME_SIZE
,
2060 .desc_size
= RXD_DESC_SIZE
,
2061 .priv_size
= sizeof(struct queue_entry_priv_usb_rx
),
2064 static const struct data_queue_desc rt73usb_queue_tx
= {
2065 .entry_num
= TX_ENTRIES
,
2066 .data_size
= DATA_FRAME_SIZE
,
2067 .desc_size
= TXD_DESC_SIZE
,
2068 .priv_size
= sizeof(struct queue_entry_priv_usb_tx
),
2071 static const struct data_queue_desc rt73usb_queue_bcn
= {
2072 .entry_num
= 4 * BEACON_ENTRIES
,
2073 .data_size
= MGMT_FRAME_SIZE
,
2074 .desc_size
= TXINFO_SIZE
,
2075 .priv_size
= sizeof(struct queue_entry_priv_usb_tx
),
2078 static const struct rt2x00_ops rt73usb_ops
= {
2079 .name
= KBUILD_MODNAME
,
2082 .eeprom_size
= EEPROM_SIZE
,
2084 .rx
= &rt73usb_queue_rx
,
2085 .tx
= &rt73usb_queue_tx
,
2086 .bcn
= &rt73usb_queue_bcn
,
2087 .lib
= &rt73usb_rt2x00_ops
,
2088 .hw
= &rt73usb_mac80211_ops
,
2089 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2090 .debugfs
= &rt73usb_rt2x00debug
,
2091 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2095 * rt73usb module information.
2097 static struct usb_device_id rt73usb_device_table
[] = {
2099 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops
) },
2101 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops
) },
2103 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops
) },
2104 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops
) },
2106 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops
) },
2107 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops
) },
2108 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops
) },
2109 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops
) },
2111 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops
) },
2113 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops
) },
2115 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops
) },
2116 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops
) },
2118 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops
) },
2120 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops
) },
2122 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops
) },
2123 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops
) },
2124 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops
) },
2126 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops
) },
2128 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops
) },
2129 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops
) },
2131 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops
) },
2133 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops
) },
2134 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops
) },
2136 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops
) },
2137 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops
) },
2139 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops
) },
2140 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops
) },
2141 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops
) },
2142 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops
) },
2144 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops
) },
2145 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops
) },
2147 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops
) },
2148 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops
) },
2149 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops
) },
2151 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops
) },
2153 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops
) },
2154 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops
) },
2156 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops
) },
2158 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops
) },
2159 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops
) },
2163 MODULE_AUTHOR(DRV_PROJECT
);
2164 MODULE_VERSION(DRV_VERSION
);
2165 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2166 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2167 MODULE_DEVICE_TABLE(usb
, rt73usb_device_table
);
2168 MODULE_FIRMWARE(FIRMWARE_RT2571
);
2169 MODULE_LICENSE("GPL");
2171 static struct usb_driver rt73usb_driver
= {
2172 .name
= KBUILD_MODNAME
,
2173 .id_table
= rt73usb_device_table
,
2174 .probe
= rt2x00usb_probe
,
2175 .disconnect
= rt2x00usb_disconnect
,
2176 .suspend
= rt2x00usb_suspend
,
2177 .resume
= rt2x00usb_resume
,
2180 static int __init
rt73usb_init(void)
2182 return usb_register(&rt73usb_driver
);
2185 static void __exit
rt73usb_exit(void)
2187 usb_deregister(&rt73usb_driver
);
2190 module_init(rt73usb_init
);
2191 module_exit(rt73usb_exit
);