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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/usb.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00usb.h"
38 #include "rt73usb.h"
39
40 /*
41 * Allow hardware encryption to be disabled.
42 */
43 static int modparam_nohwcrypt = 0;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
47 /*
48 * Register access.
49 * All access to the CSR registers will go through the methods
50 * rt2x00usb_register_read and rt2x00usb_register_write.
51 * BBP and RF register require indirect register access,
52 * and use the CSR registers BBPCSR and RFCSR to achieve this.
53 * These indirect registers work with busy bits,
54 * and we will try maximal REGISTER_BUSY_COUNT times to access
55 * the register while taking a REGISTER_BUSY_DELAY us delay
56 * between each attampt. When the busy bit is still set at that time,
57 * the access attempt is considered to have failed,
58 * and we will print an error.
59 * The _lock versions must be used if you already hold the csr_mutex
60 */
61 #define WAIT_FOR_BBP(__dev, __reg) \
62 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
63 #define WAIT_FOR_RF(__dev, __reg) \
64 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
65
66 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
67 const unsigned int word, const u8 value)
68 {
69 u32 reg;
70
71 mutex_lock(&rt2x00dev->csr_mutex);
72
73 /*
74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
76 */
77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 reg = 0;
79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
84 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
85 }
86
87 mutex_unlock(&rt2x00dev->csr_mutex);
88 }
89
90 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
91 const unsigned int word, u8 *value)
92 {
93 u32 reg;
94
95 mutex_lock(&rt2x00dev->csr_mutex);
96
97 /*
98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
104 */
105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 reg = 0;
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
110
111 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
112
113 WAIT_FOR_BBP(rt2x00dev, &reg);
114 }
115
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
117
118 mutex_unlock(&rt2x00dev->csr_mutex);
119 }
120
121 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
122 const unsigned int word, const u32 value)
123 {
124 u32 reg;
125
126 mutex_lock(&rt2x00dev->csr_mutex);
127
128 /*
129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
131 */
132 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 reg = 0;
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 /*
136 * RF5225 and RF2527 contain 21 bits per RF register value,
137 * all others contain 20 bits.
138 */
139 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
140 20 + (rt2x00_rf(rt2x00dev, RF5225) ||
141 rt2x00_rf(rt2x00dev, RF2527)));
142 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
143 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
144
145 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
146 rt2x00_rf_write(rt2x00dev, word, value);
147 }
148
149 mutex_unlock(&rt2x00dev->csr_mutex);
150 }
151
152 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
153 static const struct rt2x00debug rt73usb_rt2x00debug = {
154 .owner = THIS_MODULE,
155 .csr = {
156 .read = rt2x00usb_register_read,
157 .write = rt2x00usb_register_write,
158 .flags = RT2X00DEBUGFS_OFFSET,
159 .word_base = CSR_REG_BASE,
160 .word_size = sizeof(u32),
161 .word_count = CSR_REG_SIZE / sizeof(u32),
162 },
163 .eeprom = {
164 .read = rt2x00_eeprom_read,
165 .write = rt2x00_eeprom_write,
166 .word_base = EEPROM_BASE,
167 .word_size = sizeof(u16),
168 .word_count = EEPROM_SIZE / sizeof(u16),
169 },
170 .bbp = {
171 .read = rt73usb_bbp_read,
172 .write = rt73usb_bbp_write,
173 .word_base = BBP_BASE,
174 .word_size = sizeof(u8),
175 .word_count = BBP_SIZE / sizeof(u8),
176 },
177 .rf = {
178 .read = rt2x00_rf_read,
179 .write = rt73usb_rf_write,
180 .word_base = RF_BASE,
181 .word_size = sizeof(u32),
182 .word_count = RF_SIZE / sizeof(u32),
183 },
184 };
185 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186
187 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188 {
189 u32 reg;
190
191 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193 }
194
195 #ifdef CONFIG_RT2X00_LIB_LEDS
196 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
197 enum led_brightness brightness)
198 {
199 struct rt2x00_led *led =
200 container_of(led_cdev, struct rt2x00_led, led_dev);
201 unsigned int enabled = brightness != LED_OFF;
202 unsigned int a_mode =
203 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
204 unsigned int bg_mode =
205 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
206
207 if (led->type == LED_TYPE_RADIO) {
208 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
209 MCU_LEDCS_RADIO_STATUS, enabled);
210
211 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
212 0, led->rt2x00dev->led_mcu_reg,
213 REGISTER_TIMEOUT);
214 } else if (led->type == LED_TYPE_ASSOC) {
215 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
216 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
217 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
218 MCU_LEDCS_LINK_A_STATUS, a_mode);
219
220 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
221 0, led->rt2x00dev->led_mcu_reg,
222 REGISTER_TIMEOUT);
223 } else if (led->type == LED_TYPE_QUALITY) {
224 /*
225 * The brightness is divided into 6 levels (0 - 5),
226 * this means we need to convert the brightness
227 * argument into the matching level within that range.
228 */
229 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
230 brightness / (LED_FULL / 6),
231 led->rt2x00dev->led_mcu_reg,
232 REGISTER_TIMEOUT);
233 }
234 }
235
236 static int rt73usb_blink_set(struct led_classdev *led_cdev,
237 unsigned long *delay_on,
238 unsigned long *delay_off)
239 {
240 struct rt2x00_led *led =
241 container_of(led_cdev, struct rt2x00_led, led_dev);
242 u32 reg;
243
244 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
245 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
246 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
247 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
248
249 return 0;
250 }
251
252 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
253 struct rt2x00_led *led,
254 enum led_type type)
255 {
256 led->rt2x00dev = rt2x00dev;
257 led->type = type;
258 led->led_dev.brightness_set = rt73usb_brightness_set;
259 led->led_dev.blink_set = rt73usb_blink_set;
260 led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265 * Configuration handlers.
266 */
267 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
268 struct rt2x00lib_crypto *crypto,
269 struct ieee80211_key_conf *key)
270 {
271 struct hw_key_entry key_entry;
272 struct rt2x00_field32 field;
273 u32 mask;
274 u32 reg;
275
276 if (crypto->cmd == SET_KEY) {
277 /*
278 * rt2x00lib can't determine the correct free
279 * key_idx for shared keys. We have 1 register
280 * with key valid bits. The goal is simple, read
281 * the register, if that is full we have no slots
282 * left.
283 * Note that each BSS is allowed to have up to 4
284 * shared keys, so put a mask over the allowed
285 * entries.
286 */
287 mask = (0xf << crypto->bssidx);
288
289 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
290 reg &= mask;
291
292 if (reg && reg == mask)
293 return -ENOSPC;
294
295 key->hw_key_idx += reg ? ffz(reg) : 0;
296
297 /*
298 * Upload key to hardware
299 */
300 memcpy(key_entry.key, crypto->key,
301 sizeof(key_entry.key));
302 memcpy(key_entry.tx_mic, crypto->tx_mic,
303 sizeof(key_entry.tx_mic));
304 memcpy(key_entry.rx_mic, crypto->rx_mic,
305 sizeof(key_entry.rx_mic));
306
307 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
308 rt2x00usb_register_multiwrite(rt2x00dev, reg,
309 &key_entry, sizeof(key_entry));
310
311 /*
312 * The cipher types are stored over 2 registers.
313 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
314 * bssidx 1 and 2 keys are stored in SEC_CSR5.
315 * Using the correct defines correctly will cause overhead,
316 * so just calculate the correct offset.
317 */
318 if (key->hw_key_idx < 8) {
319 field.bit_offset = (3 * key->hw_key_idx);
320 field.bit_mask = 0x7 << field.bit_offset;
321
322 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
323 rt2x00_set_field32(&reg, field, crypto->cipher);
324 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
325 } else {
326 field.bit_offset = (3 * (key->hw_key_idx - 8));
327 field.bit_mask = 0x7 << field.bit_offset;
328
329 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
330 rt2x00_set_field32(&reg, field, crypto->cipher);
331 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
332 }
333
334 /*
335 * The driver does not support the IV/EIV generation
336 * in hardware. However it doesn't support the IV/EIV
337 * inside the ieee80211 frame either, but requires it
338 * to be provided separately for the descriptor.
339 * rt2x00lib will cut the IV/EIV data out of all frames
340 * given to us by mac80211, but we must tell mac80211
341 * to generate the IV/EIV data.
342 */
343 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
344 }
345
346 /*
347 * SEC_CSR0 contains only single-bit fields to indicate
348 * a particular key is valid. Because using the FIELD32()
349 * defines directly will cause a lot of overhead we use
350 * a calculation to determine the correct bit directly.
351 */
352 mask = 1 << key->hw_key_idx;
353
354 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
355 if (crypto->cmd == SET_KEY)
356 reg |= mask;
357 else if (crypto->cmd == DISABLE_KEY)
358 reg &= ~mask;
359 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
360
361 return 0;
362 }
363
364 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
365 struct rt2x00lib_crypto *crypto,
366 struct ieee80211_key_conf *key)
367 {
368 struct hw_pairwise_ta_entry addr_entry;
369 struct hw_key_entry key_entry;
370 u32 mask;
371 u32 reg;
372
373 if (crypto->cmd == SET_KEY) {
374 /*
375 * rt2x00lib can't determine the correct free
376 * key_idx for pairwise keys. We have 2 registers
377 * with key valid bits. The goal is simple, read
378 * the first register, if that is full move to
379 * the next register.
380 * When both registers are full, we drop the key,
381 * otherwise we use the first invalid entry.
382 */
383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
384 if (reg && reg == ~0) {
385 key->hw_key_idx = 32;
386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
387 if (reg && reg == ~0)
388 return -ENOSPC;
389 }
390
391 key->hw_key_idx += reg ? ffz(reg) : 0;
392
393 /*
394 * Upload key to hardware
395 */
396 memcpy(key_entry.key, crypto->key,
397 sizeof(key_entry.key));
398 memcpy(key_entry.tx_mic, crypto->tx_mic,
399 sizeof(key_entry.tx_mic));
400 memcpy(key_entry.rx_mic, crypto->rx_mic,
401 sizeof(key_entry.rx_mic));
402
403 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
404 rt2x00usb_register_multiwrite(rt2x00dev, reg,
405 &key_entry, sizeof(key_entry));
406
407 /*
408 * Send the address and cipher type to the hardware register.
409 */
410 memset(&addr_entry, 0, sizeof(addr_entry));
411 memcpy(&addr_entry, crypto->address, ETH_ALEN);
412 addr_entry.cipher = crypto->cipher;
413
414 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
415 rt2x00usb_register_multiwrite(rt2x00dev, reg,
416 &addr_entry, sizeof(addr_entry));
417
418 /*
419 * Enable pairwise lookup table for given BSS idx,
420 * without this received frames will not be decrypted
421 * by the hardware.
422 */
423 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
424 reg |= (1 << crypto->bssidx);
425 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
426
427 /*
428 * The driver does not support the IV/EIV generation
429 * in hardware. However it doesn't support the IV/EIV
430 * inside the ieee80211 frame either, but requires it
431 * to be provided separately for the descriptor.
432 * rt2x00lib will cut the IV/EIV data out of all frames
433 * given to us by mac80211, but we must tell mac80211
434 * to generate the IV/EIV data.
435 */
436 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
437 }
438
439 /*
440 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
441 * a particular key is valid. Because using the FIELD32()
442 * defines directly will cause a lot of overhead we use
443 * a calculation to determine the correct bit directly.
444 */
445 if (key->hw_key_idx < 32) {
446 mask = 1 << key->hw_key_idx;
447
448 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
449 if (crypto->cmd == SET_KEY)
450 reg |= mask;
451 else if (crypto->cmd == DISABLE_KEY)
452 reg &= ~mask;
453 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
454 } else {
455 mask = 1 << (key->hw_key_idx - 32);
456
457 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
458 if (crypto->cmd == SET_KEY)
459 reg |= mask;
460 else if (crypto->cmd == DISABLE_KEY)
461 reg &= ~mask;
462 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
463 }
464
465 return 0;
466 }
467
468 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
469 const unsigned int filter_flags)
470 {
471 u32 reg;
472
473 /*
474 * Start configuration steps.
475 * Note that the version error will always be dropped
476 * and broadcast frames will always be accepted since
477 * there is no filter for it at this time.
478 */
479 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
480 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
481 !(filter_flags & FIF_FCSFAIL));
482 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
483 !(filter_flags & FIF_PLCPFAIL));
484 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
485 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
487 !(filter_flags & FIF_PROMISC_IN_BSS));
488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
489 !(filter_flags & FIF_PROMISC_IN_BSS) &&
490 !rt2x00dev->intf_ap_count);
491 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
492 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
493 !(filter_flags & FIF_ALLMULTI));
494 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
495 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
496 !(filter_flags & FIF_CONTROL));
497 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
498 }
499
500 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
501 struct rt2x00_intf *intf,
502 struct rt2x00intf_conf *conf,
503 const unsigned int flags)
504 {
505 unsigned int beacon_base;
506 u32 reg;
507
508 if (flags & CONFIG_UPDATE_TYPE) {
509 /*
510 * Clear current synchronisation setup.
511 * For the Beacon base registers we only need to clear
512 * the first byte since that byte contains the VALID and OWNER
513 * bits which (when set to 0) will invalidate the entire beacon.
514 */
515 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
516 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
517
518 /*
519 * Enable synchronisation.
520 */
521 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
522 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
523 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
524 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
525 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
526 }
527
528 if (flags & CONFIG_UPDATE_MAC) {
529 reg = le32_to_cpu(conf->mac[1]);
530 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
531 conf->mac[1] = cpu_to_le32(reg);
532
533 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
534 conf->mac, sizeof(conf->mac));
535 }
536
537 if (flags & CONFIG_UPDATE_BSSID) {
538 reg = le32_to_cpu(conf->bssid[1]);
539 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
540 conf->bssid[1] = cpu_to_le32(reg);
541
542 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
543 conf->bssid, sizeof(conf->bssid));
544 }
545 }
546
547 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
548 struct rt2x00lib_erp *erp)
549 {
550 u32 reg;
551
552 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
553 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
554 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
555 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
556
557 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
558 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
559 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
560 !!erp->short_preamble);
561 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
562
563 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
564
565 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
566 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
567 erp->beacon_int * 16);
568 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
569
570 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
571 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
572 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
573
574 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
576 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
577 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
578 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
579 }
580
581 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
582 struct antenna_setup *ant)
583 {
584 u8 r3;
585 u8 r4;
586 u8 r77;
587 u8 temp;
588
589 rt73usb_bbp_read(rt2x00dev, 3, &r3);
590 rt73usb_bbp_read(rt2x00dev, 4, &r4);
591 rt73usb_bbp_read(rt2x00dev, 77, &r77);
592
593 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
594
595 /*
596 * Configure the RX antenna.
597 */
598 switch (ant->rx) {
599 case ANTENNA_HW_DIVERSITY:
600 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
601 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
602 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
603 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
604 break;
605 case ANTENNA_A:
606 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
607 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
608 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
609 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
610 else
611 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
612 break;
613 case ANTENNA_B:
614 default:
615 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
616 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
617 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
618 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
619 else
620 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
621 break;
622 }
623
624 rt73usb_bbp_write(rt2x00dev, 77, r77);
625 rt73usb_bbp_write(rt2x00dev, 3, r3);
626 rt73usb_bbp_write(rt2x00dev, 4, r4);
627 }
628
629 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
630 struct antenna_setup *ant)
631 {
632 u8 r3;
633 u8 r4;
634 u8 r77;
635
636 rt73usb_bbp_read(rt2x00dev, 3, &r3);
637 rt73usb_bbp_read(rt2x00dev, 4, &r4);
638 rt73usb_bbp_read(rt2x00dev, 77, &r77);
639
640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
641 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
642 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
643
644 /*
645 * Configure the RX antenna.
646 */
647 switch (ant->rx) {
648 case ANTENNA_HW_DIVERSITY:
649 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
650 break;
651 case ANTENNA_A:
652 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
653 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
654 break;
655 case ANTENNA_B:
656 default:
657 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
658 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
659 break;
660 }
661
662 rt73usb_bbp_write(rt2x00dev, 77, r77);
663 rt73usb_bbp_write(rt2x00dev, 3, r3);
664 rt73usb_bbp_write(rt2x00dev, 4, r4);
665 }
666
667 struct antenna_sel {
668 u8 word;
669 /*
670 * value[0] -> non-LNA
671 * value[1] -> LNA
672 */
673 u8 value[2];
674 };
675
676 static const struct antenna_sel antenna_sel_a[] = {
677 { 96, { 0x58, 0x78 } },
678 { 104, { 0x38, 0x48 } },
679 { 75, { 0xfe, 0x80 } },
680 { 86, { 0xfe, 0x80 } },
681 { 88, { 0xfe, 0x80 } },
682 { 35, { 0x60, 0x60 } },
683 { 97, { 0x58, 0x58 } },
684 { 98, { 0x58, 0x58 } },
685 };
686
687 static const struct antenna_sel antenna_sel_bg[] = {
688 { 96, { 0x48, 0x68 } },
689 { 104, { 0x2c, 0x3c } },
690 { 75, { 0xfe, 0x80 } },
691 { 86, { 0xfe, 0x80 } },
692 { 88, { 0xfe, 0x80 } },
693 { 35, { 0x50, 0x50 } },
694 { 97, { 0x48, 0x48 } },
695 { 98, { 0x48, 0x48 } },
696 };
697
698 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
699 struct antenna_setup *ant)
700 {
701 const struct antenna_sel *sel;
702 unsigned int lna;
703 unsigned int i;
704 u32 reg;
705
706 /*
707 * We should never come here because rt2x00lib is supposed
708 * to catch this and send us the correct antenna explicitely.
709 */
710 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
711 ant->tx == ANTENNA_SW_DIVERSITY);
712
713 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
714 sel = antenna_sel_a;
715 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
716 } else {
717 sel = antenna_sel_bg;
718 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
719 }
720
721 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
722 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
723
724 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
725
726 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
727 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
728 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
729 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
730
731 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
732
733 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
734 rt73usb_config_antenna_5x(rt2x00dev, ant);
735 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
736 rt73usb_config_antenna_2x(rt2x00dev, ant);
737 }
738
739 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
740 struct rt2x00lib_conf *libconf)
741 {
742 u16 eeprom;
743 short lna_gain = 0;
744
745 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
746 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
747 lna_gain += 14;
748
749 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
750 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
751 } else {
752 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
753 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
754 }
755
756 rt2x00dev->lna_gain = lna_gain;
757 }
758
759 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
760 struct rf_channel *rf, const int txpower)
761 {
762 u8 r3;
763 u8 r94;
764 u8 smart;
765
766 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
767 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
768
769 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
770
771 rt73usb_bbp_read(rt2x00dev, 3, &r3);
772 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
773 rt73usb_bbp_write(rt2x00dev, 3, r3);
774
775 r94 = 6;
776 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
777 r94 += txpower - MAX_TXPOWER;
778 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
779 r94 += txpower;
780 rt73usb_bbp_write(rt2x00dev, 94, r94);
781
782 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
783 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
784 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
785 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
786
787 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
788 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
789 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
790 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
791
792 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
793 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
794 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
795 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
796
797 udelay(10);
798 }
799
800 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
801 const int txpower)
802 {
803 struct rf_channel rf;
804
805 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
806 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
807 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
808 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
809
810 rt73usb_config_channel(rt2x00dev, &rf, txpower);
811 }
812
813 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
814 struct rt2x00lib_conf *libconf)
815 {
816 u32 reg;
817
818 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
819 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
820 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
821 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
822 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
823 libconf->conf->long_frame_max_tx_count);
824 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
825 libconf->conf->short_frame_max_tx_count);
826 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
827 }
828
829 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
830 struct rt2x00lib_conf *libconf)
831 {
832 enum dev_state state =
833 (libconf->conf->flags & IEEE80211_CONF_PS) ?
834 STATE_SLEEP : STATE_AWAKE;
835 u32 reg;
836
837 if (state == STATE_SLEEP) {
838 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
839 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
840 rt2x00dev->beacon_int - 10);
841 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
842 libconf->conf->listen_interval - 1);
843 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
844
845 /* We must first disable autowake before it can be enabled */
846 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
847 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
848
849 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
850 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
851
852 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
853 USB_MODE_SLEEP, REGISTER_TIMEOUT);
854 } else {
855 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
856 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
857 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
858 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
859 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
860 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
861
862 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
863 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
864 }
865 }
866
867 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
868 struct rt2x00lib_conf *libconf,
869 const unsigned int flags)
870 {
871 /* Always recalculate LNA gain before changing configuration */
872 rt73usb_config_lna_gain(rt2x00dev, libconf);
873
874 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
875 rt73usb_config_channel(rt2x00dev, &libconf->rf,
876 libconf->conf->power_level);
877 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
878 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
879 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
880 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
881 rt73usb_config_retry_limit(rt2x00dev, libconf);
882 if (flags & IEEE80211_CONF_CHANGE_PS)
883 rt73usb_config_ps(rt2x00dev, libconf);
884 }
885
886 /*
887 * Link tuning
888 */
889 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
890 struct link_qual *qual)
891 {
892 u32 reg;
893
894 /*
895 * Update FCS error count from register.
896 */
897 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
898 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
899
900 /*
901 * Update False CCA count from register.
902 */
903 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
904 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
905 }
906
907 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
908 struct link_qual *qual, u8 vgc_level)
909 {
910 if (qual->vgc_level != vgc_level) {
911 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
912 qual->vgc_level = vgc_level;
913 qual->vgc_level_reg = vgc_level;
914 }
915 }
916
917 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
918 struct link_qual *qual)
919 {
920 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
921 }
922
923 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
924 struct link_qual *qual, const u32 count)
925 {
926 u8 up_bound;
927 u8 low_bound;
928
929 /*
930 * Determine r17 bounds.
931 */
932 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
933 low_bound = 0x28;
934 up_bound = 0x48;
935
936 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
937 low_bound += 0x10;
938 up_bound += 0x10;
939 }
940 } else {
941 if (qual->rssi > -82) {
942 low_bound = 0x1c;
943 up_bound = 0x40;
944 } else if (qual->rssi > -84) {
945 low_bound = 0x1c;
946 up_bound = 0x20;
947 } else {
948 low_bound = 0x1c;
949 up_bound = 0x1c;
950 }
951
952 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
953 low_bound += 0x14;
954 up_bound += 0x10;
955 }
956 }
957
958 /*
959 * If we are not associated, we should go straight to the
960 * dynamic CCA tuning.
961 */
962 if (!rt2x00dev->intf_associated)
963 goto dynamic_cca_tune;
964
965 /*
966 * Special big-R17 for very short distance
967 */
968 if (qual->rssi > -35) {
969 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
970 return;
971 }
972
973 /*
974 * Special big-R17 for short distance
975 */
976 if (qual->rssi >= -58) {
977 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
978 return;
979 }
980
981 /*
982 * Special big-R17 for middle-short distance
983 */
984 if (qual->rssi >= -66) {
985 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
986 return;
987 }
988
989 /*
990 * Special mid-R17 for middle distance
991 */
992 if (qual->rssi >= -74) {
993 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
994 return;
995 }
996
997 /*
998 * Special case: Change up_bound based on the rssi.
999 * Lower up_bound when rssi is weaker then -74 dBm.
1000 */
1001 up_bound -= 2 * (-74 - qual->rssi);
1002 if (low_bound > up_bound)
1003 up_bound = low_bound;
1004
1005 if (qual->vgc_level > up_bound) {
1006 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1007 return;
1008 }
1009
1010 dynamic_cca_tune:
1011
1012 /*
1013 * r17 does not yet exceed upper limit, continue and base
1014 * the r17 tuning on the false CCA count.
1015 */
1016 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1017 rt73usb_set_vgc(rt2x00dev, qual,
1018 min_t(u8, qual->vgc_level + 4, up_bound));
1019 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1020 rt73usb_set_vgc(rt2x00dev, qual,
1021 max_t(u8, qual->vgc_level - 4, low_bound));
1022 }
1023
1024 /*
1025 * Firmware functions
1026 */
1027 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1028 {
1029 return FIRMWARE_RT2571;
1030 }
1031
1032 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1033 const u8 *data, const size_t len)
1034 {
1035 u16 fw_crc;
1036 u16 crc;
1037
1038 /*
1039 * Only support 2kb firmware files.
1040 */
1041 if (len != 2048)
1042 return FW_BAD_LENGTH;
1043
1044 /*
1045 * The last 2 bytes in the firmware array are the crc checksum itself,
1046 * this means that we should never pass those 2 bytes to the crc
1047 * algorithm.
1048 */
1049 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1050
1051 /*
1052 * Use the crc itu-t algorithm.
1053 */
1054 crc = crc_itu_t(0, data, len - 2);
1055 crc = crc_itu_t_byte(crc, 0);
1056 crc = crc_itu_t_byte(crc, 0);
1057
1058 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1059 }
1060
1061 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1062 const u8 *data, const size_t len)
1063 {
1064 unsigned int i;
1065 int status;
1066 u32 reg;
1067
1068 /*
1069 * Wait for stable hardware.
1070 */
1071 for (i = 0; i < 100; i++) {
1072 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1073 if (reg)
1074 break;
1075 msleep(1);
1076 }
1077
1078 if (!reg) {
1079 ERROR(rt2x00dev, "Unstable hardware.\n");
1080 return -EBUSY;
1081 }
1082
1083 /*
1084 * Write firmware to device.
1085 */
1086 rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1087
1088 /*
1089 * Send firmware request to device to load firmware,
1090 * we need to specify a long timeout time.
1091 */
1092 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1093 0, USB_MODE_FIRMWARE,
1094 REGISTER_TIMEOUT_FIRMWARE);
1095 if (status < 0) {
1096 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1097 return status;
1098 }
1099
1100 return 0;
1101 }
1102
1103 /*
1104 * Initialization functions.
1105 */
1106 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1107 {
1108 u32 reg;
1109
1110 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1111 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1112 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1113 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1114 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1115
1116 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1117 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1118 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1119 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1120 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1121 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1122 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1123 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1124 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1125 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1126
1127 /*
1128 * CCK TXD BBP registers
1129 */
1130 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1131 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1132 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1133 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1134 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1135 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1136 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1137 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1138 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1139 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1140
1141 /*
1142 * OFDM TXD BBP registers
1143 */
1144 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1145 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1146 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1147 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1148 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1149 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1150 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1151 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1152
1153 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1154 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1155 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1156 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1157 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1158 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1159
1160 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1161 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1162 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1163 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1164 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1165 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1166
1167 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1168 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1169 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1170 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1171 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1172 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1173 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1174 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1175
1176 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1177
1178 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1179 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1180 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1181
1182 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1183
1184 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1185 return -EBUSY;
1186
1187 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1188
1189 /*
1190 * Invalidate all Shared Keys (SEC_CSR0),
1191 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1192 */
1193 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1194 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1195 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1196
1197 reg = 0x000023b0;
1198 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1199 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1200 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1201
1202 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1203 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1204 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1205
1206 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1207 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1208 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1209
1210 /*
1211 * Clear all beacons
1212 * For the Beacon base registers we only need to clear
1213 * the first byte since that byte contains the VALID and OWNER
1214 * bits which (when set to 0) will invalidate the entire beacon.
1215 */
1216 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1217 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1218 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1219 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1220
1221 /*
1222 * We must clear the error counters.
1223 * These registers are cleared on read,
1224 * so we may pass a useless variable to store the value.
1225 */
1226 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1227 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1228 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1229
1230 /*
1231 * Reset MAC and BBP registers.
1232 */
1233 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1234 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1235 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1236 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1237
1238 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1239 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1240 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1241 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1242
1243 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1244 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1245 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1246
1247 return 0;
1248 }
1249
1250 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1251 {
1252 unsigned int i;
1253 u8 value;
1254
1255 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1256 rt73usb_bbp_read(rt2x00dev, 0, &value);
1257 if ((value != 0xff) && (value != 0x00))
1258 return 0;
1259 udelay(REGISTER_BUSY_DELAY);
1260 }
1261
1262 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1263 return -EACCES;
1264 }
1265
1266 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1267 {
1268 unsigned int i;
1269 u16 eeprom;
1270 u8 reg_id;
1271 u8 value;
1272
1273 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1274 return -EACCES;
1275
1276 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1277 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1278 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1279 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1280 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1281 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1282 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1283 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1284 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1285 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1286 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1287 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1288 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1289 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1290 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1291 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1292 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1293 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1294 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1295 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1296 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1297 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1298 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1299 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1300 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1301
1302 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1303 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1304
1305 if (eeprom != 0xffff && eeprom != 0x0000) {
1306 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1307 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1308 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1309 }
1310 }
1311
1312 return 0;
1313 }
1314
1315 /*
1316 * Device state switch handlers.
1317 */
1318 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1319 enum dev_state state)
1320 {
1321 u32 reg;
1322
1323 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1324 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1325 (state == STATE_RADIO_RX_OFF) ||
1326 (state == STATE_RADIO_RX_OFF_LINK));
1327 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1328 }
1329
1330 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1331 {
1332 /*
1333 * Initialize all registers.
1334 */
1335 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1336 rt73usb_init_bbp(rt2x00dev)))
1337 return -EIO;
1338
1339 return 0;
1340 }
1341
1342 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1343 {
1344 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1345
1346 /*
1347 * Disable synchronisation.
1348 */
1349 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1350
1351 rt2x00usb_disable_radio(rt2x00dev);
1352 }
1353
1354 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1355 {
1356 u32 reg, reg2;
1357 unsigned int i;
1358 char put_to_sleep;
1359
1360 put_to_sleep = (state != STATE_AWAKE);
1361
1362 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1363 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1364 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1365 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1366
1367 /*
1368 * Device is not guaranteed to be in the requested state yet.
1369 * We must wait until the register indicates that the
1370 * device has entered the correct state.
1371 */
1372 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1373 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1374 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1375 if (state == !put_to_sleep)
1376 return 0;
1377 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1378 msleep(10);
1379 }
1380
1381 return -EBUSY;
1382 }
1383
1384 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1385 enum dev_state state)
1386 {
1387 int retval = 0;
1388
1389 switch (state) {
1390 case STATE_RADIO_ON:
1391 retval = rt73usb_enable_radio(rt2x00dev);
1392 break;
1393 case STATE_RADIO_OFF:
1394 rt73usb_disable_radio(rt2x00dev);
1395 break;
1396 case STATE_RADIO_RX_ON:
1397 case STATE_RADIO_RX_ON_LINK:
1398 case STATE_RADIO_RX_OFF:
1399 case STATE_RADIO_RX_OFF_LINK:
1400 rt73usb_toggle_rx(rt2x00dev, state);
1401 break;
1402 case STATE_RADIO_IRQ_ON:
1403 case STATE_RADIO_IRQ_ON_ISR:
1404 case STATE_RADIO_IRQ_OFF:
1405 case STATE_RADIO_IRQ_OFF_ISR:
1406 /* No support, but no error either */
1407 break;
1408 case STATE_DEEP_SLEEP:
1409 case STATE_SLEEP:
1410 case STATE_STANDBY:
1411 case STATE_AWAKE:
1412 retval = rt73usb_set_state(rt2x00dev, state);
1413 break;
1414 default:
1415 retval = -ENOTSUPP;
1416 break;
1417 }
1418
1419 if (unlikely(retval))
1420 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1421 state, retval);
1422
1423 return retval;
1424 }
1425
1426 /*
1427 * TX descriptor initialization
1428 */
1429 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1430 struct sk_buff *skb,
1431 struct txentry_desc *txdesc)
1432 {
1433 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1434 __le32 *txd = (__le32 *) skb->data;
1435 u32 word;
1436
1437 /*
1438 * Start writing the descriptor words.
1439 */
1440 rt2x00_desc_read(txd, 0, &word);
1441 rt2x00_set_field32(&word, TXD_W0_BURST,
1442 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1443 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1444 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1445 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1446 rt2x00_set_field32(&word, TXD_W0_ACK,
1447 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1448 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1449 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1450 rt2x00_set_field32(&word, TXD_W0_OFDM,
1451 (txdesc->rate_mode == RATE_MODE_OFDM));
1452 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1453 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1454 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1455 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1456 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1457 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1458 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1459 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1460 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1461 rt2x00_set_field32(&word, TXD_W0_BURST2,
1462 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1463 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1464 rt2x00_desc_write(txd, 0, word);
1465
1466 rt2x00_desc_read(txd, 1, &word);
1467 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1468 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1469 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1470 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1471 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1472 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1473 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1474 rt2x00_desc_write(txd, 1, word);
1475
1476 rt2x00_desc_read(txd, 2, &word);
1477 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1478 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1479 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1480 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1481 rt2x00_desc_write(txd, 2, word);
1482
1483 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1484 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1485 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1486 }
1487
1488 rt2x00_desc_read(txd, 5, &word);
1489 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1490 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1491 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1492 rt2x00_desc_write(txd, 5, word);
1493
1494 /*
1495 * Register descriptor details in skb frame descriptor.
1496 */
1497 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1498 skbdesc->desc = txd;
1499 skbdesc->desc_len = TXD_DESC_SIZE;
1500 }
1501
1502 /*
1503 * TX data initialization
1504 */
1505 static void rt73usb_write_beacon(struct queue_entry *entry,
1506 struct txentry_desc *txdesc)
1507 {
1508 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1509 unsigned int beacon_base;
1510 u32 reg;
1511
1512 /*
1513 * Disable beaconing while we are reloading the beacon data,
1514 * otherwise we might be sending out invalid data.
1515 */
1516 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1517 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1518 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1519
1520 /*
1521 * Add space for the descriptor in front of the skb.
1522 */
1523 skb_push(entry->skb, TXD_DESC_SIZE);
1524 memset(entry->skb->data, 0, TXD_DESC_SIZE);
1525
1526 /*
1527 * Write the TX descriptor for the beacon.
1528 */
1529 rt73usb_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1530
1531 /*
1532 * Dump beacon to userspace through debugfs.
1533 */
1534 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1535
1536 /*
1537 * Write entire beacon with descriptor to register.
1538 */
1539 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1540 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base,
1541 entry->skb->data, entry->skb->len);
1542
1543 /*
1544 * Enable beaconing again.
1545 *
1546 * For Wi-Fi faily generated beacons between participating stations.
1547 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1548 */
1549 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1550
1551 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1552 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1553 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1554 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1555
1556 /*
1557 * Clean up the beacon skb.
1558 */
1559 dev_kfree_skb(entry->skb);
1560 entry->skb = NULL;
1561 }
1562
1563 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1564 {
1565 int length;
1566
1567 /*
1568 * The length _must_ be a multiple of 4,
1569 * but it must _not_ be a multiple of the USB packet size.
1570 */
1571 length = roundup(entry->skb->len, 4);
1572 length += (4 * !(length % entry->queue->usb_maxpacket));
1573
1574 return length;
1575 }
1576
1577 /*
1578 * RX control handlers
1579 */
1580 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1581 {
1582 u8 offset = rt2x00dev->lna_gain;
1583 u8 lna;
1584
1585 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1586 switch (lna) {
1587 case 3:
1588 offset += 90;
1589 break;
1590 case 2:
1591 offset += 74;
1592 break;
1593 case 1:
1594 offset += 64;
1595 break;
1596 default:
1597 return 0;
1598 }
1599
1600 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1601 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1602 if (lna == 3 || lna == 2)
1603 offset += 10;
1604 } else {
1605 if (lna == 3)
1606 offset += 6;
1607 else if (lna == 2)
1608 offset += 8;
1609 }
1610 }
1611
1612 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1613 }
1614
1615 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1616 struct rxdone_entry_desc *rxdesc)
1617 {
1618 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1619 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1620 __le32 *rxd = (__le32 *)entry->skb->data;
1621 u32 word0;
1622 u32 word1;
1623
1624 /*
1625 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1626 * frame data in rt2x00usb.
1627 */
1628 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1629 rxd = (__le32 *)skbdesc->desc;
1630
1631 /*
1632 * It is now safe to read the descriptor on all architectures.
1633 */
1634 rt2x00_desc_read(rxd, 0, &word0);
1635 rt2x00_desc_read(rxd, 1, &word1);
1636
1637 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1638 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1639
1640 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1641 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1642
1643 if (rxdesc->cipher != CIPHER_NONE) {
1644 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1645 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1646 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1647
1648 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1649 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1650
1651 /*
1652 * Hardware has stripped IV/EIV data from 802.11 frame during
1653 * decryption. It has provided the data separately but rt2x00lib
1654 * should decide if it should be reinserted.
1655 */
1656 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1657
1658 /*
1659 * FIXME: Legacy driver indicates that the frame does
1660 * contain the Michael Mic. Unfortunately, in rt2x00
1661 * the MIC seems to be missing completely...
1662 */
1663 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1664
1665 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1666 rxdesc->flags |= RX_FLAG_DECRYPTED;
1667 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1668 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1669 }
1670
1671 /*
1672 * Obtain the status about this packet.
1673 * When frame was received with an OFDM bitrate,
1674 * the signal is the PLCP value. If it was received with
1675 * a CCK bitrate the signal is the rate in 100kbit/s.
1676 */
1677 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1678 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1679 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1680
1681 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1682 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1683 else
1684 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1685 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1686 rxdesc->dev_flags |= RXDONE_MY_BSS;
1687
1688 /*
1689 * Set skb pointers, and update frame information.
1690 */
1691 skb_pull(entry->skb, entry->queue->desc_size);
1692 skb_trim(entry->skb, rxdesc->size);
1693 }
1694
1695 /*
1696 * Device probe functions.
1697 */
1698 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1699 {
1700 u16 word;
1701 u8 *mac;
1702 s8 value;
1703
1704 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1705
1706 /*
1707 * Start validation of the data that has been read.
1708 */
1709 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1710 if (!is_valid_ether_addr(mac)) {
1711 random_ether_addr(mac);
1712 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1713 }
1714
1715 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1716 if (word == 0xffff) {
1717 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1718 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1719 ANTENNA_B);
1720 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1721 ANTENNA_B);
1722 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1723 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1724 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1725 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1726 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1727 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1728 }
1729
1730 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1731 if (word == 0xffff) {
1732 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1733 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1734 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1735 }
1736
1737 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1738 if (word == 0xffff) {
1739 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1740 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1741 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1742 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1743 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1744 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1745 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1746 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1747 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1748 LED_MODE_DEFAULT);
1749 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1750 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1751 }
1752
1753 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1754 if (word == 0xffff) {
1755 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1756 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1757 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1758 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1759 }
1760
1761 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1762 if (word == 0xffff) {
1763 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1764 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1765 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1766 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1767 } else {
1768 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1769 if (value < -10 || value > 10)
1770 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1771 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1772 if (value < -10 || value > 10)
1773 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1774 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1775 }
1776
1777 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1778 if (word == 0xffff) {
1779 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1780 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1781 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1782 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1783 } else {
1784 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1785 if (value < -10 || value > 10)
1786 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1787 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1788 if (value < -10 || value > 10)
1789 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1790 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1791 }
1792
1793 return 0;
1794 }
1795
1796 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1797 {
1798 u32 reg;
1799 u16 value;
1800 u16 eeprom;
1801
1802 /*
1803 * Read EEPROM word for configuration.
1804 */
1805 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1806
1807 /*
1808 * Identify RF chipset.
1809 */
1810 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1811 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1812 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1813 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1814
1815 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1816 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1817 return -ENODEV;
1818 }
1819
1820 if (!rt2x00_rf(rt2x00dev, RF5226) &&
1821 !rt2x00_rf(rt2x00dev, RF2528) &&
1822 !rt2x00_rf(rt2x00dev, RF5225) &&
1823 !rt2x00_rf(rt2x00dev, RF2527)) {
1824 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1825 return -ENODEV;
1826 }
1827
1828 /*
1829 * Identify default antenna configuration.
1830 */
1831 rt2x00dev->default_ant.tx =
1832 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1833 rt2x00dev->default_ant.rx =
1834 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1835
1836 /*
1837 * Read the Frame type.
1838 */
1839 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1840 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1841
1842 /*
1843 * Detect if this device has an hardware controlled radio.
1844 */
1845 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1846 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1847
1848 /*
1849 * Read frequency offset.
1850 */
1851 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1852 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1853
1854 /*
1855 * Read external LNA informations.
1856 */
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1858
1859 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1860 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1861 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1862 }
1863
1864 /*
1865 * Store led settings, for correct led behaviour.
1866 */
1867 #ifdef CONFIG_RT2X00_LIB_LEDS
1868 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1869
1870 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1871 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1872 if (value == LED_MODE_SIGNAL_STRENGTH)
1873 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1874 LED_TYPE_QUALITY);
1875
1876 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1877 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1878 rt2x00_get_field16(eeprom,
1879 EEPROM_LED_POLARITY_GPIO_0));
1880 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1881 rt2x00_get_field16(eeprom,
1882 EEPROM_LED_POLARITY_GPIO_1));
1883 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1884 rt2x00_get_field16(eeprom,
1885 EEPROM_LED_POLARITY_GPIO_2));
1886 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1887 rt2x00_get_field16(eeprom,
1888 EEPROM_LED_POLARITY_GPIO_3));
1889 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1890 rt2x00_get_field16(eeprom,
1891 EEPROM_LED_POLARITY_GPIO_4));
1892 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1893 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1894 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1895 rt2x00_get_field16(eeprom,
1896 EEPROM_LED_POLARITY_RDY_G));
1897 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1898 rt2x00_get_field16(eeprom,
1899 EEPROM_LED_POLARITY_RDY_A));
1900 #endif /* CONFIG_RT2X00_LIB_LEDS */
1901
1902 return 0;
1903 }
1904
1905 /*
1906 * RF value list for RF2528
1907 * Supports: 2.4 GHz
1908 */
1909 static const struct rf_channel rf_vals_bg_2528[] = {
1910 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1911 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1912 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1913 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1914 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1915 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1916 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1917 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1918 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1919 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1920 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1921 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1922 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1923 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1924 };
1925
1926 /*
1927 * RF value list for RF5226
1928 * Supports: 2.4 GHz & 5.2 GHz
1929 */
1930 static const struct rf_channel rf_vals_5226[] = {
1931 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1932 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1933 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1934 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1935 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1936 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1937 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1938 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1939 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1940 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1941 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1942 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1943 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1944 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1945
1946 /* 802.11 UNI / HyperLan 2 */
1947 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1948 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1949 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1950 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1951 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1952 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1953 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1954 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1955
1956 /* 802.11 HyperLan 2 */
1957 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1958 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1959 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1960 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1961 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1962 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1963 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1964 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1965 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1966 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1967
1968 /* 802.11 UNII */
1969 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1970 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1971 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1972 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1973 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1974 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1975
1976 /* MMAC(Japan)J52 ch 34,38,42,46 */
1977 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1978 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1979 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1980 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1981 };
1982
1983 /*
1984 * RF value list for RF5225 & RF2527
1985 * Supports: 2.4 GHz & 5.2 GHz
1986 */
1987 static const struct rf_channel rf_vals_5225_2527[] = {
1988 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1989 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1990 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1991 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1992 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1993 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1994 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1995 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1996 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1997 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1998 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1999 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2000 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2001 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2002
2003 /* 802.11 UNI / HyperLan 2 */
2004 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2005 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2006 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2007 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2008 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2009 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2010 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2011 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2012
2013 /* 802.11 HyperLan 2 */
2014 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2015 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2016 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2017 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2018 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2019 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2020 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2021 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2022 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2023 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2024
2025 /* 802.11 UNII */
2026 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2027 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2028 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2029 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2030 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2031 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2032
2033 /* MMAC(Japan)J52 ch 34,38,42,46 */
2034 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2035 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2036 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2037 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2038 };
2039
2040
2041 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2042 {
2043 struct hw_mode_spec *spec = &rt2x00dev->spec;
2044 struct channel_info *info;
2045 char *tx_power;
2046 unsigned int i;
2047
2048 /*
2049 * Initialize all hw fields.
2050 */
2051 rt2x00dev->hw->flags =
2052 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2053 IEEE80211_HW_SIGNAL_DBM |
2054 IEEE80211_HW_SUPPORTS_PS |
2055 IEEE80211_HW_PS_NULLFUNC_STACK;
2056
2057 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2058 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2059 rt2x00_eeprom_addr(rt2x00dev,
2060 EEPROM_MAC_ADDR_0));
2061
2062 /*
2063 * Initialize hw_mode information.
2064 */
2065 spec->supported_bands = SUPPORT_BAND_2GHZ;
2066 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2067
2068 if (rt2x00_rf(rt2x00dev, RF2528)) {
2069 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2070 spec->channels = rf_vals_bg_2528;
2071 } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2072 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2073 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2074 spec->channels = rf_vals_5226;
2075 } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2076 spec->num_channels = 14;
2077 spec->channels = rf_vals_5225_2527;
2078 } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2079 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2080 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2081 spec->channels = rf_vals_5225_2527;
2082 }
2083
2084 /*
2085 * Create channel information array
2086 */
2087 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2088 if (!info)
2089 return -ENOMEM;
2090
2091 spec->channels_info = info;
2092
2093 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2094 for (i = 0; i < 14; i++)
2095 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2096
2097 if (spec->num_channels > 14) {
2098 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2099 for (i = 14; i < spec->num_channels; i++)
2100 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2101 }
2102
2103 return 0;
2104 }
2105
2106 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2107 {
2108 int retval;
2109
2110 /*
2111 * Allocate eeprom data.
2112 */
2113 retval = rt73usb_validate_eeprom(rt2x00dev);
2114 if (retval)
2115 return retval;
2116
2117 retval = rt73usb_init_eeprom(rt2x00dev);
2118 if (retval)
2119 return retval;
2120
2121 /*
2122 * Initialize hw specifications.
2123 */
2124 retval = rt73usb_probe_hw_mode(rt2x00dev);
2125 if (retval)
2126 return retval;
2127
2128 /*
2129 * This device has multiple filters for control frames,
2130 * but has no a separate filter for PS Poll frames.
2131 */
2132 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2133
2134 /*
2135 * This device requires firmware.
2136 */
2137 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2138 if (!modparam_nohwcrypt)
2139 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2140 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2141 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags);
2142
2143 /*
2144 * Set the rssi offset.
2145 */
2146 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2147
2148 return 0;
2149 }
2150
2151 /*
2152 * IEEE80211 stack callback functions.
2153 */
2154 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2155 const struct ieee80211_tx_queue_params *params)
2156 {
2157 struct rt2x00_dev *rt2x00dev = hw->priv;
2158 struct data_queue *queue;
2159 struct rt2x00_field32 field;
2160 int retval;
2161 u32 reg;
2162 u32 offset;
2163
2164 /*
2165 * First pass the configuration through rt2x00lib, that will
2166 * update the queue settings and validate the input. After that
2167 * we are free to update the registers based on the value
2168 * in the queue parameter.
2169 */
2170 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2171 if (retval)
2172 return retval;
2173
2174 /*
2175 * We only need to perform additional register initialization
2176 * for WMM queues/
2177 */
2178 if (queue_idx >= 4)
2179 return 0;
2180
2181 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2182
2183 /* Update WMM TXOP register */
2184 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2185 field.bit_offset = (queue_idx & 1) * 16;
2186 field.bit_mask = 0xffff << field.bit_offset;
2187
2188 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2189 rt2x00_set_field32(&reg, field, queue->txop);
2190 rt2x00usb_register_write(rt2x00dev, offset, reg);
2191
2192 /* Update WMM registers */
2193 field.bit_offset = queue_idx * 4;
2194 field.bit_mask = 0xf << field.bit_offset;
2195
2196 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2197 rt2x00_set_field32(&reg, field, queue->aifs);
2198 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2199
2200 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2201 rt2x00_set_field32(&reg, field, queue->cw_min);
2202 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2203
2204 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2205 rt2x00_set_field32(&reg, field, queue->cw_max);
2206 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2207
2208 return 0;
2209 }
2210
2211 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2212 {
2213 struct rt2x00_dev *rt2x00dev = hw->priv;
2214 u64 tsf;
2215 u32 reg;
2216
2217 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2218 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2219 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2220 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2221
2222 return tsf;
2223 }
2224
2225 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2226 .tx = rt2x00mac_tx,
2227 .start = rt2x00mac_start,
2228 .stop = rt2x00mac_stop,
2229 .add_interface = rt2x00mac_add_interface,
2230 .remove_interface = rt2x00mac_remove_interface,
2231 .config = rt2x00mac_config,
2232 .configure_filter = rt2x00mac_configure_filter,
2233 .set_tim = rt2x00mac_set_tim,
2234 .set_key = rt2x00mac_set_key,
2235 .sw_scan_start = rt2x00mac_sw_scan_start,
2236 .sw_scan_complete = rt2x00mac_sw_scan_complete,
2237 .get_stats = rt2x00mac_get_stats,
2238 .bss_info_changed = rt2x00mac_bss_info_changed,
2239 .conf_tx = rt73usb_conf_tx,
2240 .get_tsf = rt73usb_get_tsf,
2241 .rfkill_poll = rt2x00mac_rfkill_poll,
2242 };
2243
2244 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2245 .probe_hw = rt73usb_probe_hw,
2246 .get_firmware_name = rt73usb_get_firmware_name,
2247 .check_firmware = rt73usb_check_firmware,
2248 .load_firmware = rt73usb_load_firmware,
2249 .initialize = rt2x00usb_initialize,
2250 .uninitialize = rt2x00usb_uninitialize,
2251 .clear_entry = rt2x00usb_clear_entry,
2252 .set_device_state = rt73usb_set_device_state,
2253 .rfkill_poll = rt73usb_rfkill_poll,
2254 .link_stats = rt73usb_link_stats,
2255 .reset_tuner = rt73usb_reset_tuner,
2256 .link_tuner = rt73usb_link_tuner,
2257 .watchdog = rt2x00usb_watchdog,
2258 .write_tx_desc = rt73usb_write_tx_desc,
2259 .write_beacon = rt73usb_write_beacon,
2260 .get_tx_data_len = rt73usb_get_tx_data_len,
2261 .kick_tx_queue = rt2x00usb_kick_tx_queue,
2262 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2263 .fill_rxdone = rt73usb_fill_rxdone,
2264 .config_shared_key = rt73usb_config_shared_key,
2265 .config_pairwise_key = rt73usb_config_pairwise_key,
2266 .config_filter = rt73usb_config_filter,
2267 .config_intf = rt73usb_config_intf,
2268 .config_erp = rt73usb_config_erp,
2269 .config_ant = rt73usb_config_ant,
2270 .config = rt73usb_config,
2271 };
2272
2273 static const struct data_queue_desc rt73usb_queue_rx = {
2274 .entry_num = RX_ENTRIES,
2275 .data_size = DATA_FRAME_SIZE,
2276 .desc_size = RXD_DESC_SIZE,
2277 .priv_size = sizeof(struct queue_entry_priv_usb),
2278 };
2279
2280 static const struct data_queue_desc rt73usb_queue_tx = {
2281 .entry_num = TX_ENTRIES,
2282 .data_size = DATA_FRAME_SIZE,
2283 .desc_size = TXD_DESC_SIZE,
2284 .priv_size = sizeof(struct queue_entry_priv_usb),
2285 };
2286
2287 static const struct data_queue_desc rt73usb_queue_bcn = {
2288 .entry_num = 4 * BEACON_ENTRIES,
2289 .data_size = MGMT_FRAME_SIZE,
2290 .desc_size = TXINFO_SIZE,
2291 .priv_size = sizeof(struct queue_entry_priv_usb),
2292 };
2293
2294 static const struct rt2x00_ops rt73usb_ops = {
2295 .name = KBUILD_MODNAME,
2296 .max_sta_intf = 1,
2297 .max_ap_intf = 4,
2298 .eeprom_size = EEPROM_SIZE,
2299 .rf_size = RF_SIZE,
2300 .tx_queues = NUM_TX_QUEUES,
2301 .extra_tx_headroom = TXD_DESC_SIZE,
2302 .rx = &rt73usb_queue_rx,
2303 .tx = &rt73usb_queue_tx,
2304 .bcn = &rt73usb_queue_bcn,
2305 .lib = &rt73usb_rt2x00_ops,
2306 .hw = &rt73usb_mac80211_ops,
2307 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2308 .debugfs = &rt73usb_rt2x00debug,
2309 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2310 };
2311
2312 /*
2313 * rt73usb module information.
2314 */
2315 static struct usb_device_id rt73usb_device_table[] = {
2316 /* AboCom */
2317 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2318 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
2319 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2320 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2321 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2322 /* AL */
2323 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
2324 /* Amigo */
2325 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2326 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2327 /* AMIT */
2328 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
2329 /* Askey */
2330 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2331 /* ASUS */
2332 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2333 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2334 /* Belkin */
2335 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2336 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2337 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2338 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2339 /* Billionton */
2340 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2341 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2342 /* Buffalo */
2343 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2344 { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
2345 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2346 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2347 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
2348 /* CEIVA */
2349 { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
2350 /* CNet */
2351 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2352 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2353 /* Conceptronic */
2354 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2355 /* Corega */
2356 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2357 /* D-Link */
2358 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2359 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2360 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2361 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2362 /* Edimax */
2363 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2364 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2365 /* EnGenius */
2366 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
2367 /* Gemtek */
2368 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2369 /* Gigabyte */
2370 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2371 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2372 /* Huawei-3Com */
2373 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2374 /* Hercules */
2375 { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
2376 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2377 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2378 /* Linksys */
2379 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2380 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2381 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2382 /* MSI */
2383 { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
2384 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2385 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2386 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2387 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2388 /* Ovislink */
2389 { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2390 /* Ralink */
2391 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
2392 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2393 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2394 /* Qcom */
2395 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2396 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2397 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2398 /* Samsung */
2399 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
2400 /* Senao */
2401 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2402 /* Sitecom */
2403 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2404 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2405 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
2406 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2407 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2408 /* Surecom */
2409 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2410 /* Tilgin */
2411 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
2412 /* Philips */
2413 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
2414 /* Planex */
2415 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2416 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2417 /* WideTell */
2418 { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
2419 /* Zcom */
2420 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
2421 /* ZyXEL */
2422 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
2423 { 0, }
2424 };
2425
2426 MODULE_AUTHOR(DRV_PROJECT);
2427 MODULE_VERSION(DRV_VERSION);
2428 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2429 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2430 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2431 MODULE_FIRMWARE(FIRMWARE_RT2571);
2432 MODULE_LICENSE("GPL");
2433
2434 static struct usb_driver rt73usb_driver = {
2435 .name = KBUILD_MODNAME,
2436 .id_table = rt73usb_device_table,
2437 .probe = rt2x00usb_probe,
2438 .disconnect = rt2x00usb_disconnect,
2439 .suspend = rt2x00usb_suspend,
2440 .resume = rt2x00usb_resume,
2441 };
2442
2443 static int __init rt73usb_init(void)
2444 {
2445 return usb_register(&rt73usb_driver);
2446 }
2447
2448 static void __exit rt73usb_exit(void)
2449 {
2450 usb_deregister(&rt73usb_driver);
2451 }
2452
2453 module_init(rt73usb_init);
2454 module_exit(rt73usb_exit);
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