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Merge commit 'v2.6.29' into timers/core
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00usb.h"
37 #include "rt73usb.h"
38
39 /*
40 * Allow hardware encryption to be disabled.
41 */
42 static int modparam_nohwcrypt = 0;
43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64
65 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
66 const unsigned int word, const u8 value)
67 {
68 u32 reg;
69
70 mutex_lock(&rt2x00dev->csr_mutex);
71
72 /*
73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
75 */
76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
84 }
85
86 mutex_unlock(&rt2x00dev->csr_mutex);
87 }
88
89 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
90 const unsigned int word, u8 *value)
91 {
92 u32 reg;
93
94 mutex_lock(&rt2x00dev->csr_mutex);
95
96 /*
97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
103 */
104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
109
110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
111
112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
116
117 mutex_unlock(&rt2x00dev->csr_mutex);
118 }
119
120 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
121 const unsigned int word, const u32 value)
122 {
123 u32 reg;
124
125 if (!word)
126 return;
127
128 mutex_lock(&rt2x00dev->csr_mutex);
129
130 /*
131 * Wait until the RF becomes available, afterwards we
132 * can safely write the new data into the register.
133 */
134 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
135 reg = 0;
136 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
137 /*
138 * RF5225 and RF2527 contain 21 bits per RF register value,
139 * all others contain 20 bits.
140 */
141 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
142 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
143 rt2x00_rf(&rt2x00dev->chip, RF2527)));
144 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
145 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
146
147 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
148 rt2x00_rf_write(rt2x00dev, word, value);
149 }
150
151 mutex_unlock(&rt2x00dev->csr_mutex);
152 }
153
154 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
155 static const struct rt2x00debug rt73usb_rt2x00debug = {
156 .owner = THIS_MODULE,
157 .csr = {
158 .read = rt2x00usb_register_read,
159 .write = rt2x00usb_register_write,
160 .flags = RT2X00DEBUGFS_OFFSET,
161 .word_base = CSR_REG_BASE,
162 .word_size = sizeof(u32),
163 .word_count = CSR_REG_SIZE / sizeof(u32),
164 },
165 .eeprom = {
166 .read = rt2x00_eeprom_read,
167 .write = rt2x00_eeprom_write,
168 .word_base = EEPROM_BASE,
169 .word_size = sizeof(u16),
170 .word_count = EEPROM_SIZE / sizeof(u16),
171 },
172 .bbp = {
173 .read = rt73usb_bbp_read,
174 .write = rt73usb_bbp_write,
175 .word_base = BBP_BASE,
176 .word_size = sizeof(u8),
177 .word_count = BBP_SIZE / sizeof(u8),
178 },
179 .rf = {
180 .read = rt2x00_rf_read,
181 .write = rt73usb_rf_write,
182 .word_base = RF_BASE,
183 .word_size = sizeof(u32),
184 .word_count = RF_SIZE / sizeof(u32),
185 },
186 };
187 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
188
189 #ifdef CONFIG_RT2X00_LIB_LEDS
190 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
191 enum led_brightness brightness)
192 {
193 struct rt2x00_led *led =
194 container_of(led_cdev, struct rt2x00_led, led_dev);
195 unsigned int enabled = brightness != LED_OFF;
196 unsigned int a_mode =
197 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
198 unsigned int bg_mode =
199 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
200
201 if (led->type == LED_TYPE_RADIO) {
202 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
203 MCU_LEDCS_RADIO_STATUS, enabled);
204
205 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
206 0, led->rt2x00dev->led_mcu_reg,
207 REGISTER_TIMEOUT);
208 } else if (led->type == LED_TYPE_ASSOC) {
209 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
210 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
211 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
212 MCU_LEDCS_LINK_A_STATUS, a_mode);
213
214 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
215 0, led->rt2x00dev->led_mcu_reg,
216 REGISTER_TIMEOUT);
217 } else if (led->type == LED_TYPE_QUALITY) {
218 /*
219 * The brightness is divided into 6 levels (0 - 5),
220 * this means we need to convert the brightness
221 * argument into the matching level within that range.
222 */
223 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
224 brightness / (LED_FULL / 6),
225 led->rt2x00dev->led_mcu_reg,
226 REGISTER_TIMEOUT);
227 }
228 }
229
230 static int rt73usb_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233 {
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
239 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
241 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
242
243 return 0;
244 }
245
246 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249 {
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt73usb_brightness_set;
253 led->led_dev.blink_set = rt73usb_blink_set;
254 led->flags = LED_INITIALIZED;
255 }
256 #endif /* CONFIG_RT2X00_LIB_LEDS */
257
258 /*
259 * Configuration handlers.
260 */
261 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
262 struct rt2x00lib_crypto *crypto,
263 struct ieee80211_key_conf *key)
264 {
265 struct hw_key_entry key_entry;
266 struct rt2x00_field32 field;
267 int timeout;
268 u32 mask;
269 u32 reg;
270
271 if (crypto->cmd == SET_KEY) {
272 /*
273 * rt2x00lib can't determine the correct free
274 * key_idx for shared keys. We have 1 register
275 * with key valid bits. The goal is simple, read
276 * the register, if that is full we have no slots
277 * left.
278 * Note that each BSS is allowed to have up to 4
279 * shared keys, so put a mask over the allowed
280 * entries.
281 */
282 mask = (0xf << crypto->bssidx);
283
284 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
285 reg &= mask;
286
287 if (reg && reg == mask)
288 return -ENOSPC;
289
290 key->hw_key_idx += reg ? ffz(reg) : 0;
291
292 /*
293 * Upload key to hardware
294 */
295 memcpy(key_entry.key, crypto->key,
296 sizeof(key_entry.key));
297 memcpy(key_entry.tx_mic, crypto->tx_mic,
298 sizeof(key_entry.tx_mic));
299 memcpy(key_entry.rx_mic, crypto->rx_mic,
300 sizeof(key_entry.rx_mic));
301
302 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
303 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
304 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
305 USB_VENDOR_REQUEST_OUT, reg,
306 &key_entry,
307 sizeof(key_entry),
308 timeout);
309
310 /*
311 * The cipher types are stored over 2 registers.
312 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
313 * bssidx 1 and 2 keys are stored in SEC_CSR5.
314 * Using the correct defines correctly will cause overhead,
315 * so just calculate the correct offset.
316 */
317 if (key->hw_key_idx < 8) {
318 field.bit_offset = (3 * key->hw_key_idx);
319 field.bit_mask = 0x7 << field.bit_offset;
320
321 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
322 rt2x00_set_field32(&reg, field, crypto->cipher);
323 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
324 } else {
325 field.bit_offset = (3 * (key->hw_key_idx - 8));
326 field.bit_mask = 0x7 << field.bit_offset;
327
328 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
329 rt2x00_set_field32(&reg, field, crypto->cipher);
330 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
331 }
332
333 /*
334 * The driver does not support the IV/EIV generation
335 * in hardware. However it doesn't support the IV/EIV
336 * inside the ieee80211 frame either, but requires it
337 * to be provided seperately for the descriptor.
338 * rt2x00lib will cut the IV/EIV data out of all frames
339 * given to us by mac80211, but we must tell mac80211
340 * to generate the IV/EIV data.
341 */
342 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
343 }
344
345 /*
346 * SEC_CSR0 contains only single-bit fields to indicate
347 * a particular key is valid. Because using the FIELD32()
348 * defines directly will cause a lot of overhead we use
349 * a calculation to determine the correct bit directly.
350 */
351 mask = 1 << key->hw_key_idx;
352
353 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
354 if (crypto->cmd == SET_KEY)
355 reg |= mask;
356 else if (crypto->cmd == DISABLE_KEY)
357 reg &= ~mask;
358 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
359
360 return 0;
361 }
362
363 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
364 struct rt2x00lib_crypto *crypto,
365 struct ieee80211_key_conf *key)
366 {
367 struct hw_pairwise_ta_entry addr_entry;
368 struct hw_key_entry key_entry;
369 int timeout;
370 u32 mask;
371 u32 reg;
372
373 if (crypto->cmd == SET_KEY) {
374 /*
375 * rt2x00lib can't determine the correct free
376 * key_idx for pairwise keys. We have 2 registers
377 * with key valid bits. The goal is simple, read
378 * the first register, if that is full move to
379 * the next register.
380 * When both registers are full, we drop the key,
381 * otherwise we use the first invalid entry.
382 */
383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
384 if (reg && reg == ~0) {
385 key->hw_key_idx = 32;
386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
387 if (reg && reg == ~0)
388 return -ENOSPC;
389 }
390
391 key->hw_key_idx += reg ? ffz(reg) : 0;
392
393 /*
394 * Upload key to hardware
395 */
396 memcpy(key_entry.key, crypto->key,
397 sizeof(key_entry.key));
398 memcpy(key_entry.tx_mic, crypto->tx_mic,
399 sizeof(key_entry.tx_mic));
400 memcpy(key_entry.rx_mic, crypto->rx_mic,
401 sizeof(key_entry.rx_mic));
402
403 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
404 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
405 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
406 USB_VENDOR_REQUEST_OUT, reg,
407 &key_entry,
408 sizeof(key_entry),
409 timeout);
410
411 /*
412 * Send the address and cipher type to the hardware register.
413 * This data fits within the CSR cache size, so we can use
414 * rt2x00usb_register_multiwrite() directly.
415 */
416 memset(&addr_entry, 0, sizeof(addr_entry));
417 memcpy(&addr_entry, crypto->address, ETH_ALEN);
418 addr_entry.cipher = crypto->cipher;
419
420 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
421 rt2x00usb_register_multiwrite(rt2x00dev, reg,
422 &addr_entry, sizeof(addr_entry));
423
424 /*
425 * Enable pairwise lookup table for given BSS idx,
426 * without this received frames will not be decrypted
427 * by the hardware.
428 */
429 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
430 reg |= (1 << crypto->bssidx);
431 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
432
433 /*
434 * The driver does not support the IV/EIV generation
435 * in hardware. However it doesn't support the IV/EIV
436 * inside the ieee80211 frame either, but requires it
437 * to be provided seperately for the descriptor.
438 * rt2x00lib will cut the IV/EIV data out of all frames
439 * given to us by mac80211, but we must tell mac80211
440 * to generate the IV/EIV data.
441 */
442 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
443 }
444
445 /*
446 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
447 * a particular key is valid. Because using the FIELD32()
448 * defines directly will cause a lot of overhead we use
449 * a calculation to determine the correct bit directly.
450 */
451 if (key->hw_key_idx < 32) {
452 mask = 1 << key->hw_key_idx;
453
454 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
455 if (crypto->cmd == SET_KEY)
456 reg |= mask;
457 else if (crypto->cmd == DISABLE_KEY)
458 reg &= ~mask;
459 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
460 } else {
461 mask = 1 << (key->hw_key_idx - 32);
462
463 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
464 if (crypto->cmd == SET_KEY)
465 reg |= mask;
466 else if (crypto->cmd == DISABLE_KEY)
467 reg &= ~mask;
468 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
469 }
470
471 return 0;
472 }
473
474 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
475 const unsigned int filter_flags)
476 {
477 u32 reg;
478
479 /*
480 * Start configuration steps.
481 * Note that the version error will always be dropped
482 * and broadcast frames will always be accepted since
483 * there is no filter for it at this time.
484 */
485 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
487 !(filter_flags & FIF_FCSFAIL));
488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
489 !(filter_flags & FIF_PLCPFAIL));
490 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
491 !(filter_flags & FIF_CONTROL));
492 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
493 !(filter_flags & FIF_PROMISC_IN_BSS));
494 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
495 !(filter_flags & FIF_PROMISC_IN_BSS) &&
496 !rt2x00dev->intf_ap_count);
497 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
498 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
499 !(filter_flags & FIF_ALLMULTI));
500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
501 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
502 !(filter_flags & FIF_CONTROL));
503 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
504 }
505
506 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
507 struct rt2x00_intf *intf,
508 struct rt2x00intf_conf *conf,
509 const unsigned int flags)
510 {
511 unsigned int beacon_base;
512 u32 reg;
513
514 if (flags & CONFIG_UPDATE_TYPE) {
515 /*
516 * Clear current synchronisation setup.
517 * For the Beacon base registers we only need to clear
518 * the first byte since that byte contains the VALID and OWNER
519 * bits which (when set to 0) will invalidate the entire beacon.
520 */
521 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
522 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
523
524 /*
525 * Enable synchronisation.
526 */
527 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
528 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
529 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
530 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
531 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
532 }
533
534 if (flags & CONFIG_UPDATE_MAC) {
535 reg = le32_to_cpu(conf->mac[1]);
536 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
537 conf->mac[1] = cpu_to_le32(reg);
538
539 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
540 conf->mac, sizeof(conf->mac));
541 }
542
543 if (flags & CONFIG_UPDATE_BSSID) {
544 reg = le32_to_cpu(conf->bssid[1]);
545 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
546 conf->bssid[1] = cpu_to_le32(reg);
547
548 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
549 conf->bssid, sizeof(conf->bssid));
550 }
551 }
552
553 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
554 struct rt2x00lib_erp *erp)
555 {
556 u32 reg;
557
558 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
559 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
560 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
561
562 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
563 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
564 !!erp->short_preamble);
565 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
566
567 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
568
569 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
570 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
571 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
572
573 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
574 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
576 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
577 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
578 }
579
580 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
581 struct antenna_setup *ant)
582 {
583 u8 r3;
584 u8 r4;
585 u8 r77;
586 u8 temp;
587
588 rt73usb_bbp_read(rt2x00dev, 3, &r3);
589 rt73usb_bbp_read(rt2x00dev, 4, &r4);
590 rt73usb_bbp_read(rt2x00dev, 77, &r77);
591
592 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
593
594 /*
595 * Configure the RX antenna.
596 */
597 switch (ant->rx) {
598 case ANTENNA_HW_DIVERSITY:
599 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
600 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
601 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
602 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
603 break;
604 case ANTENNA_A:
605 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
606 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
607 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
608 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
609 else
610 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
611 break;
612 case ANTENNA_B:
613 default:
614 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
615 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
616 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
617 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
618 else
619 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
620 break;
621 }
622
623 rt73usb_bbp_write(rt2x00dev, 77, r77);
624 rt73usb_bbp_write(rt2x00dev, 3, r3);
625 rt73usb_bbp_write(rt2x00dev, 4, r4);
626 }
627
628 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
629 struct antenna_setup *ant)
630 {
631 u8 r3;
632 u8 r4;
633 u8 r77;
634
635 rt73usb_bbp_read(rt2x00dev, 3, &r3);
636 rt73usb_bbp_read(rt2x00dev, 4, &r4);
637 rt73usb_bbp_read(rt2x00dev, 77, &r77);
638
639 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
640 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
641 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
642
643 /*
644 * Configure the RX antenna.
645 */
646 switch (ant->rx) {
647 case ANTENNA_HW_DIVERSITY:
648 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
649 break;
650 case ANTENNA_A:
651 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
652 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
653 break;
654 case ANTENNA_B:
655 default:
656 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
657 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
658 break;
659 }
660
661 rt73usb_bbp_write(rt2x00dev, 77, r77);
662 rt73usb_bbp_write(rt2x00dev, 3, r3);
663 rt73usb_bbp_write(rt2x00dev, 4, r4);
664 }
665
666 struct antenna_sel {
667 u8 word;
668 /*
669 * value[0] -> non-LNA
670 * value[1] -> LNA
671 */
672 u8 value[2];
673 };
674
675 static const struct antenna_sel antenna_sel_a[] = {
676 { 96, { 0x58, 0x78 } },
677 { 104, { 0x38, 0x48 } },
678 { 75, { 0xfe, 0x80 } },
679 { 86, { 0xfe, 0x80 } },
680 { 88, { 0xfe, 0x80 } },
681 { 35, { 0x60, 0x60 } },
682 { 97, { 0x58, 0x58 } },
683 { 98, { 0x58, 0x58 } },
684 };
685
686 static const struct antenna_sel antenna_sel_bg[] = {
687 { 96, { 0x48, 0x68 } },
688 { 104, { 0x2c, 0x3c } },
689 { 75, { 0xfe, 0x80 } },
690 { 86, { 0xfe, 0x80 } },
691 { 88, { 0xfe, 0x80 } },
692 { 35, { 0x50, 0x50 } },
693 { 97, { 0x48, 0x48 } },
694 { 98, { 0x48, 0x48 } },
695 };
696
697 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
698 struct antenna_setup *ant)
699 {
700 const struct antenna_sel *sel;
701 unsigned int lna;
702 unsigned int i;
703 u32 reg;
704
705 /*
706 * We should never come here because rt2x00lib is supposed
707 * to catch this and send us the correct antenna explicitely.
708 */
709 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
710 ant->tx == ANTENNA_SW_DIVERSITY);
711
712 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
713 sel = antenna_sel_a;
714 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
715 } else {
716 sel = antenna_sel_bg;
717 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
718 }
719
720 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
721 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
722
723 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
724
725 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
726 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
727 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
728 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
729
730 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
731
732 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
733 rt2x00_rf(&rt2x00dev->chip, RF5225))
734 rt73usb_config_antenna_5x(rt2x00dev, ant);
735 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
736 rt2x00_rf(&rt2x00dev->chip, RF2527))
737 rt73usb_config_antenna_2x(rt2x00dev, ant);
738 }
739
740 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
741 struct rt2x00lib_conf *libconf)
742 {
743 u16 eeprom;
744 short lna_gain = 0;
745
746 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
747 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
748 lna_gain += 14;
749
750 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
751 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
752 } else {
753 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
754 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
755 }
756
757 rt2x00dev->lna_gain = lna_gain;
758 }
759
760 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
761 struct rf_channel *rf, const int txpower)
762 {
763 u8 r3;
764 u8 r94;
765 u8 smart;
766
767 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
768 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
769
770 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
771 rt2x00_rf(&rt2x00dev->chip, RF2527));
772
773 rt73usb_bbp_read(rt2x00dev, 3, &r3);
774 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
775 rt73usb_bbp_write(rt2x00dev, 3, r3);
776
777 r94 = 6;
778 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
779 r94 += txpower - MAX_TXPOWER;
780 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
781 r94 += txpower;
782 rt73usb_bbp_write(rt2x00dev, 94, r94);
783
784 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788
789 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
790 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
791 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
792 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
793
794 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
795 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
796 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
797 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
798
799 udelay(10);
800 }
801
802 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
803 const int txpower)
804 {
805 struct rf_channel rf;
806
807 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
808 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
809 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
810 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
811
812 rt73usb_config_channel(rt2x00dev, &rf, txpower);
813 }
814
815 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
816 struct rt2x00lib_conf *libconf)
817 {
818 u32 reg;
819
820 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
821 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
822 libconf->conf->long_frame_max_tx_count);
823 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
824 libconf->conf->short_frame_max_tx_count);
825 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
826 }
827
828 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
829 struct rt2x00lib_conf *libconf)
830 {
831 u32 reg;
832
833 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
834 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
835 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
836
837 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
838 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
839 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
840
841 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
842 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
843 libconf->conf->beacon_int * 16);
844 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
845 }
846
847 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
848 struct rt2x00lib_conf *libconf,
849 const unsigned int flags)
850 {
851 /* Always recalculate LNA gain before changing configuration */
852 rt73usb_config_lna_gain(rt2x00dev, libconf);
853
854 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
855 rt73usb_config_channel(rt2x00dev, &libconf->rf,
856 libconf->conf->power_level);
857 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
858 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
859 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
860 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
861 rt73usb_config_retry_limit(rt2x00dev, libconf);
862 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
863 rt73usb_config_duration(rt2x00dev, libconf);
864 }
865
866 /*
867 * Link tuning
868 */
869 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
870 struct link_qual *qual)
871 {
872 u32 reg;
873
874 /*
875 * Update FCS error count from register.
876 */
877 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
878 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
879
880 /*
881 * Update False CCA count from register.
882 */
883 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
884 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
885 }
886
887 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
888 {
889 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
890 rt2x00dev->link.vgc_level = 0x20;
891 }
892
893 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
894 {
895 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
896 u8 r17;
897 u8 up_bound;
898 u8 low_bound;
899
900 rt73usb_bbp_read(rt2x00dev, 17, &r17);
901
902 /*
903 * Determine r17 bounds.
904 */
905 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
906 low_bound = 0x28;
907 up_bound = 0x48;
908
909 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
910 low_bound += 0x10;
911 up_bound += 0x10;
912 }
913 } else {
914 if (rssi > -82) {
915 low_bound = 0x1c;
916 up_bound = 0x40;
917 } else if (rssi > -84) {
918 low_bound = 0x1c;
919 up_bound = 0x20;
920 } else {
921 low_bound = 0x1c;
922 up_bound = 0x1c;
923 }
924
925 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
926 low_bound += 0x14;
927 up_bound += 0x10;
928 }
929 }
930
931 /*
932 * If we are not associated, we should go straight to the
933 * dynamic CCA tuning.
934 */
935 if (!rt2x00dev->intf_associated)
936 goto dynamic_cca_tune;
937
938 /*
939 * Special big-R17 for very short distance
940 */
941 if (rssi > -35) {
942 if (r17 != 0x60)
943 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
944 return;
945 }
946
947 /*
948 * Special big-R17 for short distance
949 */
950 if (rssi >= -58) {
951 if (r17 != up_bound)
952 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
953 return;
954 }
955
956 /*
957 * Special big-R17 for middle-short distance
958 */
959 if (rssi >= -66) {
960 low_bound += 0x10;
961 if (r17 != low_bound)
962 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
963 return;
964 }
965
966 /*
967 * Special mid-R17 for middle distance
968 */
969 if (rssi >= -74) {
970 if (r17 != (low_bound + 0x10))
971 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
972 return;
973 }
974
975 /*
976 * Special case: Change up_bound based on the rssi.
977 * Lower up_bound when rssi is weaker then -74 dBm.
978 */
979 up_bound -= 2 * (-74 - rssi);
980 if (low_bound > up_bound)
981 up_bound = low_bound;
982
983 if (r17 > up_bound) {
984 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
985 return;
986 }
987
988 dynamic_cca_tune:
989
990 /*
991 * r17 does not yet exceed upper limit, continue and base
992 * the r17 tuning on the false CCA count.
993 */
994 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
995 r17 += 4;
996 if (r17 > up_bound)
997 r17 = up_bound;
998 rt73usb_bbp_write(rt2x00dev, 17, r17);
999 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1000 r17 -= 4;
1001 if (r17 < low_bound)
1002 r17 = low_bound;
1003 rt73usb_bbp_write(rt2x00dev, 17, r17);
1004 }
1005 }
1006
1007 /*
1008 * Firmware functions
1009 */
1010 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1011 {
1012 return FIRMWARE_RT2571;
1013 }
1014
1015 static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
1016 {
1017 u16 crc;
1018
1019 /*
1020 * Use the crc itu-t algorithm.
1021 * The last 2 bytes in the firmware array are the crc checksum itself,
1022 * this means that we should never pass those 2 bytes to the crc
1023 * algorithm.
1024 */
1025 crc = crc_itu_t(0, data, len - 2);
1026 crc = crc_itu_t_byte(crc, 0);
1027 crc = crc_itu_t_byte(crc, 0);
1028
1029 return crc;
1030 }
1031
1032 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1033 const size_t len)
1034 {
1035 unsigned int i;
1036 int status;
1037 u32 reg;
1038
1039 /*
1040 * Wait for stable hardware.
1041 */
1042 for (i = 0; i < 100; i++) {
1043 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1044 if (reg)
1045 break;
1046 msleep(1);
1047 }
1048
1049 if (!reg) {
1050 ERROR(rt2x00dev, "Unstable hardware.\n");
1051 return -EBUSY;
1052 }
1053
1054 /*
1055 * Write firmware to device.
1056 */
1057 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1058 USB_VENDOR_REQUEST_OUT,
1059 FIRMWARE_IMAGE_BASE,
1060 data, len,
1061 REGISTER_TIMEOUT32(len));
1062
1063 /*
1064 * Send firmware request to device to load firmware,
1065 * we need to specify a long timeout time.
1066 */
1067 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1068 0, USB_MODE_FIRMWARE,
1069 REGISTER_TIMEOUT_FIRMWARE);
1070 if (status < 0) {
1071 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1072 return status;
1073 }
1074
1075 return 0;
1076 }
1077
1078 /*
1079 * Initialization functions.
1080 */
1081 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1082 {
1083 u32 reg;
1084
1085 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1086 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1087 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1088 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1089 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1090
1091 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1092 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1093 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1094 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1095 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1096 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1097 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1098 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1099 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1100 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1101
1102 /*
1103 * CCK TXD BBP registers
1104 */
1105 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1106 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1107 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1108 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1109 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1110 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1111 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1112 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1113 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1114 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1115
1116 /*
1117 * OFDM TXD BBP registers
1118 */
1119 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1120 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1121 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1122 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1123 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1124 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1125 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1126 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1127
1128 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1129 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1130 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1131 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1132 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1133 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1134
1135 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1136 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1137 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1138 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1139 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1140 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1141
1142 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1143 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1144 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1145 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1146 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1147 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1148 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1149 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1150
1151 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1152
1153 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1154 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1155 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1156
1157 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1158
1159 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1160 return -EBUSY;
1161
1162 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1163
1164 /*
1165 * Invalidate all Shared Keys (SEC_CSR0),
1166 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1167 */
1168 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1169 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1170 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1171
1172 reg = 0x000023b0;
1173 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1174 rt2x00_rf(&rt2x00dev->chip, RF2527))
1175 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1176 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1177
1178 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1179 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1180 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1181
1182 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1183 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1184 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1185
1186 /*
1187 * Clear all beacons
1188 * For the Beacon base registers we only need to clear
1189 * the first byte since that byte contains the VALID and OWNER
1190 * bits which (when set to 0) will invalidate the entire beacon.
1191 */
1192 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1193 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1194 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1195 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1196
1197 /*
1198 * We must clear the error counters.
1199 * These registers are cleared on read,
1200 * so we may pass a useless variable to store the value.
1201 */
1202 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1203 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1204 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1205
1206 /*
1207 * Reset MAC and BBP registers.
1208 */
1209 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1210 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1211 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1212 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1213
1214 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1215 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1216 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1217 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1218
1219 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1220 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1221 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1222
1223 return 0;
1224 }
1225
1226 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1227 {
1228 unsigned int i;
1229 u8 value;
1230
1231 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1232 rt73usb_bbp_read(rt2x00dev, 0, &value);
1233 if ((value != 0xff) && (value != 0x00))
1234 return 0;
1235 udelay(REGISTER_BUSY_DELAY);
1236 }
1237
1238 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1239 return -EACCES;
1240 }
1241
1242 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1243 {
1244 unsigned int i;
1245 u16 eeprom;
1246 u8 reg_id;
1247 u8 value;
1248
1249 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1250 return -EACCES;
1251
1252 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1253 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1254 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1255 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1256 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1257 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1258 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1259 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1260 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1261 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1262 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1263 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1264 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1265 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1266 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1267 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1268 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1269 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1270 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1271 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1272 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1273 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1274 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1275 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1276 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1277
1278 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1279 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1280
1281 if (eeprom != 0xffff && eeprom != 0x0000) {
1282 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1283 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1284 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1285 }
1286 }
1287
1288 return 0;
1289 }
1290
1291 /*
1292 * Device state switch handlers.
1293 */
1294 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1295 enum dev_state state)
1296 {
1297 u32 reg;
1298
1299 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1300 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1301 (state == STATE_RADIO_RX_OFF) ||
1302 (state == STATE_RADIO_RX_OFF_LINK));
1303 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1304 }
1305
1306 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1307 {
1308 /*
1309 * Initialize all registers.
1310 */
1311 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1312 rt73usb_init_bbp(rt2x00dev)))
1313 return -EIO;
1314
1315 return 0;
1316 }
1317
1318 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1319 {
1320 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1321
1322 /*
1323 * Disable synchronisation.
1324 */
1325 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1326
1327 rt2x00usb_disable_radio(rt2x00dev);
1328 }
1329
1330 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1331 {
1332 u32 reg;
1333 unsigned int i;
1334 char put_to_sleep;
1335
1336 put_to_sleep = (state != STATE_AWAKE);
1337
1338 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1339 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1340 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1341 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1342
1343 /*
1344 * Device is not guaranteed to be in the requested state yet.
1345 * We must wait until the register indicates that the
1346 * device has entered the correct state.
1347 */
1348 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1349 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1350 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1351 if (state == !put_to_sleep)
1352 return 0;
1353 msleep(10);
1354 }
1355
1356 return -EBUSY;
1357 }
1358
1359 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1360 enum dev_state state)
1361 {
1362 int retval = 0;
1363
1364 switch (state) {
1365 case STATE_RADIO_ON:
1366 retval = rt73usb_enable_radio(rt2x00dev);
1367 break;
1368 case STATE_RADIO_OFF:
1369 rt73usb_disable_radio(rt2x00dev);
1370 break;
1371 case STATE_RADIO_RX_ON:
1372 case STATE_RADIO_RX_ON_LINK:
1373 case STATE_RADIO_RX_OFF:
1374 case STATE_RADIO_RX_OFF_LINK:
1375 rt73usb_toggle_rx(rt2x00dev, state);
1376 break;
1377 case STATE_RADIO_IRQ_ON:
1378 case STATE_RADIO_IRQ_OFF:
1379 /* No support, but no error either */
1380 break;
1381 case STATE_DEEP_SLEEP:
1382 case STATE_SLEEP:
1383 case STATE_STANDBY:
1384 case STATE_AWAKE:
1385 retval = rt73usb_set_state(rt2x00dev, state);
1386 break;
1387 default:
1388 retval = -ENOTSUPP;
1389 break;
1390 }
1391
1392 if (unlikely(retval))
1393 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1394 state, retval);
1395
1396 return retval;
1397 }
1398
1399 /*
1400 * TX descriptor initialization
1401 */
1402 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1403 struct sk_buff *skb,
1404 struct txentry_desc *txdesc)
1405 {
1406 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1407 __le32 *txd = skbdesc->desc;
1408 u32 word;
1409
1410 /*
1411 * Start writing the descriptor words.
1412 */
1413 rt2x00_desc_read(txd, 1, &word);
1414 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1415 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1416 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1417 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1418 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1419 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1420 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1421 rt2x00_desc_write(txd, 1, word);
1422
1423 rt2x00_desc_read(txd, 2, &word);
1424 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1425 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1426 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1427 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1428 rt2x00_desc_write(txd, 2, word);
1429
1430 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1431 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1432 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1433 }
1434
1435 rt2x00_desc_read(txd, 5, &word);
1436 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1437 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1438 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1439 rt2x00_desc_write(txd, 5, word);
1440
1441 rt2x00_desc_read(txd, 0, &word);
1442 rt2x00_set_field32(&word, TXD_W0_BURST,
1443 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1444 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1445 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1446 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1447 rt2x00_set_field32(&word, TXD_W0_ACK,
1448 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1449 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1450 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1451 rt2x00_set_field32(&word, TXD_W0_OFDM,
1452 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1453 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1454 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1455 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1456 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1457 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1458 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1459 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1460 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1461 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1462 rt2x00_set_field32(&word, TXD_W0_BURST2,
1463 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1464 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1465 rt2x00_desc_write(txd, 0, word);
1466 }
1467
1468 /*
1469 * TX data initialization
1470 */
1471 static void rt73usb_write_beacon(struct queue_entry *entry)
1472 {
1473 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1474 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1475 unsigned int beacon_base;
1476 u32 reg;
1477
1478 /*
1479 * Add the descriptor in front of the skb.
1480 */
1481 skb_push(entry->skb, entry->queue->desc_size);
1482 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1483 skbdesc->desc = entry->skb->data;
1484
1485 /*
1486 * Disable beaconing while we are reloading the beacon data,
1487 * otherwise we might be sending out invalid data.
1488 */
1489 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1490 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1491 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1492 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1493 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1494
1495 /*
1496 * Write entire beacon with descriptor to register.
1497 */
1498 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1499 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1500 USB_VENDOR_REQUEST_OUT, beacon_base,
1501 entry->skb->data, entry->skb->len,
1502 REGISTER_TIMEOUT32(entry->skb->len));
1503
1504 /*
1505 * Clean up the beacon skb.
1506 */
1507 dev_kfree_skb(entry->skb);
1508 entry->skb = NULL;
1509 }
1510
1511 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1512 {
1513 int length;
1514
1515 /*
1516 * The length _must_ be a multiple of 4,
1517 * but it must _not_ be a multiple of the USB packet size.
1518 */
1519 length = roundup(entry->skb->len, 4);
1520 length += (4 * !(length % entry->queue->usb_maxpacket));
1521
1522 return length;
1523 }
1524
1525 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1526 const enum data_queue_qid queue)
1527 {
1528 u32 reg;
1529
1530 if (queue != QID_BEACON) {
1531 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1532 return;
1533 }
1534
1535 /*
1536 * For Wi-Fi faily generated beacons between participating stations.
1537 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1538 */
1539 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1540
1541 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1542 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1543 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1544 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1545 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1546 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1547 }
1548 }
1549
1550 /*
1551 * RX control handlers
1552 */
1553 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1554 {
1555 u8 offset = rt2x00dev->lna_gain;
1556 u8 lna;
1557
1558 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1559 switch (lna) {
1560 case 3:
1561 offset += 90;
1562 break;
1563 case 2:
1564 offset += 74;
1565 break;
1566 case 1:
1567 offset += 64;
1568 break;
1569 default:
1570 return 0;
1571 }
1572
1573 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1574 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1575 if (lna == 3 || lna == 2)
1576 offset += 10;
1577 } else {
1578 if (lna == 3)
1579 offset += 6;
1580 else if (lna == 2)
1581 offset += 8;
1582 }
1583 }
1584
1585 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1586 }
1587
1588 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1589 struct rxdone_entry_desc *rxdesc)
1590 {
1591 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1592 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1593 __le32 *rxd = (__le32 *)entry->skb->data;
1594 u32 word0;
1595 u32 word1;
1596
1597 /*
1598 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1599 * frame data in rt2x00usb.
1600 */
1601 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1602 rxd = (__le32 *)skbdesc->desc;
1603
1604 /*
1605 * It is now safe to read the descriptor on all architectures.
1606 */
1607 rt2x00_desc_read(rxd, 0, &word0);
1608 rt2x00_desc_read(rxd, 1, &word1);
1609
1610 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1611 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1612
1613 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1614 rxdesc->cipher =
1615 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1616 rxdesc->cipher_status =
1617 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1618 }
1619
1620 if (rxdesc->cipher != CIPHER_NONE) {
1621 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1622 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1623 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1624
1625 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1626 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1627
1628 /*
1629 * Hardware has stripped IV/EIV data from 802.11 frame during
1630 * decryption. It has provided the data seperately but rt2x00lib
1631 * should decide if it should be reinserted.
1632 */
1633 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1634
1635 /*
1636 * FIXME: Legacy driver indicates that the frame does
1637 * contain the Michael Mic. Unfortunately, in rt2x00
1638 * the MIC seems to be missing completely...
1639 */
1640 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1641
1642 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1643 rxdesc->flags |= RX_FLAG_DECRYPTED;
1644 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1645 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1646 }
1647
1648 /*
1649 * Obtain the status about this packet.
1650 * When frame was received with an OFDM bitrate,
1651 * the signal is the PLCP value. If it was received with
1652 * a CCK bitrate the signal is the rate in 100kbit/s.
1653 */
1654 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1655 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1656 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1657
1658 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1659 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1660 else
1661 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1662 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1663 rxdesc->dev_flags |= RXDONE_MY_BSS;
1664
1665 /*
1666 * Set skb pointers, and update frame information.
1667 */
1668 skb_pull(entry->skb, entry->queue->desc_size);
1669 skb_trim(entry->skb, rxdesc->size);
1670 }
1671
1672 /*
1673 * Device probe functions.
1674 */
1675 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1676 {
1677 u16 word;
1678 u8 *mac;
1679 s8 value;
1680
1681 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1682
1683 /*
1684 * Start validation of the data that has been read.
1685 */
1686 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1687 if (!is_valid_ether_addr(mac)) {
1688 random_ether_addr(mac);
1689 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1690 }
1691
1692 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1693 if (word == 0xffff) {
1694 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1695 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1696 ANTENNA_B);
1697 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1698 ANTENNA_B);
1699 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1700 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1701 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1702 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1703 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1704 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1705 }
1706
1707 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1708 if (word == 0xffff) {
1709 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1710 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1711 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1712 }
1713
1714 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1715 if (word == 0xffff) {
1716 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1717 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1718 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1719 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1720 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1721 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1722 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1723 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1724 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1725 LED_MODE_DEFAULT);
1726 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1727 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1728 }
1729
1730 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1731 if (word == 0xffff) {
1732 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1733 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1734 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1735 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1736 }
1737
1738 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1739 if (word == 0xffff) {
1740 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1741 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1742 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1743 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1744 } else {
1745 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1746 if (value < -10 || value > 10)
1747 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1748 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1749 if (value < -10 || value > 10)
1750 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1751 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1752 }
1753
1754 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1755 if (word == 0xffff) {
1756 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1757 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1758 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1759 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1760 } else {
1761 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1762 if (value < -10 || value > 10)
1763 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1764 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1765 if (value < -10 || value > 10)
1766 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1767 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1768 }
1769
1770 return 0;
1771 }
1772
1773 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1774 {
1775 u32 reg;
1776 u16 value;
1777 u16 eeprom;
1778
1779 /*
1780 * Read EEPROM word for configuration.
1781 */
1782 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1783
1784 /*
1785 * Identify RF chipset.
1786 */
1787 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1788 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1789 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1790
1791 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1792 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1793 return -ENODEV;
1794 }
1795
1796 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1797 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1798 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1799 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1800 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1801 return -ENODEV;
1802 }
1803
1804 /*
1805 * Identify default antenna configuration.
1806 */
1807 rt2x00dev->default_ant.tx =
1808 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1809 rt2x00dev->default_ant.rx =
1810 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1811
1812 /*
1813 * Read the Frame type.
1814 */
1815 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1816 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1817
1818 /*
1819 * Read frequency offset.
1820 */
1821 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1822 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1823
1824 /*
1825 * Read external LNA informations.
1826 */
1827 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1828
1829 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1830 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1831 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1832 }
1833
1834 /*
1835 * Store led settings, for correct led behaviour.
1836 */
1837 #ifdef CONFIG_RT2X00_LIB_LEDS
1838 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1839
1840 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1841 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1842 if (value == LED_MODE_SIGNAL_STRENGTH)
1843 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1844 LED_TYPE_QUALITY);
1845
1846 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1847 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1848 rt2x00_get_field16(eeprom,
1849 EEPROM_LED_POLARITY_GPIO_0));
1850 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1851 rt2x00_get_field16(eeprom,
1852 EEPROM_LED_POLARITY_GPIO_1));
1853 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1854 rt2x00_get_field16(eeprom,
1855 EEPROM_LED_POLARITY_GPIO_2));
1856 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1857 rt2x00_get_field16(eeprom,
1858 EEPROM_LED_POLARITY_GPIO_3));
1859 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1860 rt2x00_get_field16(eeprom,
1861 EEPROM_LED_POLARITY_GPIO_4));
1862 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1863 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1864 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1865 rt2x00_get_field16(eeprom,
1866 EEPROM_LED_POLARITY_RDY_G));
1867 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1868 rt2x00_get_field16(eeprom,
1869 EEPROM_LED_POLARITY_RDY_A));
1870 #endif /* CONFIG_RT2X00_LIB_LEDS */
1871
1872 return 0;
1873 }
1874
1875 /*
1876 * RF value list for RF2528
1877 * Supports: 2.4 GHz
1878 */
1879 static const struct rf_channel rf_vals_bg_2528[] = {
1880 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1881 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1882 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1883 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1884 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1885 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1886 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1887 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1888 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1889 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1890 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1891 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1892 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1893 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1894 };
1895
1896 /*
1897 * RF value list for RF5226
1898 * Supports: 2.4 GHz & 5.2 GHz
1899 */
1900 static const struct rf_channel rf_vals_5226[] = {
1901 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1902 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1903 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1904 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1905 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1906 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1907 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1908 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1909 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1910 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1911 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1912 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1913 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1914 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1915
1916 /* 802.11 UNI / HyperLan 2 */
1917 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1918 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1919 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1920 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1921 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1922 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1923 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1924 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1925
1926 /* 802.11 HyperLan 2 */
1927 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1928 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1929 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1930 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1931 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1932 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1933 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1934 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1935 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1936 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1937
1938 /* 802.11 UNII */
1939 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1940 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1941 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1942 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1943 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1944 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1945
1946 /* MMAC(Japan)J52 ch 34,38,42,46 */
1947 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1948 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1949 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1950 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1951 };
1952
1953 /*
1954 * RF value list for RF5225 & RF2527
1955 * Supports: 2.4 GHz & 5.2 GHz
1956 */
1957 static const struct rf_channel rf_vals_5225_2527[] = {
1958 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1959 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1960 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1961 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1962 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1963 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1964 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1965 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1966 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1967 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1968 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1969 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1970 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1971 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1972
1973 /* 802.11 UNI / HyperLan 2 */
1974 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1975 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1976 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1977 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1978 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1979 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1980 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1981 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1982
1983 /* 802.11 HyperLan 2 */
1984 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1985 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1986 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1987 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1988 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1989 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1990 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1991 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1992 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1993 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1994
1995 /* 802.11 UNII */
1996 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1997 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1998 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1999 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2000 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2001 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2002
2003 /* MMAC(Japan)J52 ch 34,38,42,46 */
2004 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2005 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2006 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2007 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2008 };
2009
2010
2011 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2012 {
2013 struct hw_mode_spec *spec = &rt2x00dev->spec;
2014 struct channel_info *info;
2015 char *tx_power;
2016 unsigned int i;
2017
2018 /*
2019 * Initialize all hw fields.
2020 */
2021 rt2x00dev->hw->flags =
2022 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2023 IEEE80211_HW_SIGNAL_DBM;
2024 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2025
2026 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2027 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2028 rt2x00_eeprom_addr(rt2x00dev,
2029 EEPROM_MAC_ADDR_0));
2030
2031 /*
2032 * Initialize hw_mode information.
2033 */
2034 spec->supported_bands = SUPPORT_BAND_2GHZ;
2035 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2036
2037 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2038 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2039 spec->channels = rf_vals_bg_2528;
2040 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2041 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2042 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2043 spec->channels = rf_vals_5226;
2044 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2045 spec->num_channels = 14;
2046 spec->channels = rf_vals_5225_2527;
2047 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2048 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2049 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2050 spec->channels = rf_vals_5225_2527;
2051 }
2052
2053 /*
2054 * Create channel information array
2055 */
2056 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2057 if (!info)
2058 return -ENOMEM;
2059
2060 spec->channels_info = info;
2061
2062 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2063 for (i = 0; i < 14; i++)
2064 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2065
2066 if (spec->num_channels > 14) {
2067 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2068 for (i = 14; i < spec->num_channels; i++)
2069 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2070 }
2071
2072 return 0;
2073 }
2074
2075 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2076 {
2077 int retval;
2078
2079 /*
2080 * Allocate eeprom data.
2081 */
2082 retval = rt73usb_validate_eeprom(rt2x00dev);
2083 if (retval)
2084 return retval;
2085
2086 retval = rt73usb_init_eeprom(rt2x00dev);
2087 if (retval)
2088 return retval;
2089
2090 /*
2091 * Initialize hw specifications.
2092 */
2093 retval = rt73usb_probe_hw_mode(rt2x00dev);
2094 if (retval)
2095 return retval;
2096
2097 /*
2098 * This device requires firmware.
2099 */
2100 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2101 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2102 if (!modparam_nohwcrypt)
2103 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2104
2105 /*
2106 * Set the rssi offset.
2107 */
2108 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2109
2110 return 0;
2111 }
2112
2113 /*
2114 * IEEE80211 stack callback functions.
2115 */
2116 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2117 const struct ieee80211_tx_queue_params *params)
2118 {
2119 struct rt2x00_dev *rt2x00dev = hw->priv;
2120 struct data_queue *queue;
2121 struct rt2x00_field32 field;
2122 int retval;
2123 u32 reg;
2124
2125 /*
2126 * First pass the configuration through rt2x00lib, that will
2127 * update the queue settings and validate the input. After that
2128 * we are free to update the registers based on the value
2129 * in the queue parameter.
2130 */
2131 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2132 if (retval)
2133 return retval;
2134
2135 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2136
2137 /* Update WMM TXOP register */
2138 if (queue_idx < 2) {
2139 field.bit_offset = queue_idx * 16;
2140 field.bit_mask = 0xffff << field.bit_offset;
2141
2142 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2143 rt2x00_set_field32(&reg, field, queue->txop);
2144 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2145 } else if (queue_idx < 4) {
2146 field.bit_offset = (queue_idx - 2) * 16;
2147 field.bit_mask = 0xffff << field.bit_offset;
2148
2149 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2150 rt2x00_set_field32(&reg, field, queue->txop);
2151 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2152 }
2153
2154 /* Update WMM registers */
2155 field.bit_offset = queue_idx * 4;
2156 field.bit_mask = 0xf << field.bit_offset;
2157
2158 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2159 rt2x00_set_field32(&reg, field, queue->aifs);
2160 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2161
2162 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2163 rt2x00_set_field32(&reg, field, queue->cw_min);
2164 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2165
2166 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2167 rt2x00_set_field32(&reg, field, queue->cw_max);
2168 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2169
2170 return 0;
2171 }
2172
2173 #if 0
2174 /*
2175 * Mac80211 demands get_tsf must be atomic.
2176 * This is not possible for rt73usb since all register access
2177 * functions require sleeping. Untill mac80211 no longer needs
2178 * get_tsf to be atomic, this function should be disabled.
2179 */
2180 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2181 {
2182 struct rt2x00_dev *rt2x00dev = hw->priv;
2183 u64 tsf;
2184 u32 reg;
2185
2186 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2187 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2188 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2189 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2190
2191 return tsf;
2192 }
2193 #else
2194 #define rt73usb_get_tsf NULL
2195 #endif
2196
2197 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2198 .tx = rt2x00mac_tx,
2199 .start = rt2x00mac_start,
2200 .stop = rt2x00mac_stop,
2201 .add_interface = rt2x00mac_add_interface,
2202 .remove_interface = rt2x00mac_remove_interface,
2203 .config = rt2x00mac_config,
2204 .config_interface = rt2x00mac_config_interface,
2205 .configure_filter = rt2x00mac_configure_filter,
2206 .set_key = rt2x00mac_set_key,
2207 .get_stats = rt2x00mac_get_stats,
2208 .bss_info_changed = rt2x00mac_bss_info_changed,
2209 .conf_tx = rt73usb_conf_tx,
2210 .get_tx_stats = rt2x00mac_get_tx_stats,
2211 .get_tsf = rt73usb_get_tsf,
2212 };
2213
2214 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2215 .probe_hw = rt73usb_probe_hw,
2216 .get_firmware_name = rt73usb_get_firmware_name,
2217 .get_firmware_crc = rt73usb_get_firmware_crc,
2218 .load_firmware = rt73usb_load_firmware,
2219 .initialize = rt2x00usb_initialize,
2220 .uninitialize = rt2x00usb_uninitialize,
2221 .clear_entry = rt2x00usb_clear_entry,
2222 .set_device_state = rt73usb_set_device_state,
2223 .link_stats = rt73usb_link_stats,
2224 .reset_tuner = rt73usb_reset_tuner,
2225 .link_tuner = rt73usb_link_tuner,
2226 .write_tx_desc = rt73usb_write_tx_desc,
2227 .write_tx_data = rt2x00usb_write_tx_data,
2228 .write_beacon = rt73usb_write_beacon,
2229 .get_tx_data_len = rt73usb_get_tx_data_len,
2230 .kick_tx_queue = rt73usb_kick_tx_queue,
2231 .fill_rxdone = rt73usb_fill_rxdone,
2232 .config_shared_key = rt73usb_config_shared_key,
2233 .config_pairwise_key = rt73usb_config_pairwise_key,
2234 .config_filter = rt73usb_config_filter,
2235 .config_intf = rt73usb_config_intf,
2236 .config_erp = rt73usb_config_erp,
2237 .config_ant = rt73usb_config_ant,
2238 .config = rt73usb_config,
2239 };
2240
2241 static const struct data_queue_desc rt73usb_queue_rx = {
2242 .entry_num = RX_ENTRIES,
2243 .data_size = DATA_FRAME_SIZE,
2244 .desc_size = RXD_DESC_SIZE,
2245 .priv_size = sizeof(struct queue_entry_priv_usb),
2246 };
2247
2248 static const struct data_queue_desc rt73usb_queue_tx = {
2249 .entry_num = TX_ENTRIES,
2250 .data_size = DATA_FRAME_SIZE,
2251 .desc_size = TXD_DESC_SIZE,
2252 .priv_size = sizeof(struct queue_entry_priv_usb),
2253 };
2254
2255 static const struct data_queue_desc rt73usb_queue_bcn = {
2256 .entry_num = 4 * BEACON_ENTRIES,
2257 .data_size = MGMT_FRAME_SIZE,
2258 .desc_size = TXINFO_SIZE,
2259 .priv_size = sizeof(struct queue_entry_priv_usb),
2260 };
2261
2262 static const struct rt2x00_ops rt73usb_ops = {
2263 .name = KBUILD_MODNAME,
2264 .max_sta_intf = 1,
2265 .max_ap_intf = 4,
2266 .eeprom_size = EEPROM_SIZE,
2267 .rf_size = RF_SIZE,
2268 .tx_queues = NUM_TX_QUEUES,
2269 .rx = &rt73usb_queue_rx,
2270 .tx = &rt73usb_queue_tx,
2271 .bcn = &rt73usb_queue_bcn,
2272 .lib = &rt73usb_rt2x00_ops,
2273 .hw = &rt73usb_mac80211_ops,
2274 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2275 .debugfs = &rt73usb_rt2x00debug,
2276 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2277 };
2278
2279 /*
2280 * rt73usb module information.
2281 */
2282 static struct usb_device_id rt73usb_device_table[] = {
2283 /* AboCom */
2284 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2285 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
2286 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2287 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2288 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2289 /* AL */
2290 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
2291 /* Amigo */
2292 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2293 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2294 /* AMIT */
2295 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
2296 /* Askey */
2297 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2298 /* ASUS */
2299 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2300 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2301 /* Belkin */
2302 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2303 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2304 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2305 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2306 /* Billionton */
2307 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2308 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2309 /* Buffalo */
2310 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2311 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2312 /* CNet */
2313 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2314 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2315 /* Conceptronic */
2316 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2317 /* Corega */
2318 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2319 /* D-Link */
2320 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2321 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2322 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2323 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2324 /* Edimax */
2325 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2326 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2327 /* EnGenius */
2328 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
2329 /* Gemtek */
2330 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2331 /* Gigabyte */
2332 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2333 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2334 /* Huawei-3Com */
2335 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2336 /* Hercules */
2337 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2338 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2339 /* Linksys */
2340 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2341 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2342 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2343 /* MSI */
2344 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2345 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2346 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2347 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2348 /* Ralink */
2349 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
2350 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2351 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2352 /* Qcom */
2353 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2354 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2355 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2356 /* Samsung */
2357 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
2358 /* Senao */
2359 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2360 /* Sitecom */
2361 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2362 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2363 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
2364 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2365 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2366 /* Surecom */
2367 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2368 /* Philips */
2369 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
2370 /* Planex */
2371 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2372 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2373 /* Zcom */
2374 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
2375 /* ZyXEL */
2376 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
2377 { 0, }
2378 };
2379
2380 MODULE_AUTHOR(DRV_PROJECT);
2381 MODULE_VERSION(DRV_VERSION);
2382 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2383 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2384 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2385 MODULE_FIRMWARE(FIRMWARE_RT2571);
2386 MODULE_LICENSE("GPL");
2387
2388 static struct usb_driver rt73usb_driver = {
2389 .name = KBUILD_MODNAME,
2390 .id_table = rt73usb_device_table,
2391 .probe = rt2x00usb_probe,
2392 .disconnect = rt2x00usb_disconnect,
2393 .suspend = rt2x00usb_suspend,
2394 .resume = rt2x00usb_resume,
2395 };
2396
2397 static int __init rt73usb_init(void)
2398 {
2399 return usb_register(&rt73usb_driver);
2400 }
2401
2402 static void __exit rt73usb_exit(void)
2403 {
2404 usb_deregister(&rt73usb_driver);
2405 }
2406
2407 module_init(rt73usb_init);
2408 module_exit(rt73usb_exit);
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