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[PATCH] rt2x00: Move quality statistics into seperate structure
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt73usb"
31
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/usb.h>
38
39 #include "rt2x00.h"
40 #include "rt2x00usb.h"
41 #include "rt73usb.h"
42
43 /*
44 * Register access.
45 * All access to the CSR registers will go through the methods
46 * rt73usb_register_read and rt73usb_register_write.
47 * BBP and RF register require indirect register access,
48 * and use the CSR registers BBPCSR and RFCSR to achieve this.
49 * These indirect registers work with busy bits,
50 * and we will try maximal REGISTER_BUSY_COUNT times to access
51 * the register while taking a REGISTER_BUSY_DELAY us delay
52 * between each attampt. When the busy bit is still set at that time,
53 * the access attempt is considered to have failed,
54 * and we will print an error.
55 */
56 static inline void rt73usb_register_read(const struct rt2x00_dev *rt2x00dev,
57 const unsigned int offset, u32 *value)
58 {
59 __le32 reg;
60 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
61 USB_VENDOR_REQUEST_IN, offset,
62 &reg, sizeof(u32), REGISTER_TIMEOUT);
63 *value = le32_to_cpu(reg);
64 }
65
66 static inline void rt73usb_register_multiread(const struct rt2x00_dev
67 *rt2x00dev,
68 const unsigned int offset,
69 void *value, const u32 length)
70 {
71 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
72 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
73 USB_VENDOR_REQUEST_IN, offset,
74 value, length, timeout);
75 }
76
77 static inline void rt73usb_register_write(const struct rt2x00_dev *rt2x00dev,
78 const unsigned int offset, u32 value)
79 {
80 __le32 reg = cpu_to_le32(value);
81 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
82 USB_VENDOR_REQUEST_OUT, offset,
83 &reg, sizeof(u32), REGISTER_TIMEOUT);
84 }
85
86 static inline void rt73usb_register_multiwrite(const struct rt2x00_dev
87 *rt2x00dev,
88 const unsigned int offset,
89 void *value, const u32 length)
90 {
91 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
92 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
93 USB_VENDOR_REQUEST_OUT, offset,
94 value, length, timeout);
95 }
96
97 static u32 rt73usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
98 {
99 u32 reg;
100 unsigned int i;
101
102 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
103 rt73usb_register_read(rt2x00dev, PHY_CSR3, &reg);
104 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
105 break;
106 udelay(REGISTER_BUSY_DELAY);
107 }
108
109 return reg;
110 }
111
112 static void rt73usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, const u8 value)
114 {
115 u32 reg;
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt73usb_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
122 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
123 return;
124 }
125
126 /*
127 * Write the data into the BBP.
128 */
129 reg = 0;
130 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
131 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
132 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
133 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
134
135 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
136 }
137
138 static void rt73usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
139 const unsigned int word, u8 *value)
140 {
141 u32 reg;
142
143 /*
144 * Wait until the BBP becomes ready.
145 */
146 reg = rt73usb_bbp_check(rt2x00dev);
147 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
148 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
149 return;
150 }
151
152 /*
153 * Write the request into the BBP.
154 */
155 reg = 0;
156 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
157 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
158 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
159
160 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
161
162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
168 *value = 0xff;
169 return;
170 }
171
172 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
173 }
174
175 static void rt73usb_rf_write(const struct rt2x00_dev *rt2x00dev,
176 const unsigned int word, const u32 value)
177 {
178 u32 reg;
179 unsigned int i;
180
181 if (!word)
182 return;
183
184 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
185 rt73usb_register_read(rt2x00dev, PHY_CSR4, &reg);
186 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
187 goto rf_write;
188 udelay(REGISTER_BUSY_DELAY);
189 }
190
191 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
192 return;
193
194 rf_write:
195 reg = 0;
196 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
197
198 /*
199 * RF5225 and RF2527 contain 21 bits per RF register value,
200 * all others contain 20 bits.
201 */
202 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
203 20 + !!(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
204 rt2x00_rf(&rt2x00dev->chip, RF2527)));
205 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
206 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
207
208 rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
209 rt2x00_rf_write(rt2x00dev, word, value);
210 }
211
212 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
213 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
214
215 static void rt73usb_read_csr(const struct rt2x00_dev *rt2x00dev,
216 const unsigned int word, u32 *data)
217 {
218 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
219 }
220
221 static void rt73usb_write_csr(const struct rt2x00_dev *rt2x00dev,
222 const unsigned int word, u32 data)
223 {
224 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
225 }
226
227 static const struct rt2x00debug rt73usb_rt2x00debug = {
228 .owner = THIS_MODULE,
229 .csr = {
230 .read = rt73usb_read_csr,
231 .write = rt73usb_write_csr,
232 .word_size = sizeof(u32),
233 .word_count = CSR_REG_SIZE / sizeof(u32),
234 },
235 .eeprom = {
236 .read = rt2x00_eeprom_read,
237 .write = rt2x00_eeprom_write,
238 .word_size = sizeof(u16),
239 .word_count = EEPROM_SIZE / sizeof(u16),
240 },
241 .bbp = {
242 .read = rt73usb_bbp_read,
243 .write = rt73usb_bbp_write,
244 .word_size = sizeof(u8),
245 .word_count = BBP_SIZE / sizeof(u8),
246 },
247 .rf = {
248 .read = rt2x00_rf_read,
249 .write = rt73usb_rf_write,
250 .word_size = sizeof(u32),
251 .word_count = RF_SIZE / sizeof(u32),
252 },
253 };
254 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
255
256 /*
257 * Configuration handlers.
258 */
259 static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
260 {
261 u32 tmp;
262
263 tmp = le32_to_cpu(mac[1]);
264 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
265 mac[1] = cpu_to_le32(tmp);
266
267 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
268 (2 * sizeof(__le32)));
269 }
270
271 static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
272 {
273 u32 tmp;
274
275 tmp = le32_to_cpu(bssid[1]);
276 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
277 bssid[1] = cpu_to_le32(tmp);
278
279 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
280 (2 * sizeof(__le32)));
281 }
282
283 static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
284 const int tsf_sync)
285 {
286 u32 reg;
287
288 /*
289 * Clear current synchronisation setup.
290 * For the Beacon base registers we only need to clear
291 * the first byte since that byte contains the VALID and OWNER
292 * bits which (when set to 0) will invalidate the entire beacon.
293 */
294 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
295 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
296 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
297 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
298 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
299
300 /*
301 * Enable synchronisation.
302 */
303 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
304 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
305 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
306 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
307 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
308 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
309 }
310
311 static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
312 const int short_preamble,
313 const int ack_timeout,
314 const int ack_consume_time)
315 {
316 u32 reg;
317
318 /*
319 * When in atomic context, reschedule and let rt2x00lib
320 * call this function again.
321 */
322 if (in_atomic()) {
323 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
324 return;
325 }
326
327 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
328 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
329 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
330
331 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
332 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
333 !!short_preamble);
334 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
335 }
336
337 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
338 const int basic_rate_mask)
339 {
340 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
341 }
342
343 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
344 struct rf_channel *rf, const int txpower)
345 {
346 u8 r3;
347 u8 r94;
348 u8 smart;
349
350 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
351 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
352
353 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
354 rt2x00_rf(&rt2x00dev->chip, RF2527));
355
356 rt73usb_bbp_read(rt2x00dev, 3, &r3);
357 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
358 rt73usb_bbp_write(rt2x00dev, 3, r3);
359
360 r94 = 6;
361 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
362 r94 += txpower - MAX_TXPOWER;
363 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
364 r94 += txpower;
365 rt73usb_bbp_write(rt2x00dev, 94, r94);
366
367 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
368 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
369 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
370 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
371
372 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
373 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
374 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
375 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
376
377 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
378 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
379 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
380 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
381
382 udelay(10);
383 }
384
385 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
386 const int txpower)
387 {
388 struct rf_channel rf;
389
390 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
391 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
392 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
393 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
394
395 rt73usb_config_channel(rt2x00dev, &rf, txpower);
396 }
397
398 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
399 const int antenna_tx,
400 const int antenna_rx)
401 {
402 u8 r3;
403 u8 r4;
404 u8 r77;
405
406 rt73usb_bbp_read(rt2x00dev, 3, &r3);
407 rt73usb_bbp_read(rt2x00dev, 4, &r4);
408 rt73usb_bbp_read(rt2x00dev, 77, &r77);
409
410 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
411
412 switch (antenna_rx) {
413 case ANTENNA_SW_DIVERSITY:
414 case ANTENNA_HW_DIVERSITY:
415 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
416 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
417 !!(rt2x00dev->curr_hwmode != HWMODE_A));
418 break;
419 case ANTENNA_A:
420 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
421 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
422
423 if (rt2x00dev->curr_hwmode == HWMODE_A)
424 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
425 else
426 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
427 break;
428 case ANTENNA_B:
429 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
430 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
431
432 if (rt2x00dev->curr_hwmode == HWMODE_A)
433 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
434 else
435 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
436 break;
437 }
438
439 rt73usb_bbp_write(rt2x00dev, 77, r77);
440 rt73usb_bbp_write(rt2x00dev, 3, r3);
441 rt73usb_bbp_write(rt2x00dev, 4, r4);
442 }
443
444 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
445 const int antenna_tx,
446 const int antenna_rx)
447 {
448 u8 r3;
449 u8 r4;
450 u8 r77;
451
452 rt73usb_bbp_read(rt2x00dev, 3, &r3);
453 rt73usb_bbp_read(rt2x00dev, 4, &r4);
454 rt73usb_bbp_read(rt2x00dev, 77, &r77);
455
456 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
457 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
458 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
459
460 switch (antenna_rx) {
461 case ANTENNA_SW_DIVERSITY:
462 case ANTENNA_HW_DIVERSITY:
463 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
464 break;
465 case ANTENNA_A:
466 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
467 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
468 break;
469 case ANTENNA_B:
470 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
471 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
472 break;
473 }
474
475 rt73usb_bbp_write(rt2x00dev, 77, r77);
476 rt73usb_bbp_write(rt2x00dev, 3, r3);
477 rt73usb_bbp_write(rt2x00dev, 4, r4);
478 }
479
480 struct antenna_sel {
481 u8 word;
482 /*
483 * value[0] -> non-LNA
484 * value[1] -> LNA
485 */
486 u8 value[2];
487 };
488
489 static const struct antenna_sel antenna_sel_a[] = {
490 { 96, { 0x58, 0x78 } },
491 { 104, { 0x38, 0x48 } },
492 { 75, { 0xfe, 0x80 } },
493 { 86, { 0xfe, 0x80 } },
494 { 88, { 0xfe, 0x80 } },
495 { 35, { 0x60, 0x60 } },
496 { 97, { 0x58, 0x58 } },
497 { 98, { 0x58, 0x58 } },
498 };
499
500 static const struct antenna_sel antenna_sel_bg[] = {
501 { 96, { 0x48, 0x68 } },
502 { 104, { 0x2c, 0x3c } },
503 { 75, { 0xfe, 0x80 } },
504 { 86, { 0xfe, 0x80 } },
505 { 88, { 0xfe, 0x80 } },
506 { 35, { 0x50, 0x50 } },
507 { 97, { 0x48, 0x48 } },
508 { 98, { 0x48, 0x48 } },
509 };
510
511 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
512 const int antenna_tx, const int antenna_rx)
513 {
514 const struct antenna_sel *sel;
515 unsigned int lna;
516 unsigned int i;
517 u32 reg;
518
519 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
520
521 if (rt2x00dev->curr_hwmode == HWMODE_A) {
522 sel = antenna_sel_a;
523 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
524
525 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
526 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
527 } else {
528 sel = antenna_sel_bg;
529 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
530
531 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
532 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
533 }
534
535 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
536 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
537
538 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
539
540 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
541 rt2x00_rf(&rt2x00dev->chip, RF5225))
542 rt73usb_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
543 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
544 rt2x00_rf(&rt2x00dev->chip, RF2527))
545 rt73usb_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
546 }
547
548 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
549 struct rt2x00lib_conf *libconf)
550 {
551 u32 reg;
552
553 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
554 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
555 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
556
557 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
558 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
559 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
560 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
561 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
562
563 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
564 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
565 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
566
567 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
568 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
569 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
570
571 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
572 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
573 libconf->conf->beacon_int * 16);
574 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
575 }
576
577 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
578 const unsigned int flags,
579 struct rt2x00lib_conf *libconf)
580 {
581 if (flags & CONFIG_UPDATE_PHYMODE)
582 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
583 if (flags & CONFIG_UPDATE_CHANNEL)
584 rt73usb_config_channel(rt2x00dev, &libconf->rf,
585 libconf->conf->power_level);
586 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
587 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
588 if (flags & CONFIG_UPDATE_ANTENNA)
589 rt73usb_config_antenna(rt2x00dev, libconf->conf->antenna_sel_tx,
590 libconf->conf->antenna_sel_rx);
591 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
592 rt73usb_config_duration(rt2x00dev, libconf);
593 }
594
595 /*
596 * LED functions.
597 */
598 static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
599 {
600 u32 reg;
601
602 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
603 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
604 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
605 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
606
607 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
608 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
609 rt2x00_set_field16(&rt2x00dev->led_reg,
610 MCU_LEDCS_LINK_A_STATUS, 1);
611 else
612 rt2x00_set_field16(&rt2x00dev->led_reg,
613 MCU_LEDCS_LINK_BG_STATUS, 1);
614
615 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
616 rt2x00dev->led_reg, REGISTER_TIMEOUT);
617 }
618
619 static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
620 {
621 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
622 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
623 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
624
625 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
626 rt2x00dev->led_reg, REGISTER_TIMEOUT);
627 }
628
629 static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
630 {
631 u32 led;
632
633 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
634 return;
635
636 /*
637 * Led handling requires a positive value for the rssi,
638 * to do that correctly we need to add the correction.
639 */
640 rssi += rt2x00dev->rssi_offset;
641
642 if (rssi <= 30)
643 led = 0;
644 else if (rssi <= 39)
645 led = 1;
646 else if (rssi <= 49)
647 led = 2;
648 else if (rssi <= 53)
649 led = 3;
650 else if (rssi <= 63)
651 led = 4;
652 else
653 led = 5;
654
655 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
656 rt2x00dev->led_reg, REGISTER_TIMEOUT);
657 }
658
659 /*
660 * Link tuning
661 */
662 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
663 struct link_qual *qual)
664 {
665 u32 reg;
666
667 /*
668 * Update FCS error count from register.
669 */
670 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
671 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
672
673 /*
674 * Update False CCA count from register.
675 */
676 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
677 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
678 }
679
680 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
681 {
682 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
683 rt2x00dev->link.vgc_level = 0x20;
684 }
685
686 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
687 {
688 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
689 u8 r17;
690 u8 up_bound;
691 u8 low_bound;
692
693 /*
694 * Update Led strength
695 */
696 rt73usb_activity_led(rt2x00dev, rssi);
697
698 rt73usb_bbp_read(rt2x00dev, 17, &r17);
699
700 /*
701 * Determine r17 bounds.
702 */
703 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
704 low_bound = 0x28;
705 up_bound = 0x48;
706
707 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
708 low_bound += 0x10;
709 up_bound += 0x10;
710 }
711 } else {
712 if (rssi > -82) {
713 low_bound = 0x1c;
714 up_bound = 0x40;
715 } else if (rssi > -84) {
716 low_bound = 0x1c;
717 up_bound = 0x20;
718 } else {
719 low_bound = 0x1c;
720 up_bound = 0x1c;
721 }
722
723 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
724 low_bound += 0x14;
725 up_bound += 0x10;
726 }
727 }
728
729 /*
730 * Special big-R17 for very short distance
731 */
732 if (rssi > -35) {
733 if (r17 != 0x60)
734 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
735 return;
736 }
737
738 /*
739 * Special big-R17 for short distance
740 */
741 if (rssi >= -58) {
742 if (r17 != up_bound)
743 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
744 return;
745 }
746
747 /*
748 * Special big-R17 for middle-short distance
749 */
750 if (rssi >= -66) {
751 low_bound += 0x10;
752 if (r17 != low_bound)
753 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
754 return;
755 }
756
757 /*
758 * Special mid-R17 for middle distance
759 */
760 if (rssi >= -74) {
761 if (r17 != (low_bound + 0x10))
762 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
763 return;
764 }
765
766 /*
767 * Special case: Change up_bound based on the rssi.
768 * Lower up_bound when rssi is weaker then -74 dBm.
769 */
770 up_bound -= 2 * (-74 - rssi);
771 if (low_bound > up_bound)
772 up_bound = low_bound;
773
774 if (r17 > up_bound) {
775 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
776 return;
777 }
778
779 /*
780 * r17 does not yet exceed upper limit, continue and base
781 * the r17 tuning on the false CCA count.
782 */
783 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
784 r17 += 4;
785 if (r17 > up_bound)
786 r17 = up_bound;
787 rt73usb_bbp_write(rt2x00dev, 17, r17);
788 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
789 r17 -= 4;
790 if (r17 < low_bound)
791 r17 = low_bound;
792 rt73usb_bbp_write(rt2x00dev, 17, r17);
793 }
794 }
795
796 /*
797 * Firmware name function.
798 */
799 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
800 {
801 return FIRMWARE_RT2571;
802 }
803
804 /*
805 * Initialization functions.
806 */
807 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
808 const size_t len)
809 {
810 unsigned int i;
811 int status;
812 u32 reg;
813 char *ptr = data;
814 char *cache;
815 int buflen;
816 int timeout;
817
818 /*
819 * Wait for stable hardware.
820 */
821 for (i = 0; i < 100; i++) {
822 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
823 if (reg)
824 break;
825 msleep(1);
826 }
827
828 if (!reg) {
829 ERROR(rt2x00dev, "Unstable hardware.\n");
830 return -EBUSY;
831 }
832
833 /*
834 * Write firmware to device.
835 * We setup a seperate cache for this action,
836 * since we are going to write larger chunks of data
837 * then normally used cache size.
838 */
839 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
840 if (!cache) {
841 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
842 return -ENOMEM;
843 }
844
845 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
846 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
847 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
848
849 memcpy(cache, ptr, buflen);
850
851 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
852 USB_VENDOR_REQUEST_OUT,
853 FIRMWARE_IMAGE_BASE + i, 0x0000,
854 cache, buflen, timeout);
855
856 ptr += buflen;
857 }
858
859 kfree(cache);
860
861 /*
862 * Send firmware request to device to load firmware,
863 * we need to specify a long timeout time.
864 */
865 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
866 0x0000, USB_MODE_FIRMWARE,
867 REGISTER_TIMEOUT_FIRMWARE);
868 if (status < 0) {
869 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
870 return status;
871 }
872
873 rt73usb_disable_led(rt2x00dev);
874
875 return 0;
876 }
877
878 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
879 {
880 u32 reg;
881
882 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
883 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
884 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
885 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
886 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
887
888 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
889 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
890 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
891 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
892 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
893 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
894 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
895 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
896 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
897 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
898
899 /*
900 * CCK TXD BBP registers
901 */
902 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
903 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
904 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
905 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
906 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
907 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
908 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
909 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
910 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
911 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
912
913 /*
914 * OFDM TXD BBP registers
915 */
916 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
917 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
918 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
919 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
920 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
921 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
922 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
923 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
924
925 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
926 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
927 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
928 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
929 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
930 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
931
932 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
933 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
934 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
935 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
936 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
937 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
938
939 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
940
941 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
942 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
943 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
944
945 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
946
947 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
948 return -EBUSY;
949
950 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
951
952 /*
953 * Invalidate all Shared Keys (SEC_CSR0),
954 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
955 */
956 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
957 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
958 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
959
960 reg = 0x000023b0;
961 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
962 rt2x00_rf(&rt2x00dev->chip, RF2527))
963 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
964 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
965
966 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
967 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
968 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
969
970 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
971 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
972 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
973 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
974
975 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
976 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
977 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
978 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
979
980 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
981 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
982 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
983
984 /*
985 * We must clear the error counters.
986 * These registers are cleared on read,
987 * so we may pass a useless variable to store the value.
988 */
989 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
990 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
991 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
992
993 /*
994 * Reset MAC and BBP registers.
995 */
996 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
997 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
998 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
999 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1000
1001 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1002 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1003 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1004 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1005
1006 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1007 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1008 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1009
1010 return 0;
1011 }
1012
1013 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1014 {
1015 unsigned int i;
1016 u16 eeprom;
1017 u8 reg_id;
1018 u8 value;
1019
1020 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1021 rt73usb_bbp_read(rt2x00dev, 0, &value);
1022 if ((value != 0xff) && (value != 0x00))
1023 goto continue_csr_init;
1024 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1025 udelay(REGISTER_BUSY_DELAY);
1026 }
1027
1028 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1029 return -EACCES;
1030
1031 continue_csr_init:
1032 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1033 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1034 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1035 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1036 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1037 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1038 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1039 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1040 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1041 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1042 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1043 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1044 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1045 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1046 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1047 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1048 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1049 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1050 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1051 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1052 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1053 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1054 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1055 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1056 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1057
1058 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1059 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1060 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1061
1062 if (eeprom != 0xffff && eeprom != 0x0000) {
1063 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1064 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1065 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1066 reg_id, value);
1067 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1068 }
1069 }
1070 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1071
1072 return 0;
1073 }
1074
1075 /*
1076 * Device state switch handlers.
1077 */
1078 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1079 enum dev_state state)
1080 {
1081 u32 reg;
1082
1083 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1084 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1085 state == STATE_RADIO_RX_OFF);
1086 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1087 }
1088
1089 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1090 {
1091 /*
1092 * Initialize all registers.
1093 */
1094 if (rt73usb_init_registers(rt2x00dev) ||
1095 rt73usb_init_bbp(rt2x00dev)) {
1096 ERROR(rt2x00dev, "Register initialization failed.\n");
1097 return -EIO;
1098 }
1099
1100 rt2x00usb_enable_radio(rt2x00dev);
1101
1102 /*
1103 * Enable LED
1104 */
1105 rt73usb_enable_led(rt2x00dev);
1106
1107 return 0;
1108 }
1109
1110 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1111 {
1112 /*
1113 * Disable LED
1114 */
1115 rt73usb_disable_led(rt2x00dev);
1116
1117 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1118
1119 /*
1120 * Disable synchronisation.
1121 */
1122 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1123
1124 rt2x00usb_disable_radio(rt2x00dev);
1125 }
1126
1127 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1128 {
1129 u32 reg;
1130 unsigned int i;
1131 char put_to_sleep;
1132 char current_state;
1133
1134 put_to_sleep = (state != STATE_AWAKE);
1135
1136 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1137 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1138 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1139 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1140
1141 /*
1142 * Device is not guaranteed to be in the requested state yet.
1143 * We must wait until the register indicates that the
1144 * device has entered the correct state.
1145 */
1146 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1147 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1148 current_state =
1149 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1150 if (current_state == !put_to_sleep)
1151 return 0;
1152 msleep(10);
1153 }
1154
1155 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1156 "current device state %d.\n", !put_to_sleep, current_state);
1157
1158 return -EBUSY;
1159 }
1160
1161 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1162 enum dev_state state)
1163 {
1164 int retval = 0;
1165
1166 switch (state) {
1167 case STATE_RADIO_ON:
1168 retval = rt73usb_enable_radio(rt2x00dev);
1169 break;
1170 case STATE_RADIO_OFF:
1171 rt73usb_disable_radio(rt2x00dev);
1172 break;
1173 case STATE_RADIO_RX_ON:
1174 case STATE_RADIO_RX_OFF:
1175 rt73usb_toggle_rx(rt2x00dev, state);
1176 break;
1177 case STATE_DEEP_SLEEP:
1178 case STATE_SLEEP:
1179 case STATE_STANDBY:
1180 case STATE_AWAKE:
1181 retval = rt73usb_set_state(rt2x00dev, state);
1182 break;
1183 default:
1184 retval = -ENOTSUPP;
1185 break;
1186 }
1187
1188 return retval;
1189 }
1190
1191 /*
1192 * TX descriptor initialization
1193 */
1194 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1195 struct data_desc *txd,
1196 struct txdata_entry_desc *desc,
1197 struct ieee80211_hdr *ieee80211hdr,
1198 unsigned int length,
1199 struct ieee80211_tx_control *control)
1200 {
1201 u32 word;
1202
1203 /*
1204 * Start writing the descriptor words.
1205 */
1206 rt2x00_desc_read(txd, 1, &word);
1207 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1208 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1209 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1210 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1211 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1212 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1213 rt2x00_desc_write(txd, 1, word);
1214
1215 rt2x00_desc_read(txd, 2, &word);
1216 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1217 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1218 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1219 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1220 rt2x00_desc_write(txd, 2, word);
1221
1222 rt2x00_desc_read(txd, 5, &word);
1223 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1224 TXPOWER_TO_DEV(control->power_level));
1225 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1226 rt2x00_desc_write(txd, 5, word);
1227
1228 rt2x00_desc_read(txd, 0, &word);
1229 rt2x00_set_field32(&word, TXD_W0_BURST,
1230 test_bit(ENTRY_TXD_BURST, &desc->flags));
1231 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1232 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1233 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1234 rt2x00_set_field32(&word, TXD_W0_ACK,
1235 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1236 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1237 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1238 rt2x00_set_field32(&word, TXD_W0_OFDM,
1239 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1240 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1241 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1242 !!(control->flags &
1243 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1244 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1245 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1246 rt2x00_set_field32(&word, TXD_W0_BURST2,
1247 test_bit(ENTRY_TXD_BURST, &desc->flags));
1248 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1249 rt2x00_desc_write(txd, 0, word);
1250 }
1251
1252 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1253 struct sk_buff *skb)
1254 {
1255 int length;
1256
1257 /*
1258 * The length _must_ be a multiple of 4,
1259 * but it must _not_ be a multiple of the USB packet size.
1260 */
1261 length = roundup(skb->len, 4);
1262 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1263
1264 return length;
1265 }
1266
1267 /*
1268 * TX data initialization
1269 */
1270 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1271 unsigned int queue)
1272 {
1273 u32 reg;
1274
1275 if (queue != IEEE80211_TX_QUEUE_BEACON)
1276 return;
1277
1278 /*
1279 * For Wi-Fi faily generated beacons between participating stations.
1280 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1281 */
1282 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1283
1284 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1285 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1286 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1287 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1288 }
1289 }
1290
1291 /*
1292 * RX control handlers
1293 */
1294 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1295 {
1296 u16 eeprom;
1297 u8 offset;
1298 u8 lna;
1299
1300 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1301 switch (lna) {
1302 case 3:
1303 offset = 90;
1304 break;
1305 case 2:
1306 offset = 74;
1307 break;
1308 case 1:
1309 offset = 64;
1310 break;
1311 default:
1312 return 0;
1313 }
1314
1315 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1316 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1317 if (lna == 3 || lna == 2)
1318 offset += 10;
1319 } else {
1320 if (lna == 3)
1321 offset += 6;
1322 else if (lna == 2)
1323 offset += 8;
1324 }
1325
1326 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1327 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1328 } else {
1329 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1330 offset += 14;
1331
1332 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1333 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1334 }
1335
1336 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1337 }
1338
1339 static void rt73usb_fill_rxdone(struct data_entry *entry,
1340 struct rxdata_entry_desc *desc)
1341 {
1342 struct data_desc *rxd = (struct data_desc *)entry->skb->data;
1343 u32 word0;
1344 u32 word1;
1345
1346 rt2x00_desc_read(rxd, 0, &word0);
1347 rt2x00_desc_read(rxd, 1, &word1);
1348
1349 desc->flags = 0;
1350 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1351 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1352
1353 /*
1354 * Obtain the status about this packet.
1355 */
1356 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1357 desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1358 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1359 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1360
1361 /*
1362 * Pull the skb to clear the descriptor area.
1363 */
1364 skb_pull(entry->skb, entry->ring->desc_size);
1365
1366 return;
1367 }
1368
1369 /*
1370 * Device probe functions.
1371 */
1372 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1373 {
1374 u16 word;
1375 u8 *mac;
1376 s8 value;
1377
1378 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1379
1380 /*
1381 * Start validation of the data that has been read.
1382 */
1383 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1384 if (!is_valid_ether_addr(mac)) {
1385 DECLARE_MAC_BUF(macbuf);
1386
1387 random_ether_addr(mac);
1388 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1389 }
1390
1391 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1392 if (word == 0xffff) {
1393 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1394 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1395 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1396 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1397 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1398 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1399 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1400 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1401 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1402 }
1403
1404 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1405 if (word == 0xffff) {
1406 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1407 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1408 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1409 }
1410
1411 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1412 if (word == 0xffff) {
1413 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1414 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1415 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1416 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1417 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1418 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1419 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1420 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1421 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1422 LED_MODE_DEFAULT);
1423 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1424 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1425 }
1426
1427 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1428 if (word == 0xffff) {
1429 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1430 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1431 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1432 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1433 }
1434
1435 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1436 if (word == 0xffff) {
1437 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1438 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1439 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1440 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1441 } else {
1442 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1443 if (value < -10 || value > 10)
1444 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1445 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1446 if (value < -10 || value > 10)
1447 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1448 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1449 }
1450
1451 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1452 if (word == 0xffff) {
1453 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1454 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1455 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1456 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1457 } else {
1458 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1459 if (value < -10 || value > 10)
1460 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1461 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1462 if (value < -10 || value > 10)
1463 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1464 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1465 }
1466
1467 return 0;
1468 }
1469
1470 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1471 {
1472 u32 reg;
1473 u16 value;
1474 u16 eeprom;
1475
1476 /*
1477 * Read EEPROM word for configuration.
1478 */
1479 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1480
1481 /*
1482 * Identify RF chipset.
1483 */
1484 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1485 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1486 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1487
1488 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1489 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1490 return -ENODEV;
1491 }
1492
1493 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1494 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1495 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1496 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1497 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1498 return -ENODEV;
1499 }
1500
1501 /*
1502 * Identify default antenna configuration.
1503 */
1504 rt2x00dev->hw->conf.antenna_sel_tx =
1505 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1506 rt2x00dev->hw->conf.antenna_sel_rx =
1507 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1508
1509 /*
1510 * Read the Frame type.
1511 */
1512 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1513 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1514
1515 /*
1516 * Read frequency offset.
1517 */
1518 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1519 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1520
1521 /*
1522 * Read external LNA informations.
1523 */
1524 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1525
1526 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1527 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1528 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1529 }
1530
1531 /*
1532 * Store led settings, for correct led behaviour.
1533 */
1534 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1535
1536 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1537 rt2x00dev->led_mode);
1538 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1539 rt2x00_get_field16(eeprom,
1540 EEPROM_LED_POLARITY_GPIO_0));
1541 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1542 rt2x00_get_field16(eeprom,
1543 EEPROM_LED_POLARITY_GPIO_1));
1544 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1545 rt2x00_get_field16(eeprom,
1546 EEPROM_LED_POLARITY_GPIO_2));
1547 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1548 rt2x00_get_field16(eeprom,
1549 EEPROM_LED_POLARITY_GPIO_3));
1550 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1551 rt2x00_get_field16(eeprom,
1552 EEPROM_LED_POLARITY_GPIO_4));
1553 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1554 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1555 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1556 rt2x00_get_field16(eeprom,
1557 EEPROM_LED_POLARITY_RDY_G));
1558 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1559 rt2x00_get_field16(eeprom,
1560 EEPROM_LED_POLARITY_RDY_A));
1561
1562 return 0;
1563 }
1564
1565 /*
1566 * RF value list for RF2528
1567 * Supports: 2.4 GHz
1568 */
1569 static const struct rf_channel rf_vals_bg_2528[] = {
1570 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1571 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1572 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1573 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1574 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1575 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1576 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1577 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1578 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1579 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1580 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1581 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1582 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1583 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1584 };
1585
1586 /*
1587 * RF value list for RF5226
1588 * Supports: 2.4 GHz & 5.2 GHz
1589 */
1590 static const struct rf_channel rf_vals_5226[] = {
1591 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1592 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1593 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1594 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1595 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1596 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1597 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1598 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1599 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1600 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1601 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1602 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1603 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1604 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1605
1606 /* 802.11 UNI / HyperLan 2 */
1607 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1608 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1609 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1610 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1611 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1612 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1613 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1614 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1615
1616 /* 802.11 HyperLan 2 */
1617 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1618 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1619 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1620 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1621 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1622 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1623 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1624 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1625 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1626 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1627
1628 /* 802.11 UNII */
1629 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1630 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1631 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1632 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1633 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1634 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1635
1636 /* MMAC(Japan)J52 ch 34,38,42,46 */
1637 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1638 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1639 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1640 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1641 };
1642
1643 /*
1644 * RF value list for RF5225 & RF2527
1645 * Supports: 2.4 GHz & 5.2 GHz
1646 */
1647 static const struct rf_channel rf_vals_5225_2527[] = {
1648 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1649 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1650 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1651 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1652 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1653 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1654 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1655 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1656 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1657 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1658 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1659 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1660 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1661 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1662
1663 /* 802.11 UNI / HyperLan 2 */
1664 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1665 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1666 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1667 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1668 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1669 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1670 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1671 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1672
1673 /* 802.11 HyperLan 2 */
1674 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1675 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1676 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1677 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1678 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1679 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1680 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1681 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1682 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1683 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1684
1685 /* 802.11 UNII */
1686 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1687 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1688 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1689 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1690 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1691 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1692
1693 /* MMAC(Japan)J52 ch 34,38,42,46 */
1694 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1695 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1696 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1697 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1698 };
1699
1700
1701 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1702 {
1703 struct hw_mode_spec *spec = &rt2x00dev->spec;
1704 u8 *txpower;
1705 unsigned int i;
1706
1707 /*
1708 * Initialize all hw fields.
1709 */
1710 rt2x00dev->hw->flags =
1711 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1712 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1713 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1714 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1715 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1716 rt2x00dev->hw->queues = 5;
1717
1718 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1719 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1720 rt2x00_eeprom_addr(rt2x00dev,
1721 EEPROM_MAC_ADDR_0));
1722
1723 /*
1724 * Convert tx_power array in eeprom.
1725 */
1726 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1727 for (i = 0; i < 14; i++)
1728 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1729
1730 /*
1731 * Initialize hw_mode information.
1732 */
1733 spec->num_modes = 2;
1734 spec->num_rates = 12;
1735 spec->tx_power_a = NULL;
1736 spec->tx_power_bg = txpower;
1737 spec->tx_power_default = DEFAULT_TXPOWER;
1738
1739 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1740 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1741 spec->channels = rf_vals_bg_2528;
1742 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1743 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1744 spec->channels = rf_vals_5226;
1745 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1746 spec->num_channels = 14;
1747 spec->channels = rf_vals_5225_2527;
1748 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1749 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1750 spec->channels = rf_vals_5225_2527;
1751 }
1752
1753 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1754 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1755 spec->num_modes = 3;
1756
1757 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1758 for (i = 0; i < 14; i++)
1759 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1760
1761 spec->tx_power_a = txpower;
1762 }
1763 }
1764
1765 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1766 {
1767 int retval;
1768
1769 /*
1770 * Allocate eeprom data.
1771 */
1772 retval = rt73usb_validate_eeprom(rt2x00dev);
1773 if (retval)
1774 return retval;
1775
1776 retval = rt73usb_init_eeprom(rt2x00dev);
1777 if (retval)
1778 return retval;
1779
1780 /*
1781 * Initialize hw specifications.
1782 */
1783 rt73usb_probe_hw_mode(rt2x00dev);
1784
1785 /*
1786 * This device requires firmware
1787 */
1788 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1789
1790 /*
1791 * Set the rssi offset.
1792 */
1793 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1794
1795 return 0;
1796 }
1797
1798 /*
1799 * IEEE80211 stack callback functions.
1800 */
1801 static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1802 unsigned int changed_flags,
1803 unsigned int *total_flags,
1804 int mc_count,
1805 struct dev_addr_list *mc_list)
1806 {
1807 struct rt2x00_dev *rt2x00dev = hw->priv;
1808 struct interface *intf = &rt2x00dev->interface;
1809 u32 reg;
1810
1811 /*
1812 * Mask off any flags we are going to ignore from
1813 * the total_flags field.
1814 */
1815 *total_flags &=
1816 FIF_ALLMULTI |
1817 FIF_FCSFAIL |
1818 FIF_PLCPFAIL |
1819 FIF_CONTROL |
1820 FIF_OTHER_BSS |
1821 FIF_PROMISC_IN_BSS;
1822
1823 /*
1824 * Apply some rules to the filters:
1825 * - Some filters imply different filters to be set.
1826 * - Some things we can't filter out at all.
1827 * - Some filters are set based on interface type.
1828 */
1829 if (mc_count)
1830 *total_flags |= FIF_ALLMULTI;
1831 if (*total_flags & FIF_OTHER_BSS ||
1832 *total_flags & FIF_PROMISC_IN_BSS)
1833 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1834 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1835 *total_flags |= FIF_PROMISC_IN_BSS;
1836
1837 /*
1838 * Check if there is any work left for us.
1839 */
1840 if (intf->filter == *total_flags)
1841 return;
1842 intf->filter = *total_flags;
1843
1844 /*
1845 * When in atomic context, reschedule and let rt2x00lib
1846 * call this function again.
1847 */
1848 if (in_atomic()) {
1849 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1850 return;
1851 }
1852
1853 /*
1854 * Start configuration steps.
1855 * Note that the version error will always be dropped
1856 * and broadcast frames will always be accepted since
1857 * there is no filter for it at this time.
1858 */
1859 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1860 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1861 !(*total_flags & FIF_FCSFAIL));
1862 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1863 !(*total_flags & FIF_PLCPFAIL));
1864 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1865 !(*total_flags & FIF_CONTROL));
1866 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1867 !(*total_flags & FIF_PROMISC_IN_BSS));
1868 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1869 !(*total_flags & FIF_PROMISC_IN_BSS));
1870 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1871 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1872 !(*total_flags & FIF_ALLMULTI));
1873 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1874 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1875 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1876 }
1877
1878 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1879 u32 short_retry, u32 long_retry)
1880 {
1881 struct rt2x00_dev *rt2x00dev = hw->priv;
1882 u32 reg;
1883
1884 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1885 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1886 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1887 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1888
1889 return 0;
1890 }
1891
1892 #if 0
1893 /*
1894 * Mac80211 demands get_tsf must be atomic.
1895 * This is not possible for rt73usb since all register access
1896 * functions require sleeping. Untill mac80211 no longer needs
1897 * get_tsf to be atomic, this function should be disabled.
1898 */
1899 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1900 {
1901 struct rt2x00_dev *rt2x00dev = hw->priv;
1902 u64 tsf;
1903 u32 reg;
1904
1905 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1906 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1907 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1908 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1909
1910 return tsf;
1911 }
1912 #else
1913 #define rt73usb_get_tsf NULL
1914 #endif
1915
1916 static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1917 {
1918 struct rt2x00_dev *rt2x00dev = hw->priv;
1919
1920 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1921 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1922 }
1923
1924 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1925 struct ieee80211_tx_control *control)
1926 {
1927 struct rt2x00_dev *rt2x00dev = hw->priv;
1928 int timeout;
1929
1930 /*
1931 * Just in case the ieee80211 doesn't set this,
1932 * but we need this queue set for the descriptor
1933 * initialization.
1934 */
1935 control->queue = IEEE80211_TX_QUEUE_BEACON;
1936
1937 /*
1938 * First we create the beacon.
1939 */
1940 skb_push(skb, TXD_DESC_SIZE);
1941 memset(skb->data, 0, TXD_DESC_SIZE);
1942
1943 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
1944 (struct ieee80211_hdr *)(skb->data +
1945 TXD_DESC_SIZE),
1946 skb->len - TXD_DESC_SIZE, control);
1947
1948 /*
1949 * Write entire beacon with descriptor to register,
1950 * and kick the beacon generator.
1951 */
1952 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
1953 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1954 USB_VENDOR_REQUEST_OUT,
1955 HW_BEACON_BASE0, 0x0000,
1956 skb->data, skb->len, timeout);
1957 rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1958
1959 return 0;
1960 }
1961
1962 static const struct ieee80211_ops rt73usb_mac80211_ops = {
1963 .tx = rt2x00mac_tx,
1964 .start = rt2x00mac_start,
1965 .stop = rt2x00mac_stop,
1966 .add_interface = rt2x00mac_add_interface,
1967 .remove_interface = rt2x00mac_remove_interface,
1968 .config = rt2x00mac_config,
1969 .config_interface = rt2x00mac_config_interface,
1970 .configure_filter = rt73usb_configure_filter,
1971 .get_stats = rt2x00mac_get_stats,
1972 .set_retry_limit = rt73usb_set_retry_limit,
1973 .erp_ie_changed = rt2x00mac_erp_ie_changed,
1974 .conf_tx = rt2x00mac_conf_tx,
1975 .get_tx_stats = rt2x00mac_get_tx_stats,
1976 .get_tsf = rt73usb_get_tsf,
1977 .reset_tsf = rt73usb_reset_tsf,
1978 .beacon_update = rt73usb_beacon_update,
1979 };
1980
1981 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
1982 .probe_hw = rt73usb_probe_hw,
1983 .get_firmware_name = rt73usb_get_firmware_name,
1984 .load_firmware = rt73usb_load_firmware,
1985 .initialize = rt2x00usb_initialize,
1986 .uninitialize = rt2x00usb_uninitialize,
1987 .set_device_state = rt73usb_set_device_state,
1988 .link_stats = rt73usb_link_stats,
1989 .reset_tuner = rt73usb_reset_tuner,
1990 .link_tuner = rt73usb_link_tuner,
1991 .write_tx_desc = rt73usb_write_tx_desc,
1992 .write_tx_data = rt2x00usb_write_tx_data,
1993 .get_tx_data_len = rt73usb_get_tx_data_len,
1994 .kick_tx_queue = rt73usb_kick_tx_queue,
1995 .fill_rxdone = rt73usb_fill_rxdone,
1996 .config_mac_addr = rt73usb_config_mac_addr,
1997 .config_bssid = rt73usb_config_bssid,
1998 .config_type = rt73usb_config_type,
1999 .config_preamble = rt73usb_config_preamble,
2000 .config = rt73usb_config,
2001 };
2002
2003 static const struct rt2x00_ops rt73usb_ops = {
2004 .name = DRV_NAME,
2005 .rxd_size = RXD_DESC_SIZE,
2006 .txd_size = TXD_DESC_SIZE,
2007 .eeprom_size = EEPROM_SIZE,
2008 .rf_size = RF_SIZE,
2009 .lib = &rt73usb_rt2x00_ops,
2010 .hw = &rt73usb_mac80211_ops,
2011 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2012 .debugfs = &rt73usb_rt2x00debug,
2013 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2014 };
2015
2016 /*
2017 * rt73usb module information.
2018 */
2019 static struct usb_device_id rt73usb_device_table[] = {
2020 /* AboCom */
2021 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2022 /* Askey */
2023 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2024 /* ASUS */
2025 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2026 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2027 /* Belkin */
2028 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2029 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2030 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2031 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2032 /* Billionton */
2033 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2034 /* Buffalo */
2035 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2036 /* CNet */
2037 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2038 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2039 /* Conceptronic */
2040 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2041 /* D-Link */
2042 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2043 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2044 /* Gemtek */
2045 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2046 /* Gigabyte */
2047 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2048 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2049 /* Huawei-3Com */
2050 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2051 /* Hercules */
2052 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2053 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2054 /* Linksys */
2055 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2056 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2057 /* MSI */
2058 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2059 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2060 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2061 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2062 /* Ralink */
2063 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2064 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2065 /* Qcom */
2066 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2067 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2068 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2069 /* Senao */
2070 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2071 /* Sitecom */
2072 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2073 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2074 /* Surecom */
2075 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2076 /* Planex */
2077 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2078 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2079 { 0, }
2080 };
2081
2082 MODULE_AUTHOR(DRV_PROJECT);
2083 MODULE_VERSION(DRV_VERSION);
2084 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2085 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2086 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2087 MODULE_FIRMWARE(FIRMWARE_RT2571);
2088 MODULE_LICENSE("GPL");
2089
2090 static struct usb_driver rt73usb_driver = {
2091 .name = DRV_NAME,
2092 .id_table = rt73usb_device_table,
2093 .probe = rt2x00usb_probe,
2094 .disconnect = rt2x00usb_disconnect,
2095 .suspend = rt2x00usb_suspend,
2096 .resume = rt2x00usb_resume,
2097 };
2098
2099 static int __init rt73usb_init(void)
2100 {
2101 return usb_register(&rt73usb_driver);
2102 }
2103
2104 static void __exit rt73usb_exit(void)
2105 {
2106 usb_deregister(&rt73usb_driver);
2107 }
2108
2109 module_init(rt73usb_init);
2110 module_exit(rt73usb_exit);
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