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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rtlwifi / pci.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "wifi.h"
31 #include "core.h"
32 #include "pci.h"
33 #include "base.h"
34 #include "ps.h"
35 #include "efuse.h"
36 #include <linux/export.h>
37 #include <linux/kmemleak.h>
38
39 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
40 PCI_VENDOR_ID_INTEL,
41 PCI_VENDOR_ID_ATI,
42 PCI_VENDOR_ID_AMD,
43 PCI_VENDOR_ID_SI
44 };
45
46 static const u8 ac_to_hwq[] = {
47 VO_QUEUE,
48 VI_QUEUE,
49 BE_QUEUE,
50 BK_QUEUE
51 };
52
53 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
54 struct sk_buff *skb)
55 {
56 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
57 __le16 fc = rtl_get_fc(skb);
58 u8 queue_index = skb_get_queue_mapping(skb);
59
60 if (unlikely(ieee80211_is_beacon(fc)))
61 return BEACON_QUEUE;
62 if (ieee80211_is_mgmt(fc))
63 return MGNT_QUEUE;
64 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
65 if (ieee80211_is_nullfunc(fc))
66 return HIGH_QUEUE;
67
68 return ac_to_hwq[queue_index];
69 }
70
71 /* Update PCI dependent default settings*/
72 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
73 {
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
76 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
77 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
79 u8 init_aspm;
80
81 ppsc->reg_rfps_level = 0;
82 ppsc->support_aspm = false;
83
84 /*Update PCI ASPM setting */
85 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
86 switch (rtlpci->const_pci_aspm) {
87 case 0:
88 /*No ASPM */
89 break;
90
91 case 1:
92 /*ASPM dynamically enabled/disable. */
93 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
94 break;
95
96 case 2:
97 /*ASPM with Clock Req dynamically enabled/disable. */
98 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
99 RT_RF_OFF_LEVL_CLK_REQ);
100 break;
101
102 case 3:
103 /*
104 * Always enable ASPM and Clock Req
105 * from initialization to halt.
106 * */
107 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
108 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
109 RT_RF_OFF_LEVL_CLK_REQ);
110 break;
111
112 case 4:
113 /*
114 * Always enable ASPM without Clock Req
115 * from initialization to halt.
116 * */
117 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
118 RT_RF_OFF_LEVL_CLK_REQ);
119 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
120 break;
121 }
122
123 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
124
125 /*Update Radio OFF setting */
126 switch (rtlpci->const_hwsw_rfoff_d3) {
127 case 1:
128 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
129 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
130 break;
131
132 case 2:
133 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
136 break;
137
138 case 3:
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
140 break;
141 }
142
143 /*Set HW definition to determine if it supports ASPM. */
144 switch (rtlpci->const_support_pciaspm) {
145 case 0:{
146 /*Not support ASPM. */
147 bool support_aspm = false;
148 ppsc->support_aspm = support_aspm;
149 break;
150 }
151 case 1:{
152 /*Support ASPM. */
153 bool support_aspm = true;
154 bool support_backdoor = true;
155 ppsc->support_aspm = support_aspm;
156
157 /*if (priv->oem_id == RT_CID_TOSHIBA &&
158 !priv->ndis_adapter.amd_l1_patch)
159 support_backdoor = false; */
160
161 ppsc->support_backdoor = support_backdoor;
162
163 break;
164 }
165 case 2:
166 /*ASPM value set by chipset. */
167 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
168 bool support_aspm = true;
169 ppsc->support_aspm = support_aspm;
170 }
171 break;
172 default:
173 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
174 "switch case not processed\n");
175 break;
176 }
177
178 /* toshiba aspm issue, toshiba will set aspm selfly
179 * so we should not set aspm in driver */
180 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
181 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
182 init_aspm == 0x43)
183 ppsc->support_aspm = false;
184 }
185
186 static bool _rtl_pci_platform_switch_device_pci_aspm(
187 struct ieee80211_hw *hw,
188 u8 value)
189 {
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192
193 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
194 value |= 0x40;
195
196 pci_write_config_byte(rtlpci->pdev, 0x80, value);
197
198 return false;
199 }
200
201 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
202 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
203 {
204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
206
207 pci_write_config_byte(rtlpci->pdev, 0x81, value);
208
209 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
210 udelay(100);
211 }
212
213 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
215 {
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
221 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
222 /*Retrieve original configuration settings. */
223 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
224 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
225 pcibridge_linkctrlreg;
226 u16 aspmlevel = 0;
227 u8 tmp_u1b = 0;
228
229 if (!ppsc->support_aspm)
230 return;
231
232 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
233 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
234 "PCI(Bridge) UNKNOWN\n");
235
236 return;
237 }
238
239 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
240 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
241 _rtl_pci_switch_clk_req(hw, 0x0);
242 }
243
244 /*for promising device will in L0 state after an I/O. */
245 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
246
247 /*Set corresponding value. */
248 aspmlevel |= BIT(0) | BIT(1);
249 linkctrl_reg &= ~aspmlevel;
250 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
251
252 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
253 udelay(50);
254
255 /*4 Disable Pci Bridge ASPM */
256 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
257 pcibridge_linkctrlreg);
258
259 udelay(50);
260 }
261
262 /*
263 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
264 *power saving We should follow the sequence to enable
265 *RTL8192SE first then enable Pci Bridge ASPM
266 *or the system will show bluescreen.
267 */
268 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
269 {
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
274 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
275 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
276 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
277 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
278 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
279 u16 aspmlevel;
280 u8 u_pcibridge_aspmsetting;
281 u8 u_device_aspmsetting;
282
283 if (!ppsc->support_aspm)
284 return;
285
286 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
287 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
288 "PCI(Bridge) UNKNOWN\n");
289 return;
290 }
291
292 /*4 Enable Pci Bridge ASPM */
293
294 u_pcibridge_aspmsetting =
295 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
296 rtlpci->const_hostpci_aspm_setting;
297
298 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
299 u_pcibridge_aspmsetting &= ~BIT(0);
300
301 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
302 u_pcibridge_aspmsetting);
303
304 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
305 "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
306 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
308 u_pcibridge_aspmsetting);
309
310 udelay(50);
311
312 /*Get ASPM level (with/without Clock Req) */
313 aspmlevel = rtlpci->const_devicepci_aspm_setting;
314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
315
316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
318
319 u_device_aspmsetting |= aspmlevel;
320
321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
322
323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
327 }
328 udelay(100);
329 }
330
331 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
332 {
333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
334
335 bool status = false;
336 u8 offset_e0;
337 unsigned offset_e4;
338
339 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
340
341 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
342
343 if (offset_e0 == 0xA0) {
344 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
345 if (offset_e4 & BIT(23))
346 status = true;
347 }
348
349 return status;
350 }
351
352 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
353 {
354 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
355 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
356 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
357 u8 linkctrl_reg;
358 u8 num4bbytes;
359
360 num4bbytes = (capabilityoffset + 0x10) / 4;
361
362 /*Read Link Control Register */
363 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
364
365 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
366 }
367
368 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
369 struct ieee80211_hw *hw)
370 {
371 struct rtl_priv *rtlpriv = rtl_priv(hw);
372 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
373
374 u8 tmp;
375 int pos;
376 u8 linkctrl_reg;
377
378 /*Link Control Register */
379 pos = pci_pcie_cap(pdev);
380 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
381 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
382
383 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
384 pcipriv->ndis_adapter.linkctrl_reg);
385
386 pci_read_config_byte(pdev, 0x98, &tmp);
387 tmp |= BIT(4);
388 pci_write_config_byte(pdev, 0x98, tmp);
389
390 tmp = 0x17;
391 pci_write_config_byte(pdev, 0x70f, tmp);
392 }
393
394 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
395 {
396 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
397
398 _rtl_pci_update_default_setting(hw);
399
400 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
401 /*Always enable ASPM & Clock Req. */
402 rtl_pci_enable_aspm(hw);
403 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
404 }
405
406 }
407
408 static void _rtl_pci_io_handler_init(struct device *dev,
409 struct ieee80211_hw *hw)
410 {
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412
413 rtlpriv->io.dev = dev;
414
415 rtlpriv->io.write8_async = pci_write8_async;
416 rtlpriv->io.write16_async = pci_write16_async;
417 rtlpriv->io.write32_async = pci_write32_async;
418
419 rtlpriv->io.read8_sync = pci_read8_sync;
420 rtlpriv->io.read16_sync = pci_read16_sync;
421 rtlpriv->io.read32_sync = pci_read32_sync;
422
423 }
424
425 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
426 {
427 }
428
429 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
430 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
431 {
432 struct rtl_priv *rtlpriv = rtl_priv(hw);
433 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
434 u8 additionlen = FCS_LEN;
435 struct sk_buff *next_skb;
436
437 /* here open is 4, wep/tkip is 8, aes is 12*/
438 if (info->control.hw_key)
439 additionlen += info->control.hw_key->icv_len;
440
441 /* The most skb num is 6 */
442 tcb_desc->empkt_num = 0;
443 spin_lock_bh(&rtlpriv->locks.waitq_lock);
444 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
445 struct ieee80211_tx_info *next_info;
446
447 next_info = IEEE80211_SKB_CB(next_skb);
448 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
449 tcb_desc->empkt_len[tcb_desc->empkt_num] =
450 next_skb->len + additionlen;
451 tcb_desc->empkt_num++;
452 } else {
453 break;
454 }
455
456 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
457 next_skb))
458 break;
459
460 if (tcb_desc->empkt_num >= 5)
461 break;
462 }
463 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
464
465 return true;
466 }
467
468 /* just for early mode now */
469 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
470 {
471 struct rtl_priv *rtlpriv = rtl_priv(hw);
472 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
473 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
474 struct sk_buff *skb = NULL;
475 struct ieee80211_tx_info *info = NULL;
476 int tid;
477
478 if (!rtlpriv->rtlhal.earlymode_enable)
479 return;
480
481 /* we juse use em for BE/BK/VI/VO */
482 for (tid = 7; tid >= 0; tid--) {
483 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
484 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
485 while (!mac->act_scanning &&
486 rtlpriv->psc.rfpwr_state == ERFON) {
487 struct rtl_tcb_desc tcb_desc;
488 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
489
490 spin_lock_bh(&rtlpriv->locks.waitq_lock);
491 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
492 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
493 skb = skb_dequeue(&mac->skb_waitq[tid]);
494 } else {
495 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
496 break;
497 }
498 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
499
500 /* Some macaddr can't do early mode. like
501 * multicast/broadcast/no_qos data */
502 info = IEEE80211_SKB_CB(skb);
503 if (info->flags & IEEE80211_TX_CTL_AMPDU)
504 _rtl_update_earlymode_info(hw, skb,
505 &tcb_desc, tid);
506
507 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
508 }
509 }
510 }
511
512
513 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
514 {
515 struct rtl_priv *rtlpriv = rtl_priv(hw);
516 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
517
518 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
519
520 while (skb_queue_len(&ring->queue)) {
521 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
522 struct sk_buff *skb;
523 struct ieee80211_tx_info *info;
524 __le16 fc;
525 u8 tid;
526
527 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
528 HW_DESC_OWN);
529
530 /*
531 *beacon packet will only use the first
532 *descriptor defautly,and the own may not
533 *be cleared by the hardware
534 */
535 if (own)
536 return;
537 ring->idx = (ring->idx + 1) % ring->entries;
538
539 skb = __skb_dequeue(&ring->queue);
540 pci_unmap_single(rtlpci->pdev,
541 rtlpriv->cfg->ops->
542 get_desc((u8 *) entry, true,
543 HW_DESC_TXBUFF_ADDR),
544 skb->len, PCI_DMA_TODEVICE);
545
546 /* remove early mode header */
547 if (rtlpriv->rtlhal.earlymode_enable)
548 skb_pull(skb, EM_HDR_LEN);
549
550 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
551 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
552 ring->idx,
553 skb_queue_len(&ring->queue),
554 *(u16 *) (skb->data + 22));
555
556 if (prio == TXCMD_QUEUE) {
557 dev_kfree_skb(skb);
558 goto tx_status_ok;
559
560 }
561
562 /* for sw LPS, just after NULL skb send out, we can
563 * sure AP kown we are sleeped, our we should not let
564 * rf to sleep*/
565 fc = rtl_get_fc(skb);
566 if (ieee80211_is_nullfunc(fc)) {
567 if (ieee80211_has_pm(fc)) {
568 rtlpriv->mac80211.offchan_delay = true;
569 rtlpriv->psc.state_inap = true;
570 } else {
571 rtlpriv->psc.state_inap = false;
572 }
573 }
574
575 /* update tid tx pkt num */
576 tid = rtl_get_tid(skb);
577 if (tid <= 7)
578 rtlpriv->link_info.tidtx_inperiod[tid]++;
579
580 info = IEEE80211_SKB_CB(skb);
581 ieee80211_tx_info_clear_status(info);
582
583 info->flags |= IEEE80211_TX_STAT_ACK;
584 /*info->status.rates[0].count = 1; */
585
586 ieee80211_tx_status_irqsafe(hw, skb);
587
588 if ((ring->entries - skb_queue_len(&ring->queue))
589 == 2) {
590
591 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
592 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
593 prio, ring->idx,
594 skb_queue_len(&ring->queue));
595
596 ieee80211_wake_queue(hw,
597 skb_get_queue_mapping
598 (skb));
599 }
600 tx_status_ok:
601 skb = NULL;
602 }
603
604 if (((rtlpriv->link_info.num_rx_inperiod +
605 rtlpriv->link_info.num_tx_inperiod) > 8) ||
606 (rtlpriv->link_info.num_rx_inperiod > 2)) {
607 schedule_work(&rtlpriv->works.lps_leave_work);
608 }
609 }
610
611 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
612 struct ieee80211_rx_status rx_status)
613 {
614 struct rtl_priv *rtlpriv = rtl_priv(hw);
615 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
616 __le16 fc = rtl_get_fc(skb);
617 bool unicast = false;
618 struct sk_buff *uskb = NULL;
619 u8 *pdata;
620
621
622 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
623
624 if (is_broadcast_ether_addr(hdr->addr1)) {
625 ;/*TODO*/
626 } else if (is_multicast_ether_addr(hdr->addr1)) {
627 ;/*TODO*/
628 } else {
629 unicast = true;
630 rtlpriv->stats.rxbytesunicast += skb->len;
631 }
632
633 rtl_is_special_data(hw, skb, false);
634
635 if (ieee80211_is_data(fc)) {
636 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
637
638 if (unicast)
639 rtlpriv->link_info.num_rx_inperiod++;
640 }
641
642 /* for sw lps */
643 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
644 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
645 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
646 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
647 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
648 return;
649
650 if (unlikely(!rtl_action_proc(hw, skb, false)))
651 return;
652
653 uskb = dev_alloc_skb(skb->len + 128);
654 if (!uskb)
655 return; /* exit if allocation failed */
656 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
657 pdata = (u8 *)skb_put(uskb, skb->len);
658 memcpy(pdata, skb->data, skb->len);
659
660 ieee80211_rx_irqsafe(hw, uskb);
661 }
662
663 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
664 {
665 struct rtl_priv *rtlpriv = rtl_priv(hw);
666 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
667 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
668
669 struct ieee80211_rx_status rx_status = { 0 };
670 unsigned int count = rtlpci->rxringcount;
671 u8 own;
672 u8 tmp_one;
673 u32 bufferaddress;
674
675 struct rtl_stats stats = {
676 .signal = 0,
677 .noise = -98,
678 .rate = 0,
679 };
680 int index = rtlpci->rx_ring[rx_queue_idx].idx;
681
682 /*RX NORMAL PKT */
683 while (count--) {
684 /*rx descriptor */
685 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
686 index];
687 /*rx pkt */
688 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
689 index];
690 struct sk_buff *new_skb = NULL;
691
692 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
693 false, HW_DESC_OWN);
694
695 /*wait data to be filled by hardware */
696 if (own)
697 break;
698
699 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
700 &rx_status,
701 (u8 *) pdesc, skb);
702
703 if (stats.crc || stats.hwerror)
704 goto done;
705
706 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
707 if (unlikely(!new_skb)) {
708 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
709 "can't alloc skb for rx\n");
710 goto done;
711 }
712
713 pci_unmap_single(rtlpci->pdev,
714 *((dma_addr_t *) skb->cb),
715 rtlpci->rxbuffersize,
716 PCI_DMA_FROMDEVICE);
717
718 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
719 HW_DESC_RXPKT_LEN));
720 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
721
722 /*
723 * NOTICE This can not be use for mac80211,
724 * this is done in mac80211 code,
725 * if you done here sec DHCP will fail
726 * skb_trim(skb, skb->len - 4);
727 */
728
729 _rtl_receive_one(hw, skb, rx_status);
730
731 if (((rtlpriv->link_info.num_rx_inperiod +
732 rtlpriv->link_info.num_tx_inperiod) > 8) ||
733 (rtlpriv->link_info.num_rx_inperiod > 2)) {
734 schedule_work(&rtlpriv->works.lps_leave_work);
735 }
736
737 dev_kfree_skb_any(skb);
738 skb = new_skb;
739
740 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
741 *((dma_addr_t *) skb->cb) =
742 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
743 rtlpci->rxbuffersize,
744 PCI_DMA_FROMDEVICE);
745
746 done:
747 bufferaddress = (*((dma_addr_t *)skb->cb));
748 tmp_one = 1;
749 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
750 HW_DESC_RXBUFF_ADDR,
751 (u8 *)&bufferaddress);
752 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
753 HW_DESC_RXPKT_LEN,
754 (u8 *)&rtlpci->rxbuffersize);
755
756 if (index == rtlpci->rxringcount - 1)
757 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
758 HW_DESC_RXERO,
759 &tmp_one);
760
761 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
762 &tmp_one);
763
764 index = (index + 1) % rtlpci->rxringcount;
765 }
766
767 rtlpci->rx_ring[rx_queue_idx].idx = index;
768 }
769
770 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
771 {
772 struct ieee80211_hw *hw = dev_id;
773 struct rtl_priv *rtlpriv = rtl_priv(hw);
774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
775 unsigned long flags;
776 u32 inta = 0;
777 u32 intb = 0;
778 irqreturn_t ret = IRQ_HANDLED;
779
780 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
781
782 /*read ISR: 4/8bytes */
783 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
784
785 /*Shared IRQ or HW disappared */
786 if (!inta || inta == 0xffff) {
787 ret = IRQ_NONE;
788 goto done;
789 }
790
791 /*<1> beacon related */
792 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
793 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
794 "beacon ok interrupt!\n");
795 }
796
797 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
798 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
799 "beacon err interrupt!\n");
800 }
801
802 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
803 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
804 }
805
806 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
807 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
808 "prepare beacon for interrupt!\n");
809 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
810 }
811
812 /*<3> Tx related */
813 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
814 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
815
816 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
817 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
818 "Manage ok interrupt!\n");
819 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
820 }
821
822 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
823 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
824 "HIGH_QUEUE ok interrupt!\n");
825 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
826 }
827
828 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
829 rtlpriv->link_info.num_tx_inperiod++;
830
831 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
832 "BK Tx OK interrupt!\n");
833 _rtl_pci_tx_isr(hw, BK_QUEUE);
834 }
835
836 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
837 rtlpriv->link_info.num_tx_inperiod++;
838
839 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
840 "BE TX OK interrupt!\n");
841 _rtl_pci_tx_isr(hw, BE_QUEUE);
842 }
843
844 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
845 rtlpriv->link_info.num_tx_inperiod++;
846
847 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
848 "VI TX OK interrupt!\n");
849 _rtl_pci_tx_isr(hw, VI_QUEUE);
850 }
851
852 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
853 rtlpriv->link_info.num_tx_inperiod++;
854
855 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
856 "Vo TX OK interrupt!\n");
857 _rtl_pci_tx_isr(hw, VO_QUEUE);
858 }
859
860 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
861 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
862 rtlpriv->link_info.num_tx_inperiod++;
863
864 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
865 "CMD TX OK interrupt!\n");
866 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
867 }
868 }
869
870 /*<2> Rx related */
871 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
872 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
873 _rtl_pci_rx_interrupt(hw);
874 }
875
876 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
877 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
878 "rx descriptor unavailable!\n");
879 _rtl_pci_rx_interrupt(hw);
880 }
881
882 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
883 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
884 _rtl_pci_rx_interrupt(hw);
885 }
886
887 if (rtlpriv->rtlhal.earlymode_enable)
888 tasklet_schedule(&rtlpriv->works.irq_tasklet);
889
890 done:
891 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
892 return ret;
893 }
894
895 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
896 {
897 _rtl_pci_tx_chk_waitq(hw);
898 }
899
900 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
901 {
902 struct rtl_priv *rtlpriv = rtl_priv(hw);
903 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
904 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
905 struct rtl8192_tx_ring *ring = NULL;
906 struct ieee80211_hdr *hdr = NULL;
907 struct ieee80211_tx_info *info = NULL;
908 struct sk_buff *pskb = NULL;
909 struct rtl_tx_desc *pdesc = NULL;
910 struct rtl_tcb_desc tcb_desc;
911 u8 temp_one = 1;
912
913 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
914 ring = &rtlpci->tx_ring[BEACON_QUEUE];
915 pskb = __skb_dequeue(&ring->queue);
916 if (pskb) {
917 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
918 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
919 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
920 pskb->len, PCI_DMA_TODEVICE);
921 kfree_skb(pskb);
922 }
923
924 /*NB: the beacon data buffer must be 32-bit aligned. */
925 pskb = ieee80211_beacon_get(hw, mac->vif);
926 if (pskb == NULL)
927 return;
928 hdr = rtl_get_hdr(pskb);
929 info = IEEE80211_SKB_CB(pskb);
930 pdesc = &ring->desc[0];
931 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
932 info, pskb, BEACON_QUEUE, &tcb_desc);
933
934 __skb_queue_tail(&ring->queue, pskb);
935
936 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
937 &temp_one);
938
939 return;
940 }
941
942 static void rtl_lps_leave_work_callback(struct work_struct *work)
943 {
944 struct rtl_works *rtlworks =
945 container_of(work, struct rtl_works, lps_leave_work);
946 struct ieee80211_hw *hw = rtlworks->hw;
947
948 rtl_lps_leave(hw);
949 }
950
951 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
952 {
953 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
954 u8 i;
955
956 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
957 rtlpci->txringcount[i] = RT_TXDESC_NUM;
958
959 /*
960 *we just alloc 2 desc for beacon queue,
961 *because we just need first desc in hw beacon.
962 */
963 rtlpci->txringcount[BEACON_QUEUE] = 2;
964
965 /*
966 *BE queue need more descriptor for performance
967 *consideration or, No more tx desc will happen,
968 *and may cause mac80211 mem leakage.
969 */
970 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
971
972 rtlpci->rxbuffersize = 9100; /*2048/1024; */
973 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
974 }
975
976 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
977 struct pci_dev *pdev)
978 {
979 struct rtl_priv *rtlpriv = rtl_priv(hw);
980 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
981 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
982 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
983
984 rtlpci->up_first_time = true;
985 rtlpci->being_init_adapter = false;
986
987 rtlhal->hw = hw;
988 rtlpci->pdev = pdev;
989
990 /*Tx/Rx related var */
991 _rtl_pci_init_trx_var(hw);
992
993 /*IBSS*/ mac->beacon_interval = 100;
994
995 /*AMPDU*/
996 mac->min_space_cfg = 0;
997 mac->max_mss_density = 0;
998 /*set sane AMPDU defaults */
999 mac->current_ampdu_density = 7;
1000 mac->current_ampdu_factor = 3;
1001
1002 /*QOS*/
1003 rtlpci->acm_method = eAcmWay2_SW;
1004
1005 /*task */
1006 tasklet_init(&rtlpriv->works.irq_tasklet,
1007 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1008 (unsigned long)hw);
1009 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1010 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1011 (unsigned long)hw);
1012 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
1013 }
1014
1015 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1016 unsigned int prio, unsigned int entries)
1017 {
1018 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1019 struct rtl_priv *rtlpriv = rtl_priv(hw);
1020 struct rtl_tx_desc *ring;
1021 dma_addr_t dma;
1022 u32 nextdescaddress;
1023 int i;
1024
1025 ring = pci_alloc_consistent(rtlpci->pdev,
1026 sizeof(*ring) * entries, &dma);
1027
1028 if (!ring || (unsigned long)ring & 0xFF) {
1029 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1030 "Cannot allocate TX ring (prio = %d)\n", prio);
1031 return -ENOMEM;
1032 }
1033
1034 memset(ring, 0, sizeof(*ring) * entries);
1035 rtlpci->tx_ring[prio].desc = ring;
1036 rtlpci->tx_ring[prio].dma = dma;
1037 rtlpci->tx_ring[prio].idx = 0;
1038 rtlpci->tx_ring[prio].entries = entries;
1039 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1040
1041 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1042 prio, ring);
1043
1044 for (i = 0; i < entries; i++) {
1045 nextdescaddress = (u32) dma +
1046 ((i + 1) % entries) *
1047 sizeof(*ring);
1048
1049 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1050 true, HW_DESC_TX_NEXTDESC_ADDR,
1051 (u8 *)&nextdescaddress);
1052 }
1053
1054 return 0;
1055 }
1056
1057 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1058 {
1059 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1060 struct rtl_priv *rtlpriv = rtl_priv(hw);
1061 struct rtl_rx_desc *entry = NULL;
1062 int i, rx_queue_idx;
1063 u8 tmp_one = 1;
1064
1065 /*
1066 *rx_queue_idx 0:RX_MPDU_QUEUE
1067 *rx_queue_idx 1:RX_CMD_QUEUE
1068 */
1069 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1070 rx_queue_idx++) {
1071 rtlpci->rx_ring[rx_queue_idx].desc =
1072 pci_alloc_consistent(rtlpci->pdev,
1073 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1074 desc) * rtlpci->rxringcount,
1075 &rtlpci->rx_ring[rx_queue_idx].dma);
1076
1077 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1078 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1079 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1080 "Cannot allocate RX ring\n");
1081 return -ENOMEM;
1082 }
1083
1084 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1085 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1086 rtlpci->rxringcount);
1087
1088 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1089
1090 /* If amsdu_8k is disabled, set buffersize to 4096. This
1091 * change will reduce memory fragmentation.
1092 */
1093 if (rtlpci->rxbuffersize > 4096 &&
1094 rtlpriv->rtlhal.disable_amsdu_8k)
1095 rtlpci->rxbuffersize = 4096;
1096
1097 for (i = 0; i < rtlpci->rxringcount; i++) {
1098 struct sk_buff *skb =
1099 dev_alloc_skb(rtlpci->rxbuffersize);
1100 u32 bufferaddress;
1101 if (!skb)
1102 return 0;
1103 kmemleak_not_leak(skb);
1104 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1105
1106 /*skb->dev = dev; */
1107
1108 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1109
1110 /*
1111 *just set skb->cb to mapping addr
1112 *for pci_unmap_single use
1113 */
1114 *((dma_addr_t *) skb->cb) =
1115 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1116 rtlpci->rxbuffersize,
1117 PCI_DMA_FROMDEVICE);
1118
1119 bufferaddress = (*((dma_addr_t *)skb->cb));
1120 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1121 HW_DESC_RXBUFF_ADDR,
1122 (u8 *)&bufferaddress);
1123 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1124 HW_DESC_RXPKT_LEN,
1125 (u8 *)&rtlpci->
1126 rxbuffersize);
1127 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1128 HW_DESC_RXOWN,
1129 &tmp_one);
1130 }
1131
1132 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1133 HW_DESC_RXERO, &tmp_one);
1134 }
1135 return 0;
1136 }
1137
1138 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1139 unsigned int prio)
1140 {
1141 struct rtl_priv *rtlpriv = rtl_priv(hw);
1142 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1143 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1144
1145 while (skb_queue_len(&ring->queue)) {
1146 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1147 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1148
1149 pci_unmap_single(rtlpci->pdev,
1150 rtlpriv->cfg->
1151 ops->get_desc((u8 *) entry, true,
1152 HW_DESC_TXBUFF_ADDR),
1153 skb->len, PCI_DMA_TODEVICE);
1154 kfree_skb(skb);
1155 ring->idx = (ring->idx + 1) % ring->entries;
1156 }
1157
1158 if (ring->desc) {
1159 pci_free_consistent(rtlpci->pdev,
1160 sizeof(*ring->desc) * ring->entries,
1161 ring->desc, ring->dma);
1162 ring->desc = NULL;
1163 }
1164 }
1165
1166 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1167 {
1168 int i, rx_queue_idx;
1169
1170 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1171 /*rx_queue_idx 1:RX_CMD_QUEUE */
1172 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1173 rx_queue_idx++) {
1174 for (i = 0; i < rtlpci->rxringcount; i++) {
1175 struct sk_buff *skb =
1176 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1177 if (!skb)
1178 continue;
1179
1180 pci_unmap_single(rtlpci->pdev,
1181 *((dma_addr_t *) skb->cb),
1182 rtlpci->rxbuffersize,
1183 PCI_DMA_FROMDEVICE);
1184 kfree_skb(skb);
1185 }
1186
1187 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1188 pci_free_consistent(rtlpci->pdev,
1189 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1190 desc) * rtlpci->rxringcount,
1191 rtlpci->rx_ring[rx_queue_idx].desc,
1192 rtlpci->rx_ring[rx_queue_idx].dma);
1193 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1194 }
1195 }
1196 }
1197
1198 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1199 {
1200 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1201 int ret;
1202 int i;
1203
1204 ret = _rtl_pci_init_rx_ring(hw);
1205 if (ret)
1206 return ret;
1207
1208 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1209 ret = _rtl_pci_init_tx_ring(hw, i,
1210 rtlpci->txringcount[i]);
1211 if (ret)
1212 goto err_free_rings;
1213 }
1214
1215 return 0;
1216
1217 err_free_rings:
1218 _rtl_pci_free_rx_ring(rtlpci);
1219
1220 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1221 if (rtlpci->tx_ring[i].desc)
1222 _rtl_pci_free_tx_ring(hw, i);
1223
1224 return 1;
1225 }
1226
1227 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1228 {
1229 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1230 u32 i;
1231
1232 /*free rx rings */
1233 _rtl_pci_free_rx_ring(rtlpci);
1234
1235 /*free tx rings */
1236 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1237 _rtl_pci_free_tx_ring(hw, i);
1238
1239 return 0;
1240 }
1241
1242 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1243 {
1244 struct rtl_priv *rtlpriv = rtl_priv(hw);
1245 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1246 int i, rx_queue_idx;
1247 unsigned long flags;
1248 u8 tmp_one = 1;
1249
1250 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1251 /*rx_queue_idx 1:RX_CMD_QUEUE */
1252 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1253 rx_queue_idx++) {
1254 /*
1255 *force the rx_ring[RX_MPDU_QUEUE/
1256 *RX_CMD_QUEUE].idx to the first one
1257 */
1258 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1259 struct rtl_rx_desc *entry = NULL;
1260
1261 for (i = 0; i < rtlpci->rxringcount; i++) {
1262 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1263 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1264 false,
1265 HW_DESC_RXOWN,
1266 &tmp_one);
1267 }
1268 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1269 }
1270 }
1271
1272 /*
1273 *after reset, release previous pending packet,
1274 *and force the tx idx to the first one
1275 */
1276 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1277 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1278 if (rtlpci->tx_ring[i].desc) {
1279 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1280
1281 while (skb_queue_len(&ring->queue)) {
1282 struct rtl_tx_desc *entry =
1283 &ring->desc[ring->idx];
1284 struct sk_buff *skb =
1285 __skb_dequeue(&ring->queue);
1286
1287 pci_unmap_single(rtlpci->pdev,
1288 rtlpriv->cfg->ops->
1289 get_desc((u8 *)
1290 entry,
1291 true,
1292 HW_DESC_TXBUFF_ADDR),
1293 skb->len, PCI_DMA_TODEVICE);
1294 kfree_skb(skb);
1295 ring->idx = (ring->idx + 1) % ring->entries;
1296 }
1297 ring->idx = 0;
1298 }
1299 }
1300
1301 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1302
1303 return 0;
1304 }
1305
1306 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1307 struct sk_buff *skb)
1308 {
1309 struct rtl_priv *rtlpriv = rtl_priv(hw);
1310 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1311 struct ieee80211_sta *sta = info->control.sta;
1312 struct rtl_sta_info *sta_entry = NULL;
1313 u8 tid = rtl_get_tid(skb);
1314
1315 if (!sta)
1316 return false;
1317 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1318
1319 if (!rtlpriv->rtlhal.earlymode_enable)
1320 return false;
1321 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1322 return false;
1323 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1324 return false;
1325 if (tid > 7)
1326 return false;
1327
1328 /* maybe every tid should be checked */
1329 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1330 return false;
1331
1332 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1333 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1334 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1335
1336 return true;
1337 }
1338
1339 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1340 struct rtl_tcb_desc *ptcb_desc)
1341 {
1342 struct rtl_priv *rtlpriv = rtl_priv(hw);
1343 struct rtl_sta_info *sta_entry = NULL;
1344 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1345 struct ieee80211_sta *sta = info->control.sta;
1346 struct rtl8192_tx_ring *ring;
1347 struct rtl_tx_desc *pdesc;
1348 u8 idx;
1349 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1350 unsigned long flags;
1351 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1352 __le16 fc = rtl_get_fc(skb);
1353 u8 *pda_addr = hdr->addr1;
1354 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1355 /*ssn */
1356 u8 tid = 0;
1357 u16 seq_number = 0;
1358 u8 own;
1359 u8 temp_one = 1;
1360
1361 if (ieee80211_is_auth(fc)) {
1362 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n");
1363 rtl_ips_nic_on(hw);
1364 }
1365
1366 if (rtlpriv->psc.sw_ps_enabled) {
1367 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1368 !ieee80211_has_pm(fc))
1369 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1370 }
1371
1372 rtl_action_proc(hw, skb, true);
1373
1374 if (is_multicast_ether_addr(pda_addr))
1375 rtlpriv->stats.txbytesmulticast += skb->len;
1376 else if (is_broadcast_ether_addr(pda_addr))
1377 rtlpriv->stats.txbytesbroadcast += skb->len;
1378 else
1379 rtlpriv->stats.txbytesunicast += skb->len;
1380
1381 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1382 ring = &rtlpci->tx_ring[hw_queue];
1383 if (hw_queue != BEACON_QUEUE)
1384 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1385 ring->entries;
1386 else
1387 idx = 0;
1388
1389 pdesc = &ring->desc[idx];
1390 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1391 true, HW_DESC_OWN);
1392
1393 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1394 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1395 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1396 hw_queue, ring->idx, idx,
1397 skb_queue_len(&ring->queue));
1398
1399 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1400 return skb->len;
1401 }
1402
1403 if (ieee80211_is_data_qos(fc)) {
1404 tid = rtl_get_tid(skb);
1405 if (sta) {
1406 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1407 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1408 IEEE80211_SCTL_SEQ) >> 4;
1409 seq_number += 1;
1410
1411 if (!ieee80211_has_morefrags(hdr->frame_control))
1412 sta_entry->tids[tid].seq_number = seq_number;
1413 }
1414 }
1415
1416 if (ieee80211_is_data(fc))
1417 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1418
1419 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1420 info, skb, hw_queue, ptcb_desc);
1421
1422 __skb_queue_tail(&ring->queue, skb);
1423
1424 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1425 HW_DESC_OWN, &temp_one);
1426
1427
1428 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1429 hw_queue != BEACON_QUEUE) {
1430
1431 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1432 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1433 hw_queue, ring->idx, idx,
1434 skb_queue_len(&ring->queue));
1435
1436 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1437 }
1438
1439 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1440
1441 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1442
1443 return 0;
1444 }
1445
1446 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1447 {
1448 struct rtl_priv *rtlpriv = rtl_priv(hw);
1449 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1450 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1451 u16 i = 0;
1452 int queue_id;
1453 struct rtl8192_tx_ring *ring;
1454
1455 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1456 u32 queue_len;
1457 ring = &pcipriv->dev.tx_ring[queue_id];
1458 queue_len = skb_queue_len(&ring->queue);
1459 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1460 queue_id == TXCMD_QUEUE) {
1461 queue_id--;
1462 continue;
1463 } else {
1464 msleep(20);
1465 i++;
1466 }
1467
1468 /* we just wait 1s for all queues */
1469 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1470 is_hal_stop(rtlhal) || i >= 200)
1471 return;
1472 }
1473 }
1474
1475 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1476 {
1477 struct rtl_priv *rtlpriv = rtl_priv(hw);
1478 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1479
1480 _rtl_pci_deinit_trx_ring(hw);
1481
1482 synchronize_irq(rtlpci->pdev->irq);
1483 tasklet_kill(&rtlpriv->works.irq_tasklet);
1484 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1485
1486 flush_workqueue(rtlpriv->works.rtl_wq);
1487 destroy_workqueue(rtlpriv->works.rtl_wq);
1488
1489 }
1490
1491 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1492 {
1493 struct rtl_priv *rtlpriv = rtl_priv(hw);
1494 int err;
1495
1496 _rtl_pci_init_struct(hw, pdev);
1497
1498 err = _rtl_pci_init_trx_ring(hw);
1499 if (err) {
1500 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1501 "tx ring initialization failed\n");
1502 return err;
1503 }
1504
1505 return 0;
1506 }
1507
1508 static int rtl_pci_start(struct ieee80211_hw *hw)
1509 {
1510 struct rtl_priv *rtlpriv = rtl_priv(hw);
1511 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1512 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1513 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1514
1515 int err;
1516
1517 rtl_pci_reset_trx_ring(hw);
1518
1519 rtlpci->driver_is_goingto_unload = false;
1520 err = rtlpriv->cfg->ops->hw_init(hw);
1521 if (err) {
1522 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1523 "Failed to config hardware!\n");
1524 return err;
1525 }
1526
1527 rtlpriv->cfg->ops->enable_interrupt(hw);
1528 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1529
1530 rtl_init_rx_config(hw);
1531
1532 /*should be after adapter start and interrupt enable. */
1533 set_hal_start(rtlhal);
1534
1535 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1536
1537 rtlpci->up_first_time = false;
1538
1539 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1540 return 0;
1541 }
1542
1543 static void rtl_pci_stop(struct ieee80211_hw *hw)
1544 {
1545 struct rtl_priv *rtlpriv = rtl_priv(hw);
1546 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1547 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1548 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1549 unsigned long flags;
1550 u8 RFInProgressTimeOut = 0;
1551
1552 /*
1553 *should be before disable interrupt&adapter
1554 *and will do it immediately.
1555 */
1556 set_hal_stop(rtlhal);
1557
1558 rtlpriv->cfg->ops->disable_interrupt(hw);
1559 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1560
1561 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1562 while (ppsc->rfchange_inprogress) {
1563 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1564 if (RFInProgressTimeOut > 100) {
1565 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1566 break;
1567 }
1568 mdelay(1);
1569 RFInProgressTimeOut++;
1570 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1571 }
1572 ppsc->rfchange_inprogress = true;
1573 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1574
1575 rtlpci->driver_is_goingto_unload = true;
1576 rtlpriv->cfg->ops->hw_disable(hw);
1577 /* some things are not needed if firmware not available */
1578 if (!rtlpriv->max_fw_size)
1579 return;
1580 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1581
1582 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1583 ppsc->rfchange_inprogress = false;
1584 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1585
1586 rtl_pci_enable_aspm(hw);
1587 }
1588
1589 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1590 struct ieee80211_hw *hw)
1591 {
1592 struct rtl_priv *rtlpriv = rtl_priv(hw);
1593 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1594 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1595 struct pci_dev *bridge_pdev = pdev->bus->self;
1596 u16 venderid;
1597 u16 deviceid;
1598 u8 revisionid;
1599 u16 irqline;
1600 u8 tmp;
1601
1602 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1603 venderid = pdev->vendor;
1604 deviceid = pdev->device;
1605 pci_read_config_byte(pdev, 0x8, &revisionid);
1606 pci_read_config_word(pdev, 0x3C, &irqline);
1607
1608 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1609 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1610 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1611 * the correct driver is r8192e_pci, thus this routine should
1612 * return false.
1613 */
1614 if (deviceid == RTL_PCI_8192SE_DID &&
1615 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1616 return false;
1617
1618 if (deviceid == RTL_PCI_8192_DID ||
1619 deviceid == RTL_PCI_0044_DID ||
1620 deviceid == RTL_PCI_0047_DID ||
1621 deviceid == RTL_PCI_8192SE_DID ||
1622 deviceid == RTL_PCI_8174_DID ||
1623 deviceid == RTL_PCI_8173_DID ||
1624 deviceid == RTL_PCI_8172_DID ||
1625 deviceid == RTL_PCI_8171_DID) {
1626 switch (revisionid) {
1627 case RTL_PCI_REVISION_ID_8192PCIE:
1628 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1629 "8192 PCI-E is found - vid/did=%x/%x\n",
1630 venderid, deviceid);
1631 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1632 break;
1633 case RTL_PCI_REVISION_ID_8192SE:
1634 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1635 "8192SE is found - vid/did=%x/%x\n",
1636 venderid, deviceid);
1637 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1638 break;
1639 default:
1640 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1641 "Err: Unknown device - vid/did=%x/%x\n",
1642 venderid, deviceid);
1643 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1644 break;
1645
1646 }
1647 } else if (deviceid == RTL_PCI_8192CET_DID ||
1648 deviceid == RTL_PCI_8192CE_DID ||
1649 deviceid == RTL_PCI_8191CE_DID ||
1650 deviceid == RTL_PCI_8188CE_DID) {
1651 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1652 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1653 "8192C PCI-E is found - vid/did=%x/%x\n",
1654 venderid, deviceid);
1655 } else if (deviceid == RTL_PCI_8192DE_DID ||
1656 deviceid == RTL_PCI_8192DE_DID2) {
1657 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1658 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1659 "8192D PCI-E is found - vid/did=%x/%x\n",
1660 venderid, deviceid);
1661 } else {
1662 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1663 "Err: Unknown device - vid/did=%x/%x\n",
1664 venderid, deviceid);
1665
1666 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1667 }
1668
1669 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1670 if (revisionid == 0 || revisionid == 1) {
1671 if (revisionid == 0) {
1672 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1673 "Find 92DE MAC0\n");
1674 rtlhal->interfaceindex = 0;
1675 } else if (revisionid == 1) {
1676 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1677 "Find 92DE MAC1\n");
1678 rtlhal->interfaceindex = 1;
1679 }
1680 } else {
1681 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1682 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1683 venderid, deviceid, revisionid);
1684 rtlhal->interfaceindex = 0;
1685 }
1686 }
1687 /*find bus info */
1688 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1689 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1690 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1691
1692 if (bridge_pdev) {
1693 /*find bridge info if available */
1694 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1695 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1696 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1697 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1698 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1699 "Pci Bridge Vendor is found index: %d\n",
1700 tmp);
1701 break;
1702 }
1703 }
1704 }
1705
1706 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1707 PCI_BRIDGE_VENDOR_UNKNOWN) {
1708 pcipriv->ndis_adapter.pcibridge_busnum =
1709 bridge_pdev->bus->number;
1710 pcipriv->ndis_adapter.pcibridge_devnum =
1711 PCI_SLOT(bridge_pdev->devfn);
1712 pcipriv->ndis_adapter.pcibridge_funcnum =
1713 PCI_FUNC(bridge_pdev->devfn);
1714 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1715 pci_pcie_cap(bridge_pdev);
1716 pcipriv->ndis_adapter.num4bytes =
1717 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1718
1719 rtl_pci_get_linkcontrol_field(hw);
1720
1721 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1722 PCI_BRIDGE_VENDOR_AMD) {
1723 pcipriv->ndis_adapter.amd_l1_patch =
1724 rtl_pci_get_amd_l1_patch(hw);
1725 }
1726 }
1727
1728 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1729 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1730 pcipriv->ndis_adapter.busnumber,
1731 pcipriv->ndis_adapter.devnumber,
1732 pcipriv->ndis_adapter.funcnumber,
1733 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1734
1735 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1736 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1737 pcipriv->ndis_adapter.pcibridge_busnum,
1738 pcipriv->ndis_adapter.pcibridge_devnum,
1739 pcipriv->ndis_adapter.pcibridge_funcnum,
1740 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1741 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1742 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1743 pcipriv->ndis_adapter.amd_l1_patch);
1744
1745 rtl_pci_parse_configuration(pdev, hw);
1746
1747 return true;
1748 }
1749
1750 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1751 const struct pci_device_id *id)
1752 {
1753 struct ieee80211_hw *hw = NULL;
1754
1755 struct rtl_priv *rtlpriv = NULL;
1756 struct rtl_pci_priv *pcipriv = NULL;
1757 struct rtl_pci *rtlpci;
1758 unsigned long pmem_start, pmem_len, pmem_flags;
1759 int err;
1760
1761 err = pci_enable_device(pdev);
1762 if (err) {
1763 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1764 pci_name(pdev));
1765 return err;
1766 }
1767
1768 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1769 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1770 RT_ASSERT(false,
1771 "Unable to obtain 32bit DMA for consistent allocations\n");
1772 err = -ENOMEM;
1773 goto fail1;
1774 }
1775 }
1776
1777 pci_set_master(pdev);
1778
1779 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1780 sizeof(struct rtl_priv), &rtl_ops);
1781 if (!hw) {
1782 RT_ASSERT(false,
1783 "%s : ieee80211 alloc failed\n", pci_name(pdev));
1784 err = -ENOMEM;
1785 goto fail1;
1786 }
1787
1788 SET_IEEE80211_DEV(hw, &pdev->dev);
1789 pci_set_drvdata(pdev, hw);
1790
1791 rtlpriv = hw->priv;
1792 pcipriv = (void *)rtlpriv->priv;
1793 pcipriv->dev.pdev = pdev;
1794 init_completion(&rtlpriv->firmware_loading_complete);
1795
1796 /* init cfg & intf_ops */
1797 rtlpriv->rtlhal.interface = INTF_PCI;
1798 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1799 rtlpriv->intf_ops = &rtl_pci_ops;
1800
1801 /*
1802 *init dbgp flags before all
1803 *other functions, because we will
1804 *use it in other funtions like
1805 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1806 *you can not use these macro
1807 *before this
1808 */
1809 rtl_dbgp_flag_init(hw);
1810
1811 /* MEM map */
1812 err = pci_request_regions(pdev, KBUILD_MODNAME);
1813 if (err) {
1814 RT_ASSERT(false, "Can't obtain PCI resources\n");
1815 goto fail1;
1816 }
1817
1818 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1819 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1820 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1821
1822 /*shared mem start */
1823 rtlpriv->io.pci_mem_start =
1824 (unsigned long)pci_iomap(pdev,
1825 rtlpriv->cfg->bar_id, pmem_len);
1826 if (rtlpriv->io.pci_mem_start == 0) {
1827 RT_ASSERT(false, "Can't map PCI mem\n");
1828 err = -ENOMEM;
1829 goto fail2;
1830 }
1831
1832 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1833 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1834 pmem_start, pmem_len, pmem_flags,
1835 rtlpriv->io.pci_mem_start);
1836
1837 /* Disable Clk Request */
1838 pci_write_config_byte(pdev, 0x81, 0);
1839 /* leave D3 mode */
1840 pci_write_config_byte(pdev, 0x44, 0);
1841 pci_write_config_byte(pdev, 0x04, 0x06);
1842 pci_write_config_byte(pdev, 0x04, 0x07);
1843
1844 /* find adapter */
1845 if (!_rtl_pci_find_adapter(pdev, hw)) {
1846 err = -ENODEV;
1847 goto fail3;
1848 }
1849
1850 /* Init IO handler */
1851 _rtl_pci_io_handler_init(&pdev->dev, hw);
1852
1853 /*like read eeprom and so on */
1854 rtlpriv->cfg->ops->read_eeprom_info(hw);
1855
1856 /*aspm */
1857 rtl_pci_init_aspm(hw);
1858
1859 /* Init mac80211 sw */
1860 err = rtl_init_core(hw);
1861 if (err) {
1862 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1863 "Can't allocate sw for mac80211\n");
1864 goto fail3;
1865 }
1866
1867 /* Init PCI sw */
1868 err = rtl_pci_init(hw, pdev);
1869 if (err) {
1870 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
1871 goto fail3;
1872 }
1873
1874 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1875 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1876 err = -ENODEV;
1877 goto fail3;
1878 }
1879
1880 rtlpriv->cfg->ops->init_sw_leds(hw);
1881
1882 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1883 if (err) {
1884 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1885 "failed to create sysfs device attributes\n");
1886 goto fail3;
1887 }
1888
1889 rtlpci = rtl_pcidev(pcipriv);
1890 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1891 IRQF_SHARED, KBUILD_MODNAME, hw);
1892 if (err) {
1893 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1894 "%s: failed to register IRQ handler\n",
1895 wiphy_name(hw->wiphy));
1896 goto fail3;
1897 }
1898 rtlpci->irq_alloc = 1;
1899
1900 return 0;
1901
1902 fail3:
1903 rtl_deinit_core(hw);
1904 _rtl_pci_io_handler_release(hw);
1905
1906 if (rtlpriv->io.pci_mem_start != 0)
1907 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1908
1909 fail2:
1910 pci_release_regions(pdev);
1911 complete(&rtlpriv->firmware_loading_complete);
1912
1913 fail1:
1914 if (hw)
1915 ieee80211_free_hw(hw);
1916 pci_set_drvdata(pdev, NULL);
1917 pci_disable_device(pdev);
1918
1919 return err;
1920
1921 }
1922 EXPORT_SYMBOL(rtl_pci_probe);
1923
1924 void rtl_pci_disconnect(struct pci_dev *pdev)
1925 {
1926 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1927 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1928 struct rtl_priv *rtlpriv = rtl_priv(hw);
1929 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1930 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1931
1932 /* just in case driver is removed before firmware callback */
1933 wait_for_completion(&rtlpriv->firmware_loading_complete);
1934 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1935
1936 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1937
1938 /*ieee80211_unregister_hw will call ops_stop */
1939 if (rtlmac->mac80211_registered == 1) {
1940 ieee80211_unregister_hw(hw);
1941 rtlmac->mac80211_registered = 0;
1942 } else {
1943 rtl_deinit_deferred_work(hw);
1944 rtlpriv->intf_ops->adapter_stop(hw);
1945 }
1946 rtlpriv->cfg->ops->disable_interrupt(hw);
1947
1948 /*deinit rfkill */
1949 rtl_deinit_rfkill(hw);
1950
1951 rtl_pci_deinit(hw);
1952 rtl_deinit_core(hw);
1953 _rtl_pci_io_handler_release(hw);
1954 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1955
1956 if (rtlpci->irq_alloc) {
1957 free_irq(rtlpci->pdev->irq, hw);
1958 rtlpci->irq_alloc = 0;
1959 }
1960
1961 if (rtlpriv->io.pci_mem_start != 0) {
1962 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1963 pci_release_regions(pdev);
1964 }
1965
1966 pci_disable_device(pdev);
1967
1968 rtl_pci_disable_aspm(hw);
1969
1970 pci_set_drvdata(pdev, NULL);
1971
1972 ieee80211_free_hw(hw);
1973 }
1974 EXPORT_SYMBOL(rtl_pci_disconnect);
1975
1976 /***************************************
1977 kernel pci power state define:
1978 PCI_D0 ((pci_power_t __force) 0)
1979 PCI_D1 ((pci_power_t __force) 1)
1980 PCI_D2 ((pci_power_t __force) 2)
1981 PCI_D3hot ((pci_power_t __force) 3)
1982 PCI_D3cold ((pci_power_t __force) 4)
1983 PCI_UNKNOWN ((pci_power_t __force) 5)
1984
1985 This function is called when system
1986 goes into suspend state mac80211 will
1987 call rtl_mac_stop() from the mac80211
1988 suspend function first, So there is
1989 no need to call hw_disable here.
1990 ****************************************/
1991 int rtl_pci_suspend(struct device *dev)
1992 {
1993 struct pci_dev *pdev = to_pci_dev(dev);
1994 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1995 struct rtl_priv *rtlpriv = rtl_priv(hw);
1996
1997 rtlpriv->cfg->ops->hw_suspend(hw);
1998 rtl_deinit_rfkill(hw);
1999
2000 return 0;
2001 }
2002 EXPORT_SYMBOL(rtl_pci_suspend);
2003
2004 int rtl_pci_resume(struct device *dev)
2005 {
2006 struct pci_dev *pdev = to_pci_dev(dev);
2007 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2008 struct rtl_priv *rtlpriv = rtl_priv(hw);
2009
2010 rtlpriv->cfg->ops->hw_resume(hw);
2011 rtl_init_rfkill(hw);
2012 return 0;
2013 }
2014 EXPORT_SYMBOL(rtl_pci_resume);
2015
2016 struct rtl_intf_ops rtl_pci_ops = {
2017 .read_efuse_byte = read_efuse_byte,
2018 .adapter_start = rtl_pci_start,
2019 .adapter_stop = rtl_pci_stop,
2020 .adapter_tx = rtl_pci_tx,
2021 .flush = rtl_pci_flush,
2022 .reset_trx_ring = rtl_pci_reset_trx_ring,
2023 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2024
2025 .disable_aspm = rtl_pci_disable_aspm,
2026 .enable_aspm = rtl_pci_enable_aspm,
2027 };
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