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1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "../rtl8192c/fw_common.h"
41 #include "dm.h"
42 #include "led.h"
43 #include "hw.h"
44
45 #define LLT_CONFIG 5
46
47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
48 u8 set_bits, u8 clear_bits)
49 {
50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52
53 rtlpci->reg_bcn_ctrl_val |= set_bits;
54 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
55
56 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
57 }
58
59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
60 {
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
62 u8 tmp1byte;
63
64 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
65 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
66 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
67 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
68 tmp1byte &= ~(BIT(0));
69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
70 }
71
72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
73 {
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 u8 tmp1byte;
76
77 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
78 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
79 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
80 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
81 tmp1byte |= BIT(0);
82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
83 }
84
85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
86 {
87 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
88 }
89
90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
91 {
92 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
93 }
94
95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
96 {
97 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
99 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
100
101 switch (variable) {
102 case HW_VAR_RCR:
103 *((u32 *) (val)) = rtlpci->receive_config;
104 break;
105 case HW_VAR_RF_STATE:
106 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
107 break;
108 case HW_VAR_FWLPS_RF_ON:{
109 enum rf_pwrstate rfState;
110 u32 val_rcr;
111
112 rtlpriv->cfg->ops->get_hw_reg(hw,
113 HW_VAR_RF_STATE,
114 (u8 *) (&rfState));
115 if (rfState == ERFOFF) {
116 *((bool *) (val)) = true;
117 } else {
118 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
119 val_rcr &= 0x00070000;
120 if (val_rcr)
121 *((bool *) (val)) = false;
122 else
123 *((bool *) (val)) = true;
124 }
125 break;
126 }
127 case HW_VAR_FW_PSMODE_STATUS:
128 *((bool *) (val)) = ppsc->fw_current_inpsmode;
129 break;
130 case HW_VAR_CORRECT_TSF:{
131 u64 tsf;
132 u32 *ptsf_low = (u32 *)&tsf;
133 u32 *ptsf_high = ((u32 *)&tsf) + 1;
134
135 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
136 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
137
138 *((u64 *) (val)) = tsf;
139
140 break;
141 }
142 default:
143 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
144 "switch case not processed\n");
145 break;
146 }
147 }
148
149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150 {
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
153 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
157 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
158 u8 idx;
159
160 switch (variable) {
161 case HW_VAR_ETHER_ADDR:{
162 for (idx = 0; idx < ETH_ALEN; idx++) {
163 rtl_write_byte(rtlpriv, (REG_MACID + idx),
164 val[idx]);
165 }
166 break;
167 }
168 case HW_VAR_BASIC_RATE:{
169 u16 rate_cfg = ((u16 *) val)[0];
170 u8 rate_index = 0;
171 rate_cfg &= 0x15f;
172 rate_cfg |= 0x01;
173 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
174 rtl_write_byte(rtlpriv, REG_RRSR + 1,
175 (rate_cfg >> 8) & 0xff);
176 while (rate_cfg > 0x1) {
177 rate_cfg = (rate_cfg >> 1);
178 rate_index++;
179 }
180 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
181 rate_index);
182 break;
183 }
184 case HW_VAR_BSSID:{
185 for (idx = 0; idx < ETH_ALEN; idx++) {
186 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
187 val[idx]);
188 }
189 break;
190 }
191 case HW_VAR_SIFS:{
192 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
193 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
194
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
197
198 if (!mac->ht_enable)
199 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
200 0x0e0e);
201 else
202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
203 *((u16 *) val));
204 break;
205 }
206 case HW_VAR_SLOT_TIME:{
207 u8 e_aci;
208
209 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
210 "HW_VAR_SLOT_TIME %x\n", val[0]);
211
212 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
213
214 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
215 rtlpriv->cfg->ops->set_hw_reg(hw,
216 HW_VAR_AC_PARAM,
217 (u8 *) (&e_aci));
218 }
219 break;
220 }
221 case HW_VAR_ACK_PREAMBLE:{
222 u8 reg_tmp;
223 u8 short_preamble = (bool) (*(u8 *) val);
224 reg_tmp = (mac->cur_40_prime_sc) << 5;
225 if (short_preamble)
226 reg_tmp |= 0x80;
227
228 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
229 break;
230 }
231 case HW_VAR_AMPDU_MIN_SPACE:{
232 u8 min_spacing_to_set;
233 u8 sec_min_space;
234
235 min_spacing_to_set = *((u8 *) val);
236 if (min_spacing_to_set <= 7) {
237 sec_min_space = 0;
238
239 if (min_spacing_to_set < sec_min_space)
240 min_spacing_to_set = sec_min_space;
241
242 mac->min_space_cfg = ((mac->min_space_cfg &
243 0xf8) |
244 min_spacing_to_set);
245
246 *val = min_spacing_to_set;
247
248 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
249 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
250 mac->min_space_cfg);
251
252 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
253 mac->min_space_cfg);
254 }
255 break;
256 }
257 case HW_VAR_SHORTGI_DENSITY:{
258 u8 density_to_set;
259
260 density_to_set = *((u8 *) val);
261 mac->min_space_cfg |= (density_to_set << 3);
262
263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
265 mac->min_space_cfg);
266
267 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
268 mac->min_space_cfg);
269
270 break;
271 }
272 case HW_VAR_AMPDU_FACTOR:{
273 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
274 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
275
276 u8 factor_toset;
277 u8 *p_regtoset = NULL;
278 u8 index = 0;
279
280 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
281 (rtlpcipriv->bt_coexist.bt_coexist_type ==
282 BT_CSR_BC4))
283 p_regtoset = regtoset_bt;
284 else
285 p_regtoset = regtoset_normal;
286
287 factor_toset = *((u8 *) val);
288 if (factor_toset <= 3) {
289 factor_toset = (1 << (factor_toset + 2));
290 if (factor_toset > 0xf)
291 factor_toset = 0xf;
292
293 for (index = 0; index < 4; index++) {
294 if ((p_regtoset[index] & 0xf0) >
295 (factor_toset << 4))
296 p_regtoset[index] =
297 (p_regtoset[index] & 0x0f) |
298 (factor_toset << 4);
299
300 if ((p_regtoset[index] & 0x0f) >
301 factor_toset)
302 p_regtoset[index] =
303 (p_regtoset[index] & 0xf0) |
304 (factor_toset);
305
306 rtl_write_byte(rtlpriv,
307 (REG_AGGLEN_LMT + index),
308 p_regtoset[index]);
309
310 }
311
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset);
315 }
316 break;
317 }
318 case HW_VAR_AC_PARAM:{
319 u8 e_aci = *((u8 *) val);
320 rtl92c_dm_init_edca_turbo(hw);
321
322 if (rtlpci->acm_method != eAcmWay2_SW)
323 rtlpriv->cfg->ops->set_hw_reg(hw,
324 HW_VAR_ACM_CTRL,
325 (u8 *) (&e_aci));
326 break;
327 }
328 case HW_VAR_ACM_CTRL:{
329 u8 e_aci = *((u8 *) val);
330 union aci_aifsn *p_aci_aifsn =
331 (union aci_aifsn *)(&(mac->ac[0].aifs));
332 u8 acm = p_aci_aifsn->f.acm;
333 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
334
335 acm_ctrl =
336 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
337
338 if (acm) {
339 switch (e_aci) {
340 case AC0_BE:
341 acm_ctrl |= AcmHw_BeqEn;
342 break;
343 case AC2_VI:
344 acm_ctrl |= AcmHw_ViqEn;
345 break;
346 case AC3_VO:
347 acm_ctrl |= AcmHw_VoqEn;
348 break;
349 default:
350 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
351 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
352 acm);
353 break;
354 }
355 } else {
356 switch (e_aci) {
357 case AC0_BE:
358 acm_ctrl &= (~AcmHw_BeqEn);
359 break;
360 case AC2_VI:
361 acm_ctrl &= (~AcmHw_ViqEn);
362 break;
363 case AC3_VO:
364 acm_ctrl &= (~AcmHw_BeqEn);
365 break;
366 default:
367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
368 "switch case not processed\n");
369 break;
370 }
371 }
372
373 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
374 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
375 acm_ctrl);
376 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
377 break;
378 }
379 case HW_VAR_RCR:{
380 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
381 rtlpci->receive_config = ((u32 *) (val))[0];
382 break;
383 }
384 case HW_VAR_RETRY_LIMIT:{
385 u8 retry_limit = ((u8 *) (val))[0];
386
387 rtl_write_word(rtlpriv, REG_RL,
388 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
389 retry_limit << RETRY_LIMIT_LONG_SHIFT);
390 break;
391 }
392 case HW_VAR_DUAL_TSF_RST:
393 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
394 break;
395 case HW_VAR_EFUSE_BYTES:
396 rtlefuse->efuse_usedbytes = *((u16 *) val);
397 break;
398 case HW_VAR_EFUSE_USAGE:
399 rtlefuse->efuse_usedpercentage = *((u8 *) val);
400 break;
401 case HW_VAR_IO_CMD:
402 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
403 break;
404 case HW_VAR_WPA_CONFIG:
405 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
406 break;
407 case HW_VAR_SET_RPWM:{
408 u8 rpwm_val;
409
410 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
411 udelay(1);
412
413 if (rpwm_val & BIT(7)) {
414 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
415 (*(u8 *) val));
416 } else {
417 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
418 ((*(u8 *) val) | BIT(7)));
419 }
420
421 break;
422 }
423 case HW_VAR_H2C_FW_PWRMODE:{
424 u8 psmode = (*(u8 *) val);
425
426 if ((psmode != FW_PS_ACTIVE_MODE) &&
427 (!IS_92C_SERIAL(rtlhal->version))) {
428 rtl92c_dm_rf_saving(hw, true);
429 }
430
431 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
432 break;
433 }
434 case HW_VAR_FW_PSMODE_STATUS:
435 ppsc->fw_current_inpsmode = *((bool *) val);
436 break;
437 case HW_VAR_H2C_FW_JOINBSSRPT:{
438 u8 mstatus = (*(u8 *) val);
439 u8 tmp_regcr, tmp_reg422;
440 bool recover = false;
441
442 if (mstatus == RT_MEDIA_CONNECT) {
443 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
444 NULL);
445
446 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
447 rtl_write_byte(rtlpriv, REG_CR + 1,
448 (tmp_regcr | BIT(0)));
449
450 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
451 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
452
453 tmp_reg422 =
454 rtl_read_byte(rtlpriv,
455 REG_FWHW_TXQ_CTRL + 2);
456 if (tmp_reg422 & BIT(6))
457 recover = true;
458 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
459 tmp_reg422 & (~BIT(6)));
460
461 rtl92c_set_fw_rsvdpagepkt(hw, 0);
462
463 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
464 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
465
466 if (recover) {
467 rtl_write_byte(rtlpriv,
468 REG_FWHW_TXQ_CTRL + 2,
469 tmp_reg422);
470 }
471
472 rtl_write_byte(rtlpriv, REG_CR + 1,
473 (tmp_regcr & ~(BIT(0))));
474 }
475 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
476
477 break;
478 }
479 case HW_VAR_AID:{
480 u16 u2btmp;
481 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
482 u2btmp &= 0xC000;
483 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
484 mac->assoc_id));
485
486 break;
487 }
488 case HW_VAR_CORRECT_TSF:{
489 u8 btype_ibss = ((u8 *) (val))[0];
490
491 if (btype_ibss)
492 _rtl92ce_stop_tx_beacon(hw);
493
494 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
495
496 rtl_write_dword(rtlpriv, REG_TSFTR,
497 (u32) (mac->tsf & 0xffffffff));
498 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
499 (u32) ((mac->tsf >> 32) & 0xffffffff));
500
501 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
502
503 if (btype_ibss)
504 _rtl92ce_resume_tx_beacon(hw);
505
506 break;
507
508 }
509 default:
510 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
511 "switch case not processed\n");
512 break;
513 }
514 }
515
516 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
517 {
518 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 bool status = true;
520 long count = 0;
521 u32 value = _LLT_INIT_ADDR(address) |
522 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
523
524 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
525
526 do {
527 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
528 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
529 break;
530
531 if (count > POLLING_LLT_THRESHOLD) {
532 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
533 "Failed to polling write LLT done at address %d!\n",
534 address);
535 status = false;
536 break;
537 }
538 } while (++count);
539
540 return status;
541 }
542
543 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
544 {
545 struct rtl_priv *rtlpriv = rtl_priv(hw);
546 unsigned short i;
547 u8 txpktbuf_bndy;
548 u8 maxPage;
549 bool status;
550
551 #if LLT_CONFIG == 1
552 maxPage = 255;
553 txpktbuf_bndy = 252;
554 #elif LLT_CONFIG == 2
555 maxPage = 127;
556 txpktbuf_bndy = 124;
557 #elif LLT_CONFIG == 3
558 maxPage = 255;
559 txpktbuf_bndy = 174;
560 #elif LLT_CONFIG == 4
561 maxPage = 255;
562 txpktbuf_bndy = 246;
563 #elif LLT_CONFIG == 5
564 maxPage = 255;
565 txpktbuf_bndy = 246;
566 #endif
567
568 #if LLT_CONFIG == 1
569 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
570 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
571 #elif LLT_CONFIG == 2
572 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
573 #elif LLT_CONFIG == 3
574 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
575 #elif LLT_CONFIG == 4
576 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
577 #elif LLT_CONFIG == 5
578 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
579
580 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
581 #endif
582
583 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
584 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
585
586 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
587 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
588
589 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
590 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
591 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
592
593 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
594 status = _rtl92ce_llt_write(hw, i, i + 1);
595 if (true != status)
596 return status;
597 }
598
599 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
600 if (true != status)
601 return status;
602
603 for (i = txpktbuf_bndy; i < maxPage; i++) {
604 status = _rtl92ce_llt_write(hw, i, (i + 1));
605 if (true != status)
606 return status;
607 }
608
609 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
610 if (true != status)
611 return status;
612
613 return true;
614 }
615
616 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
617 {
618 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
619 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
620 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
621 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
622
623 if (rtlpci->up_first_time)
624 return;
625
626 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
627 rtl92ce_sw_led_on(hw, pLed0);
628 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
629 rtl92ce_sw_led_on(hw, pLed0);
630 else
631 rtl92ce_sw_led_off(hw, pLed0);
632 }
633
634 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
635 {
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
638 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
639 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
640
641 unsigned char bytetmp;
642 unsigned short wordtmp;
643 u16 retry;
644
645 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
646 if (rtlpcipriv->bt_coexist.bt_coexistence) {
647 u32 value32;
648 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
649 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
650 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
651 }
652 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
653 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
654
655 if (rtlpcipriv->bt_coexist.bt_coexistence) {
656 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
657
658 u4b_tmp &= (~0x00024800);
659 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
660 }
661
662 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
663 udelay(2);
664
665 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
666 udelay(2);
667
668 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
669 udelay(2);
670
671 retry = 0;
672 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
673 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
674
675 while ((bytetmp & BIT(0)) && retry < 1000) {
676 retry++;
677 udelay(50);
678 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
679 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
680 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
681 udelay(50);
682 }
683
684 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
685
686 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
687 udelay(2);
688
689 if (rtlpcipriv->bt_coexist.bt_coexistence) {
690 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
691 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
692 }
693
694 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
695
696 if (_rtl92ce_llt_table_init(hw) == false)
697 return false;
698
699 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
700 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
701
702 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
703
704 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
705 wordtmp &= 0xf;
706 wordtmp |= 0xF771;
707 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
708
709 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
710 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
711 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
712
713 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
714
715 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
716 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
717 DMA_BIT_MASK(32));
718 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
719 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
720 DMA_BIT_MASK(32));
721 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
722 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
723 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
724 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
725 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
726 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
727 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
728 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
729 rtl_write_dword(rtlpriv, REG_HQ_DESA,
730 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
731 DMA_BIT_MASK(32));
732 rtl_write_dword(rtlpriv, REG_RX_DESA,
733 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
734 DMA_BIT_MASK(32));
735
736 if (IS_92C_SERIAL(rtlhal->version))
737 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
738 else
739 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
740
741 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
742
743 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
744 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
745 do {
746 retry++;
747 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
748 } while ((retry < 200) && (bytetmp & BIT(7)));
749
750 _rtl92ce_gen_refresh_led_state(hw);
751
752 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
753
754 return true;
755 }
756
757 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
758 {
759 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
760 struct rtl_priv *rtlpriv = rtl_priv(hw);
761 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
762 u8 reg_bw_opmode;
763 u32 reg_prsr;
764
765 reg_bw_opmode = BW_OPMODE_20MHZ;
766 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
767
768 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
769
770 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
771
772 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
773
774 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
775
776 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
777
778 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
779
780 rtl_write_word(rtlpriv, REG_RL, 0x0707);
781
782 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
783
784 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
785
786 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
787 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
788 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
789 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
790
791 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
792 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
793 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
794 else
795 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
796
797 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
798
799 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
800
801 rtlpci->reg_bcn_ctrl_val = 0x1f;
802 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
803
804 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
805
806 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
807
808 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
809 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
810
811 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
812 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
813 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
814 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
815 } else {
816 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
817 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
818 }
819
820 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
821 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
822 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
823 else
824 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
825
826 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
827
828 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
829 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
830
831 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
832
833 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
834
835 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
836 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
837
838 }
839
840 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
841 {
842 struct rtl_priv *rtlpriv = rtl_priv(hw);
843 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
844
845 rtl_write_byte(rtlpriv, 0x34b, 0x93);
846 rtl_write_word(rtlpriv, 0x350, 0x870c);
847 rtl_write_byte(rtlpriv, 0x352, 0x1);
848
849 if (ppsc->support_backdoor)
850 rtl_write_byte(rtlpriv, 0x349, 0x1b);
851 else
852 rtl_write_byte(rtlpriv, 0x349, 0x03);
853
854 rtl_write_word(rtlpriv, 0x350, 0x2718);
855 rtl_write_byte(rtlpriv, 0x352, 0x1);
856 }
857
858 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
859 {
860 struct rtl_priv *rtlpriv = rtl_priv(hw);
861 u8 sec_reg_value;
862
863 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
864 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
865 rtlpriv->sec.pairwise_enc_algorithm,
866 rtlpriv->sec.group_enc_algorithm);
867
868 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
869 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
870 "not open hw encryption\n");
871 return;
872 }
873
874 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
875
876 if (rtlpriv->sec.use_defaultkey) {
877 sec_reg_value |= SCR_TxUseDK;
878 sec_reg_value |= SCR_RxUseDK;
879 }
880
881 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
882
883 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
884
885 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
886 "The SECR-value %x\n", sec_reg_value);
887
888 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
889
890 }
891
892 int rtl92ce_hw_init(struct ieee80211_hw *hw)
893 {
894 struct rtl_priv *rtlpriv = rtl_priv(hw);
895 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
896 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
897 struct rtl_phy *rtlphy = &(rtlpriv->phy);
898 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
899 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
900 static bool iqk_initialized; /* initialized to false */
901 bool rtstatus = true;
902 bool is92c;
903 int err;
904 u8 tmp_u1b;
905
906 rtlpci->being_init_adapter = true;
907 rtlpriv->intf_ops->disable_aspm(hw);
908 rtstatus = _rtl92ce_init_mac(hw);
909 if (rtstatus != true) {
910 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
911 err = 1;
912 return err;
913 }
914
915 err = rtl92c_download_fw(hw);
916 if (err) {
917 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
918 "Failed to download FW. Init HW without FW now..\n");
919 err = 1;
920 rtlhal->fw_ready = false;
921 return err;
922 } else {
923 rtlhal->fw_ready = true;
924 }
925
926 rtlhal->last_hmeboxnum = 0;
927 rtl92c_phy_mac_config(hw);
928 rtl92c_phy_bb_config(hw);
929 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
930 rtl92c_phy_rf_config(hw);
931 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
932 RF_CHNLBW, RFREG_OFFSET_MASK);
933 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
934 RF_CHNLBW, RFREG_OFFSET_MASK);
935 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
936 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
937 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
938 _rtl92ce_hw_configure(hw);
939 rtl_cam_reset_all_entry(hw);
940 rtl92ce_enable_hw_security_config(hw);
941
942 ppsc->rfpwr_state = ERFON;
943
944 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
945 _rtl92ce_enable_aspm_back_door(hw);
946 rtlpriv->intf_ops->enable_aspm(hw);
947
948 rtl8192ce_bt_hw_init(hw);
949
950 if (ppsc->rfpwr_state == ERFON) {
951 rtl92c_phy_set_rfpath_switch(hw, 1);
952 if (iqk_initialized) {
953 rtl92c_phy_iq_calibrate(hw, true);
954 } else {
955 rtl92c_phy_iq_calibrate(hw, false);
956 iqk_initialized = true;
957 }
958
959 rtl92c_dm_check_txpower_tracking(hw);
960 rtl92c_phy_lc_calibrate(hw);
961 }
962
963 is92c = IS_92C_SERIAL(rtlhal->version);
964 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
965 if (!(tmp_u1b & BIT(0))) {
966 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
967 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
968 }
969
970 if (!(tmp_u1b & BIT(1)) && is92c) {
971 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
972 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
973 }
974
975 if (!(tmp_u1b & BIT(4))) {
976 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
977 tmp_u1b &= 0x0F;
978 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
979 udelay(10);
980 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
981 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
982 }
983 rtl92c_dm_init(hw);
984 rtlpci->being_init_adapter = false;
985 return err;
986 }
987
988 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
989 {
990 struct rtl_priv *rtlpriv = rtl_priv(hw);
991 struct rtl_phy *rtlphy = &(rtlpriv->phy);
992 enum version_8192c version = VERSION_UNKNOWN;
993 u32 value32;
994 const char *versionid;
995
996 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
997 if (value32 & TRP_VAUX_EN) {
998 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
999 VERSION_A_CHIP_88C;
1000 } else {
1001 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1002 VERSION_B_CHIP_88C;
1003 }
1004
1005 switch (version) {
1006 case VERSION_B_CHIP_92C:
1007 versionid = "B_CHIP_92C";
1008 break;
1009 case VERSION_B_CHIP_88C:
1010 versionid = "B_CHIP_88C";
1011 break;
1012 case VERSION_A_CHIP_92C:
1013 versionid = "A_CHIP_92C";
1014 break;
1015 case VERSION_A_CHIP_88C:
1016 versionid = "A_CHIP_88C";
1017 break;
1018 default:
1019 versionid = "Unknown. Bug?";
1020 break;
1021 }
1022
1023 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1024 "Chip Version ID: %s\n", versionid);
1025
1026 switch (version & 0x3) {
1027 case CHIP_88C:
1028 rtlphy->rf_type = RF_1T1R;
1029 break;
1030 case CHIP_92C:
1031 rtlphy->rf_type = RF_2T2R;
1032 break;
1033 case CHIP_92C_1T2R:
1034 rtlphy->rf_type = RF_1T2R;
1035 break;
1036 default:
1037 rtlphy->rf_type = RF_1T1R;
1038 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1039 "ERROR RF_Type is set!!\n");
1040 break;
1041 }
1042
1043 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1044 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1045
1046 return version;
1047 }
1048
1049 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1050 enum nl80211_iftype type)
1051 {
1052 struct rtl_priv *rtlpriv = rtl_priv(hw);
1053 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1054 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1055 bt_msr &= 0xfc;
1056
1057 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1058 type == NL80211_IFTYPE_STATION) {
1059 _rtl92ce_stop_tx_beacon(hw);
1060 _rtl92ce_enable_bcn_sub_func(hw);
1061 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1062 _rtl92ce_resume_tx_beacon(hw);
1063 _rtl92ce_disable_bcn_sub_func(hw);
1064 } else {
1065 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1066 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1067 type);
1068 }
1069
1070 switch (type) {
1071 case NL80211_IFTYPE_UNSPECIFIED:
1072 bt_msr |= MSR_NOLINK;
1073 ledaction = LED_CTL_LINK;
1074 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1075 "Set Network type to NO LINK!\n");
1076 break;
1077 case NL80211_IFTYPE_ADHOC:
1078 bt_msr |= MSR_ADHOC;
1079 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1080 "Set Network type to Ad Hoc!\n");
1081 break;
1082 case NL80211_IFTYPE_STATION:
1083 bt_msr |= MSR_INFRA;
1084 ledaction = LED_CTL_LINK;
1085 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1086 "Set Network type to STA!\n");
1087 break;
1088 case NL80211_IFTYPE_AP:
1089 bt_msr |= MSR_AP;
1090 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1091 "Set Network type to AP!\n");
1092 break;
1093 default:
1094 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1095 "Network type %d not supported!\n", type);
1096 return 1;
1097 break;
1098
1099 }
1100
1101 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1102 rtlpriv->cfg->ops->led_control(hw, ledaction);
1103 if ((bt_msr & 0xfc) == MSR_AP)
1104 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1105 else
1106 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1107 return 0;
1108 }
1109
1110 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1111 {
1112 struct rtl_priv *rtlpriv = rtl_priv(hw);
1113 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1114
1115 if (rtlpriv->psc.rfpwr_state != ERFON)
1116 return;
1117
1118 if (check_bssid) {
1119 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1120 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1121 (u8 *) (&reg_rcr));
1122 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1123 } else if (check_bssid == false) {
1124 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1125 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1126 rtlpriv->cfg->ops->set_hw_reg(hw,
1127 HW_VAR_RCR, (u8 *) (&reg_rcr));
1128 }
1129
1130 }
1131
1132 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1133 {
1134 struct rtl_priv *rtlpriv = rtl_priv(hw);
1135
1136 if (_rtl92ce_set_media_status(hw, type))
1137 return -EOPNOTSUPP;
1138
1139 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1140 if (type != NL80211_IFTYPE_AP)
1141 rtl92ce_set_check_bssid(hw, true);
1142 } else {
1143 rtl92ce_set_check_bssid(hw, false);
1144 }
1145
1146 return 0;
1147 }
1148
1149 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1150 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1151 {
1152 struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 rtl92c_dm_init_edca_turbo(hw);
1154 switch (aci) {
1155 case AC1_BK:
1156 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1157 break;
1158 case AC0_BE:
1159 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1160 break;
1161 case AC2_VI:
1162 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1163 break;
1164 case AC3_VO:
1165 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1166 break;
1167 default:
1168 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1169 break;
1170 }
1171 }
1172
1173 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1174 {
1175 struct rtl_priv *rtlpriv = rtl_priv(hw);
1176 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1177
1178 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1179 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1180 }
1181
1182 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1183 {
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1186
1187 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1188 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1189 synchronize_irq(rtlpci->pdev->irq);
1190 }
1191
1192 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1193 {
1194 struct rtl_priv *rtlpriv = rtl_priv(hw);
1195 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1196 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1197 u8 u1b_tmp;
1198 u32 u4b_tmp;
1199
1200 rtlpriv->intf_ops->enable_aspm(hw);
1201 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1202 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1203 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1204 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1205 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1206 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1207 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1208 rtl92c_firmware_selfreset(hw);
1209 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1210 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1211 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1212 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1213 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1214 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1215 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1216 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1217 (u1b_tmp << 8));
1218 } else {
1219 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1220 (u1b_tmp << 8));
1221 }
1222 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1223 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1224 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1225 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1226 if (rtlpcipriv->bt_coexist.bt_coexistence) {
1227 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1228 u4b_tmp |= 0x03824800;
1229 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1230 } else {
1231 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1232 }
1233
1234 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1235 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1236 }
1237
1238 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1239 {
1240 struct rtl_priv *rtlpriv = rtl_priv(hw);
1241 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1242 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1243 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1244 enum nl80211_iftype opmode;
1245
1246 mac->link_state = MAC80211_NOLINK;
1247 opmode = NL80211_IFTYPE_UNSPECIFIED;
1248 _rtl92ce_set_media_status(hw, opmode);
1249 if (rtlpci->driver_is_goingto_unload ||
1250 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1251 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1252 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1253 _rtl92ce_poweroff_adapter(hw);
1254 }
1255
1256 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1257 u32 *p_inta, u32 *p_intb)
1258 {
1259 struct rtl_priv *rtlpriv = rtl_priv(hw);
1260 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1261
1262 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1263 rtl_write_dword(rtlpriv, ISR, *p_inta);
1264
1265 /*
1266 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1267 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1268 */
1269 }
1270
1271 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1272 {
1273
1274 struct rtl_priv *rtlpriv = rtl_priv(hw);
1275 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1276 u16 bcn_interval, atim_window;
1277
1278 bcn_interval = mac->beacon_interval;
1279 atim_window = 2; /*FIX MERGE */
1280 rtl92ce_disable_interrupt(hw);
1281 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1282 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1283 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1284 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1285 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1286 rtl_write_byte(rtlpriv, 0x606, 0x30);
1287 rtl92ce_enable_interrupt(hw);
1288 }
1289
1290 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1291 {
1292 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1294 u16 bcn_interval = mac->beacon_interval;
1295
1296 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1297 "beacon_interval:%d\n", bcn_interval);
1298 rtl92ce_disable_interrupt(hw);
1299 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1300 rtl92ce_enable_interrupt(hw);
1301 }
1302
1303 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1304 u32 add_msr, u32 rm_msr)
1305 {
1306 struct rtl_priv *rtlpriv = rtl_priv(hw);
1307 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1308
1309 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1310 add_msr, rm_msr);
1311
1312 if (add_msr)
1313 rtlpci->irq_mask[0] |= add_msr;
1314 if (rm_msr)
1315 rtlpci->irq_mask[0] &= (~rm_msr);
1316 rtl92ce_disable_interrupt(hw);
1317 rtl92ce_enable_interrupt(hw);
1318 }
1319
1320 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1321 bool autoload_fail,
1322 u8 *hwinfo)
1323 {
1324 struct rtl_priv *rtlpriv = rtl_priv(hw);
1325 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1326 u8 rf_path, index, tempval;
1327 u16 i;
1328
1329 for (rf_path = 0; rf_path < 2; rf_path++) {
1330 for (i = 0; i < 3; i++) {
1331 if (!autoload_fail) {
1332 rtlefuse->
1333 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1334 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1335 rtlefuse->
1336 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1337 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1338 i];
1339 } else {
1340 rtlefuse->
1341 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1342 EEPROM_DEFAULT_TXPOWERLEVEL;
1343 rtlefuse->
1344 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1345 EEPROM_DEFAULT_TXPOWERLEVEL;
1346 }
1347 }
1348 }
1349
1350 for (i = 0; i < 3; i++) {
1351 if (!autoload_fail)
1352 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1353 else
1354 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1355 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1356 (tempval & 0xf);
1357 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1358 ((tempval & 0xf0) >> 4);
1359 }
1360
1361 for (rf_path = 0; rf_path < 2; rf_path++)
1362 for (i = 0; i < 3; i++)
1363 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1364 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1365 rf_path, i,
1366 rtlefuse->
1367 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1368 for (rf_path = 0; rf_path < 2; rf_path++)
1369 for (i = 0; i < 3; i++)
1370 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1371 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1372 rf_path, i,
1373 rtlefuse->
1374 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1375 for (rf_path = 0; rf_path < 2; rf_path++)
1376 for (i = 0; i < 3; i++)
1377 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1378 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1379 rf_path, i,
1380 rtlefuse->
1381 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]);
1382
1383 for (rf_path = 0; rf_path < 2; rf_path++) {
1384 for (i = 0; i < 14; i++) {
1385 index = _rtl92c_get_chnl_group((u8) i);
1386
1387 rtlefuse->txpwrlevel_cck[rf_path][i] =
1388 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1389 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1390 rtlefuse->
1391 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1392
1393 if ((rtlefuse->
1394 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1395 rtlefuse->
1396 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1397 > 0) {
1398 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1399 rtlefuse->
1400 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1401 [index] -
1402 rtlefuse->
1403 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1404 [index];
1405 } else {
1406 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1407 }
1408 }
1409
1410 for (i = 0; i < 14; i++) {
1411 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1412 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1413 rf_path, i,
1414 rtlefuse->txpwrlevel_cck[rf_path][i],
1415 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1416 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1417 }
1418 }
1419
1420 for (i = 0; i < 3; i++) {
1421 if (!autoload_fail) {
1422 rtlefuse->eeprom_pwrlimit_ht40[i] =
1423 hwinfo[EEPROM_TXPWR_GROUP + i];
1424 rtlefuse->eeprom_pwrlimit_ht20[i] =
1425 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1426 } else {
1427 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1428 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1429 }
1430 }
1431
1432 for (rf_path = 0; rf_path < 2; rf_path++) {
1433 for (i = 0; i < 14; i++) {
1434 index = _rtl92c_get_chnl_group((u8) i);
1435
1436 if (rf_path == RF90_PATH_A) {
1437 rtlefuse->pwrgroup_ht20[rf_path][i] =
1438 (rtlefuse->eeprom_pwrlimit_ht20[index]
1439 & 0xf);
1440 rtlefuse->pwrgroup_ht40[rf_path][i] =
1441 (rtlefuse->eeprom_pwrlimit_ht40[index]
1442 & 0xf);
1443 } else if (rf_path == RF90_PATH_B) {
1444 rtlefuse->pwrgroup_ht20[rf_path][i] =
1445 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1446 & 0xf0) >> 4);
1447 rtlefuse->pwrgroup_ht40[rf_path][i] =
1448 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1449 & 0xf0) >> 4);
1450 }
1451
1452 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1453 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1454 rf_path, i,
1455 rtlefuse->pwrgroup_ht20[rf_path][i]);
1456 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1457 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1458 rf_path, i,
1459 rtlefuse->pwrgroup_ht40[rf_path][i]);
1460 }
1461 }
1462
1463 for (i = 0; i < 14; i++) {
1464 index = _rtl92c_get_chnl_group((u8) i);
1465
1466 if (!autoload_fail)
1467 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1468 else
1469 tempval = EEPROM_DEFAULT_HT20_DIFF;
1470
1471 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1472 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1473 ((tempval >> 4) & 0xF);
1474
1475 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1476 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1477
1478 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1479 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1480
1481 index = _rtl92c_get_chnl_group((u8) i);
1482
1483 if (!autoload_fail)
1484 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1485 else
1486 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1487
1488 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1489 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1490 ((tempval >> 4) & 0xF);
1491 }
1492
1493 rtlefuse->legacy_ht_txpowerdiff =
1494 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1495
1496 for (i = 0; i < 14; i++)
1497 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1498 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1499 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1500 for (i = 0; i < 14; i++)
1501 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1502 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1503 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1504 for (i = 0; i < 14; i++)
1505 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1506 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1507 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1508 for (i = 0; i < 14; i++)
1509 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1510 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1511 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1512
1513 if (!autoload_fail)
1514 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1515 else
1516 rtlefuse->eeprom_regulatory = 0;
1517 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1518 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1519
1520 if (!autoload_fail) {
1521 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1522 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1523 } else {
1524 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1525 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1526 }
1527 RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1528 rtlefuse->eeprom_tssi[RF90_PATH_A],
1529 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1530
1531 if (!autoload_fail)
1532 tempval = hwinfo[EEPROM_THERMAL_METER];
1533 else
1534 tempval = EEPROM_DEFAULT_THERMALMETER;
1535 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1536
1537 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1538 rtlefuse->apk_thermalmeterignore = true;
1539
1540 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1541 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1542 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1543 }
1544
1545 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1546 {
1547 struct rtl_priv *rtlpriv = rtl_priv(hw);
1548 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1549 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1550 u16 i, usvalue;
1551 u8 hwinfo[HWSET_MAX_SIZE];
1552 u16 eeprom_id;
1553
1554 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1555 rtl_efuse_shadow_map_update(hw);
1556
1557 memcpy((void *)hwinfo,
1558 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1559 HWSET_MAX_SIZE);
1560 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1561 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1562 "RTL819X Not boot from eeprom, check it !!");
1563 }
1564
1565 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1566 hwinfo, HWSET_MAX_SIZE);
1567
1568 eeprom_id = *((u16 *)&hwinfo[0]);
1569 if (eeprom_id != RTL8190_EEPROM_ID) {
1570 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1571 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1572 rtlefuse->autoload_failflag = true;
1573 } else {
1574 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1575 rtlefuse->autoload_failflag = false;
1576 }
1577
1578 if (rtlefuse->autoload_failflag)
1579 return;
1580
1581 for (i = 0; i < 6; i += 2) {
1582 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1583 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1584 }
1585
1586 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1587
1588 _rtl92ce_read_txpower_info_from_hwpg(hw,
1589 rtlefuse->autoload_failflag,
1590 hwinfo);
1591
1592 rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1593 rtlefuse->autoload_failflag,
1594 hwinfo);
1595
1596 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1597 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1598 rtlefuse->txpwr_fromeprom = true;
1599 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1600
1601 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1602 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1603
1604 /* set channel paln to world wide 13 */
1605 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1606
1607 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1608 switch (rtlefuse->eeprom_oemid) {
1609 case EEPROM_CID_DEFAULT:
1610 if (rtlefuse->eeprom_did == 0x8176) {
1611 if ((rtlefuse->eeprom_svid == 0x103C &&
1612 rtlefuse->eeprom_smid == 0x1629))
1613 rtlhal->oem_id = RT_CID_819x_HP;
1614 else
1615 rtlhal->oem_id = RT_CID_DEFAULT;
1616 } else {
1617 rtlhal->oem_id = RT_CID_DEFAULT;
1618 }
1619 break;
1620 case EEPROM_CID_TOSHIBA:
1621 rtlhal->oem_id = RT_CID_TOSHIBA;
1622 break;
1623 case EEPROM_CID_QMI:
1624 rtlhal->oem_id = RT_CID_819x_QMI;
1625 break;
1626 case EEPROM_CID_WHQL:
1627 default:
1628 rtlhal->oem_id = RT_CID_DEFAULT;
1629 break;
1630
1631 }
1632 }
1633
1634 }
1635
1636 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1637 {
1638 struct rtl_priv *rtlpriv = rtl_priv(hw);
1639 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1640 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1641
1642 switch (rtlhal->oem_id) {
1643 case RT_CID_819x_HP:
1644 pcipriv->ledctl.led_opendrain = true;
1645 break;
1646 case RT_CID_819x_Lenovo:
1647 case RT_CID_DEFAULT:
1648 case RT_CID_TOSHIBA:
1649 case RT_CID_CCX:
1650 case RT_CID_819x_Acer:
1651 case RT_CID_WHQL:
1652 default:
1653 break;
1654 }
1655 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1656 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1657 }
1658
1659 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1660 {
1661 struct rtl_priv *rtlpriv = rtl_priv(hw);
1662 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1663 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1664 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1665 u8 tmp_u1b;
1666
1667 rtlhal->version = _rtl92ce_read_chip_version(hw);
1668 if (get_rf_type(rtlphy) == RF_1T1R)
1669 rtlpriv->dm.rfpath_rxenable[0] = true;
1670 else
1671 rtlpriv->dm.rfpath_rxenable[0] =
1672 rtlpriv->dm.rfpath_rxenable[1] = true;
1673 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1674 rtlhal->version);
1675 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1676 if (tmp_u1b & BIT(4)) {
1677 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1678 rtlefuse->epromtype = EEPROM_93C46;
1679 } else {
1680 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1681 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1682 }
1683 if (tmp_u1b & BIT(5)) {
1684 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1685 rtlefuse->autoload_failflag = false;
1686 _rtl92ce_read_adapter_info(hw);
1687 } else {
1688 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1689 }
1690 _rtl92ce_hal_customized_behavior(hw);
1691 }
1692
1693 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1694 struct ieee80211_sta *sta)
1695 {
1696 struct rtl_priv *rtlpriv = rtl_priv(hw);
1697 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1698 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1699 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1700 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1701 u32 ratr_value;
1702 u8 ratr_index = 0;
1703 u8 nmode = mac->ht_enable;
1704 u8 mimo_ps = IEEE80211_SMPS_OFF;
1705 u16 shortgi_rate;
1706 u32 tmp_ratr_value;
1707 u8 curtxbw_40mhz = mac->bw_40;
1708 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1709 1 : 0;
1710 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1711 1 : 0;
1712 enum wireless_mode wirelessmode = mac->mode;
1713
1714 if (rtlhal->current_bandtype == BAND_ON_5G)
1715 ratr_value = sta->supp_rates[1] << 4;
1716 else
1717 ratr_value = sta->supp_rates[0];
1718 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1719 sta->ht_cap.mcs.rx_mask[0] << 12);
1720 switch (wirelessmode) {
1721 case WIRELESS_MODE_B:
1722 if (ratr_value & 0x0000000c)
1723 ratr_value &= 0x0000000d;
1724 else
1725 ratr_value &= 0x0000000f;
1726 break;
1727 case WIRELESS_MODE_G:
1728 ratr_value &= 0x00000FF5;
1729 break;
1730 case WIRELESS_MODE_N_24G:
1731 case WIRELESS_MODE_N_5G:
1732 nmode = 1;
1733 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1734 ratr_value &= 0x0007F005;
1735 } else {
1736 u32 ratr_mask;
1737
1738 if (get_rf_type(rtlphy) == RF_1T2R ||
1739 get_rf_type(rtlphy) == RF_1T1R)
1740 ratr_mask = 0x000ff005;
1741 else
1742 ratr_mask = 0x0f0ff005;
1743
1744 ratr_value &= ratr_mask;
1745 }
1746 break;
1747 default:
1748 if (rtlphy->rf_type == RF_1T2R)
1749 ratr_value &= 0x000ff0ff;
1750 else
1751 ratr_value &= 0x0f0ff0ff;
1752
1753 break;
1754 }
1755
1756 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1757 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1758 (rtlpcipriv->bt_coexist.bt_cur_state) &&
1759 (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1760 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1761 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1762 ratr_value &= 0x0fffcfc0;
1763 else
1764 ratr_value &= 0x0FFFFFFF;
1765
1766 if (nmode && ((curtxbw_40mhz &&
1767 curshortgi_40mhz) || (!curtxbw_40mhz &&
1768 curshortgi_20mhz))) {
1769
1770 ratr_value |= 0x10000000;
1771 tmp_ratr_value = (ratr_value >> 12);
1772
1773 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1774 if ((1 << shortgi_rate) & tmp_ratr_value)
1775 break;
1776 }
1777
1778 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1779 (shortgi_rate << 4) | (shortgi_rate);
1780 }
1781
1782 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1783
1784 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1785 rtl_read_dword(rtlpriv, REG_ARFR0));
1786 }
1787
1788 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1789 struct ieee80211_sta *sta, u8 rssi_level)
1790 {
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1793 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1794 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1795 struct rtl_sta_info *sta_entry = NULL;
1796 u32 ratr_bitmap;
1797 u8 ratr_index;
1798 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1799 ? 1 : 0;
1800 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1801 1 : 0;
1802 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1803 1 : 0;
1804 enum wireless_mode wirelessmode = 0;
1805 bool shortgi = false;
1806 u8 rate_mask[5];
1807 u8 macid = 0;
1808 u8 mimo_ps = IEEE80211_SMPS_OFF;
1809
1810 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1811 wirelessmode = sta_entry->wireless_mode;
1812 if (mac->opmode == NL80211_IFTYPE_STATION)
1813 curtxbw_40mhz = mac->bw_40;
1814 else if (mac->opmode == NL80211_IFTYPE_AP ||
1815 mac->opmode == NL80211_IFTYPE_ADHOC)
1816 macid = sta->aid + 1;
1817
1818 if (rtlhal->current_bandtype == BAND_ON_5G)
1819 ratr_bitmap = sta->supp_rates[1] << 4;
1820 else
1821 ratr_bitmap = sta->supp_rates[0];
1822 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1823 sta->ht_cap.mcs.rx_mask[0] << 12);
1824 switch (wirelessmode) {
1825 case WIRELESS_MODE_B:
1826 ratr_index = RATR_INX_WIRELESS_B;
1827 if (ratr_bitmap & 0x0000000c)
1828 ratr_bitmap &= 0x0000000d;
1829 else
1830 ratr_bitmap &= 0x0000000f;
1831 break;
1832 case WIRELESS_MODE_G:
1833 ratr_index = RATR_INX_WIRELESS_GB;
1834
1835 if (rssi_level == 1)
1836 ratr_bitmap &= 0x00000f00;
1837 else if (rssi_level == 2)
1838 ratr_bitmap &= 0x00000ff0;
1839 else
1840 ratr_bitmap &= 0x00000ff5;
1841 break;
1842 case WIRELESS_MODE_A:
1843 ratr_index = RATR_INX_WIRELESS_A;
1844 ratr_bitmap &= 0x00000ff0;
1845 break;
1846 case WIRELESS_MODE_N_24G:
1847 case WIRELESS_MODE_N_5G:
1848 ratr_index = RATR_INX_WIRELESS_NGB;
1849
1850 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1851 if (rssi_level == 1)
1852 ratr_bitmap &= 0x00070000;
1853 else if (rssi_level == 2)
1854 ratr_bitmap &= 0x0007f000;
1855 else
1856 ratr_bitmap &= 0x0007f005;
1857 } else {
1858 if (rtlphy->rf_type == RF_1T2R ||
1859 rtlphy->rf_type == RF_1T1R) {
1860 if (curtxbw_40mhz) {
1861 if (rssi_level == 1)
1862 ratr_bitmap &= 0x000f0000;
1863 else if (rssi_level == 2)
1864 ratr_bitmap &= 0x000ff000;
1865 else
1866 ratr_bitmap &= 0x000ff015;
1867 } else {
1868 if (rssi_level == 1)
1869 ratr_bitmap &= 0x000f0000;
1870 else if (rssi_level == 2)
1871 ratr_bitmap &= 0x000ff000;
1872 else
1873 ratr_bitmap &= 0x000ff005;
1874 }
1875 } else {
1876 if (curtxbw_40mhz) {
1877 if (rssi_level == 1)
1878 ratr_bitmap &= 0x0f0f0000;
1879 else if (rssi_level == 2)
1880 ratr_bitmap &= 0x0f0ff000;
1881 else
1882 ratr_bitmap &= 0x0f0ff015;
1883 } else {
1884 if (rssi_level == 1)
1885 ratr_bitmap &= 0x0f0f0000;
1886 else if (rssi_level == 2)
1887 ratr_bitmap &= 0x0f0ff000;
1888 else
1889 ratr_bitmap &= 0x0f0ff005;
1890 }
1891 }
1892 }
1893
1894 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1895 (!curtxbw_40mhz && curshortgi_20mhz)) {
1896
1897 if (macid == 0)
1898 shortgi = true;
1899 else if (macid == 1)
1900 shortgi = false;
1901 }
1902 break;
1903 default:
1904 ratr_index = RATR_INX_WIRELESS_NGB;
1905
1906 if (rtlphy->rf_type == RF_1T2R)
1907 ratr_bitmap &= 0x000ff0ff;
1908 else
1909 ratr_bitmap &= 0x0f0ff0ff;
1910 break;
1911 }
1912 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1913 "ratr_bitmap :%x\n", ratr_bitmap);
1914 *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1915 (ratr_index << 28));
1916 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1917 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1918 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
1919 ratr_index, ratr_bitmap,
1920 rate_mask[0], rate_mask[1], rate_mask[2], rate_mask[3],
1921 rate_mask[4]);
1922 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1923
1924 if (macid != 0)
1925 sta_entry->ratr_index = ratr_index;
1926 }
1927
1928 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1929 struct ieee80211_sta *sta, u8 rssi_level)
1930 {
1931 struct rtl_priv *rtlpriv = rtl_priv(hw);
1932
1933 if (rtlpriv->dm.useramask)
1934 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1935 else
1936 rtl92ce_update_hal_rate_table(hw, sta);
1937 }
1938
1939 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1940 {
1941 struct rtl_priv *rtlpriv = rtl_priv(hw);
1942 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1943 u16 sifs_timer;
1944
1945 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1946 (u8 *)&mac->slot_time);
1947 if (!mac->ht_enable)
1948 sifs_timer = 0x0a0a;
1949 else
1950 sifs_timer = 0x1010;
1951 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1952 }
1953
1954 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1955 {
1956 struct rtl_priv *rtlpriv = rtl_priv(hw);
1957 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1958 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1959 enum rf_pwrstate e_rfpowerstate_toset;
1960 u8 u1tmp;
1961 bool actuallyset = false;
1962 unsigned long flag;
1963
1964 if (rtlpci->being_init_adapter)
1965 return false;
1966
1967 if (ppsc->swrf_processing)
1968 return false;
1969
1970 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1971 if (ppsc->rfchange_inprogress) {
1972 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1973 return false;
1974 } else {
1975 ppsc->rfchange_inprogress = true;
1976 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1977 }
1978
1979 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1980 REG_MAC_PINMUX_CFG)&~(BIT(3)));
1981
1982 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1983 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1984
1985 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
1986 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1987 "GPIOChangeRF - HW Radio ON, RF ON\n");
1988
1989 e_rfpowerstate_toset = ERFON;
1990 ppsc->hwradiooff = false;
1991 actuallyset = true;
1992 } else if ((ppsc->hwradiooff == false)
1993 && (e_rfpowerstate_toset == ERFOFF)) {
1994 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1995 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
1996
1997 e_rfpowerstate_toset = ERFOFF;
1998 ppsc->hwradiooff = true;
1999 actuallyset = true;
2000 }
2001
2002 if (actuallyset) {
2003 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2004 ppsc->rfchange_inprogress = false;
2005 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2006 } else {
2007 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2008 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2009
2010 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2011 ppsc->rfchange_inprogress = false;
2012 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2013 }
2014
2015 *valid = 1;
2016 return !ppsc->hwradiooff;
2017
2018 }
2019
2020 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2021 u8 *p_macaddr, bool is_group, u8 enc_algo,
2022 bool is_wepkey, bool clear_all)
2023 {
2024 struct rtl_priv *rtlpriv = rtl_priv(hw);
2025 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2026 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2027 u8 *macaddr = p_macaddr;
2028 u32 entry_id = 0;
2029 bool is_pairwise = false;
2030
2031 static u8 cam_const_addr[4][6] = {
2032 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2033 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2034 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2035 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2036 };
2037 static u8 cam_const_broad[] = {
2038 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2039 };
2040
2041 if (clear_all) {
2042 u8 idx = 0;
2043 u8 cam_offset = 0;
2044 u8 clear_number = 5;
2045
2046 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2047
2048 for (idx = 0; idx < clear_number; idx++) {
2049 rtl_cam_mark_invalid(hw, cam_offset + idx);
2050 rtl_cam_empty_entry(hw, cam_offset + idx);
2051
2052 if (idx < 5) {
2053 memset(rtlpriv->sec.key_buf[idx], 0,
2054 MAX_KEY_LEN);
2055 rtlpriv->sec.key_len[idx] = 0;
2056 }
2057 }
2058
2059 } else {
2060 switch (enc_algo) {
2061 case WEP40_ENCRYPTION:
2062 enc_algo = CAM_WEP40;
2063 break;
2064 case WEP104_ENCRYPTION:
2065 enc_algo = CAM_WEP104;
2066 break;
2067 case TKIP_ENCRYPTION:
2068 enc_algo = CAM_TKIP;
2069 break;
2070 case AESCCMP_ENCRYPTION:
2071 enc_algo = CAM_AES;
2072 break;
2073 default:
2074 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2075 "switch case not processed\n");
2076 enc_algo = CAM_TKIP;
2077 break;
2078 }
2079
2080 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2081 macaddr = cam_const_addr[key_index];
2082 entry_id = key_index;
2083 } else {
2084 if (is_group) {
2085 macaddr = cam_const_broad;
2086 entry_id = key_index;
2087 } else {
2088 if (mac->opmode == NL80211_IFTYPE_AP) {
2089 entry_id = rtl_cam_get_free_entry(hw,
2090 p_macaddr);
2091 if (entry_id >= TOTAL_CAM_ENTRY) {
2092 RT_TRACE(rtlpriv, COMP_SEC,
2093 DBG_EMERG,
2094 "Can not find free hw security cam entry\n");
2095 return;
2096 }
2097 } else {
2098 entry_id = CAM_PAIRWISE_KEY_POSITION;
2099 }
2100
2101 key_index = PAIRWISE_KEYIDX;
2102 is_pairwise = true;
2103 }
2104 }
2105
2106 if (rtlpriv->sec.key_len[key_index] == 0) {
2107 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2108 "delete one entry, entry_id is %d\n",
2109 entry_id);
2110 if (mac->opmode == NL80211_IFTYPE_AP)
2111 rtl_cam_del_entry(hw, p_macaddr);
2112 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2113 } else {
2114 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2115 "The insert KEY length is %d\n",
2116 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2117 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2118 "The insert KEY is %x %x\n",
2119 rtlpriv->sec.key_buf[0][0],
2120 rtlpriv->sec.key_buf[0][1]);
2121
2122 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2123 "add one entry\n");
2124 if (is_pairwise) {
2125 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2126 "Pairwise Key content",
2127 rtlpriv->sec.pairwise_key,
2128 rtlpriv->sec.
2129 key_len[PAIRWISE_KEYIDX]);
2130
2131 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2132 "set Pairwise key\n");
2133
2134 rtl_cam_add_one_entry(hw, macaddr, key_index,
2135 entry_id, enc_algo,
2136 CAM_CONFIG_NO_USEDK,
2137 rtlpriv->sec.
2138 key_buf[key_index]);
2139 } else {
2140 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2141 "set group key\n");
2142
2143 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2144 rtl_cam_add_one_entry(hw,
2145 rtlefuse->dev_addr,
2146 PAIRWISE_KEYIDX,
2147 CAM_PAIRWISE_KEY_POSITION,
2148 enc_algo,
2149 CAM_CONFIG_NO_USEDK,
2150 rtlpriv->sec.key_buf
2151 [entry_id]);
2152 }
2153
2154 rtl_cam_add_one_entry(hw, macaddr, key_index,
2155 entry_id, enc_algo,
2156 CAM_CONFIG_NO_USEDK,
2157 rtlpriv->sec.key_buf[entry_id]);
2158 }
2159
2160 }
2161 }
2162 }
2163
2164 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2165 {
2166 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2167
2168 rtlpcipriv->bt_coexist.bt_coexistence =
2169 rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2170 rtlpcipriv->bt_coexist.bt_ant_num =
2171 rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2172 rtlpcipriv->bt_coexist.bt_coexist_type =
2173 rtlpcipriv->bt_coexist.eeprom_bt_type;
2174
2175 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2176 rtlpcipriv->bt_coexist.bt_ant_isolation =
2177 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2178 else
2179 rtlpcipriv->bt_coexist.bt_ant_isolation =
2180 rtlpcipriv->bt_coexist.reg_bt_iso;
2181
2182 rtlpcipriv->bt_coexist.bt_radio_shared_type =
2183 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2184
2185 if (rtlpcipriv->bt_coexist.bt_coexistence) {
2186
2187 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2188 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2189 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2190 rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2191 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2192 rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2193 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2194 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2195 else
2196 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2197
2198 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2199 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2200 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2201 }
2202 }
2203
2204 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2205 bool auto_load_fail, u8 *hwinfo)
2206 {
2207 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2208 u8 value;
2209
2210 if (!auto_load_fail) {
2211 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2212 ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2213 value = hwinfo[RF_OPTION4];
2214 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2215 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2216 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2217 ((value & 0x10) >> 4);
2218 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2219 ((value & 0x20) >> 5);
2220 } else {
2221 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2222 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2223 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2224 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2225 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2226 }
2227
2228 rtl8192ce_bt_var_init(hw);
2229 }
2230
2231 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2232 {
2233 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2234
2235 /* 0:Low, 1:High, 2:From Efuse. */
2236 rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2237 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2238 rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2239 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2240 rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2241 }
2242
2243
2244 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2245 {
2246 struct rtl_priv *rtlpriv = rtl_priv(hw);
2247 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2248 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2249
2250 u8 u1_tmp;
2251
2252 if (rtlpcipriv->bt_coexist.bt_coexistence &&
2253 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2254 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2255
2256 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2257 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2258
2259 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2260 BIT_OFFSET_LEN_MASK_32(0, 1);
2261 u1_tmp = u1_tmp |
2262 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2263 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2264 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2265 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2266 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2267
2268 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2269 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2270 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2271
2272 /* Config to 1T1R. */
2273 if (rtlphy->rf_type == RF_1T1R) {
2274 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2275 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2276 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2277
2278 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2279 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2280 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2281 }
2282 }
2283 }
2284
2285 void rtl92ce_suspend(struct ieee80211_hw *hw)
2286 {
2287 }
2288
2289 void rtl92ce_resume(struct ieee80211_hw *hw)
2290 {
2291 }
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