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mac80211: stop toggling IEEE80211_HT_CAP_SUP_WIDTH_20_40
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rtlwifi / rtl8192se / hw.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "dm.h"
41 #include "fw.h"
42 #include "led.h"
43 #include "hw.h"
44
45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
46 {
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 switch (variable) {
52 case HW_VAR_RCR: {
53 *((u32 *) (val)) = rtlpci->receive_config;
54 break;
55 }
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
58 break;
59 }
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
62 break;
63 }
64 case HW_VAR_CORRECT_TSF: {
65 u64 tsf;
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
68
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
71
72 *((u64 *) (val)) = tsf;
73
74 break;
75 }
76 case HW_VAR_MRC: {
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
78 break;
79 }
80 default: {
81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 "switch case not processed\n");
83 break;
84 }
85 }
86 }
87
88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
89 {
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
96
97 switch (variable) {
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
101 break;
102 }
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
105 u8 rate_index = 0;
106
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
109 else
110 rate_cfg = rate_cfg & 0x15f;
111
112 rate_cfg |= 0x01;
113
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
117
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
120 rate_index++;
121 }
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
123
124 break;
125 }
126 case HW_VAR_BSSID:{
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
130 break;
131 }
132 case HW_VAR_SIFS:{
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
135 break;
136 }
137 case HW_VAR_SLOT_TIME:{
138 u8 e_aci;
139
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
141 "HW_VAR_SLOT_TIME %x\n", val[0]);
142
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
144
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
147 HW_VAR_AC_PARAM,
148 (&e_aci));
149 }
150 break;
151 }
152 case HW_VAR_ACK_PREAMBLE:{
153 u8 reg_tmp;
154 u8 short_preamble = (bool) (*val);
155 reg_tmp = (mac->cur_40_prime_sc) << 5;
156 if (short_preamble)
157 reg_tmp |= 0x80;
158
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
160 break;
161 }
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
164 u8 sec_min_space;
165
166 min_spacing_to_set = *val;
167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
169 NO_ENCRYPTION)
170 sec_min_space = 0;
171 else
172 sec_min_space = 1;
173
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
178
179 mac->min_space_cfg =
180 ((mac->min_space_cfg & 0xf8) |
181 min_spacing_to_set);
182
183 *val = min_spacing_to_set;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
187 mac->min_space_cfg);
188
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
190 mac->min_space_cfg);
191 }
192 break;
193 }
194 case HW_VAR_SHORTGI_DENSITY:{
195 u8 density_to_set;
196
197 density_to_set = *val;
198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
200
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
203 mac->min_space_cfg);
204
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
206 mac->min_space_cfg);
207
208 break;
209 }
210 case HW_VAR_AMPDU_FACTOR:{
211 u8 factor_toset;
212 u8 regtoset;
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
215 13, 2, 7, 7, 13, 13,
216 15, 15, 15, 15, 0};
217 u8 index = 0;
218
219 factor_toset = *val;
220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
223 factor_toset = 0xf;
224
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
227 factorlevel[index] =
228 factor_toset;
229 }
230
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
233 (factorlevel[index *
234 2 + 1] << 4));
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
237 regtoset);
238 }
239
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
243
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
246 factor_toset);
247 }
248 break;
249 }
250 case HW_VAR_AC_PARAM:{
251 u8 e_aci = *val;
252 rtl92s_dm_init_edca_turbo(hw);
253
254 if (rtlpci->acm_method != eAcmWay2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
256 HW_VAR_ACM_CTRL,
257 &e_aci);
258 break;
259 }
260 case HW_VAR_ACM_CTRL:{
261 u8 e_aci = *val;
262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
263 mac->ac[0].aifs));
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
266
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
268 0x0 : 0x1);
269
270 if (acm) {
271 switch (e_aci) {
272 case AC0_BE:
273 acm_ctrl |= AcmHw_BeqEn;
274 break;
275 case AC2_VI:
276 acm_ctrl |= AcmHw_ViqEn;
277 break;
278 case AC3_VO:
279 acm_ctrl |= AcmHw_VoqEn;
280 break;
281 default:
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
284 acm);
285 break;
286 }
287 } else {
288 switch (e_aci) {
289 case AC0_BE:
290 acm_ctrl &= (~AcmHw_BeqEn);
291 break;
292 case AC2_VI:
293 acm_ctrl &= (~AcmHw_ViqEn);
294 break;
295 case AC3_VO:
296 acm_ctrl &= (~AcmHw_BeqEn);
297 break;
298 default:
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
300 "switch case not processed\n");
301 break;
302 }
303 }
304
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
308 break;
309 }
310 case HW_VAR_RCR:{
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
313 break;
314 }
315 case HW_VAR_RETRY_LIMIT:{
316 u8 retry_limit = val[0];
317
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
321 break;
322 }
323 case HW_VAR_DUAL_TSF_RST: {
324 break;
325 }
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
328 break;
329 }
330 case HW_VAR_EFUSE_USAGE: {
331 rtlefuse->efuse_usedpercentage = *val;
332 break;
333 }
334 case HW_VAR_IO_CMD: {
335 break;
336 }
337 case HW_VAR_WPA_CONFIG: {
338 rtl_write_byte(rtlpriv, REG_SECR, *val);
339 break;
340 }
341 case HW_VAR_SET_RPWM:{
342 break;
343 }
344 case HW_VAR_H2C_FW_PWRMODE:{
345 break;
346 }
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
349 break;
350 }
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
352 break;
353 }
354 case HW_VAR_AID:{
355 break;
356 }
357 case HW_VAR_CORRECT_TSF:{
358 break;
359 }
360 case HW_VAR_MRC: {
361 bool bmrc_toset = *((bool *)val);
362 u8 u1bdata = 0;
363
364 if (bmrc_toset) {
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
366 MASKBYTE0, 0x33);
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
369 MASKBYTE0);
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
371 MASKBYTE0,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
375 MASKBYTE1);
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
377 MASKBYTE1,
378 (u1bdata | 0x04));
379
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
382 } else {
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
384 MASKBYTE0, 0x13);
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
387 MASKBYTE0);
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
389 MASKBYTE0,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
393 MASKBYTE1);
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
396
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
399 }
400
401 break;
402 }
403 default:
404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
405 "switch case not processed\n");
406 break;
407 }
408
409 }
410
411 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
412 {
413 struct rtl_priv *rtlpriv = rtl_priv(hw);
414 u8 sec_reg_value = 0x0;
415
416 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
417 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
418 rtlpriv->sec.pairwise_enc_algorithm,
419 rtlpriv->sec.group_enc_algorithm);
420
421 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
422 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
423 "not open hw encryption\n");
424 return;
425 }
426
427 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
428
429 if (rtlpriv->sec.use_defaultkey) {
430 sec_reg_value |= SCR_TXUSEDK;
431 sec_reg_value |= SCR_RXUSEDK;
432 }
433
434 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
435 sec_reg_value);
436
437 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
438
439 }
440
441 static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
442 {
443 struct rtl_priv *rtlpriv = rtl_priv(hw);
444 u8 waitcount = 100;
445 bool bresult = false;
446 u8 tmpvalue;
447
448 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
449
450 /* Wait the MAC synchronized. */
451 udelay(400);
452
453 /* Check if it is set ready. */
454 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
455 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
456
457 if ((data & (BIT(6) | BIT(7))) == false) {
458 waitcount = 100;
459 tmpvalue = 0;
460
461 while (1) {
462 waitcount--;
463
464 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
465 if ((tmpvalue & BIT(6)))
466 break;
467
468 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
469 if (waitcount == 0)
470 break;
471
472 udelay(10);
473 }
474
475 if (waitcount == 0)
476 bresult = false;
477 else
478 bresult = true;
479 }
480
481 return bresult;
482 }
483
484 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
485 {
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 u8 u1tmp;
488
489 /* The following config GPIO function */
490 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
491 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
492
493 /* config GPIO3 to input */
494 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
495 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
496
497 }
498
499 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
500 {
501 struct rtl_priv *rtlpriv = rtl_priv(hw);
502 u8 u1tmp;
503 u8 retval = ERFON;
504
505 /* The following config GPIO function */
506 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
507 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
508
509 /* config GPIO3 to input */
510 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
511 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
512
513 /* On some of the platform, driver cannot read correct
514 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
515 mdelay(10);
516
517 /* check GPIO3 */
518 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
519 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
520
521 return retval;
522 }
523
524 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
525 {
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
528 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
529
530 u8 i;
531 u8 tmpu1b;
532 u16 tmpu2b;
533 u8 pollingcnt = 20;
534
535 if (rtlpci->first_init) {
536 /* Reset PCIE Digital */
537 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
538 tmpu1b &= 0xFE;
539 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
540 udelay(1);
541 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
542 }
543
544 /* Switch to SW IO control */
545 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
546 if (tmpu1b & BIT(7)) {
547 tmpu1b &= ~(BIT(6) | BIT(7));
548
549 /* Set failed, return to prevent hang. */
550 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
551 return;
552 }
553
554 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
555 udelay(50);
556 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
557 udelay(50);
558
559 /* Clear FW RPWM for FW control LPS.*/
560 rtl_write_byte(rtlpriv, RPWM, 0x0);
561
562 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
563 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
564 tmpu1b &= 0x73;
565 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
566 /* wait for BIT 10/11/15 to pull high automatically!! */
567 mdelay(1);
568
569 rtl_write_byte(rtlpriv, CMDR, 0);
570 rtl_write_byte(rtlpriv, TCR, 0);
571
572 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
573 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
574 tmpu1b |= 0x08;
575 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
576 tmpu1b &= ~(BIT(3));
577 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
578
579 /* Enable AFE clock source */
580 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
581 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
582 /* Delay 1.5ms */
583 mdelay(2);
584 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
585 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
586
587 /* Enable AFE Macro Block's Bandgap */
588 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
589 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
590 mdelay(1);
591
592 /* Enable AFE Mbias */
593 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
594 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
595 mdelay(1);
596
597 /* Enable LDOA15 block */
598 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
599 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
600
601 /* Set Digital Vdd to Retention isolation Path. */
602 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
603 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
604
605 /* For warm reboot NIC disappera bug. */
606 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
607 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
608
609 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
610
611 /* Enable AFE PLL Macro Block */
612 /* We need to delay 100u before enabling PLL. */
613 udelay(200);
614 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
615 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
616
617 /* for divider reset */
618 udelay(100);
619 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
620 BIT(4) | BIT(6)));
621 udelay(10);
622 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
623 udelay(10);
624
625 /* Enable MAC 80MHZ clock */
626 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
627 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
628 mdelay(1);
629
630 /* Release isolation AFE PLL & MD */
631 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
632
633 /* Enable MAC clock */
634 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
635 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
636
637 /* Enable Core digital and enable IOREG R/W */
638 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
639 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
640
641 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
642 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
643
644 /* enable REG_EN */
645 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
646
647 /* Switch the control path. */
648 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
649 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
650
651 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
652 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
653 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
654 return; /* Set failed, return to prevent hang. */
655
656 rtl_write_word(rtlpriv, CMDR, 0x07FC);
657
658 /* MH We must enable the section of code to prevent load IMEM fail. */
659 /* Load MAC register from WMAc temporarily We simulate macreg. */
660 /* txt HW will provide MAC txt later */
661 rtl_write_byte(rtlpriv, 0x6, 0x30);
662 rtl_write_byte(rtlpriv, 0x49, 0xf0);
663
664 rtl_write_byte(rtlpriv, 0x4b, 0x81);
665
666 rtl_write_byte(rtlpriv, 0xb5, 0x21);
667
668 rtl_write_byte(rtlpriv, 0xdc, 0xff);
669 rtl_write_byte(rtlpriv, 0xdd, 0xff);
670 rtl_write_byte(rtlpriv, 0xde, 0xff);
671 rtl_write_byte(rtlpriv, 0xdf, 0xff);
672
673 rtl_write_byte(rtlpriv, 0x11a, 0x00);
674 rtl_write_byte(rtlpriv, 0x11b, 0x00);
675
676 for (i = 0; i < 32; i++)
677 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
678
679 rtl_write_byte(rtlpriv, 0x236, 0xff);
680
681 rtl_write_byte(rtlpriv, 0x503, 0x22);
682
683 if (ppsc->support_aspm && !ppsc->support_backdoor)
684 rtl_write_byte(rtlpriv, 0x560, 0x40);
685 else
686 rtl_write_byte(rtlpriv, 0x560, 0x00);
687
688 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
689
690 /* Set RX Desc Address */
691 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
692 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
693
694 /* Set TX Desc Address */
695 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
696 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
697 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
698 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
699 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
700 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
701 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
702 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
703 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
704
705 rtl_write_word(rtlpriv, CMDR, 0x37FC);
706
707 /* To make sure that TxDMA can ready to download FW. */
708 /* We should reset TxDMA if IMEM RPT was not ready. */
709 do {
710 tmpu1b = rtl_read_byte(rtlpriv, TCR);
711 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
712 break;
713
714 udelay(5);
715 } while (pollingcnt--);
716
717 if (pollingcnt <= 0) {
718 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
719 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
720 tmpu1b);
721 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
722 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
723 udelay(2);
724 /* Reset TxDMA */
725 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
726 }
727
728 /* After MACIO reset,we must refresh LED state. */
729 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
730 (ppsc->rfoff_reason == 0)) {
731 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
732 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
733 enum rf_pwrstate rfpwr_state_toset;
734 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
735
736 if (rfpwr_state_toset == ERFON)
737 rtl92se_sw_led_on(hw, pLed0);
738 }
739 }
740
741 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
742 {
743 struct rtl_priv *rtlpriv = rtl_priv(hw);
744 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
745 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
746 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
747 u8 i;
748 u16 tmpu2b;
749
750 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
751
752 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
753 /* Turn on 0x40 Command register */
754 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
755 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
756 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
757
758 /* Set TCR TX DMA pre 2 FULL enable bit */
759 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
760 TXDMAPRE2FULL);
761
762 /* Set RCR */
763 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
764
765 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
766
767 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
768 /* Set CCK/OFDM SIFS */
769 /* CCK SIFS shall always be 10us. */
770 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
771 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
772
773 /* Set AckTimeout */
774 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
775
776 /* Beacon related */
777 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
778 rtl_write_word(rtlpriv, ATIMWND, 2);
779
780 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
781 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
782 /* Firmware allocate now, associate with FW internal setting.!!! */
783
784 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
785 /* 5.3 Set driver info, we only accept PHY status now. */
786 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
787 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
788
789 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
790 /* Set RRSR to all legacy rate and HT rate
791 * CCK rate is supported by default.
792 * CCK rate will be filtered out only when associated
793 * AP does not support it.
794 * Only enable ACK rate to OFDM 24M
795 * Disable RRSR for CCK rate in A-Cut */
796
797 if (rtlhal->version == VERSION_8192S_ACUT)
798 rtl_write_byte(rtlpriv, RRSR, 0xf0);
799 else if (rtlhal->version == VERSION_8192S_BCUT)
800 rtl_write_byte(rtlpriv, RRSR, 0xff);
801 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
802 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
803
804 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
805 /* fallback to CCK rate */
806 for (i = 0; i < 8; i++) {
807 /*Disable RRSR for CCK rate in A-Cut */
808 if (rtlhal->version == VERSION_8192S_ACUT)
809 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
810 }
811
812 /* Different rate use different AMPDU size */
813 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
814 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
815 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
816 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
817 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
818 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
819 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
820 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
821 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
822 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
823
824 /* Set Data / Response auto rate fallack retry count */
825 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
826 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
827 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
828 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
829
830 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
831 /* Set all rate to support SG */
832 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
833
834 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
835 /* Set NAV protection length */
836 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
837 /* CF-END Threshold */
838 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
839 /* Set AMPDU minimum space */
840 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
841 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
842 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
843
844 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
845 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
846 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
847 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
848 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
849
850 /* 14. Set driver info, we only accept PHY status now. */
851 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
852
853 /* 15. For EEPROM R/W Workaround */
854 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
855 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
856 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
857 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
858 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
859
860 /* 17. For EFUSE */
861 /* We may R/W EFUSE in EEPROM mode */
862 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
863 u8 tempval;
864
865 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
866 tempval &= 0xFE;
867 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
868
869 /* Change Program timing */
870 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
871 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
872 }
873
874 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
875
876 }
877
878 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
879 {
880 struct rtl_priv *rtlpriv = rtl_priv(hw);
881 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
882 struct rtl_phy *rtlphy = &(rtlpriv->phy);
883 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
884
885 u8 reg_bw_opmode = 0;
886 u32 reg_rrsr = 0;
887 u8 regtmp = 0;
888
889 reg_bw_opmode = BW_OPMODE_20MHZ;
890 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
891
892 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
893 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
894 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
895 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
896
897 /* Set Retry Limit here */
898 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
899 (u8 *)(&rtlpci->shortretry_limit));
900
901 rtl_write_byte(rtlpriv, MLT, 0x8f);
902
903 /* For Min Spacing configuration. */
904 switch (rtlphy->rf_type) {
905 case RF_1T2R:
906 case RF_1T1R:
907 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
908 break;
909 case RF_2T2R:
910 case RF_2T2R_GREEN:
911 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
912 break;
913 }
914 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
915 }
916
917 int rtl92se_hw_init(struct ieee80211_hw *hw)
918 {
919 struct rtl_priv *rtlpriv = rtl_priv(hw);
920 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
921 struct rtl_phy *rtlphy = &(rtlpriv->phy);
922 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
923 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
924 u8 tmp_byte = 0;
925
926 bool rtstatus = true;
927 u8 tmp_u1b;
928 int err = false;
929 u8 i;
930 int wdcapra_add[] = {
931 EDCAPARA_BE, EDCAPARA_BK,
932 EDCAPARA_VI, EDCAPARA_VO};
933 u8 secr_value = 0x0;
934
935 rtlpci->being_init_adapter = true;
936
937 rtlpriv->intf_ops->disable_aspm(hw);
938
939 /* 1. MAC Initialize */
940 /* Before FW download, we have to set some MAC register */
941 _rtl92se_macconfig_before_fwdownload(hw);
942
943 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
944 PMC_FSM) >> 16) & 0xF);
945
946 rtl8192se_gpiobit3_cfg_inputmode(hw);
947
948 /* 2. download firmware */
949 rtstatus = rtl92s_download_fw(hw);
950 if (!rtstatus) {
951 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
952 "Failed to download FW. Init HW without FW now... "
953 "Please copy FW into /lib/firmware/rtlwifi\n");
954 return 1;
955 }
956
957 /* After FW download, we have to reset MAC register */
958 _rtl92se_macconfig_after_fwdownload(hw);
959
960 /*Retrieve default FW Cmd IO map. */
961 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
962 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
963
964 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
965 if (!rtl92s_phy_mac_config(hw)) {
966 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
967 return rtstatus;
968 }
969
970 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
971 /* We must set flag avoid BB/RF config period later!! */
972 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
973
974 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
975 if (!rtl92s_phy_bb_config(hw)) {
976 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
977 return rtstatus;
978 }
979
980 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
981 /* Before initalizing RF. We can not use FW to do RF-R/W. */
982
983 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
984
985 /* RF Power Save */
986 #if 0
987 /* H/W or S/W RF OFF before sleep. */
988 if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
989 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
990
991 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
992 rtlpriv->psc.rfpwr_state = ERFON;
993 /* FIXME: check spinlocks if this block is uncommented */
994 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
995 } else {
996 /* gpio radio on/off is out of adapter start */
997 if (rtlpriv->psc.hwradiooff == false) {
998 rtlpriv->psc.rfpwr_state = ERFON;
999 rtlpriv->psc.rfoff_reason = 0;
1000 }
1001 }
1002 #endif
1003
1004 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1005 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1006 if (rtlhal->version == VERSION_8192S_ACUT)
1007 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1008 else
1009 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1010
1011 if (!rtl92s_phy_rf_config(hw)) {
1012 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1013 return rtstatus;
1014 }
1015
1016 /* After read predefined TXT, we must set BB/MAC/RF
1017 * register as our requirement */
1018
1019 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1020 (enum radio_path)0,
1021 RF_CHNLBW,
1022 RFREG_OFFSET_MASK);
1023 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1024 (enum radio_path)1,
1025 RF_CHNLBW,
1026 RFREG_OFFSET_MASK);
1027
1028 /*---- Set CCK and OFDM Block "ON"----*/
1029 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1030 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1031
1032 /*3 Set Hardware(Do nothing now) */
1033 _rtl92se_hw_configure(hw);
1034
1035 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1036 /* TX power index for different rate set. */
1037 /* Get original hw reg values */
1038 rtl92s_phy_get_hw_reg_originalvalue(hw);
1039 /* Write correct tx power index */
1040 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1041
1042 /* We must set MAC address after firmware download. */
1043 for (i = 0; i < 6; i++)
1044 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1045
1046 /* EEPROM R/W workaround */
1047 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1048 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1049
1050 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1051
1052 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1053 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1054 tmp_byte = tmp_byte | BIT(5);
1055 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1056 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1057 }
1058
1059 /* We enable high power and RA related mechanism after NIC
1060 * initialized. */
1061 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1062
1063 /* Add to prevent ASPM bug. */
1064 /* Always enable hst and NIC clock request. */
1065 rtl92s_phy_switch_ephy_parameter(hw);
1066
1067 /* Security related
1068 * 1. Clear all H/W keys.
1069 * 2. Enable H/W encryption/decryption. */
1070 rtl_cam_reset_all_entry(hw);
1071 secr_value |= SCR_TXENCENABLE;
1072 secr_value |= SCR_RXENCENABLE;
1073 secr_value |= SCR_NOSKMC;
1074 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1075
1076 for (i = 0; i < 4; i++)
1077 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1078
1079 if (rtlphy->rf_type == RF_1T2R) {
1080 bool mrc2set = true;
1081 /* Turn on B-Path */
1082 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1083 }
1084
1085 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1086 rtl92s_dm_init(hw);
1087 rtlpci->being_init_adapter = false;
1088
1089 return err;
1090 }
1091
1092 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1093 {
1094 /* This is a stub. */
1095 }
1096
1097 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1098 {
1099 struct rtl_priv *rtlpriv = rtl_priv(hw);
1100 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1101 u32 reg_rcr = rtlpci->receive_config;
1102
1103 if (rtlpriv->psc.rfpwr_state != ERFON)
1104 return;
1105
1106 if (check_bssid) {
1107 reg_rcr |= (RCR_CBSSID);
1108 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1109 } else if (!check_bssid) {
1110 reg_rcr &= (~RCR_CBSSID);
1111 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1112 }
1113
1114 }
1115
1116 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1117 enum nl80211_iftype type)
1118 {
1119 struct rtl_priv *rtlpriv = rtl_priv(hw);
1120 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1121 u32 temp;
1122 bt_msr &= ~MSR_LINK_MASK;
1123
1124 switch (type) {
1125 case NL80211_IFTYPE_UNSPECIFIED:
1126 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1127 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1128 "Set Network type to NO LINK!\n");
1129 break;
1130 case NL80211_IFTYPE_ADHOC:
1131 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1132 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1133 "Set Network type to Ad Hoc!\n");
1134 break;
1135 case NL80211_IFTYPE_STATION:
1136 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1137 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1138 "Set Network type to STA!\n");
1139 break;
1140 case NL80211_IFTYPE_AP:
1141 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1142 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1143 "Set Network type to AP!\n");
1144 break;
1145 default:
1146 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1147 "Network type %d not supported!\n", type);
1148 return 1;
1149 break;
1150
1151 }
1152
1153 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1154
1155 temp = rtl_read_dword(rtlpriv, TCR);
1156 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1157 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1158
1159
1160 return 0;
1161 }
1162
1163 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1164 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1165 {
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167
1168 if (_rtl92se_set_media_status(hw, type))
1169 return -EOPNOTSUPP;
1170
1171 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1172 if (type != NL80211_IFTYPE_AP)
1173 rtl92se_set_check_bssid(hw, true);
1174 } else {
1175 rtl92se_set_check_bssid(hw, false);
1176 }
1177
1178 return 0;
1179 }
1180
1181 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1182 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1183 {
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 rtl92s_dm_init_edca_turbo(hw);
1186
1187 switch (aci) {
1188 case AC1_BK:
1189 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1190 break;
1191 case AC0_BE:
1192 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1193 break;
1194 case AC2_VI:
1195 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1196 break;
1197 case AC3_VO:
1198 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1199 break;
1200 default:
1201 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1202 break;
1203 }
1204 }
1205
1206 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1207 {
1208 struct rtl_priv *rtlpriv = rtl_priv(hw);
1209 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1210
1211 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1212 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1213 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1214 }
1215
1216 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1217 {
1218 struct rtl_priv *rtlpriv;
1219 struct rtl_pci *rtlpci;
1220
1221 rtlpriv = rtl_priv(hw);
1222 /* if firmware not available, no interrupts */
1223 if (!rtlpriv || !rtlpriv->max_fw_size)
1224 return;
1225 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1226 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1227 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1228
1229 synchronize_irq(rtlpci->pdev->irq);
1230 }
1231
1232
1233 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1234 {
1235 struct rtl_priv *rtlpriv = rtl_priv(hw);
1236 u8 waitcnt = 100;
1237 bool result = false;
1238 u8 tmp;
1239
1240 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1241
1242 /* Wait the MAC synchronized. */
1243 udelay(400);
1244
1245 /* Check if it is set ready. */
1246 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1247 result = ((tmp & BIT(7)) == (data & BIT(7)));
1248
1249 if ((data & (BIT(6) | BIT(7))) == false) {
1250 waitcnt = 100;
1251 tmp = 0;
1252
1253 while (1) {
1254 waitcnt--;
1255 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1256
1257 if ((tmp & BIT(6)))
1258 break;
1259
1260 pr_err("wait for BIT(6) return value %x\n", tmp);
1261
1262 if (waitcnt == 0)
1263 break;
1264 udelay(10);
1265 }
1266
1267 if (waitcnt == 0)
1268 result = false;
1269 else
1270 result = true;
1271 }
1272
1273 return result;
1274 }
1275
1276 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1277 {
1278 struct rtl_priv *rtlpriv = rtl_priv(hw);
1279 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1281 u8 u1btmp;
1282
1283 if (rtlhal->driver_going2unload)
1284 rtl_write_byte(rtlpriv, 0x560, 0x0);
1285
1286 /* Power save for BB/RF */
1287 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1288 u1btmp |= BIT(0);
1289 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1290 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1291 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1292 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1293 udelay(100);
1294 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1295 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1296 udelay(10);
1297 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1298 udelay(10);
1299 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1300 udelay(10);
1301 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1302 rtl_write_word(rtlpriv, CMDR, 0x0000);
1303
1304 if (rtlhal->driver_going2unload) {
1305 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1306 u1btmp &= ~(BIT(0));
1307 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1308 }
1309
1310 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1311
1312 /* Add description. After switch control path. register
1313 * after page1 will be invisible. We can not do any IO
1314 * for register>0x40. After resume&MACIO reset, we need
1315 * to remember previous reg content. */
1316 if (u1btmp & BIT(7)) {
1317 u1btmp &= ~(BIT(6) | BIT(7));
1318 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1319 pr_err("Switch ctrl path fail\n");
1320 return;
1321 }
1322 }
1323
1324 /* Power save for MAC */
1325 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1326 !rtlhal->driver_going2unload) {
1327 /* enable LED function */
1328 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1329 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1330 } else {
1331 /* LED function disable. Power range is about 8mA now. */
1332 /* if write 0xF1 disconnet_pci power
1333 * ifconfig wlan0 down power are both high 35:70 */
1334 /* if write oxF9 disconnet_pci power
1335 * ifconfig wlan0 down power are both low 12:45*/
1336 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1337 }
1338
1339 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1340 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1341 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1342 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1343 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1344 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1345
1346 }
1347
1348 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1349 {
1350 struct rtl_priv *rtlpriv = rtl_priv(hw);
1351 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1352 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1353 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1354
1355 if (rtlpci->up_first_time == 1)
1356 return;
1357
1358 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1359 rtl92se_sw_led_on(hw, pLed0);
1360 else
1361 rtl92se_sw_led_off(hw, pLed0);
1362 }
1363
1364
1365 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1366 {
1367 struct rtl_priv *rtlpriv = rtl_priv(hw);
1368 u16 tmpu2b;
1369 u8 tmpu1b;
1370
1371 rtlpriv->psc.pwrdomain_protect = true;
1372
1373 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1374 if (tmpu1b & BIT(7)) {
1375 tmpu1b &= ~(BIT(6) | BIT(7));
1376 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1377 rtlpriv->psc.pwrdomain_protect = false;
1378 return;
1379 }
1380 }
1381
1382 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1383 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1384
1385 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1386 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1387
1388 /* If IPS we need to turn LED on. So we not
1389 * not disable BIT 3/7 of reg3. */
1390 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1391 tmpu1b &= 0xFB;
1392 else
1393 tmpu1b &= 0x73;
1394
1395 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1396 /* wait for BIT 10/11/15 to pull high automatically!! */
1397 mdelay(1);
1398
1399 rtl_write_byte(rtlpriv, CMDR, 0);
1400 rtl_write_byte(rtlpriv, TCR, 0);
1401
1402 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1403 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1404 tmpu1b |= 0x08;
1405 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1406 tmpu1b &= ~(BIT(3));
1407 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1408
1409 /* Enable AFE clock source */
1410 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1411 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1412 /* Delay 1.5ms */
1413 udelay(1500);
1414 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1415 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1416
1417 /* Enable AFE Macro Block's Bandgap */
1418 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1419 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1420 mdelay(1);
1421
1422 /* Enable AFE Mbias */
1423 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1424 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1425 mdelay(1);
1426
1427 /* Enable LDOA15 block */
1428 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1429 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1430
1431 /* Set Digital Vdd to Retention isolation Path. */
1432 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1433 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1434
1435
1436 /* For warm reboot NIC disappera bug. */
1437 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1438 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1439
1440 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1441
1442 /* Enable AFE PLL Macro Block */
1443 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1444 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1445 /* Enable MAC 80MHZ clock */
1446 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1447 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1448 mdelay(1);
1449
1450 /* Release isolation AFE PLL & MD */
1451 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1452
1453 /* Enable MAC clock */
1454 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1455 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1456
1457 /* Enable Core digital and enable IOREG R/W */
1458 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1459 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1460 /* enable REG_EN */
1461 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1462
1463 /* Switch the control path. */
1464 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1465 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1466
1467 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1468 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1469 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1470 rtlpriv->psc.pwrdomain_protect = false;
1471 return;
1472 }
1473
1474 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1475
1476 /* After MACIO reset,we must refresh LED state. */
1477 _rtl92se_gen_refreshledstate(hw);
1478
1479 rtlpriv->psc.pwrdomain_protect = false;
1480 }
1481
1482 void rtl92se_card_disable(struct ieee80211_hw *hw)
1483 {
1484 struct rtl_priv *rtlpriv = rtl_priv(hw);
1485 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1486 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1487 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1488 enum nl80211_iftype opmode;
1489 u8 wait = 30;
1490
1491 rtlpriv->intf_ops->enable_aspm(hw);
1492
1493 if (rtlpci->driver_is_goingto_unload ||
1494 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1495 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1496
1497 /* we should chnge GPIO to input mode
1498 * this will drop away current about 25mA*/
1499 rtl8192se_gpiobit3_cfg_inputmode(hw);
1500
1501 /* this is very important for ips power save */
1502 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1503 if (rtlpriv->psc.pwrdomain_protect)
1504 mdelay(20);
1505 else
1506 break;
1507 }
1508
1509 mac->link_state = MAC80211_NOLINK;
1510 opmode = NL80211_IFTYPE_UNSPECIFIED;
1511 _rtl92se_set_media_status(hw, opmode);
1512
1513 _rtl92s_phy_set_rfhalt(hw);
1514 udelay(100);
1515 }
1516
1517 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1518 u32 *p_intb)
1519 {
1520 struct rtl_priv *rtlpriv = rtl_priv(hw);
1521 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1522
1523 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1524 rtl_write_dword(rtlpriv, ISR, *p_inta);
1525
1526 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1527 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1528 }
1529
1530 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1531 {
1532 struct rtl_priv *rtlpriv = rtl_priv(hw);
1533 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1534 u16 bcntime_cfg = 0;
1535 u16 bcn_cw = 6, bcn_ifs = 0xf;
1536 u16 atim_window = 2;
1537
1538 /* ATIM Window (in unit of TU). */
1539 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1540
1541 /* Beacon interval (in unit of TU). */
1542 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1543
1544 /* DrvErlyInt (in unit of TU). (Time to send
1545 * interrupt to notify driver to change
1546 * beacon content) */
1547 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1548
1549 /* BcnDMATIM(in unit of us). Indicates the
1550 * time before TBTT to perform beacon queue DMA */
1551 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1552
1553 /* Force beacon frame transmission even
1554 * after receiving beacon frame from
1555 * other ad hoc STA */
1556 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1557
1558 /* Beacon Time Configuration */
1559 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1560 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1561
1562 /* TODO: bcn_ifs may required to be changed on ASIC */
1563 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1564
1565 /*for beacon changed */
1566 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1567 }
1568
1569 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1570 {
1571 struct rtl_priv *rtlpriv = rtl_priv(hw);
1572 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1573 u16 bcn_interval = mac->beacon_interval;
1574
1575 /* Beacon interval (in unit of TU). */
1576 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1577 /* 2008.10.24 added by tynli for beacon changed. */
1578 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1579 }
1580
1581 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1582 u32 add_msr, u32 rm_msr)
1583 {
1584 struct rtl_priv *rtlpriv = rtl_priv(hw);
1585 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1586
1587 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1588 add_msr, rm_msr);
1589
1590 if (add_msr)
1591 rtlpci->irq_mask[0] |= add_msr;
1592
1593 if (rm_msr)
1594 rtlpci->irq_mask[0] &= (~rm_msr);
1595
1596 rtl92se_disable_interrupt(hw);
1597 rtl92se_enable_interrupt(hw);
1598 }
1599
1600 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1601 {
1602 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1603 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1604 u8 efuse_id;
1605
1606 rtlhal->ic_class = IC_INFERIORITY_A;
1607
1608 /* Only retrieving while using EFUSE. */
1609 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1610 !rtlefuse->autoload_failflag) {
1611 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1612
1613 if (efuse_id == 0xfe)
1614 rtlhal->ic_class = IC_INFERIORITY_B;
1615 }
1616 }
1617
1618 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1619 {
1620 struct rtl_priv *rtlpriv = rtl_priv(hw);
1621 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1622 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1623 u16 i, usvalue;
1624 u16 eeprom_id;
1625 u8 tempval;
1626 u8 hwinfo[HWSET_MAX_SIZE_92S];
1627 u8 rf_path, index;
1628
1629 if (rtlefuse->epromtype == EEPROM_93C46) {
1630 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1631 "RTL819X Not boot from eeprom, check it !!\n");
1632 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1633 rtl_efuse_shadow_map_update(hw);
1634
1635 memcpy((void *)hwinfo, (void *)
1636 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1637 HWSET_MAX_SIZE_92S);
1638 }
1639
1640 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1641 hwinfo, HWSET_MAX_SIZE_92S);
1642
1643 eeprom_id = *((u16 *)&hwinfo[0]);
1644 if (eeprom_id != RTL8190_EEPROM_ID) {
1645 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1646 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1647 rtlefuse->autoload_failflag = true;
1648 } else {
1649 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1650 rtlefuse->autoload_failflag = false;
1651 }
1652
1653 if (rtlefuse->autoload_failflag)
1654 return;
1655
1656 _rtl8192se_get_IC_Inferiority(hw);
1657
1658 /* Read IC Version && Channel Plan */
1659 /* VID, DID SE 0xA-D */
1660 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1661 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1662 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1663 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1664 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1665
1666 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1667 "EEPROMId = 0x%4x\n", eeprom_id);
1668 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1669 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1670 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1671 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1672 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1673 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1674 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1675 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1676
1677 for (i = 0; i < 6; i += 2) {
1678 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1679 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1680 }
1681
1682 for (i = 0; i < 6; i++)
1683 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1684
1685 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1686
1687 /* Get Tx Power Level by Channel */
1688 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1689 /* 92S suupport RF A & B */
1690 for (rf_path = 0; rf_path < 2; rf_path++) {
1691 for (i = 0; i < 3; i++) {
1692 /* Read CCK RF A & B Tx power */
1693 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1694 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1695
1696 /* Read OFDM RF A & B Tx power for 1T */
1697 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1698 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1699
1700 /* Read OFDM RF A & B Tx power for 2T */
1701 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1702 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1703 rf_path * 3 + i];
1704 }
1705 }
1706
1707 for (rf_path = 0; rf_path < 2; rf_path++)
1708 for (i = 0; i < 3; i++)
1709 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1710 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1711 rf_path, i,
1712 rtlefuse->eeprom_chnlarea_txpwr_cck
1713 [rf_path][i]);
1714 for (rf_path = 0; rf_path < 2; rf_path++)
1715 for (i = 0; i < 3; i++)
1716 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1717 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1718 rf_path, i,
1719 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1720 [rf_path][i]);
1721 for (rf_path = 0; rf_path < 2; rf_path++)
1722 for (i = 0; i < 3; i++)
1723 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1724 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1725 rf_path, i,
1726 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1727 [rf_path][i]);
1728
1729 for (rf_path = 0; rf_path < 2; rf_path++) {
1730
1731 /* Assign dedicated channel tx power */
1732 for (i = 0; i < 14; i++) {
1733 /* channel 1~3 use the same Tx Power Level. */
1734 if (i < 3)
1735 index = 0;
1736 /* Channel 4-8 */
1737 else if (i < 8)
1738 index = 1;
1739 /* Channel 9-14 */
1740 else
1741 index = 2;
1742
1743 /* Record A & B CCK /OFDM - 1T/2T Channel area
1744 * tx power */
1745 rtlefuse->txpwrlevel_cck[rf_path][i] =
1746 rtlefuse->eeprom_chnlarea_txpwr_cck
1747 [rf_path][index];
1748 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1749 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1750 [rf_path][index];
1751 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1752 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1753 [rf_path][index];
1754 }
1755
1756 for (i = 0; i < 14; i++) {
1757 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1758 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1759 rf_path, i,
1760 rtlefuse->txpwrlevel_cck[rf_path][i],
1761 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1762 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1763 }
1764 }
1765
1766 for (rf_path = 0; rf_path < 2; rf_path++) {
1767 for (i = 0; i < 3; i++) {
1768 /* Read Power diff limit. */
1769 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1770 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1771 }
1772 }
1773
1774 for (rf_path = 0; rf_path < 2; rf_path++) {
1775 /* Fill Pwr group */
1776 for (i = 0; i < 14; i++) {
1777 /* Chanel 1-3 */
1778 if (i < 3)
1779 index = 0;
1780 /* Channel 4-8 */
1781 else if (i < 8)
1782 index = 1;
1783 /* Channel 9-13 */
1784 else
1785 index = 2;
1786
1787 rtlefuse->pwrgroup_ht20[rf_path][i] =
1788 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1789 0xf);
1790 rtlefuse->pwrgroup_ht40[rf_path][i] =
1791 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1792 0xf0) >> 4);
1793
1794 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1795 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1796 rf_path, i,
1797 rtlefuse->pwrgroup_ht20[rf_path][i]);
1798 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1799 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1800 rf_path, i,
1801 rtlefuse->pwrgroup_ht40[rf_path][i]);
1802 }
1803 }
1804
1805 for (i = 0; i < 14; i++) {
1806 /* Read tx power difference between HT OFDM 20/40 MHZ */
1807 /* channel 1-3 */
1808 if (i < 3)
1809 index = 0;
1810 /* Channel 4-8 */
1811 else if (i < 8)
1812 index = 1;
1813 /* Channel 9-14 */
1814 else
1815 index = 2;
1816
1817 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1818 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1819 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1820 ((tempval >> 4) & 0xF);
1821
1822 /* Read OFDM<->HT tx power diff */
1823 /* Channel 1-3 */
1824 if (i < 3)
1825 index = 0;
1826 /* Channel 4-8 */
1827 else if (i < 8)
1828 index = 0x11;
1829 /* Channel 9-14 */
1830 else
1831 index = 1;
1832
1833 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1834 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1835 (tempval & 0xF);
1836 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1837 ((tempval >> 4) & 0xF);
1838
1839 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1840 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1841 }
1842
1843 rtlefuse->eeprom_regulatory = 0;
1844 if (rtlefuse->eeprom_version >= 2) {
1845 /* BIT(0)~2 */
1846 if (rtlefuse->eeprom_version >= 4)
1847 rtlefuse->eeprom_regulatory =
1848 (hwinfo[EEPROM_REGULATORY] & 0x7);
1849 else /* BIT(0) */
1850 rtlefuse->eeprom_regulatory =
1851 (hwinfo[EEPROM_REGULATORY] & 0x1);
1852 }
1853 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1854 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1855
1856 for (i = 0; i < 14; i++)
1857 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1858 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1859 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1860 for (i = 0; i < 14; i++)
1861 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1862 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1863 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1864 for (i = 0; i < 14; i++)
1865 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1866 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1867 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1868 for (i = 0; i < 14; i++)
1869 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1870 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1871 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1872
1873 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1874 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1875
1876 /* Read RF-indication and Tx Power gain
1877 * index diff of legacy to HT OFDM rate. */
1878 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1879 rtlefuse->eeprom_txpowerdiff = tempval;
1880 rtlefuse->legacy_httxpowerdiff =
1881 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1882
1883 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1884 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1885
1886 /* Get TSSI value for each path. */
1887 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1888 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1889 usvalue = hwinfo[EEPROM_TSSI_B];
1890 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1891
1892 RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1893 rtlefuse->eeprom_tssi[RF90_PATH_A],
1894 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1895
1896 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1897 /* and read ThermalMeter from EEPROM */
1898 tempval = hwinfo[EEPROM_THERMALMETER];
1899 rtlefuse->eeprom_thermalmeter = tempval;
1900 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1901 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1902
1903 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1904 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1905 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1906
1907 /* Read CrystalCap from EEPROM */
1908 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1909 rtlefuse->eeprom_crystalcap = tempval;
1910 /* CrystalCap, BIT(12)~15 */
1911 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1912
1913 /* Read IC Version && Channel Plan */
1914 /* Version ID, Channel plan */
1915 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1916 rtlefuse->txpwr_fromeprom = true;
1917 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1918 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1919
1920 /* Read Customer ID or Board Type!!! */
1921 tempval = hwinfo[EEPROM_BOARDTYPE];
1922 /* Change RF type definition */
1923 if (tempval == 0)
1924 rtlphy->rf_type = RF_2T2R;
1925 else if (tempval == 1)
1926 rtlphy->rf_type = RF_1T2R;
1927 else if (tempval == 2)
1928 rtlphy->rf_type = RF_1T2R;
1929 else if (tempval == 3)
1930 rtlphy->rf_type = RF_1T1R;
1931
1932 /* 1T2R but 1SS (1x1 receive combining) */
1933 rtlefuse->b1x1_recvcombine = false;
1934 if (rtlphy->rf_type == RF_1T2R) {
1935 tempval = rtl_read_byte(rtlpriv, 0x07);
1936 if (!(tempval & BIT(0))) {
1937 rtlefuse->b1x1_recvcombine = true;
1938 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1939 "RF_TYPE=1T2R but only 1SS\n");
1940 }
1941 }
1942 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1943 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
1944
1945 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1946 rtlefuse->eeprom_oemid);
1947
1948 /* set channel paln to world wide 13 */
1949 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1950 }
1951
1952 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1953 {
1954 struct rtl_priv *rtlpriv = rtl_priv(hw);
1955 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1956 u8 tmp_u1b = 0;
1957
1958 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1959
1960 if (tmp_u1b & BIT(4)) {
1961 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1962 rtlefuse->epromtype = EEPROM_93C46;
1963 } else {
1964 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1965 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1966 }
1967
1968 if (tmp_u1b & BIT(5)) {
1969 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1970 rtlefuse->autoload_failflag = false;
1971 _rtl92se_read_adapter_info(hw);
1972 } else {
1973 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1974 rtlefuse->autoload_failflag = true;
1975 }
1976 }
1977
1978 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1979 struct ieee80211_sta *sta)
1980 {
1981 struct rtl_priv *rtlpriv = rtl_priv(hw);
1982 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1983 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1984 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1985 u32 ratr_value;
1986 u8 ratr_index = 0;
1987 u8 nmode = mac->ht_enable;
1988 u8 mimo_ps = IEEE80211_SMPS_OFF;
1989 u16 shortgi_rate = 0;
1990 u32 tmp_ratr_value = 0;
1991 u8 curtxbw_40mhz = mac->bw_40;
1992 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1993 1 : 0;
1994 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1995 1 : 0;
1996 enum wireless_mode wirelessmode = mac->mode;
1997
1998 if (rtlhal->current_bandtype == BAND_ON_5G)
1999 ratr_value = sta->supp_rates[1] << 4;
2000 else
2001 ratr_value = sta->supp_rates[0];
2002 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2003 sta->ht_cap.mcs.rx_mask[0] << 12);
2004 switch (wirelessmode) {
2005 case WIRELESS_MODE_B:
2006 ratr_value &= 0x0000000D;
2007 break;
2008 case WIRELESS_MODE_G:
2009 ratr_value &= 0x00000FF5;
2010 break;
2011 case WIRELESS_MODE_N_24G:
2012 case WIRELESS_MODE_N_5G:
2013 nmode = 1;
2014 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2015 ratr_value &= 0x0007F005;
2016 } else {
2017 u32 ratr_mask;
2018
2019 if (get_rf_type(rtlphy) == RF_1T2R ||
2020 get_rf_type(rtlphy) == RF_1T1R) {
2021 if (curtxbw_40mhz)
2022 ratr_mask = 0x000ff015;
2023 else
2024 ratr_mask = 0x000ff005;
2025 } else {
2026 if (curtxbw_40mhz)
2027 ratr_mask = 0x0f0ff015;
2028 else
2029 ratr_mask = 0x0f0ff005;
2030 }
2031
2032 ratr_value &= ratr_mask;
2033 }
2034 break;
2035 default:
2036 if (rtlphy->rf_type == RF_1T2R)
2037 ratr_value &= 0x000ff0ff;
2038 else
2039 ratr_value &= 0x0f0ff0ff;
2040
2041 break;
2042 }
2043
2044 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2045 ratr_value &= 0x0FFFFFFF;
2046 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2047 ratr_value &= 0x0FFFFFF0;
2048
2049 if (nmode && ((curtxbw_40mhz &&
2050 curshortgi_40mhz) || (!curtxbw_40mhz &&
2051 curshortgi_20mhz))) {
2052
2053 ratr_value |= 0x10000000;
2054 tmp_ratr_value = (ratr_value >> 12);
2055
2056 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2057 if ((1 << shortgi_rate) & tmp_ratr_value)
2058 break;
2059 }
2060
2061 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2062 (shortgi_rate << 4) | (shortgi_rate);
2063
2064 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2065 }
2066
2067 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2068 if (ratr_value & 0xfffff000)
2069 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2070 else
2071 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2072
2073 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2074 rtl_read_dword(rtlpriv, ARFR0));
2075 }
2076
2077 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2078 struct ieee80211_sta *sta,
2079 u8 rssi_level)
2080 {
2081 struct rtl_priv *rtlpriv = rtl_priv(hw);
2082 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2083 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2084 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2085 struct rtl_sta_info *sta_entry = NULL;
2086 u32 ratr_bitmap;
2087 u8 ratr_index = 0;
2088 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2089 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2090 1 : 0;
2091 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2092 1 : 0;
2093 enum wireless_mode wirelessmode = 0;
2094 bool shortgi = false;
2095 u32 ratr_value = 0;
2096 u8 shortgi_rate = 0;
2097 u32 mask = 0;
2098 u32 band = 0;
2099 bool bmulticast = false;
2100 u8 macid = 0;
2101 u8 mimo_ps = IEEE80211_SMPS_OFF;
2102
2103 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2104 wirelessmode = sta_entry->wireless_mode;
2105 if (mac->opmode == NL80211_IFTYPE_STATION)
2106 curtxbw_40mhz = mac->bw_40;
2107 else if (mac->opmode == NL80211_IFTYPE_AP ||
2108 mac->opmode == NL80211_IFTYPE_ADHOC)
2109 macid = sta->aid + 1;
2110
2111 if (rtlhal->current_bandtype == BAND_ON_5G)
2112 ratr_bitmap = sta->supp_rates[1] << 4;
2113 else
2114 ratr_bitmap = sta->supp_rates[0];
2115 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2116 sta->ht_cap.mcs.rx_mask[0] << 12);
2117 switch (wirelessmode) {
2118 case WIRELESS_MODE_B:
2119 band |= WIRELESS_11B;
2120 ratr_index = RATR_INX_WIRELESS_B;
2121 if (ratr_bitmap & 0x0000000c)
2122 ratr_bitmap &= 0x0000000d;
2123 else
2124 ratr_bitmap &= 0x0000000f;
2125 break;
2126 case WIRELESS_MODE_G:
2127 band |= (WIRELESS_11G | WIRELESS_11B);
2128 ratr_index = RATR_INX_WIRELESS_GB;
2129
2130 if (rssi_level == 1)
2131 ratr_bitmap &= 0x00000f00;
2132 else if (rssi_level == 2)
2133 ratr_bitmap &= 0x00000ff0;
2134 else
2135 ratr_bitmap &= 0x00000ff5;
2136 break;
2137 case WIRELESS_MODE_A:
2138 band |= WIRELESS_11A;
2139 ratr_index = RATR_INX_WIRELESS_A;
2140 ratr_bitmap &= 0x00000ff0;
2141 break;
2142 case WIRELESS_MODE_N_24G:
2143 case WIRELESS_MODE_N_5G:
2144 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2145 ratr_index = RATR_INX_WIRELESS_NGB;
2146
2147 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2148 if (rssi_level == 1)
2149 ratr_bitmap &= 0x00070000;
2150 else if (rssi_level == 2)
2151 ratr_bitmap &= 0x0007f000;
2152 else
2153 ratr_bitmap &= 0x0007f005;
2154 } else {
2155 if (rtlphy->rf_type == RF_1T2R ||
2156 rtlphy->rf_type == RF_1T1R) {
2157 if (rssi_level == 1) {
2158 ratr_bitmap &= 0x000f0000;
2159 } else if (rssi_level == 3) {
2160 ratr_bitmap &= 0x000fc000;
2161 } else if (rssi_level == 5) {
2162 ratr_bitmap &= 0x000ff000;
2163 } else {
2164 if (curtxbw_40mhz)
2165 ratr_bitmap &= 0x000ff015;
2166 else
2167 ratr_bitmap &= 0x000ff005;
2168 }
2169 } else {
2170 if (rssi_level == 1) {
2171 ratr_bitmap &= 0x0f8f0000;
2172 } else if (rssi_level == 3) {
2173 ratr_bitmap &= 0x0f8fc000;
2174 } else if (rssi_level == 5) {
2175 ratr_bitmap &= 0x0f8ff000;
2176 } else {
2177 if (curtxbw_40mhz)
2178 ratr_bitmap &= 0x0f8ff015;
2179 else
2180 ratr_bitmap &= 0x0f8ff005;
2181 }
2182 }
2183 }
2184
2185 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2186 (!curtxbw_40mhz && curshortgi_20mhz)) {
2187 if (macid == 0)
2188 shortgi = true;
2189 else if (macid == 1)
2190 shortgi = false;
2191 }
2192 break;
2193 default:
2194 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2195 ratr_index = RATR_INX_WIRELESS_NGB;
2196
2197 if (rtlphy->rf_type == RF_1T2R)
2198 ratr_bitmap &= 0x000ff0ff;
2199 else
2200 ratr_bitmap &= 0x0f8ff0ff;
2201 break;
2202 }
2203
2204 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2205 ratr_bitmap &= 0x0FFFFFFF;
2206 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2207 ratr_bitmap &= 0x0FFFFFF0;
2208
2209 if (shortgi) {
2210 ratr_bitmap |= 0x10000000;
2211 /* Get MAX MCS available. */
2212 ratr_value = (ratr_bitmap >> 12);
2213 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2214 if ((1 << shortgi_rate) & ratr_value)
2215 break;
2216 }
2217
2218 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2219 (shortgi_rate << 4) | (shortgi_rate);
2220 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2221 }
2222
2223 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2224
2225 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2226 mask, ratr_bitmap);
2227 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2228 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2229
2230 if (macid != 0)
2231 sta_entry->ratr_index = ratr_index;
2232 }
2233
2234 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2235 struct ieee80211_sta *sta, u8 rssi_level)
2236 {
2237 struct rtl_priv *rtlpriv = rtl_priv(hw);
2238
2239 if (rtlpriv->dm.useramask)
2240 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2241 else
2242 rtl92se_update_hal_rate_table(hw, sta);
2243 }
2244
2245 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2246 {
2247 struct rtl_priv *rtlpriv = rtl_priv(hw);
2248 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2249 u16 sifs_timer;
2250
2251 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2252 &mac->slot_time);
2253 sifs_timer = 0x0e0e;
2254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2255
2256 }
2257
2258 /* this ifunction is for RFKILL, it's different with windows,
2259 * because UI will disable wireless when GPIO Radio Off.
2260 * And here we not check or Disable/Enable ASPM like windows*/
2261 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2262 {
2263 struct rtl_priv *rtlpriv = rtl_priv(hw);
2264 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2265 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2266 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2267 unsigned long flag = 0;
2268 bool actuallyset = false;
2269 bool turnonbypowerdomain = false;
2270
2271 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2272 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2273 return false;
2274
2275 if (ppsc->swrf_processing)
2276 return false;
2277
2278 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2279 if (ppsc->rfchange_inprogress) {
2280 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2281 return false;
2282 } else {
2283 ppsc->rfchange_inprogress = true;
2284 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2285 }
2286
2287 /* cur_rfstate = ppsc->rfpwr_state;*/
2288
2289 /* because after _rtl92s_phy_set_rfhalt, all power
2290 * closed, so we must open some power for GPIO check,
2291 * or we will always check GPIO RFOFF here,
2292 * And we should close power after GPIO check */
2293 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2294 _rtl92se_power_domain_init(hw);
2295 turnonbypowerdomain = true;
2296 }
2297
2298 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2299
2300 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2301 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2302 "RFKILL-HW Radio ON, RF ON\n");
2303
2304 rfpwr_toset = ERFON;
2305 ppsc->hwradiooff = false;
2306 actuallyset = true;
2307 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2308 RT_TRACE(rtlpriv, COMP_RF,
2309 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2310
2311 rfpwr_toset = ERFOFF;
2312 ppsc->hwradiooff = true;
2313 actuallyset = true;
2314 }
2315
2316 if (actuallyset) {
2317 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2318 ppsc->rfchange_inprogress = false;
2319 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2320
2321 /* this not include ifconfig wlan0 down case */
2322 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2323 } else {
2324 /* because power_domain_init may be happen when
2325 * _rtl92s_phy_set_rfhalt, this will open some powers
2326 * and cause current increasing about 40 mA for ips,
2327 * rfoff and ifconfig down, so we set
2328 * _rtl92s_phy_set_rfhalt again here */
2329 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2330 turnonbypowerdomain) {
2331 _rtl92s_phy_set_rfhalt(hw);
2332 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2333 }
2334
2335 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2336 ppsc->rfchange_inprogress = false;
2337 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2338 }
2339
2340 *valid = 1;
2341 return !ppsc->hwradiooff;
2342
2343 }
2344
2345 /* Is_wepkey just used for WEP used as group & pairwise key
2346 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2347 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2348 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2349 {
2350 struct rtl_priv *rtlpriv = rtl_priv(hw);
2351 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2352 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2353 u8 *macaddr = p_macaddr;
2354
2355 u32 entry_id = 0;
2356 bool is_pairwise = false;
2357
2358 static u8 cam_const_addr[4][6] = {
2359 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2360 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2361 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2362 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2363 };
2364 static u8 cam_const_broad[] = {
2365 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2366 };
2367
2368 if (clear_all) {
2369 u8 idx = 0;
2370 u8 cam_offset = 0;
2371 u8 clear_number = 5;
2372
2373 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2374
2375 for (idx = 0; idx < clear_number; idx++) {
2376 rtl_cam_mark_invalid(hw, cam_offset + idx);
2377 rtl_cam_empty_entry(hw, cam_offset + idx);
2378
2379 if (idx < 5) {
2380 memset(rtlpriv->sec.key_buf[idx], 0,
2381 MAX_KEY_LEN);
2382 rtlpriv->sec.key_len[idx] = 0;
2383 }
2384 }
2385
2386 } else {
2387 switch (enc_algo) {
2388 case WEP40_ENCRYPTION:
2389 enc_algo = CAM_WEP40;
2390 break;
2391 case WEP104_ENCRYPTION:
2392 enc_algo = CAM_WEP104;
2393 break;
2394 case TKIP_ENCRYPTION:
2395 enc_algo = CAM_TKIP;
2396 break;
2397 case AESCCMP_ENCRYPTION:
2398 enc_algo = CAM_AES;
2399 break;
2400 default:
2401 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2402 "switch case not processed\n");
2403 enc_algo = CAM_TKIP;
2404 break;
2405 }
2406
2407 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2408 macaddr = cam_const_addr[key_index];
2409 entry_id = key_index;
2410 } else {
2411 if (is_group) {
2412 macaddr = cam_const_broad;
2413 entry_id = key_index;
2414 } else {
2415 if (mac->opmode == NL80211_IFTYPE_AP) {
2416 entry_id = rtl_cam_get_free_entry(hw,
2417 p_macaddr);
2418 if (entry_id >= TOTAL_CAM_ENTRY) {
2419 RT_TRACE(rtlpriv,
2420 COMP_SEC, DBG_EMERG,
2421 "Can not find free hw security cam entry\n");
2422 return;
2423 }
2424 } else {
2425 entry_id = CAM_PAIRWISE_KEY_POSITION;
2426 }
2427
2428 key_index = PAIRWISE_KEYIDX;
2429 is_pairwise = true;
2430 }
2431 }
2432
2433 if (rtlpriv->sec.key_len[key_index] == 0) {
2434 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2435 "delete one entry, entry_id is %d\n",
2436 entry_id);
2437 if (mac->opmode == NL80211_IFTYPE_AP)
2438 rtl_cam_del_entry(hw, p_macaddr);
2439 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2440 } else {
2441 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2442 "The insert KEY length is %d\n",
2443 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2444 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2445 "The insert KEY is %x %x\n",
2446 rtlpriv->sec.key_buf[0][0],
2447 rtlpriv->sec.key_buf[0][1]);
2448
2449 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2450 "add one entry\n");
2451 if (is_pairwise) {
2452 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2453 "Pairwise Key content",
2454 rtlpriv->sec.pairwise_key,
2455 rtlpriv->sec.
2456 key_len[PAIRWISE_KEYIDX]);
2457
2458 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2459 "set Pairwise key\n");
2460
2461 rtl_cam_add_one_entry(hw, macaddr, key_index,
2462 entry_id, enc_algo,
2463 CAM_CONFIG_NO_USEDK,
2464 rtlpriv->sec.key_buf[key_index]);
2465 } else {
2466 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2467 "set group key\n");
2468
2469 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2470 rtl_cam_add_one_entry(hw,
2471 rtlefuse->dev_addr,
2472 PAIRWISE_KEYIDX,
2473 CAM_PAIRWISE_KEY_POSITION,
2474 enc_algo, CAM_CONFIG_NO_USEDK,
2475 rtlpriv->sec.key_buf[entry_id]);
2476 }
2477
2478 rtl_cam_add_one_entry(hw, macaddr, key_index,
2479 entry_id, enc_algo,
2480 CAM_CONFIG_NO_USEDK,
2481 rtlpriv->sec.key_buf[entry_id]);
2482 }
2483
2484 }
2485 }
2486 }
2487
2488 void rtl92se_suspend(struct ieee80211_hw *hw)
2489 {
2490 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2491
2492 rtlpci->up_first_time = true;
2493 }
2494
2495 void rtl92se_resume(struct ieee80211_hw *hw)
2496 {
2497 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2498 u32 val;
2499
2500 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2501 if ((val & 0x0000ff00) != 0)
2502 pci_write_config_dword(rtlpci->pdev, 0x40,
2503 val & 0xffff00ff);
2504 }
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