1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
45 void rtl92se_get_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
47 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
48 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
49 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
53 *((u32
*) (val
)) = rtlpci
->receive_config
;
56 case HW_VAR_RF_STATE
: {
57 *((enum rf_pwrstate
*)(val
)) = ppsc
->rfpwr_state
;
60 case HW_VAR_FW_PSMODE_STATUS
: {
61 *((bool *) (val
)) = ppsc
->fw_current_inpsmode
;
64 case HW_VAR_CORRECT_TSF
: {
66 u32
*ptsf_low
= (u32
*)&tsf
;
67 u32
*ptsf_high
= ((u32
*)&tsf
) + 1;
69 *ptsf_high
= rtl_read_dword(rtlpriv
, (TSFR
+ 4));
70 *ptsf_low
= rtl_read_dword(rtlpriv
, TSFR
);
72 *((u64
*) (val
)) = tsf
;
77 *((bool *)(val
)) = rtlpriv
->dm
.current_mrc_switch
;
81 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
82 "switch case not processed\n");
88 void rtl92se_set_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
90 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
91 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
92 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
93 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
94 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
95 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
98 case HW_VAR_ETHER_ADDR
:{
99 rtl_write_dword(rtlpriv
, IDR0
, ((u32
*)(val
))[0]);
100 rtl_write_word(rtlpriv
, IDR4
, ((u16
*)(val
+ 4))[0]);
103 case HW_VAR_BASIC_RATE
:{
104 u16 rate_cfg
= ((u16
*) val
)[0];
107 if (rtlhal
->version
== VERSION_8192S_ACUT
)
108 rate_cfg
= rate_cfg
& 0x150;
110 rate_cfg
= rate_cfg
& 0x15f;
114 rtl_write_byte(rtlpriv
, RRSR
, rate_cfg
& 0xff);
115 rtl_write_byte(rtlpriv
, RRSR
+ 1,
116 (rate_cfg
>> 8) & 0xff);
118 while (rate_cfg
> 0x1) {
119 rate_cfg
= (rate_cfg
>> 1);
122 rtl_write_byte(rtlpriv
, INIRTSMCS_SEL
, rate_index
);
127 rtl_write_dword(rtlpriv
, BSSIDR
, ((u32
*)(val
))[0]);
128 rtl_write_word(rtlpriv
, BSSIDR
+ 4,
129 ((u16
*)(val
+ 4))[0]);
133 rtl_write_byte(rtlpriv
, SIFS_OFDM
, val
[0]);
134 rtl_write_byte(rtlpriv
, SIFS_OFDM
+ 1, val
[1]);
137 case HW_VAR_SLOT_TIME
:{
140 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
141 "HW_VAR_SLOT_TIME %x\n", val
[0]);
143 rtl_write_byte(rtlpriv
, SLOT_TIME
, val
[0]);
145 for (e_aci
= 0; e_aci
< AC_MAX
; e_aci
++) {
146 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
152 case HW_VAR_ACK_PREAMBLE
:{
154 u8 short_preamble
= (bool) (*val
);
155 reg_tmp
= (mac
->cur_40_prime_sc
) << 5;
159 rtl_write_byte(rtlpriv
, RRSR
+ 2, reg_tmp
);
162 case HW_VAR_AMPDU_MIN_SPACE
:{
163 u8 min_spacing_to_set
;
166 min_spacing_to_set
= *val
;
167 if (min_spacing_to_set
<= 7) {
168 if (rtlpriv
->sec
.pairwise_enc_algorithm
==
174 if (min_spacing_to_set
< sec_min_space
)
175 min_spacing_to_set
= sec_min_space
;
176 if (min_spacing_to_set
> 5)
177 min_spacing_to_set
= 5;
180 ((mac
->min_space_cfg
& 0xf8) |
183 *val
= min_spacing_to_set
;
185 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
189 rtl_write_byte(rtlpriv
, AMPDU_MIN_SPACE
,
194 case HW_VAR_SHORTGI_DENSITY
:{
197 density_to_set
= *val
;
198 mac
->min_space_cfg
= rtlpriv
->rtlhal
.minspace_cfg
;
199 mac
->min_space_cfg
|= (density_to_set
<< 3);
201 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
205 rtl_write_byte(rtlpriv
, AMPDU_MIN_SPACE
,
210 case HW_VAR_AMPDU_FACTOR
:{
213 u8 factorlevel
[18] = {
214 2, 4, 4, 7, 7, 13, 13,
220 if (factor_toset
<= 3) {
221 factor_toset
= (1 << (factor_toset
+ 2));
222 if (factor_toset
> 0xf)
225 for (index
= 0; index
< 17; index
++) {
226 if (factorlevel
[index
] > factor_toset
)
231 for (index
= 0; index
< 8; index
++) {
232 regtoset
= ((factorlevel
[index
* 2]) |
235 rtl_write_byte(rtlpriv
,
236 AGGLEN_LMT_L
+ index
,
240 regtoset
= ((factorlevel
[16]) |
241 (factorlevel
[17] << 4));
242 rtl_write_byte(rtlpriv
, AGGLEN_LMT_H
, regtoset
);
244 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
250 case HW_VAR_AC_PARAM
:{
252 rtl92s_dm_init_edca_turbo(hw
);
254 if (rtlpci
->acm_method
!= eAcmWay2_SW
)
255 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
260 case HW_VAR_ACM_CTRL
:{
262 union aci_aifsn
*p_aci_aifsn
= (union aci_aifsn
*)(&(
264 u8 acm
= p_aci_aifsn
->f
.acm
;
265 u8 acm_ctrl
= rtl_read_byte(rtlpriv
, AcmHwCtrl
);
267 acm_ctrl
= acm_ctrl
| ((rtlpci
->acm_method
== 2) ?
273 acm_ctrl
|= AcmHw_BeqEn
;
276 acm_ctrl
|= AcmHw_ViqEn
;
279 acm_ctrl
|= AcmHw_VoqEn
;
282 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
290 acm_ctrl
&= (~AcmHw_BeqEn
);
293 acm_ctrl
&= (~AcmHw_ViqEn
);
296 acm_ctrl
&= (~AcmHw_BeqEn
);
299 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
300 "switch case not processed\n");
305 RT_TRACE(rtlpriv
, COMP_QOS
, DBG_TRACE
,
306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl
);
307 rtl_write_byte(rtlpriv
, AcmHwCtrl
, acm_ctrl
);
311 rtl_write_dword(rtlpriv
, RCR
, ((u32
*) (val
))[0]);
312 rtlpci
->receive_config
= ((u32
*) (val
))[0];
315 case HW_VAR_RETRY_LIMIT
:{
316 u8 retry_limit
= val
[0];
318 rtl_write_word(rtlpriv
, RETRY_LIMIT
,
319 retry_limit
<< RETRY_LIMIT_SHORT_SHIFT
|
320 retry_limit
<< RETRY_LIMIT_LONG_SHIFT
);
323 case HW_VAR_DUAL_TSF_RST
: {
326 case HW_VAR_EFUSE_BYTES
: {
327 rtlefuse
->efuse_usedbytes
= *((u16
*) val
);
330 case HW_VAR_EFUSE_USAGE
: {
331 rtlefuse
->efuse_usedpercentage
= *val
;
334 case HW_VAR_IO_CMD
: {
337 case HW_VAR_WPA_CONFIG
: {
338 rtl_write_byte(rtlpriv
, REG_SECR
, *val
);
341 case HW_VAR_SET_RPWM
:{
344 case HW_VAR_H2C_FW_PWRMODE
:{
347 case HW_VAR_FW_PSMODE_STATUS
: {
348 ppsc
->fw_current_inpsmode
= *((bool *) val
);
351 case HW_VAR_H2C_FW_JOINBSSRPT
:{
357 case HW_VAR_CORRECT_TSF
:{
361 bool bmrc_toset
= *((bool *)val
);
365 rtl_set_bbreg(hw
, ROFDM0_TRXPATHENABLE
,
367 u1bdata
= (u8
)rtl_get_bbreg(hw
,
368 ROFDM1_TRXPATHENABLE
,
370 rtl_set_bbreg(hw
, ROFDM1_TRXPATHENABLE
,
372 ((u1bdata
& 0xf0) | 0x03));
373 u1bdata
= (u8
)rtl_get_bbreg(hw
,
374 ROFDM0_TRXPATHENABLE
,
376 rtl_set_bbreg(hw
, ROFDM0_TRXPATHENABLE
,
380 /* Update current settings. */
381 rtlpriv
->dm
.current_mrc_switch
= bmrc_toset
;
383 rtl_set_bbreg(hw
, ROFDM0_TRXPATHENABLE
,
385 u1bdata
= (u8
)rtl_get_bbreg(hw
,
386 ROFDM1_TRXPATHENABLE
,
388 rtl_set_bbreg(hw
, ROFDM1_TRXPATHENABLE
,
390 ((u1bdata
& 0xf0) | 0x01));
391 u1bdata
= (u8
)rtl_get_bbreg(hw
,
392 ROFDM0_TRXPATHENABLE
,
394 rtl_set_bbreg(hw
, ROFDM0_TRXPATHENABLE
,
395 MASKBYTE1
, (u1bdata
& 0xfb));
397 /* Update current settings. */
398 rtlpriv
->dm
.current_mrc_switch
= bmrc_toset
;
404 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
405 "switch case not processed\n");
411 void rtl92se_enable_hw_security_config(struct ieee80211_hw
*hw
)
413 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
414 u8 sec_reg_value
= 0x0;
416 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
417 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
418 rtlpriv
->sec
.pairwise_enc_algorithm
,
419 rtlpriv
->sec
.group_enc_algorithm
);
421 if (rtlpriv
->cfg
->mod_params
->sw_crypto
|| rtlpriv
->sec
.use_sw_sec
) {
422 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
423 "not open hw encryption\n");
427 sec_reg_value
= SCR_TXENCENABLE
| SCR_RXENCENABLE
;
429 if (rtlpriv
->sec
.use_defaultkey
) {
430 sec_reg_value
|= SCR_TXUSEDK
;
431 sec_reg_value
|= SCR_RXUSEDK
;
434 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
, "The SECR-value %x\n",
437 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_WPA_CONFIG
, &sec_reg_value
);
441 static u8
_rtl92ce_halset_sysclk(struct ieee80211_hw
*hw
, u8 data
)
443 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
445 bool bresult
= false;
448 rtl_write_byte(rtlpriv
, SYS_CLKR
+ 1, data
);
450 /* Wait the MAC synchronized. */
453 /* Check if it is set ready. */
454 tmpvalue
= rtl_read_byte(rtlpriv
, SYS_CLKR
+ 1);
455 bresult
= ((tmpvalue
& BIT(7)) == (data
& BIT(7)));
457 if ((data
& (BIT(6) | BIT(7))) == false) {
464 tmpvalue
= rtl_read_byte(rtlpriv
, SYS_CLKR
+ 1);
465 if ((tmpvalue
& BIT(6)))
468 pr_err("wait for BIT(6) return value %x\n", tmpvalue
);
484 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw
*hw
)
486 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
489 /* The following config GPIO function */
490 rtl_write_byte(rtlpriv
, MAC_PINMUX_CFG
, (GPIOMUX_EN
| GPIOSEL_GPIO
));
491 u1tmp
= rtl_read_byte(rtlpriv
, GPIO_IO_SEL
);
493 /* config GPIO3 to input */
494 u1tmp
&= HAL_8192S_HW_GPIO_OFF_MASK
;
495 rtl_write_byte(rtlpriv
, GPIO_IO_SEL
, u1tmp
);
499 static u8
_rtl92se_rf_onoff_detect(struct ieee80211_hw
*hw
)
501 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
505 /* The following config GPIO function */
506 rtl_write_byte(rtlpriv
, MAC_PINMUX_CFG
, (GPIOMUX_EN
| GPIOSEL_GPIO
));
507 u1tmp
= rtl_read_byte(rtlpriv
, GPIO_IO_SEL
);
509 /* config GPIO3 to input */
510 u1tmp
&= HAL_8192S_HW_GPIO_OFF_MASK
;
511 rtl_write_byte(rtlpriv
, GPIO_IO_SEL
, u1tmp
);
513 /* On some of the platform, driver cannot read correct
514 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
518 u1tmp
= rtl_read_byte(rtlpriv
, GPIO_IN_SE
);
519 retval
= (u1tmp
& HAL_8192S_HW_GPIO_OFF_BIT
) ? ERFON
: ERFOFF
;
524 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw
*hw
)
526 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
527 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
528 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
535 if (rtlpci
->first_init
) {
536 /* Reset PCIE Digital */
537 tmpu1b
= rtl_read_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1);
539 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, tmpu1b
);
541 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, tmpu1b
| BIT(0));
544 /* Switch to SW IO control */
545 tmpu1b
= rtl_read_byte(rtlpriv
, (SYS_CLKR
+ 1));
546 if (tmpu1b
& BIT(7)) {
547 tmpu1b
&= ~(BIT(6) | BIT(7));
549 /* Set failed, return to prevent hang. */
550 if (!_rtl92ce_halset_sysclk(hw
, tmpu1b
))
554 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
, 0x0);
556 rtl_write_byte(rtlpriv
, LDOA15_CTRL
, 0x34);
559 /* Clear FW RPWM for FW control LPS.*/
560 rtl_write_byte(rtlpriv
, RPWM
, 0x0);
562 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
563 tmpu1b
= rtl_read_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1);
565 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, tmpu1b
);
566 /* wait for BIT 10/11/15 to pull high automatically!! */
569 rtl_write_byte(rtlpriv
, CMDR
, 0);
570 rtl_write_byte(rtlpriv
, TCR
, 0);
572 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
573 tmpu1b
= rtl_read_byte(rtlpriv
, 0x562);
575 rtl_write_byte(rtlpriv
, 0x562, tmpu1b
);
577 rtl_write_byte(rtlpriv
, 0x562, tmpu1b
);
579 /* Enable AFE clock source */
580 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_XTAL_CTRL
);
581 rtl_write_byte(rtlpriv
, AFE_XTAL_CTRL
, (tmpu1b
| 0x01));
584 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_XTAL_CTRL
+ 1);
585 rtl_write_byte(rtlpriv
, AFE_XTAL_CTRL
+ 1, (tmpu1b
& 0xfb));
587 /* Enable AFE Macro Block's Bandgap */
588 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_MISC
);
589 rtl_write_byte(rtlpriv
, AFE_MISC
, (tmpu1b
| BIT(0)));
592 /* Enable AFE Mbias */
593 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_MISC
);
594 rtl_write_byte(rtlpriv
, AFE_MISC
, (tmpu1b
| 0x02));
597 /* Enable LDOA15 block */
598 tmpu1b
= rtl_read_byte(rtlpriv
, LDOA15_CTRL
);
599 rtl_write_byte(rtlpriv
, LDOA15_CTRL
, (tmpu1b
| BIT(0)));
601 /* Set Digital Vdd to Retention isolation Path. */
602 tmpu2b
= rtl_read_word(rtlpriv
, REG_SYS_ISO_CTRL
);
603 rtl_write_word(rtlpriv
, REG_SYS_ISO_CTRL
, (tmpu2b
| BIT(11)));
605 /* For warm reboot NIC disappera bug. */
606 tmpu2b
= rtl_read_word(rtlpriv
, REG_SYS_FUNC_EN
);
607 rtl_write_word(rtlpriv
, REG_SYS_FUNC_EN
, (tmpu2b
| BIT(13)));
609 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
+ 1, 0x68);
611 /* Enable AFE PLL Macro Block */
612 /* We need to delay 100u before enabling PLL. */
614 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_PLL_CTRL
);
615 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
, (tmpu1b
| BIT(0) | BIT(4)));
617 /* for divider reset */
619 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
, (tmpu1b
| BIT(0) |
622 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
, (tmpu1b
| BIT(0) | BIT(4)));
625 /* Enable MAC 80MHZ clock */
626 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_PLL_CTRL
+ 1);
627 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
+ 1, (tmpu1b
| BIT(0)));
630 /* Release isolation AFE PLL & MD */
631 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
, 0xA6);
633 /* Enable MAC clock */
634 tmpu2b
= rtl_read_word(rtlpriv
, SYS_CLKR
);
635 rtl_write_word(rtlpriv
, SYS_CLKR
, (tmpu2b
| BIT(12) | BIT(11)));
637 /* Enable Core digital and enable IOREG R/W */
638 tmpu2b
= rtl_read_word(rtlpriv
, REG_SYS_FUNC_EN
);
639 rtl_write_word(rtlpriv
, REG_SYS_FUNC_EN
, (tmpu2b
| BIT(11)));
641 tmpu1b
= rtl_read_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1);
642 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, tmpu1b
& ~(BIT(7)));
645 rtl_write_word(rtlpriv
, REG_SYS_FUNC_EN
, (tmpu2b
| BIT(11) | BIT(15)));
647 /* Switch the control path. */
648 tmpu2b
= rtl_read_word(rtlpriv
, SYS_CLKR
);
649 rtl_write_word(rtlpriv
, SYS_CLKR
, (tmpu2b
& (~BIT(2))));
651 tmpu1b
= rtl_read_byte(rtlpriv
, (SYS_CLKR
+ 1));
652 tmpu1b
= ((tmpu1b
| BIT(7)) & (~BIT(6)));
653 if (!_rtl92ce_halset_sysclk(hw
, tmpu1b
))
654 return; /* Set failed, return to prevent hang. */
656 rtl_write_word(rtlpriv
, CMDR
, 0x07FC);
658 /* MH We must enable the section of code to prevent load IMEM fail. */
659 /* Load MAC register from WMAc temporarily We simulate macreg. */
660 /* txt HW will provide MAC txt later */
661 rtl_write_byte(rtlpriv
, 0x6, 0x30);
662 rtl_write_byte(rtlpriv
, 0x49, 0xf0);
664 rtl_write_byte(rtlpriv
, 0x4b, 0x81);
666 rtl_write_byte(rtlpriv
, 0xb5, 0x21);
668 rtl_write_byte(rtlpriv
, 0xdc, 0xff);
669 rtl_write_byte(rtlpriv
, 0xdd, 0xff);
670 rtl_write_byte(rtlpriv
, 0xde, 0xff);
671 rtl_write_byte(rtlpriv
, 0xdf, 0xff);
673 rtl_write_byte(rtlpriv
, 0x11a, 0x00);
674 rtl_write_byte(rtlpriv
, 0x11b, 0x00);
676 for (i
= 0; i
< 32; i
++)
677 rtl_write_byte(rtlpriv
, INIMCS_SEL
+ i
, 0x1b);
679 rtl_write_byte(rtlpriv
, 0x236, 0xff);
681 rtl_write_byte(rtlpriv
, 0x503, 0x22);
683 if (ppsc
->support_aspm
&& !ppsc
->support_backdoor
)
684 rtl_write_byte(rtlpriv
, 0x560, 0x40);
686 rtl_write_byte(rtlpriv
, 0x560, 0x00);
688 rtl_write_byte(rtlpriv
, DBG_PORT
, 0x91);
690 /* Set RX Desc Address */
691 rtl_write_dword(rtlpriv
, RDQDA
, rtlpci
->rx_ring
[RX_MPDU_QUEUE
].dma
);
692 rtl_write_dword(rtlpriv
, RCDA
, rtlpci
->rx_ring
[RX_CMD_QUEUE
].dma
);
694 /* Set TX Desc Address */
695 rtl_write_dword(rtlpriv
, TBKDA
, rtlpci
->tx_ring
[BK_QUEUE
].dma
);
696 rtl_write_dword(rtlpriv
, TBEDA
, rtlpci
->tx_ring
[BE_QUEUE
].dma
);
697 rtl_write_dword(rtlpriv
, TVIDA
, rtlpci
->tx_ring
[VI_QUEUE
].dma
);
698 rtl_write_dword(rtlpriv
, TVODA
, rtlpci
->tx_ring
[VO_QUEUE
].dma
);
699 rtl_write_dword(rtlpriv
, TBDA
, rtlpci
->tx_ring
[BEACON_QUEUE
].dma
);
700 rtl_write_dword(rtlpriv
, TCDA
, rtlpci
->tx_ring
[TXCMD_QUEUE
].dma
);
701 rtl_write_dword(rtlpriv
, TMDA
, rtlpci
->tx_ring
[MGNT_QUEUE
].dma
);
702 rtl_write_dword(rtlpriv
, THPDA
, rtlpci
->tx_ring
[HIGH_QUEUE
].dma
);
703 rtl_write_dword(rtlpriv
, HDA
, rtlpci
->tx_ring
[HCCA_QUEUE
].dma
);
705 rtl_write_word(rtlpriv
, CMDR
, 0x37FC);
707 /* To make sure that TxDMA can ready to download FW. */
708 /* We should reset TxDMA if IMEM RPT was not ready. */
710 tmpu1b
= rtl_read_byte(rtlpriv
, TCR
);
711 if ((tmpu1b
& TXDMA_INIT_VALUE
) == TXDMA_INIT_VALUE
)
715 } while (pollingcnt
--);
717 if (pollingcnt
<= 0) {
718 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
719 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
721 tmpu1b
= rtl_read_byte(rtlpriv
, CMDR
);
722 rtl_write_byte(rtlpriv
, CMDR
, tmpu1b
& (~TXDMA_EN
));
725 rtl_write_byte(rtlpriv
, CMDR
, tmpu1b
| TXDMA_EN
);
728 /* After MACIO reset,we must refresh LED state. */
729 if ((ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
) ||
730 (ppsc
->rfoff_reason
== 0)) {
731 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
732 struct rtl_led
*pLed0
= &(pcipriv
->ledctl
.sw_led0
);
733 enum rf_pwrstate rfpwr_state_toset
;
734 rfpwr_state_toset
= _rtl92se_rf_onoff_detect(hw
);
736 if (rfpwr_state_toset
== ERFON
)
737 rtl92se_sw_led_on(hw
, pLed0
);
741 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw
*hw
)
743 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
744 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
745 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
746 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
750 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
752 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
753 /* Turn on 0x40 Command register */
754 rtl_write_word(rtlpriv
, CMDR
, (BBRSTN
| BB_GLB_RSTN
|
755 SCHEDULE_EN
| MACRXEN
| MACTXEN
| DDMA_EN
| FW2HW_EN
|
756 RXDMA_EN
| TXDMA_EN
| HCI_RXDMA_EN
| HCI_TXDMA_EN
));
758 /* Set TCR TX DMA pre 2 FULL enable bit */
759 rtl_write_dword(rtlpriv
, TCR
, rtl_read_dword(rtlpriv
, TCR
) |
763 rtl_write_dword(rtlpriv
, RCR
, rtlpci
->receive_config
);
765 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
767 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
768 /* Set CCK/OFDM SIFS */
769 /* CCK SIFS shall always be 10us. */
770 rtl_write_word(rtlpriv
, SIFS_CCK
, 0x0a0a);
771 rtl_write_word(rtlpriv
, SIFS_OFDM
, 0x1010);
774 rtl_write_byte(rtlpriv
, ACK_TIMEOUT
, 0x40);
777 rtl_write_word(rtlpriv
, BCN_INTERVAL
, 100);
778 rtl_write_word(rtlpriv
, ATIMWND
, 2);
780 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
781 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
782 /* Firmware allocate now, associate with FW internal setting.!!! */
784 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
785 /* 5.3 Set driver info, we only accept PHY status now. */
786 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
787 rtl_write_byte(rtlpriv
, RXDMA
, rtl_read_byte(rtlpriv
, RXDMA
) | BIT(6));
789 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
790 /* Set RRSR to all legacy rate and HT rate
791 * CCK rate is supported by default.
792 * CCK rate will be filtered out only when associated
793 * AP does not support it.
794 * Only enable ACK rate to OFDM 24M
795 * Disable RRSR for CCK rate in A-Cut */
797 if (rtlhal
->version
== VERSION_8192S_ACUT
)
798 rtl_write_byte(rtlpriv
, RRSR
, 0xf0);
799 else if (rtlhal
->version
== VERSION_8192S_BCUT
)
800 rtl_write_byte(rtlpriv
, RRSR
, 0xff);
801 rtl_write_byte(rtlpriv
, RRSR
+ 1, 0x01);
802 rtl_write_byte(rtlpriv
, RRSR
+ 2, 0x00);
804 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
805 /* fallback to CCK rate */
806 for (i
= 0; i
< 8; i
++) {
807 /*Disable RRSR for CCK rate in A-Cut */
808 if (rtlhal
->version
== VERSION_8192S_ACUT
)
809 rtl_write_dword(rtlpriv
, ARFR0
+ i
* 4, 0x1f0ff0f0);
812 /* Different rate use different AMPDU size */
813 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
814 rtl_write_byte(rtlpriv
, AGGLEN_LMT_H
, 0x0f);
815 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
816 rtl_write_word(rtlpriv
, AGGLEN_LMT_L
, 0x7442);
817 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
818 rtl_write_word(rtlpriv
, AGGLEN_LMT_L
+ 2, 0xddd7);
819 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
820 rtl_write_word(rtlpriv
, AGGLEN_LMT_L
+ 4, 0xd772);
821 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
822 rtl_write_word(rtlpriv
, AGGLEN_LMT_L
+ 6, 0xfffd);
824 /* Set Data / Response auto rate fallack retry count */
825 rtl_write_dword(rtlpriv
, DARFRC
, 0x04010000);
826 rtl_write_dword(rtlpriv
, DARFRC
+ 4, 0x09070605);
827 rtl_write_dword(rtlpriv
, RARFRC
, 0x04010000);
828 rtl_write_dword(rtlpriv
, RARFRC
+ 4, 0x09070605);
830 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
831 /* Set all rate to support SG */
832 rtl_write_word(rtlpriv
, SG_RATE
, 0xFFFF);
834 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
835 /* Set NAV protection length */
836 rtl_write_word(rtlpriv
, NAV_PROT_LEN
, 0x0080);
837 /* CF-END Threshold */
838 rtl_write_byte(rtlpriv
, CFEND_TH
, 0xFF);
839 /* Set AMPDU minimum space */
840 rtl_write_byte(rtlpriv
, AMPDU_MIN_SPACE
, 0x07);
841 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
842 rtl_write_byte(rtlpriv
, TXOP_STALL_CTRL
, 0x00);
844 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
845 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
846 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
847 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
848 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
850 /* 14. Set driver info, we only accept PHY status now. */
851 rtl_write_byte(rtlpriv
, RXDRVINFO_SZ
, 4);
853 /* 15. For EEPROM R/W Workaround */
854 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
855 tmpu2b
= rtl_read_byte(rtlpriv
, REG_SYS_FUNC_EN
);
856 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, tmpu2b
| BIT(13));
857 tmpu2b
= rtl_read_byte(rtlpriv
, REG_SYS_ISO_CTRL
);
858 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
, tmpu2b
& (~BIT(8)));
861 /* We may R/W EFUSE in EEPROM mode */
862 if (rtlefuse
->epromtype
== EEPROM_BOOT_EFUSE
) {
865 tempval
= rtl_read_byte(rtlpriv
, REG_SYS_ISO_CTRL
+ 1);
867 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
+ 1, tempval
);
869 /* Change Program timing */
870 rtl_write_byte(rtlpriv
, REG_EFUSE_CTRL
+ 3, 0x72);
871 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "EFUSE CONFIG OK\n");
874 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "OK\n");
878 static void _rtl92se_hw_configure(struct ieee80211_hw
*hw
)
880 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
881 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
882 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
883 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
885 u8 reg_bw_opmode
= 0;
889 reg_bw_opmode
= BW_OPMODE_20MHZ
;
890 reg_rrsr
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
892 regtmp
= rtl_read_byte(rtlpriv
, INIRTSMCS_SEL
);
893 reg_rrsr
= ((reg_rrsr
& 0x000fffff) << 8) | regtmp
;
894 rtl_write_dword(rtlpriv
, INIRTSMCS_SEL
, reg_rrsr
);
895 rtl_write_byte(rtlpriv
, BW_OPMODE
, reg_bw_opmode
);
897 /* Set Retry Limit here */
898 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_RETRY_LIMIT
,
899 (u8
*)(&rtlpci
->shortretry_limit
));
901 rtl_write_byte(rtlpriv
, MLT
, 0x8f);
903 /* For Min Spacing configuration. */
904 switch (rtlphy
->rf_type
) {
907 rtlhal
->minspace_cfg
= (MAX_MSS_DENSITY_1T
<< 3);
911 rtlhal
->minspace_cfg
= (MAX_MSS_DENSITY_2T
<< 3);
914 rtl_write_byte(rtlpriv
, AMPDU_MIN_SPACE
, rtlhal
->minspace_cfg
);
917 int rtl92se_hw_init(struct ieee80211_hw
*hw
)
919 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
920 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
921 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
922 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
923 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
926 bool rtstatus
= true;
930 int wdcapra_add
[] = {
931 EDCAPARA_BE
, EDCAPARA_BK
,
932 EDCAPARA_VI
, EDCAPARA_VO
};
935 rtlpci
->being_init_adapter
= true;
937 rtlpriv
->intf_ops
->disable_aspm(hw
);
939 /* 1. MAC Initialize */
940 /* Before FW download, we have to set some MAC register */
941 _rtl92se_macconfig_before_fwdownload(hw
);
943 rtlhal
->version
= (enum version_8192s
)((rtl_read_dword(rtlpriv
,
944 PMC_FSM
) >> 16) & 0xF);
946 rtl8192se_gpiobit3_cfg_inputmode(hw
);
948 /* 2. download firmware */
949 rtstatus
= rtl92s_download_fw(hw
);
951 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
952 "Failed to download FW. Init HW without FW now... "
953 "Please copy FW into /lib/firmware/rtlwifi\n");
957 /* After FW download, we have to reset MAC register */
958 _rtl92se_macconfig_after_fwdownload(hw
);
960 /*Retrieve default FW Cmd IO map. */
961 rtlhal
->fwcmd_iomap
= rtl_read_word(rtlpriv
, LBUS_MON_ADDR
);
962 rtlhal
->fwcmd_ioparam
= rtl_read_dword(rtlpriv
, LBUS_ADDR_MASK
);
964 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
965 if (!rtl92s_phy_mac_config(hw
)) {
966 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "MAC Config failed\n");
970 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
971 /* We must set flag avoid BB/RF config period later!! */
972 rtl_write_dword(rtlpriv
, CMDR
, 0x37FC);
974 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
975 if (!rtl92s_phy_bb_config(hw
)) {
976 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_EMERG
, "BB Config failed\n");
980 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
981 /* Before initalizing RF. We can not use FW to do RF-R/W. */
983 rtlphy
->rf_mode
= RF_OP_BY_SW_3WIRE
;
987 /* H/W or S/W RF OFF before sleep. */
988 if (rtlpriv
->psc
.rfoff_reason
> RF_CHANGE_BY_PS
) {
989 u32 rfoffreason
= rtlpriv
->psc
.rfoff_reason
;
991 rtlpriv
->psc
.rfoff_reason
= RF_CHANGE_BY_INIT
;
992 rtlpriv
->psc
.rfpwr_state
= ERFON
;
993 /* FIXME: check spinlocks if this block is uncommented */
994 rtl_ps_set_rf_state(hw
, ERFOFF
, rfoffreason
);
996 /* gpio radio on/off is out of adapter start */
997 if (rtlpriv
->psc
.hwradiooff
== false) {
998 rtlpriv
->psc
.rfpwr_state
= ERFON
;
999 rtlpriv
->psc
.rfoff_reason
= 0;
1004 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1005 rtl_write_byte(rtlpriv
, AFE_XTAL_CTRL
+ 1, 0xDB);
1006 if (rtlhal
->version
== VERSION_8192S_ACUT
)
1007 rtl_write_byte(rtlpriv
, SPS1_CTRL
+ 3, 0x07);
1009 rtl_write_byte(rtlpriv
, RF_CTRL
, 0x07);
1011 if (!rtl92s_phy_rf_config(hw
)) {
1012 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "RF Config failed\n");
1016 /* After read predefined TXT, we must set BB/MAC/RF
1017 * register as our requirement */
1019 rtlphy
->rfreg_chnlval
[0] = rtl92s_phy_query_rf_reg(hw
,
1023 rtlphy
->rfreg_chnlval
[1] = rtl92s_phy_query_rf_reg(hw
,
1028 /*---- Set CCK and OFDM Block "ON"----*/
1029 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BCCKEN
, 0x1);
1030 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BOFDMEN
, 0x1);
1032 /*3 Set Hardware(Do nothing now) */
1033 _rtl92se_hw_configure(hw
);
1035 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1036 /* TX power index for different rate set. */
1037 /* Get original hw reg values */
1038 rtl92s_phy_get_hw_reg_originalvalue(hw
);
1039 /* Write correct tx power index */
1040 rtl92s_phy_set_txpower(hw
, rtlphy
->current_channel
);
1042 /* We must set MAC address after firmware download. */
1043 for (i
= 0; i
< 6; i
++)
1044 rtl_write_byte(rtlpriv
, MACIDR0
+ i
, rtlefuse
->dev_addr
[i
]);
1046 /* EEPROM R/W workaround */
1047 tmp_u1b
= rtl_read_byte(rtlpriv
, MAC_PINMUX_CFG
);
1048 rtl_write_byte(rtlpriv
, MAC_PINMUX_CFG
, tmp_u1b
& (~BIT(3)));
1050 rtl_write_byte(rtlpriv
, 0x4d, 0x0);
1052 if (hal_get_firmwareversion(rtlpriv
) >= 0x49) {
1053 tmp_byte
= rtl_read_byte(rtlpriv
, FW_RSVD_PG_CRTL
) & (~BIT(4));
1054 tmp_byte
= tmp_byte
| BIT(5);
1055 rtl_write_byte(rtlpriv
, FW_RSVD_PG_CRTL
, tmp_byte
);
1056 rtl_write_dword(rtlpriv
, TXDESC_MSK
, 0xFFFFCFFF);
1059 /* We enable high power and RA related mechanism after NIC
1061 rtl92s_phy_set_fw_cmd(hw
, FW_CMD_RA_INIT
);
1063 /* Add to prevent ASPM bug. */
1064 /* Always enable hst and NIC clock request. */
1065 rtl92s_phy_switch_ephy_parameter(hw
);
1068 * 1. Clear all H/W keys.
1069 * 2. Enable H/W encryption/decryption. */
1070 rtl_cam_reset_all_entry(hw
);
1071 secr_value
|= SCR_TXENCENABLE
;
1072 secr_value
|= SCR_RXENCENABLE
;
1073 secr_value
|= SCR_NOSKMC
;
1074 rtl_write_byte(rtlpriv
, REG_SECR
, secr_value
);
1076 for (i
= 0; i
< 4; i
++)
1077 rtl_write_dword(rtlpriv
, wdcapra_add
[i
], 0x5e4322);
1079 if (rtlphy
->rf_type
== RF_1T2R
) {
1080 bool mrc2set
= true;
1081 /* Turn on B-Path */
1082 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_MRC
, (u8
*)&mrc2set
);
1085 rtlpriv
->cfg
->ops
->led_control(hw
, LED_CTL_POWER_ON
);
1087 rtlpci
->being_init_adapter
= false;
1092 void rtl92se_set_mac_addr(struct rtl_io
*io
, const u8
*addr
)
1094 /* This is a stub. */
1097 void rtl92se_set_check_bssid(struct ieee80211_hw
*hw
, bool check_bssid
)
1099 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1100 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1101 u32 reg_rcr
= rtlpci
->receive_config
;
1103 if (rtlpriv
->psc
.rfpwr_state
!= ERFON
)
1107 reg_rcr
|= (RCR_CBSSID
);
1108 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_RCR
, (u8
*)(®_rcr
));
1109 } else if (!check_bssid
) {
1110 reg_rcr
&= (~RCR_CBSSID
);
1111 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_RCR
, (u8
*)(®_rcr
));
1116 static int _rtl92se_set_media_status(struct ieee80211_hw
*hw
,
1117 enum nl80211_iftype type
)
1119 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1120 u8 bt_msr
= rtl_read_byte(rtlpriv
, MSR
);
1122 bt_msr
&= ~MSR_LINK_MASK
;
1125 case NL80211_IFTYPE_UNSPECIFIED
:
1126 bt_msr
|= (MSR_LINK_NONE
<< MSR_LINK_SHIFT
);
1127 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1128 "Set Network type to NO LINK!\n");
1130 case NL80211_IFTYPE_ADHOC
:
1131 bt_msr
|= (MSR_LINK_ADHOC
<< MSR_LINK_SHIFT
);
1132 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1133 "Set Network type to Ad Hoc!\n");
1135 case NL80211_IFTYPE_STATION
:
1136 bt_msr
|= (MSR_LINK_MANAGED
<< MSR_LINK_SHIFT
);
1137 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1138 "Set Network type to STA!\n");
1140 case NL80211_IFTYPE_AP
:
1141 bt_msr
|= (MSR_LINK_MASTER
<< MSR_LINK_SHIFT
);
1142 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1143 "Set Network type to AP!\n");
1146 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1147 "Network type %d not supported!\n", type
);
1153 rtl_write_byte(rtlpriv
, (MSR
), bt_msr
);
1155 temp
= rtl_read_dword(rtlpriv
, TCR
);
1156 rtl_write_dword(rtlpriv
, TCR
, temp
& (~BIT(8)));
1157 rtl_write_dword(rtlpriv
, TCR
, temp
| BIT(8));
1163 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1164 int rtl92se_set_network_type(struct ieee80211_hw
*hw
, enum nl80211_iftype type
)
1166 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1168 if (_rtl92se_set_media_status(hw
, type
))
1171 if (rtlpriv
->mac80211
.link_state
== MAC80211_LINKED
) {
1172 if (type
!= NL80211_IFTYPE_AP
)
1173 rtl92se_set_check_bssid(hw
, true);
1175 rtl92se_set_check_bssid(hw
, false);
1181 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1182 void rtl92se_set_qos(struct ieee80211_hw
*hw
, int aci
)
1184 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1185 rtl92s_dm_init_edca_turbo(hw
);
1189 rtl_write_dword(rtlpriv
, EDCAPARA_BK
, 0xa44f);
1192 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1195 rtl_write_dword(rtlpriv
, EDCAPARA_VI
, 0x5e4322);
1198 rtl_write_dword(rtlpriv
, EDCAPARA_VO
, 0x2f3222);
1201 RT_ASSERT(false, "invalid aci: %d !\n", aci
);
1206 void rtl92se_enable_interrupt(struct ieee80211_hw
*hw
)
1208 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1209 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1211 rtl_write_dword(rtlpriv
, INTA_MASK
, rtlpci
->irq_mask
[0]);
1212 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1213 rtl_write_dword(rtlpriv
, INTA_MASK
+ 4, rtlpci
->irq_mask
[1] & 0x3F);
1216 void rtl92se_disable_interrupt(struct ieee80211_hw
*hw
)
1218 struct rtl_priv
*rtlpriv
;
1219 struct rtl_pci
*rtlpci
;
1221 rtlpriv
= rtl_priv(hw
);
1222 /* if firmware not available, no interrupts */
1223 if (!rtlpriv
|| !rtlpriv
->max_fw_size
)
1225 rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1226 rtl_write_dword(rtlpriv
, INTA_MASK
, 0);
1227 rtl_write_dword(rtlpriv
, INTA_MASK
+ 4, 0);
1229 synchronize_irq(rtlpci
->pdev
->irq
);
1233 static u8
_rtl92s_set_sysclk(struct ieee80211_hw
*hw
, u8 data
)
1235 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1237 bool result
= false;
1240 rtl_write_byte(rtlpriv
, SYS_CLKR
+ 1, data
);
1242 /* Wait the MAC synchronized. */
1245 /* Check if it is set ready. */
1246 tmp
= rtl_read_byte(rtlpriv
, SYS_CLKR
+ 1);
1247 result
= ((tmp
& BIT(7)) == (data
& BIT(7)));
1249 if ((data
& (BIT(6) | BIT(7))) == false) {
1255 tmp
= rtl_read_byte(rtlpriv
, SYS_CLKR
+ 1);
1260 pr_err("wait for BIT(6) return value %x\n", tmp
);
1276 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw
*hw
)
1278 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1279 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1280 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1283 if (rtlhal
->driver_going2unload
)
1284 rtl_write_byte(rtlpriv
, 0x560, 0x0);
1286 /* Power save for BB/RF */
1287 u1btmp
= rtl_read_byte(rtlpriv
, LDOV12D_CTRL
);
1289 rtl_write_byte(rtlpriv
, LDOV12D_CTRL
, u1btmp
);
1290 rtl_write_byte(rtlpriv
, SPS1_CTRL
, 0x0);
1291 rtl_write_byte(rtlpriv
, TXPAUSE
, 0xFF);
1292 rtl_write_word(rtlpriv
, CMDR
, 0x57FC);
1294 rtl_write_word(rtlpriv
, CMDR
, 0x77FC);
1295 rtl_write_byte(rtlpriv
, PHY_CCA
, 0x0);
1297 rtl_write_word(rtlpriv
, CMDR
, 0x37FC);
1299 rtl_write_word(rtlpriv
, CMDR
, 0x77FC);
1301 rtl_write_word(rtlpriv
, CMDR
, 0x57FC);
1302 rtl_write_word(rtlpriv
, CMDR
, 0x0000);
1304 if (rtlhal
->driver_going2unload
) {
1305 u1btmp
= rtl_read_byte(rtlpriv
, (REG_SYS_FUNC_EN
+ 1));
1306 u1btmp
&= ~(BIT(0));
1307 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, u1btmp
);
1310 u1btmp
= rtl_read_byte(rtlpriv
, (SYS_CLKR
+ 1));
1312 /* Add description. After switch control path. register
1313 * after page1 will be invisible. We can not do any IO
1314 * for register>0x40. After resume&MACIO reset, we need
1315 * to remember previous reg content. */
1316 if (u1btmp
& BIT(7)) {
1317 u1btmp
&= ~(BIT(6) | BIT(7));
1318 if (!_rtl92s_set_sysclk(hw
, u1btmp
)) {
1319 pr_err("Switch ctrl path fail\n");
1324 /* Power save for MAC */
1325 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
&&
1326 !rtlhal
->driver_going2unload
) {
1327 /* enable LED function */
1328 rtl_write_byte(rtlpriv
, 0x03, 0xF9);
1329 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1331 /* LED function disable. Power range is about 8mA now. */
1332 /* if write 0xF1 disconnet_pci power
1333 * ifconfig wlan0 down power are both high 35:70 */
1334 /* if write oxF9 disconnet_pci power
1335 * ifconfig wlan0 down power are both low 12:45*/
1336 rtl_write_byte(rtlpriv
, 0x03, 0xF9);
1339 rtl_write_byte(rtlpriv
, SYS_CLKR
+ 1, 0x70);
1340 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
+ 1, 0x68);
1341 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
, 0x00);
1342 rtl_write_byte(rtlpriv
, LDOA15_CTRL
, 0x34);
1343 rtl_write_byte(rtlpriv
, AFE_XTAL_CTRL
, 0x0E);
1344 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
1348 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw
*hw
)
1350 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1351 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1352 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
1353 struct rtl_led
*pLed0
= &(pcipriv
->ledctl
.sw_led0
);
1355 if (rtlpci
->up_first_time
== 1)
1358 if (rtlpriv
->psc
.rfoff_reason
== RF_CHANGE_BY_IPS
)
1359 rtl92se_sw_led_on(hw
, pLed0
);
1361 rtl92se_sw_led_off(hw
, pLed0
);
1365 static void _rtl92se_power_domain_init(struct ieee80211_hw
*hw
)
1367 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1371 rtlpriv
->psc
.pwrdomain_protect
= true;
1373 tmpu1b
= rtl_read_byte(rtlpriv
, (SYS_CLKR
+ 1));
1374 if (tmpu1b
& BIT(7)) {
1375 tmpu1b
&= ~(BIT(6) | BIT(7));
1376 if (!_rtl92s_set_sysclk(hw
, tmpu1b
)) {
1377 rtlpriv
->psc
.pwrdomain_protect
= false;
1382 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
, 0x0);
1383 rtl_write_byte(rtlpriv
, LDOA15_CTRL
, 0x34);
1385 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1386 tmpu1b
= rtl_read_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1);
1388 /* If IPS we need to turn LED on. So we not
1389 * not disable BIT 3/7 of reg3. */
1390 if (rtlpriv
->psc
.rfoff_reason
& (RF_CHANGE_BY_IPS
| RF_CHANGE_BY_HW
))
1395 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, tmpu1b
);
1396 /* wait for BIT 10/11/15 to pull high automatically!! */
1399 rtl_write_byte(rtlpriv
, CMDR
, 0);
1400 rtl_write_byte(rtlpriv
, TCR
, 0);
1402 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1403 tmpu1b
= rtl_read_byte(rtlpriv
, 0x562);
1405 rtl_write_byte(rtlpriv
, 0x562, tmpu1b
);
1406 tmpu1b
&= ~(BIT(3));
1407 rtl_write_byte(rtlpriv
, 0x562, tmpu1b
);
1409 /* Enable AFE clock source */
1410 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_XTAL_CTRL
);
1411 rtl_write_byte(rtlpriv
, AFE_XTAL_CTRL
, (tmpu1b
| 0x01));
1414 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_XTAL_CTRL
+ 1);
1415 rtl_write_byte(rtlpriv
, AFE_XTAL_CTRL
+ 1, (tmpu1b
& 0xfb));
1417 /* Enable AFE Macro Block's Bandgap */
1418 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_MISC
);
1419 rtl_write_byte(rtlpriv
, AFE_MISC
, (tmpu1b
| BIT(0)));
1422 /* Enable AFE Mbias */
1423 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_MISC
);
1424 rtl_write_byte(rtlpriv
, AFE_MISC
, (tmpu1b
| 0x02));
1427 /* Enable LDOA15 block */
1428 tmpu1b
= rtl_read_byte(rtlpriv
, LDOA15_CTRL
);
1429 rtl_write_byte(rtlpriv
, LDOA15_CTRL
, (tmpu1b
| BIT(0)));
1431 /* Set Digital Vdd to Retention isolation Path. */
1432 tmpu2b
= rtl_read_word(rtlpriv
, REG_SYS_ISO_CTRL
);
1433 rtl_write_word(rtlpriv
, REG_SYS_ISO_CTRL
, (tmpu2b
| BIT(11)));
1436 /* For warm reboot NIC disappera bug. */
1437 tmpu2b
= rtl_read_word(rtlpriv
, REG_SYS_FUNC_EN
);
1438 rtl_write_word(rtlpriv
, REG_SYS_FUNC_EN
, (tmpu2b
| BIT(13)));
1440 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
+ 1, 0x68);
1442 /* Enable AFE PLL Macro Block */
1443 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_PLL_CTRL
);
1444 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
, (tmpu1b
| BIT(0) | BIT(4)));
1445 /* Enable MAC 80MHZ clock */
1446 tmpu1b
= rtl_read_byte(rtlpriv
, AFE_PLL_CTRL
+ 1);
1447 rtl_write_byte(rtlpriv
, AFE_PLL_CTRL
+ 1, (tmpu1b
| BIT(0)));
1450 /* Release isolation AFE PLL & MD */
1451 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
, 0xA6);
1453 /* Enable MAC clock */
1454 tmpu2b
= rtl_read_word(rtlpriv
, SYS_CLKR
);
1455 rtl_write_word(rtlpriv
, SYS_CLKR
, (tmpu2b
| BIT(12) | BIT(11)));
1457 /* Enable Core digital and enable IOREG R/W */
1458 tmpu2b
= rtl_read_word(rtlpriv
, REG_SYS_FUNC_EN
);
1459 rtl_write_word(rtlpriv
, REG_SYS_FUNC_EN
, (tmpu2b
| BIT(11)));
1461 rtl_write_word(rtlpriv
, REG_SYS_FUNC_EN
, (tmpu2b
| BIT(11) | BIT(15)));
1463 /* Switch the control path. */
1464 tmpu2b
= rtl_read_word(rtlpriv
, SYS_CLKR
);
1465 rtl_write_word(rtlpriv
, SYS_CLKR
, (tmpu2b
& (~BIT(2))));
1467 tmpu1b
= rtl_read_byte(rtlpriv
, (SYS_CLKR
+ 1));
1468 tmpu1b
= ((tmpu1b
| BIT(7)) & (~BIT(6)));
1469 if (!_rtl92s_set_sysclk(hw
, tmpu1b
)) {
1470 rtlpriv
->psc
.pwrdomain_protect
= false;
1474 rtl_write_word(rtlpriv
, CMDR
, 0x37FC);
1476 /* After MACIO reset,we must refresh LED state. */
1477 _rtl92se_gen_refreshledstate(hw
);
1479 rtlpriv
->psc
.pwrdomain_protect
= false;
1482 void rtl92se_card_disable(struct ieee80211_hw
*hw
)
1484 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1485 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1486 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1487 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1488 enum nl80211_iftype opmode
;
1491 rtlpriv
->intf_ops
->enable_aspm(hw
);
1493 if (rtlpci
->driver_is_goingto_unload
||
1494 ppsc
->rfoff_reason
> RF_CHANGE_BY_PS
)
1495 rtlpriv
->cfg
->ops
->led_control(hw
, LED_CTL_POWER_OFF
);
1497 /* we should chnge GPIO to input mode
1498 * this will drop away current about 25mA*/
1499 rtl8192se_gpiobit3_cfg_inputmode(hw
);
1501 /* this is very important for ips power save */
1502 while (wait
-- >= 10 && rtlpriv
->psc
.pwrdomain_protect
) {
1503 if (rtlpriv
->psc
.pwrdomain_protect
)
1509 mac
->link_state
= MAC80211_NOLINK
;
1510 opmode
= NL80211_IFTYPE_UNSPECIFIED
;
1511 _rtl92se_set_media_status(hw
, opmode
);
1513 _rtl92s_phy_set_rfhalt(hw
);
1517 void rtl92se_interrupt_recognized(struct ieee80211_hw
*hw
, u32
*p_inta
,
1520 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1521 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1523 *p_inta
= rtl_read_dword(rtlpriv
, ISR
) & rtlpci
->irq_mask
[0];
1524 rtl_write_dword(rtlpriv
, ISR
, *p_inta
);
1526 *p_intb
= rtl_read_dword(rtlpriv
, ISR
+ 4) & rtlpci
->irq_mask
[1];
1527 rtl_write_dword(rtlpriv
, ISR
+ 4, *p_intb
);
1530 void rtl92se_set_beacon_related_registers(struct ieee80211_hw
*hw
)
1532 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1533 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1534 u16 bcntime_cfg
= 0;
1535 u16 bcn_cw
= 6, bcn_ifs
= 0xf;
1536 u16 atim_window
= 2;
1538 /* ATIM Window (in unit of TU). */
1539 rtl_write_word(rtlpriv
, ATIMWND
, atim_window
);
1541 /* Beacon interval (in unit of TU). */
1542 rtl_write_word(rtlpriv
, BCN_INTERVAL
, mac
->beacon_interval
);
1544 /* DrvErlyInt (in unit of TU). (Time to send
1545 * interrupt to notify driver to change
1546 * beacon content) */
1547 rtl_write_word(rtlpriv
, BCN_DRV_EARLY_INT
, 10 << 4);
1549 /* BcnDMATIM(in unit of us). Indicates the
1550 * time before TBTT to perform beacon queue DMA */
1551 rtl_write_word(rtlpriv
, BCN_DMATIME
, 256);
1553 /* Force beacon frame transmission even
1554 * after receiving beacon frame from
1555 * other ad hoc STA */
1556 rtl_write_byte(rtlpriv
, BCN_ERR_THRESH
, 100);
1558 /* Beacon Time Configuration */
1559 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
)
1560 bcntime_cfg
|= (bcn_cw
<< BCN_TCFG_CW_SHIFT
);
1562 /* TODO: bcn_ifs may required to be changed on ASIC */
1563 bcntime_cfg
|= bcn_ifs
<< BCN_TCFG_IFS
;
1565 /*for beacon changed */
1566 rtl92s_phy_set_beacon_hwreg(hw
, mac
->beacon_interval
);
1569 void rtl92se_set_beacon_interval(struct ieee80211_hw
*hw
)
1571 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1572 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1573 u16 bcn_interval
= mac
->beacon_interval
;
1575 /* Beacon interval (in unit of TU). */
1576 rtl_write_word(rtlpriv
, BCN_INTERVAL
, bcn_interval
);
1577 /* 2008.10.24 added by tynli for beacon changed. */
1578 rtl92s_phy_set_beacon_hwreg(hw
, bcn_interval
);
1581 void rtl92se_update_interrupt_mask(struct ieee80211_hw
*hw
,
1582 u32 add_msr
, u32 rm_msr
)
1584 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1585 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1587 RT_TRACE(rtlpriv
, COMP_INTR
, DBG_LOUD
, "add_msr:%x, rm_msr:%x\n",
1591 rtlpci
->irq_mask
[0] |= add_msr
;
1594 rtlpci
->irq_mask
[0] &= (~rm_msr
);
1596 rtl92se_disable_interrupt(hw
);
1597 rtl92se_enable_interrupt(hw
);
1600 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw
*hw
)
1602 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1603 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1606 rtlhal
->ic_class
= IC_INFERIORITY_A
;
1608 /* Only retrieving while using EFUSE. */
1609 if ((rtlefuse
->epromtype
== EEPROM_BOOT_EFUSE
) &&
1610 !rtlefuse
->autoload_failflag
) {
1611 efuse_id
= efuse_read_1byte(hw
, EFUSE_IC_ID_OFFSET
);
1613 if (efuse_id
== 0xfe)
1614 rtlhal
->ic_class
= IC_INFERIORITY_B
;
1618 static void _rtl92se_read_adapter_info(struct ieee80211_hw
*hw
)
1620 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1621 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1622 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1626 u8 hwinfo
[HWSET_MAX_SIZE_92S
];
1629 if (rtlefuse
->epromtype
== EEPROM_93C46
) {
1630 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1631 "RTL819X Not boot from eeprom, check it !!\n");
1632 } else if (rtlefuse
->epromtype
== EEPROM_BOOT_EFUSE
) {
1633 rtl_efuse_shadow_map_update(hw
);
1635 memcpy((void *)hwinfo
, (void *)
1636 &rtlefuse
->efuse_map
[EFUSE_INIT_MAP
][0],
1637 HWSET_MAX_SIZE_92S
);
1640 RT_PRINT_DATA(rtlpriv
, COMP_INIT
, DBG_DMESG
, "MAP",
1641 hwinfo
, HWSET_MAX_SIZE_92S
);
1643 eeprom_id
= *((u16
*)&hwinfo
[0]);
1644 if (eeprom_id
!= RTL8190_EEPROM_ID
) {
1645 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1646 "EEPROM ID(%#x) is invalid!!\n", eeprom_id
);
1647 rtlefuse
->autoload_failflag
= true;
1649 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1650 rtlefuse
->autoload_failflag
= false;
1653 if (rtlefuse
->autoload_failflag
)
1656 _rtl8192se_get_IC_Inferiority(hw
);
1658 /* Read IC Version && Channel Plan */
1659 /* VID, DID SE 0xA-D */
1660 rtlefuse
->eeprom_vid
= *(u16
*)&hwinfo
[EEPROM_VID
];
1661 rtlefuse
->eeprom_did
= *(u16
*)&hwinfo
[EEPROM_DID
];
1662 rtlefuse
->eeprom_svid
= *(u16
*)&hwinfo
[EEPROM_SVID
];
1663 rtlefuse
->eeprom_smid
= *(u16
*)&hwinfo
[EEPROM_SMID
];
1664 rtlefuse
->eeprom_version
= *(u16
*)&hwinfo
[EEPROM_VERSION
];
1666 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1667 "EEPROMId = 0x%4x\n", eeprom_id
);
1668 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1669 "EEPROM VID = 0x%4x\n", rtlefuse
->eeprom_vid
);
1670 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1671 "EEPROM DID = 0x%4x\n", rtlefuse
->eeprom_did
);
1672 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1673 "EEPROM SVID = 0x%4x\n", rtlefuse
->eeprom_svid
);
1674 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1675 "EEPROM SMID = 0x%4x\n", rtlefuse
->eeprom_smid
);
1677 for (i
= 0; i
< 6; i
+= 2) {
1678 usvalue
= *(u16
*)&hwinfo
[EEPROM_MAC_ADDR
+ i
];
1679 *((u16
*) (&rtlefuse
->dev_addr
[i
])) = usvalue
;
1682 for (i
= 0; i
< 6; i
++)
1683 rtl_write_byte(rtlpriv
, MACIDR0
+ i
, rtlefuse
->dev_addr
[i
]);
1685 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "%pM\n", rtlefuse
->dev_addr
);
1687 /* Get Tx Power Level by Channel */
1688 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1689 /* 92S suupport RF A & B */
1690 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1691 for (i
= 0; i
< 3; i
++) {
1692 /* Read CCK RF A & B Tx power */
1693 rtlefuse
->eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1694 hwinfo
[EEPROM_TXPOWERBASE
+ rf_path
* 3 + i
];
1696 /* Read OFDM RF A & B Tx power for 1T */
1697 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1698 hwinfo
[EEPROM_TXPOWERBASE
+ 6 + rf_path
* 3 + i
];
1700 /* Read OFDM RF A & B Tx power for 2T */
1701 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
[rf_path
][i
]
1702 = hwinfo
[EEPROM_TXPOWERBASE
+ 12 +
1707 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1708 for (i
= 0; i
< 3; i
++)
1709 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1710 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1712 rtlefuse
->eeprom_chnlarea_txpwr_cck
1714 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1715 for (i
= 0; i
< 3; i
++)
1716 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1717 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1719 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
1721 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1722 for (i
= 0; i
< 3; i
++)
1723 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1724 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1726 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
1729 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1731 /* Assign dedicated channel tx power */
1732 for (i
= 0; i
< 14; i
++) {
1733 /* channel 1~3 use the same Tx Power Level. */
1743 /* Record A & B CCK /OFDM - 1T/2T Channel area
1745 rtlefuse
->txpwrlevel_cck
[rf_path
][i
] =
1746 rtlefuse
->eeprom_chnlarea_txpwr_cck
1748 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
] =
1749 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
1751 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] =
1752 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
1756 for (i
= 0; i
< 14; i
++) {
1757 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1758 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1760 rtlefuse
->txpwrlevel_cck
[rf_path
][i
],
1761 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
],
1762 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
]);
1766 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1767 for (i
= 0; i
< 3; i
++) {
1768 /* Read Power diff limit. */
1769 rtlefuse
->eeprom_pwrgroup
[rf_path
][i
] =
1770 hwinfo
[EEPROM_TXPWRGROUP
+ rf_path
* 3 + i
];
1774 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1775 /* Fill Pwr group */
1776 for (i
= 0; i
< 14; i
++) {
1787 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1788 (rtlefuse
->eeprom_pwrgroup
[rf_path
][index
] &
1790 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1791 ((rtlefuse
->eeprom_pwrgroup
[rf_path
][index
] &
1794 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1795 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1797 rtlefuse
->pwrgroup_ht20
[rf_path
][i
]);
1798 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1799 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1801 rtlefuse
->pwrgroup_ht40
[rf_path
][i
]);
1805 for (i
= 0; i
< 14; i
++) {
1806 /* Read tx power difference between HT OFDM 20/40 MHZ */
1817 tempval
= hwinfo
[EEPROM_TX_PWR_HT20_DIFF
+ index
] & 0xff;
1818 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1819 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] =
1820 ((tempval
>> 4) & 0xF);
1822 /* Read OFDM<->HT tx power diff */
1833 tempval
= hwinfo
[EEPROM_TX_PWR_OFDM_DIFF
+ index
] & 0xff;
1834 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
] =
1836 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
] =
1837 ((tempval
>> 4) & 0xF);
1839 tempval
= hwinfo
[TX_PWR_SAFETY_CHK
];
1840 rtlefuse
->txpwr_safetyflag
= (tempval
& 0x01);
1843 rtlefuse
->eeprom_regulatory
= 0;
1844 if (rtlefuse
->eeprom_version
>= 2) {
1846 if (rtlefuse
->eeprom_version
>= 4)
1847 rtlefuse
->eeprom_regulatory
=
1848 (hwinfo
[EEPROM_REGULATORY
] & 0x7);
1850 rtlefuse
->eeprom_regulatory
=
1851 (hwinfo
[EEPROM_REGULATORY
] & 0x1);
1853 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1854 "eeprom_regulatory = 0x%x\n", rtlefuse
->eeprom_regulatory
);
1856 for (i
= 0; i
< 14; i
++)
1857 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1858 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1859 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
]);
1860 for (i
= 0; i
< 14; i
++)
1861 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1862 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1863 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
]);
1864 for (i
= 0; i
< 14; i
++)
1865 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1866 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1867 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
]);
1868 for (i
= 0; i
< 14; i
++)
1869 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1870 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1871 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
]);
1873 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1874 "TxPwrSafetyFlag = %d\n", rtlefuse
->txpwr_safetyflag
);
1876 /* Read RF-indication and Tx Power gain
1877 * index diff of legacy to HT OFDM rate. */
1878 tempval
= hwinfo
[EEPROM_RFIND_POWERDIFF
] & 0xff;
1879 rtlefuse
->eeprom_txpowerdiff
= tempval
;
1880 rtlefuse
->legacy_httxpowerdiff
=
1881 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][0];
1883 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1884 "TxPowerDiff = %#x\n", rtlefuse
->eeprom_txpowerdiff
);
1886 /* Get TSSI value for each path. */
1887 usvalue
= *(u16
*)&hwinfo
[EEPROM_TSSI_A
];
1888 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = (u8
)((usvalue
& 0xff00) >> 8);
1889 usvalue
= hwinfo
[EEPROM_TSSI_B
];
1890 rtlefuse
->eeprom_tssi
[RF90_PATH_B
] = (u8
)(usvalue
& 0xff);
1892 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1893 rtlefuse
->eeprom_tssi
[RF90_PATH_A
],
1894 rtlefuse
->eeprom_tssi
[RF90_PATH_B
]);
1896 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1897 /* and read ThermalMeter from EEPROM */
1898 tempval
= hwinfo
[EEPROM_THERMALMETER
];
1899 rtlefuse
->eeprom_thermalmeter
= tempval
;
1900 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1901 "thermalmeter = 0x%x\n", rtlefuse
->eeprom_thermalmeter
);
1903 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1904 rtlefuse
->thermalmeter
[0] = (rtlefuse
->eeprom_thermalmeter
& 0x1f);
1905 rtlefuse
->tssi_13dbm
= rtlefuse
->eeprom_thermalmeter
* 100;
1907 /* Read CrystalCap from EEPROM */
1908 tempval
= hwinfo
[EEPROM_CRYSTALCAP
] >> 4;
1909 rtlefuse
->eeprom_crystalcap
= tempval
;
1910 /* CrystalCap, BIT(12)~15 */
1911 rtlefuse
->crystalcap
= rtlefuse
->eeprom_crystalcap
;
1913 /* Read IC Version && Channel Plan */
1914 /* Version ID, Channel plan */
1915 rtlefuse
->eeprom_channelplan
= hwinfo
[EEPROM_CHANNELPLAN
];
1916 rtlefuse
->txpwr_fromeprom
= true;
1917 RTPRINT(rtlpriv
, FINIT
, INIT_TxPower
,
1918 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse
->eeprom_channelplan
);
1920 /* Read Customer ID or Board Type!!! */
1921 tempval
= hwinfo
[EEPROM_BOARDTYPE
];
1922 /* Change RF type definition */
1924 rtlphy
->rf_type
= RF_2T2R
;
1925 else if (tempval
== 1)
1926 rtlphy
->rf_type
= RF_1T2R
;
1927 else if (tempval
== 2)
1928 rtlphy
->rf_type
= RF_1T2R
;
1929 else if (tempval
== 3)
1930 rtlphy
->rf_type
= RF_1T1R
;
1932 /* 1T2R but 1SS (1x1 receive combining) */
1933 rtlefuse
->b1x1_recvcombine
= false;
1934 if (rtlphy
->rf_type
== RF_1T2R
) {
1935 tempval
= rtl_read_byte(rtlpriv
, 0x07);
1936 if (!(tempval
& BIT(0))) {
1937 rtlefuse
->b1x1_recvcombine
= true;
1938 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1939 "RF_TYPE=1T2R but only 1SS\n");
1942 rtlefuse
->b1ss_support
= rtlefuse
->b1x1_recvcombine
;
1943 rtlefuse
->eeprom_oemid
= *&hwinfo
[EEPROM_CUSTOMID
];
1945 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "EEPROM Customer ID: 0x%2x",
1946 rtlefuse
->eeprom_oemid
);
1948 /* set channel paln to world wide 13 */
1949 rtlefuse
->channel_plan
= COUNTRY_CODE_WORLD_WIDE_13
;
1952 void rtl92se_read_eeprom_info(struct ieee80211_hw
*hw
)
1954 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1955 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1958 tmp_u1b
= rtl_read_byte(rtlpriv
, EPROM_CMD
);
1960 if (tmp_u1b
& BIT(4)) {
1961 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EEPROM\n");
1962 rtlefuse
->epromtype
= EEPROM_93C46
;
1964 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EFUSE\n");
1965 rtlefuse
->epromtype
= EEPROM_BOOT_EFUSE
;
1968 if (tmp_u1b
& BIT(5)) {
1969 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1970 rtlefuse
->autoload_failflag
= false;
1971 _rtl92se_read_adapter_info(hw
);
1973 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Autoload ERR!!\n");
1974 rtlefuse
->autoload_failflag
= true;
1978 static void rtl92se_update_hal_rate_table(struct ieee80211_hw
*hw
,
1979 struct ieee80211_sta
*sta
)
1981 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1982 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1983 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1984 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1987 u8 nmode
= mac
->ht_enable
;
1988 u8 mimo_ps
= IEEE80211_SMPS_OFF
;
1989 u16 shortgi_rate
= 0;
1990 u32 tmp_ratr_value
= 0;
1991 u8 curtxbw_40mhz
= mac
->bw_40
;
1992 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
1994 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1996 enum wireless_mode wirelessmode
= mac
->mode
;
1998 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1999 ratr_value
= sta
->supp_rates
[1] << 4;
2001 ratr_value
= sta
->supp_rates
[0];
2002 ratr_value
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
2003 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
2004 switch (wirelessmode
) {
2005 case WIRELESS_MODE_B
:
2006 ratr_value
&= 0x0000000D;
2008 case WIRELESS_MODE_G
:
2009 ratr_value
&= 0x00000FF5;
2011 case WIRELESS_MODE_N_24G
:
2012 case WIRELESS_MODE_N_5G
:
2014 if (mimo_ps
== IEEE80211_SMPS_STATIC
) {
2015 ratr_value
&= 0x0007F005;
2019 if (get_rf_type(rtlphy
) == RF_1T2R
||
2020 get_rf_type(rtlphy
) == RF_1T1R
) {
2022 ratr_mask
= 0x000ff015;
2024 ratr_mask
= 0x000ff005;
2027 ratr_mask
= 0x0f0ff015;
2029 ratr_mask
= 0x0f0ff005;
2032 ratr_value
&= ratr_mask
;
2036 if (rtlphy
->rf_type
== RF_1T2R
)
2037 ratr_value
&= 0x000ff0ff;
2039 ratr_value
&= 0x0f0ff0ff;
2044 if (rtlpriv
->rtlhal
.version
>= VERSION_8192S_BCUT
)
2045 ratr_value
&= 0x0FFFFFFF;
2046 else if (rtlpriv
->rtlhal
.version
== VERSION_8192S_ACUT
)
2047 ratr_value
&= 0x0FFFFFF0;
2049 if (nmode
&& ((curtxbw_40mhz
&&
2050 curshortgi_40mhz
) || (!curtxbw_40mhz
&&
2051 curshortgi_20mhz
))) {
2053 ratr_value
|= 0x10000000;
2054 tmp_ratr_value
= (ratr_value
>> 12);
2056 for (shortgi_rate
= 15; shortgi_rate
> 0; shortgi_rate
--) {
2057 if ((1 << shortgi_rate
) & tmp_ratr_value
)
2061 shortgi_rate
= (shortgi_rate
<< 12) | (shortgi_rate
<< 8) |
2062 (shortgi_rate
<< 4) | (shortgi_rate
);
2064 rtl_write_byte(rtlpriv
, SG_RATE
, shortgi_rate
);
2067 rtl_write_dword(rtlpriv
, ARFR0
+ ratr_index
* 4, ratr_value
);
2068 if (ratr_value
& 0xfffff000)
2069 rtl92s_phy_set_fw_cmd(hw
, FW_CMD_RA_REFRESH_N
);
2071 rtl92s_phy_set_fw_cmd(hw
, FW_CMD_RA_REFRESH_BG
);
2073 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
, "%x\n",
2074 rtl_read_dword(rtlpriv
, ARFR0
));
2077 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw
*hw
,
2078 struct ieee80211_sta
*sta
,
2081 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2082 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
2083 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2084 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
2085 struct rtl_sta_info
*sta_entry
= NULL
;
2088 u8 curtxbw_40mhz
= (sta
->bandwidth
>= IEEE80211_STA_RX_BW_40
) ? 1 : 0;
2089 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
2091 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
2093 enum wireless_mode wirelessmode
= 0;
2094 bool shortgi
= false;
2096 u8 shortgi_rate
= 0;
2099 bool bmulticast
= false;
2101 u8 mimo_ps
= IEEE80211_SMPS_OFF
;
2103 sta_entry
= (struct rtl_sta_info
*) sta
->drv_priv
;
2104 wirelessmode
= sta_entry
->wireless_mode
;
2105 if (mac
->opmode
== NL80211_IFTYPE_STATION
)
2106 curtxbw_40mhz
= mac
->bw_40
;
2107 else if (mac
->opmode
== NL80211_IFTYPE_AP
||
2108 mac
->opmode
== NL80211_IFTYPE_ADHOC
)
2109 macid
= sta
->aid
+ 1;
2111 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
2112 ratr_bitmap
= sta
->supp_rates
[1] << 4;
2114 ratr_bitmap
= sta
->supp_rates
[0];
2115 ratr_bitmap
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
2116 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
2117 switch (wirelessmode
) {
2118 case WIRELESS_MODE_B
:
2119 band
|= WIRELESS_11B
;
2120 ratr_index
= RATR_INX_WIRELESS_B
;
2121 if (ratr_bitmap
& 0x0000000c)
2122 ratr_bitmap
&= 0x0000000d;
2124 ratr_bitmap
&= 0x0000000f;
2126 case WIRELESS_MODE_G
:
2127 band
|= (WIRELESS_11G
| WIRELESS_11B
);
2128 ratr_index
= RATR_INX_WIRELESS_GB
;
2130 if (rssi_level
== 1)
2131 ratr_bitmap
&= 0x00000f00;
2132 else if (rssi_level
== 2)
2133 ratr_bitmap
&= 0x00000ff0;
2135 ratr_bitmap
&= 0x00000ff5;
2137 case WIRELESS_MODE_A
:
2138 band
|= WIRELESS_11A
;
2139 ratr_index
= RATR_INX_WIRELESS_A
;
2140 ratr_bitmap
&= 0x00000ff0;
2142 case WIRELESS_MODE_N_24G
:
2143 case WIRELESS_MODE_N_5G
:
2144 band
|= (WIRELESS_11N
| WIRELESS_11G
| WIRELESS_11B
);
2145 ratr_index
= RATR_INX_WIRELESS_NGB
;
2147 if (mimo_ps
== IEEE80211_SMPS_STATIC
) {
2148 if (rssi_level
== 1)
2149 ratr_bitmap
&= 0x00070000;
2150 else if (rssi_level
== 2)
2151 ratr_bitmap
&= 0x0007f000;
2153 ratr_bitmap
&= 0x0007f005;
2155 if (rtlphy
->rf_type
== RF_1T2R
||
2156 rtlphy
->rf_type
== RF_1T1R
) {
2157 if (rssi_level
== 1) {
2158 ratr_bitmap
&= 0x000f0000;
2159 } else if (rssi_level
== 3) {
2160 ratr_bitmap
&= 0x000fc000;
2161 } else if (rssi_level
== 5) {
2162 ratr_bitmap
&= 0x000ff000;
2165 ratr_bitmap
&= 0x000ff015;
2167 ratr_bitmap
&= 0x000ff005;
2170 if (rssi_level
== 1) {
2171 ratr_bitmap
&= 0x0f8f0000;
2172 } else if (rssi_level
== 3) {
2173 ratr_bitmap
&= 0x0f8fc000;
2174 } else if (rssi_level
== 5) {
2175 ratr_bitmap
&= 0x0f8ff000;
2178 ratr_bitmap
&= 0x0f8ff015;
2180 ratr_bitmap
&= 0x0f8ff005;
2185 if ((curtxbw_40mhz
&& curshortgi_40mhz
) ||
2186 (!curtxbw_40mhz
&& curshortgi_20mhz
)) {
2189 else if (macid
== 1)
2194 band
|= (WIRELESS_11N
| WIRELESS_11G
| WIRELESS_11B
);
2195 ratr_index
= RATR_INX_WIRELESS_NGB
;
2197 if (rtlphy
->rf_type
== RF_1T2R
)
2198 ratr_bitmap
&= 0x000ff0ff;
2200 ratr_bitmap
&= 0x0f8ff0ff;
2204 if (rtlpriv
->rtlhal
.version
>= VERSION_8192S_BCUT
)
2205 ratr_bitmap
&= 0x0FFFFFFF;
2206 else if (rtlpriv
->rtlhal
.version
== VERSION_8192S_ACUT
)
2207 ratr_bitmap
&= 0x0FFFFFF0;
2210 ratr_bitmap
|= 0x10000000;
2211 /* Get MAX MCS available. */
2212 ratr_value
= (ratr_bitmap
>> 12);
2213 for (shortgi_rate
= 15; shortgi_rate
> 0; shortgi_rate
--) {
2214 if ((1 << shortgi_rate
) & ratr_value
)
2218 shortgi_rate
= (shortgi_rate
<< 12) | (shortgi_rate
<< 8) |
2219 (shortgi_rate
<< 4) | (shortgi_rate
);
2220 rtl_write_byte(rtlpriv
, SG_RATE
, shortgi_rate
);
2223 mask
|= (bmulticast
? 1 : 0) << 9 | (macid
& 0x1f) << 4 | (band
& 0xf);
2225 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_TRACE
, "mask = %x, bitmap = %x\n",
2227 rtl_write_dword(rtlpriv
, 0x2c4, ratr_bitmap
);
2228 rtl_write_dword(rtlpriv
, WFM5
, (FW_RA_UPDATE_MASK
| (mask
<< 8)));
2231 sta_entry
->ratr_index
= ratr_index
;
2234 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw
*hw
,
2235 struct ieee80211_sta
*sta
, u8 rssi_level
)
2237 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2239 if (rtlpriv
->dm
.useramask
)
2240 rtl92se_update_hal_rate_mask(hw
, sta
, rssi_level
);
2242 rtl92se_update_hal_rate_table(hw
, sta
);
2245 void rtl92se_update_channel_access_setting(struct ieee80211_hw
*hw
)
2247 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2248 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2251 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SLOT_TIME
,
2253 sifs_timer
= 0x0e0e;
2254 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SIFS
, (u8
*)&sifs_timer
);
2258 /* this ifunction is for RFKILL, it's different with windows,
2259 * because UI will disable wireless when GPIO Radio Off.
2260 * And here we not check or Disable/Enable ASPM like windows*/
2261 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw
*hw
, u8
*valid
)
2263 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2264 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
2265 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
2266 enum rf_pwrstate rfpwr_toset
/*, cur_rfstate */;
2267 unsigned long flag
= 0;
2268 bool actuallyset
= false;
2269 bool turnonbypowerdomain
= false;
2271 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2272 if ((rtlpci
->up_first_time
== 1) || (rtlpci
->being_init_adapter
))
2275 if (ppsc
->swrf_processing
)
2278 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2279 if (ppsc
->rfchange_inprogress
) {
2280 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2283 ppsc
->rfchange_inprogress
= true;
2284 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2287 /* cur_rfstate = ppsc->rfpwr_state;*/
2289 /* because after _rtl92s_phy_set_rfhalt, all power
2290 * closed, so we must open some power for GPIO check,
2291 * or we will always check GPIO RFOFF here,
2292 * And we should close power after GPIO check */
2293 if (RT_IN_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
)) {
2294 _rtl92se_power_domain_init(hw
);
2295 turnonbypowerdomain
= true;
2298 rfpwr_toset
= _rtl92se_rf_onoff_detect(hw
);
2300 if ((ppsc
->hwradiooff
) && (rfpwr_toset
== ERFON
)) {
2301 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
2302 "RFKILL-HW Radio ON, RF ON\n");
2304 rfpwr_toset
= ERFON
;
2305 ppsc
->hwradiooff
= false;
2307 } else if ((!ppsc
->hwradiooff
) && (rfpwr_toset
== ERFOFF
)) {
2308 RT_TRACE(rtlpriv
, COMP_RF
,
2309 DBG_DMESG
, "RFKILL-HW Radio OFF, RF OFF\n");
2311 rfpwr_toset
= ERFOFF
;
2312 ppsc
->hwradiooff
= true;
2317 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2318 ppsc
->rfchange_inprogress
= false;
2319 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2321 /* this not include ifconfig wlan0 down case */
2322 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2324 /* because power_domain_init may be happen when
2325 * _rtl92s_phy_set_rfhalt, this will open some powers
2326 * and cause current increasing about 40 mA for ips,
2327 * rfoff and ifconfig down, so we set
2328 * _rtl92s_phy_set_rfhalt again here */
2329 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
&&
2330 turnonbypowerdomain
) {
2331 _rtl92s_phy_set_rfhalt(hw
);
2332 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
2335 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2336 ppsc
->rfchange_inprogress
= false;
2337 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2341 return !ppsc
->hwradiooff
;
2345 /* Is_wepkey just used for WEP used as group & pairwise key
2346 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2347 void rtl92se_set_key(struct ieee80211_hw
*hw
, u32 key_index
, u8
*p_macaddr
,
2348 bool is_group
, u8 enc_algo
, bool is_wepkey
, bool clear_all
)
2350 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2351 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2352 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
2353 u8
*macaddr
= p_macaddr
;
2356 bool is_pairwise
= false;
2358 static u8 cam_const_addr
[4][6] = {
2359 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2360 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2361 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2362 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2364 static u8 cam_const_broad
[] = {
2365 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2371 u8 clear_number
= 5;
2373 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
, "clear_all\n");
2375 for (idx
= 0; idx
< clear_number
; idx
++) {
2376 rtl_cam_mark_invalid(hw
, cam_offset
+ idx
);
2377 rtl_cam_empty_entry(hw
, cam_offset
+ idx
);
2380 memset(rtlpriv
->sec
.key_buf
[idx
], 0,
2382 rtlpriv
->sec
.key_len
[idx
] = 0;
2388 case WEP40_ENCRYPTION
:
2389 enc_algo
= CAM_WEP40
;
2391 case WEP104_ENCRYPTION
:
2392 enc_algo
= CAM_WEP104
;
2394 case TKIP_ENCRYPTION
:
2395 enc_algo
= CAM_TKIP
;
2397 case AESCCMP_ENCRYPTION
:
2401 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2402 "switch case not processed\n");
2403 enc_algo
= CAM_TKIP
;
2407 if (is_wepkey
|| rtlpriv
->sec
.use_defaultkey
) {
2408 macaddr
= cam_const_addr
[key_index
];
2409 entry_id
= key_index
;
2412 macaddr
= cam_const_broad
;
2413 entry_id
= key_index
;
2415 if (mac
->opmode
== NL80211_IFTYPE_AP
) {
2416 entry_id
= rtl_cam_get_free_entry(hw
,
2418 if (entry_id
>= TOTAL_CAM_ENTRY
) {
2420 COMP_SEC
, DBG_EMERG
,
2421 "Can not find free hw security cam entry\n");
2425 entry_id
= CAM_PAIRWISE_KEY_POSITION
;
2428 key_index
= PAIRWISE_KEYIDX
;
2433 if (rtlpriv
->sec
.key_len
[key_index
] == 0) {
2434 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2435 "delete one entry, entry_id is %d\n",
2437 if (mac
->opmode
== NL80211_IFTYPE_AP
)
2438 rtl_cam_del_entry(hw
, p_macaddr
);
2439 rtl_cam_delete_one_entry(hw
, p_macaddr
, entry_id
);
2441 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2442 "The insert KEY length is %d\n",
2443 rtlpriv
->sec
.key_len
[PAIRWISE_KEYIDX
]);
2444 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2445 "The insert KEY is %x %x\n",
2446 rtlpriv
->sec
.key_buf
[0][0],
2447 rtlpriv
->sec
.key_buf
[0][1]);
2449 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2452 RT_PRINT_DATA(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2453 "Pairwise Key content",
2454 rtlpriv
->sec
.pairwise_key
,
2456 key_len
[PAIRWISE_KEYIDX
]);
2458 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2459 "set Pairwise key\n");
2461 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2463 CAM_CONFIG_NO_USEDK
,
2464 rtlpriv
->sec
.key_buf
[key_index
]);
2466 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2469 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
) {
2470 rtl_cam_add_one_entry(hw
,
2473 CAM_PAIRWISE_KEY_POSITION
,
2474 enc_algo
, CAM_CONFIG_NO_USEDK
,
2475 rtlpriv
->sec
.key_buf
[entry_id
]);
2478 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2480 CAM_CONFIG_NO_USEDK
,
2481 rtlpriv
->sec
.key_buf
[entry_id
]);
2488 void rtl92se_suspend(struct ieee80211_hw
*hw
)
2490 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
2492 rtlpci
->up_first_time
= true;
2495 void rtl92se_resume(struct ieee80211_hw
*hw
)
2497 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
2500 pci_read_config_dword(rtlpci
->pdev
, 0x40, &val
);
2501 if ((val
& 0x0000ff00) != 0)
2502 pci_write_config_dword(rtlpci
->pdev
, 0x40,