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Merge tag 'kvm-arm-for-3.18-take-2' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rtlwifi / rtl8821ae / hw.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../efuse.h"
28 #include "../base.h"
29 #include "../regd.h"
30 #include "../cam.h"
31 #include "../ps.h"
32 #include "../pci.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "dm.h"
37 #include "fw.h"
38 #include "led.h"
39 #include "hw.h"
40 #include "../pwrseqcmd.h"
41 #include "pwrseq.h"
42 #include "../btcoexist/rtl_btc.h"
43
44 #define LLT_CONFIG 5
45
46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
47 {
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
51 unsigned long flags;
52
53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
54 while (skb_queue_len(&ring->queue)) {
55 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
56 struct sk_buff *skb = __skb_dequeue(&ring->queue);
57
58 pci_unmap_single(rtlpci->pdev,
59 rtlpriv->cfg->ops->get_desc(
60 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
61 skb->len, PCI_DMA_TODEVICE);
62 kfree_skb(skb);
63 ring->idx = (ring->idx + 1) % ring->entries;
64 }
65 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
66 }
67
68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69 u8 set_bits, u8 clear_bits)
70 {
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73
74 rtlpci->reg_bcn_ctrl_val |= set_bits;
75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
76
77 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
78 }
79
80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
81 {
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
83 u8 tmp1byte;
84
85 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
86 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89 tmp1byte &= ~(BIT(0));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
91 }
92
93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
94 {
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
96 u8 tmp1byte;
97
98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
101 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
102 tmp1byte |= BIT(0);
103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
104 }
105
106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
107 {
108 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
109 }
110
111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
112 {
113 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
114 }
115
116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
117 u8 rpwm_val, bool b_need_turn_off_ckk)
118 {
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
121 bool b_support_remote_wake_up;
122 u32 count = 0, isr_regaddr, content;
123 bool b_schedule_timer = b_need_turn_off_ckk;
124
125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
126 (u8 *)(&b_support_remote_wake_up));
127
128 if (!rtlhal->fw_ready)
129 return;
130 if (!rtlpriv->psc.fw_current_inpsmode)
131 return;
132
133 while (1) {
134 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
135 if (rtlhal->fw_clk_change_in_progress) {
136 while (rtlhal->fw_clk_change_in_progress) {
137 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
138 count++;
139 udelay(100);
140 if (count > 1000)
141 goto change_done;
142 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
143 }
144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
145 } else {
146 rtlhal->fw_clk_change_in_progress = false;
147 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
148 goto change_done;
149 }
150 }
151 change_done:
152 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
153 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
154 (u8 *)(&rpwm_val));
155 if (FW_PS_IS_ACK(rpwm_val)) {
156 isr_regaddr = REG_HISR;
157 content = rtl_read_dword(rtlpriv, isr_regaddr);
158 while (!(content & IMR_CPWM) && (count < 500)) {
159 udelay(50);
160 count++;
161 content = rtl_read_dword(rtlpriv, isr_regaddr);
162 }
163
164 if (content & IMR_CPWM) {
165 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
166 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
167 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
168 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
169 rtlhal->fw_ps_state);
170 }
171 }
172
173 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
174 rtlhal->fw_clk_change_in_progress = false;
175 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
176 if (b_schedule_timer)
177 mod_timer(&rtlpriv->works.fw_clockoff_timer,
178 jiffies + MSECS(10));
179 } else {
180 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
181 rtlhal->fw_clk_change_in_progress = false;
182 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
183 }
184 }
185
186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
187 u8 rpwm_val)
188 {
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
192 struct rtl8192_tx_ring *ring;
193 enum rf_pwrstate rtstate;
194 bool b_schedule_timer = false;
195 u8 queue;
196
197 if (!rtlhal->fw_ready)
198 return;
199 if (!rtlpriv->psc.fw_current_inpsmode)
200 return;
201 if (!rtlhal->allow_sw_to_change_hwclc)
202 return;
203 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
204 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
205 return;
206
207 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
208 ring = &rtlpci->tx_ring[queue];
209 if (skb_queue_len(&ring->queue)) {
210 b_schedule_timer = true;
211 break;
212 }
213 }
214
215 if (b_schedule_timer) {
216 mod_timer(&rtlpriv->works.fw_clockoff_timer,
217 jiffies + MSECS(10));
218 return;
219 }
220
221 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
222 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
224 if (!rtlhal->fw_clk_change_in_progress) {
225 rtlhal->fw_clk_change_in_progress = true;
226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
230 (u8 *)(&rpwm_val));
231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
232 rtlhal->fw_clk_change_in_progress = false;
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
234 } else {
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 mod_timer(&rtlpriv->works.fw_clockoff_timer,
237 jiffies + MSECS(10));
238 }
239 }
240 }
241
242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
243 {
244 u8 rpwm_val = 0;
245
246 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
247 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
248 }
249
250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
251 {
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
255 bool fw_current_inps = false;
256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
257
258 if (ppsc->low_power_enable) {
259 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
260 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
261 rtlhal->allow_sw_to_change_hwclc = false;
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 (u8 *)(&fw_pwrmode));
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
266 } else {
267 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
269 (u8 *)(&rpwm_val));
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
271 (u8 *)(&fw_pwrmode));
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
273 (u8 *)(&fw_current_inps));
274 }
275 }
276
277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
278 {
279 struct rtl_priv *rtlpriv = rtl_priv(hw);
280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
281 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
282 bool fw_current_inps = true;
283 u8 rpwm_val;
284
285 if (ppsc->low_power_enable) {
286 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
287 rtlpriv->cfg->ops->set_hw_reg(hw,
288 HW_VAR_FW_PSMODE_STATUS,
289 (u8 *)(&fw_current_inps));
290 rtlpriv->cfg->ops->set_hw_reg(hw,
291 HW_VAR_H2C_FW_PWRMODE,
292 (u8 *)(&ppsc->fwctrl_psmode));
293 rtlhal->allow_sw_to_change_hwclc = true;
294 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
295 } else {
296 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
297 rtlpriv->cfg->ops->set_hw_reg(hw,
298 HW_VAR_FW_PSMODE_STATUS,
299 (u8 *)(&fw_current_inps));
300 rtlpriv->cfg->ops->set_hw_reg(hw,
301 HW_VAR_H2C_FW_PWRMODE,
302 (u8 *)(&ppsc->fwctrl_psmode));
303 rtlpriv->cfg->ops->set_hw_reg(hw,
304 HW_VAR_SET_RPWM,
305 (u8 *)(&rpwm_val));
306 }
307 }
308
309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
310 bool dl_whole_packets)
311 {
312 struct rtl_priv *rtlpriv = rtl_priv(hw);
313 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
314 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
315 u8 count = 0, dlbcn_count = 0;
316 bool send_beacon = false;
317
318 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
319 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
320
321 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
322 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
323
324 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
325 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
326 tmp_reg422 & (~BIT(6)));
327 if (tmp_reg422 & BIT(6))
328 send_beacon = true;
329
330 do {
331 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
332 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
333 (bcnvalid_reg | BIT(0)));
334 _rtl8821ae_return_beacon_queue_skb(hw);
335
336 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
337 rtl8812ae_set_fw_rsvdpagepkt(hw, false,
338 dl_whole_packets);
339 else
340 rtl8821ae_set_fw_rsvdpagepkt(hw, false,
341 dl_whole_packets);
342
343 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
344 count = 0;
345 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
346 count++;
347 udelay(10);
348 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
349 }
350 dlbcn_count++;
351 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
352
353 if (!(bcnvalid_reg & BIT(0)))
354 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
355 "Download RSVD page failed!\n");
356 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
357 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
358 _rtl8821ae_return_beacon_queue_skb(hw);
359 if (send_beacon) {
360 dlbcn_count = 0;
361 do {
362 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
363 bcnvalid_reg | BIT(0));
364
365 _rtl8821ae_return_beacon_queue_skb(hw);
366
367 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
368 rtl8812ae_set_fw_rsvdpagepkt(hw, true,
369 false);
370 else
371 rtl8821ae_set_fw_rsvdpagepkt(hw, true,
372 false);
373
374 /* check rsvd page download OK. */
375 bcnvalid_reg = rtl_read_byte(rtlpriv,
376 REG_TDECTRL + 2);
377 count = 0;
378 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
379 count++;
380 udelay(10);
381 bcnvalid_reg =
382 rtl_read_byte(rtlpriv,
383 REG_TDECTRL + 2);
384 }
385 dlbcn_count++;
386 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
387
388 if (!(bcnvalid_reg & BIT(0)))
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
390 "2 Download RSVD page failed!\n");
391 }
392 }
393
394 if (bcnvalid_reg & BIT(0))
395 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
396
397 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
398 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
399
400 if (send_beacon)
401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
402
403 if (!rtlhal->enter_pnp_sleep) {
404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
406 }
407 }
408
409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
410 {
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
414 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
415
416 switch (variable) {
417 case HW_VAR_ETHER_ADDR:
418 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
419 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
420 break;
421 case HW_VAR_BSSID:
422 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
423 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
424 break;
425 case HW_VAR_MEDIA_STATUS:
426 val[0] = rtl_read_byte(rtlpriv, REG_CR+2) & 0x3;
427 break;
428 case HW_VAR_SLOT_TIME:
429 *((u8 *)(val)) = mac->slot_time;
430 break;
431 case HW_VAR_BEACON_INTERVAL:
432 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
433 break;
434 case HW_VAR_ATIM_WINDOW:
435 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
436 break;
437 case HW_VAR_RCR:
438 *((u32 *)(val)) = rtlpci->receive_config;
439 break;
440 case HW_VAR_RF_STATE:
441 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
442 break;
443 case HW_VAR_FWLPS_RF_ON:{
444 enum rf_pwrstate rfstate;
445 u32 val_rcr;
446
447 rtlpriv->cfg->ops->get_hw_reg(hw,
448 HW_VAR_RF_STATE,
449 (u8 *)(&rfstate));
450 if (rfstate == ERFOFF) {
451 *((bool *)(val)) = true;
452 } else {
453 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
454 val_rcr &= 0x00070000;
455 if (val_rcr)
456 *((bool *)(val)) = false;
457 else
458 *((bool *)(val)) = true;
459 }
460 break; }
461 case HW_VAR_FW_PSMODE_STATUS:
462 *((bool *)(val)) = ppsc->fw_current_inpsmode;
463 break;
464 case HW_VAR_CORRECT_TSF:{
465 u64 tsf;
466 u32 *ptsf_low = (u32 *)&tsf;
467 u32 *ptsf_high = ((u32 *)&tsf) + 1;
468
469 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
470 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
471
472 *((u64 *)(val)) = tsf;
473
474 break; }
475 case HAL_DEF_WOWLAN:
476 if (ppsc->wo_wlan_mode)
477 *((bool *)(val)) = true;
478 else
479 *((bool *)(val)) = false;
480 break;
481 default:
482 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
483 "switch case not process %x\n", variable);
484 break;
485 }
486 }
487
488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
489 {
490 struct rtl_priv *rtlpriv = rtl_priv(hw);
491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
492 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
493 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
494 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
496 u8 idx;
497
498 switch (variable) {
499 case HW_VAR_ETHER_ADDR:{
500 for (idx = 0; idx < ETH_ALEN; idx++) {
501 rtl_write_byte(rtlpriv, (REG_MACID + idx),
502 val[idx]);
503 }
504 break;
505 }
506 case HW_VAR_BASIC_RATE:{
507 u16 b_rate_cfg = ((u16 *)val)[0];
508 b_rate_cfg = b_rate_cfg & 0x15f;
509 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
510 break;
511 }
512 case HW_VAR_BSSID:{
513 for (idx = 0; idx < ETH_ALEN; idx++) {
514 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
515 val[idx]);
516 }
517 break;
518 }
519 case HW_VAR_SIFS:
520 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
521 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
522
523 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
524 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
525
526 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
527 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
528 break;
529 case HW_VAR_R2T_SIFS:
530 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
531 break;
532 case HW_VAR_SLOT_TIME:{
533 u8 e_aci;
534
535 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
536 "HW_VAR_SLOT_TIME %x\n", val[0]);
537
538 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
539
540 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
541 rtlpriv->cfg->ops->set_hw_reg(hw,
542 HW_VAR_AC_PARAM,
543 (u8 *)(&e_aci));
544 }
545 break; }
546 case HW_VAR_ACK_PREAMBLE:{
547 u8 reg_tmp;
548 u8 short_preamble = (bool)(*(u8 *)val);
549
550 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
551 if (short_preamble) {
552 reg_tmp |= BIT(1);
553 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
554 reg_tmp);
555 } else {
556 reg_tmp &= (~BIT(1));
557 rtl_write_byte(rtlpriv,
558 REG_TRXPTCL_CTL + 2,
559 reg_tmp);
560 }
561 break; }
562 case HW_VAR_WPA_CONFIG:
563 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
564 break;
565 case HW_VAR_AMPDU_MIN_SPACE:{
566 u8 min_spacing_to_set;
567 u8 sec_min_space;
568
569 min_spacing_to_set = *((u8 *)val);
570 if (min_spacing_to_set <= 7) {
571 sec_min_space = 0;
572
573 if (min_spacing_to_set < sec_min_space)
574 min_spacing_to_set = sec_min_space;
575
576 mac->min_space_cfg = ((mac->min_space_cfg &
577 0xf8) |
578 min_spacing_to_set);
579
580 *val = min_spacing_to_set;
581
582 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
583 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
584 mac->min_space_cfg);
585
586 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
587 mac->min_space_cfg);
588 }
589 break; }
590 case HW_VAR_SHORTGI_DENSITY:{
591 u8 density_to_set;
592
593 density_to_set = *((u8 *)val);
594 mac->min_space_cfg |= (density_to_set << 3);
595
596 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
597 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
598 mac->min_space_cfg);
599
600 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
601 mac->min_space_cfg);
602
603 break; }
604 case HW_VAR_AMPDU_FACTOR:{
605 u32 ampdu_len = (*((u8 *)val));
606
607 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
608 if (ampdu_len < VHT_AGG_SIZE_128K)
609 ampdu_len =
610 (0x2000 << (*((u8 *)val))) - 1;
611 else
612 ampdu_len = 0x1ffff;
613 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
614 if (ampdu_len < HT_AGG_SIZE_64K)
615 ampdu_len =
616 (0x2000 << (*((u8 *)val))) - 1;
617 else
618 ampdu_len = 0xffff;
619 }
620 ampdu_len |= BIT(31);
621
622 rtl_write_dword(rtlpriv,
623 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
624 break; }
625 case HW_VAR_AC_PARAM:{
626 u8 e_aci = *((u8 *)val);
627
628 rtl8821ae_dm_init_edca_turbo(hw);
629 if (rtlpci->acm_method != EACMWAY2_SW)
630 rtlpriv->cfg->ops->set_hw_reg(hw,
631 HW_VAR_ACM_CTRL,
632 (u8 *)(&e_aci));
633 break; }
634 case HW_VAR_ACM_CTRL:{
635 u8 e_aci = *((u8 *)val);
636 union aci_aifsn *p_aci_aifsn =
637 (union aci_aifsn *)(&mac->ac[0].aifs);
638 u8 acm = p_aci_aifsn->f.acm;
639 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
640
641 acm_ctrl =
642 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
643
644 if (acm) {
645 switch (e_aci) {
646 case AC0_BE:
647 acm_ctrl |= ACMHW_BEQEN;
648 break;
649 case AC2_VI:
650 acm_ctrl |= ACMHW_VIQEN;
651 break;
652 case AC3_VO:
653 acm_ctrl |= ACMHW_VOQEN;
654 break;
655 default:
656 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
657 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
658 acm);
659 break;
660 }
661 } else {
662 switch (e_aci) {
663 case AC0_BE:
664 acm_ctrl &= (~ACMHW_BEQEN);
665 break;
666 case AC2_VI:
667 acm_ctrl &= (~ACMHW_VIQEN);
668 break;
669 case AC3_VO:
670 acm_ctrl &= (~ACMHW_BEQEN);
671 break;
672 default:
673 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
674 "switch case not process\n");
675 break;
676 }
677 }
678
679 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
680 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
681 acm_ctrl);
682 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
683 break; }
684 case HW_VAR_RCR:
685 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
686 rtlpci->receive_config = ((u32 *)(val))[0];
687 break;
688 case HW_VAR_RETRY_LIMIT:{
689 u8 retry_limit = ((u8 *)(val))[0];
690
691 rtl_write_word(rtlpriv, REG_RL,
692 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
693 retry_limit << RETRY_LIMIT_LONG_SHIFT);
694 break; }
695 case HW_VAR_DUAL_TSF_RST:
696 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
697 break;
698 case HW_VAR_EFUSE_BYTES:
699 rtlefuse->efuse_usedbytes = *((u16 *)val);
700 break;
701 case HW_VAR_EFUSE_USAGE:
702 rtlefuse->efuse_usedpercentage = *((u8 *)val);
703 break;
704 case HW_VAR_IO_CMD:
705 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
706 break;
707 case HW_VAR_SET_RPWM:{
708 u8 rpwm_val;
709
710 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
711 udelay(1);
712
713 if (rpwm_val & BIT(7)) {
714 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
715 (*(u8 *)val));
716 } else {
717 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
718 ((*(u8 *)val) | BIT(7)));
719 }
720
721 break; }
722 case HW_VAR_H2C_FW_PWRMODE:
723 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
724 break;
725 case HW_VAR_FW_PSMODE_STATUS:
726 ppsc->fw_current_inpsmode = *((bool *)val);
727 break;
728 case HW_VAR_INIT_RTS_RATE:
729 break;
730 case HW_VAR_RESUME_CLK_ON:
731 _rtl8821ae_set_fw_ps_rf_on(hw);
732 break;
733 case HW_VAR_FW_LPS_ACTION:{
734 bool b_enter_fwlps = *((bool *)val);
735
736 if (b_enter_fwlps)
737 _rtl8821ae_fwlps_enter(hw);
738 else
739 _rtl8821ae_fwlps_leave(hw);
740 break; }
741 case HW_VAR_H2C_FW_JOINBSSRPT:{
742 u8 mstatus = (*(u8 *)val);
743
744 if (mstatus == RT_MEDIA_CONNECT) {
745 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
746 NULL);
747 _rtl8821ae_download_rsvd_page(hw, false);
748 }
749 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
750
751 break; }
752 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
753 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
754 break;
755 case HW_VAR_AID:{
756 u16 u2btmp;
757 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
758 u2btmp &= 0xC000;
759 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
760 mac->assoc_id));
761 break; }
762 case HW_VAR_CORRECT_TSF:{
763 u8 btype_ibss = ((u8 *)(val))[0];
764
765 if (btype_ibss)
766 _rtl8821ae_stop_tx_beacon(hw);
767
768 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
769
770 rtl_write_dword(rtlpriv, REG_TSFTR,
771 (u32)(mac->tsf & 0xffffffff));
772 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
773 (u32)((mac->tsf >> 32) & 0xffffffff));
774
775 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
776
777 if (btype_ibss)
778 _rtl8821ae_resume_tx_beacon(hw);
779 break; }
780 case HW_VAR_NAV_UPPER: {
781 u32 us_nav_upper = ((u32)*val);
782
783 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
784 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
785 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
786 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
787 break;
788 }
789 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
790 ((u8)((us_nav_upper +
791 HAL_92C_NAV_UPPER_UNIT - 1) /
792 HAL_92C_NAV_UPPER_UNIT)));
793 break; }
794 case HW_VAR_KEEP_ALIVE: {
795 u8 array[2];
796 array[0] = 0xff;
797 array[1] = *((u8 *)val);
798 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
799 array);
800 break; }
801 default:
802 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
803 "switch case not process %x\n", variable);
804 break;
805 }
806 }
807
808 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
809 {
810 struct rtl_priv *rtlpriv = rtl_priv(hw);
811 bool status = true;
812 long count = 0;
813 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
814 _LLT_OP(_LLT_WRITE_ACCESS);
815
816 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
817
818 do {
819 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
820 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
821 break;
822
823 if (count > POLLING_LLT_THRESHOLD) {
824 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
825 "Failed to polling write LLT done at address %d!\n",
826 address);
827 status = false;
828 break;
829 }
830 } while (++count);
831
832 return status;
833 }
834
835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
836 {
837 struct rtl_priv *rtlpriv = rtl_priv(hw);
838 unsigned short i;
839 u8 txpktbuf_bndy;
840 u32 rqpn;
841 u8 maxpage;
842 bool status;
843
844 maxpage = 255;
845 txpktbuf_bndy = 0xF8;
846 rqpn = 0x80e70808;
847 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
848 txpktbuf_bndy = 0xFA;
849 rqpn = 0x80e90808;
850 }
851
852 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
853 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
854
855 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
856
857 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
858 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
859
860 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
861 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
862
863 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
864 status = _rtl8821ae_llt_write(hw, i, i + 1);
865 if (!status)
866 return status;
867 }
868
869 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
870 if (!status)
871 return status;
872
873 for (i = txpktbuf_bndy; i < maxpage; i++) {
874 status = _rtl8821ae_llt_write(hw, i, (i + 1));
875 if (!status)
876 return status;
877 }
878
879 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
880 if (!status)
881 return status;
882
883 rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
884
885 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
886
887 return true;
888 }
889
890 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
891 {
892 struct rtl_priv *rtlpriv = rtl_priv(hw);
893 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
894 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
895 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
896 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
897
898 if (rtlpriv->rtlhal.up_first_time)
899 return;
900
901 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
902 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
903 rtl8812ae_sw_led_on(hw, pled0);
904 else
905 rtl8821ae_sw_led_on(hw, pled0);
906 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
907 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
908 rtl8812ae_sw_led_on(hw, pled0);
909 else
910 rtl8821ae_sw_led_on(hw, pled0);
911 else
912 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
913 rtl8812ae_sw_led_off(hw, pled0);
914 else
915 rtl8821ae_sw_led_off(hw, pled0);
916 }
917
918 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
919 {
920 struct rtl_priv *rtlpriv = rtl_priv(hw);
921 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
923
924 u8 bytetmp = 0;
925 u16 wordtmp = 0;
926 bool mac_func_enable = rtlhal->mac_func_enable;
927
928 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
929
930 /*Auto Power Down to CHIP-off State*/
931 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
932 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
933
934 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
935 /* HW Power on sequence*/
936 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
937 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
938 RTL8812_NIC_ENABLE_FLOW)) {
939 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
940 "init 8812 MAC Fail as power on failure\n");
941 return false;
942 }
943 } else {
944 /* HW Power on sequence */
945 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
946 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
947 RTL8821A_NIC_ENABLE_FLOW)){
948 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
949 "init 8821 MAC Fail as power on failure\n");
950 return false;
951 }
952 }
953
954 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
955 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
956
957 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
958 bytetmp = 0xff;
959 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
960 mdelay(2);
961
962 bytetmp = 0xff;
963 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
964 mdelay(2);
965
966 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
967 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
968 if (bytetmp & BIT(0)) {
969 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
970 bytetmp |= BIT(6);
971 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
972 }
973 }
974
975 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
976 bytetmp &= ~BIT(4);
977 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
978
979 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
980
981 if (!mac_func_enable) {
982 if (!_rtl8821ae_llt_table_init(hw))
983 return false;
984 }
985
986 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
987 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
988
989 /* Enable FW Beamformer Interrupt */
990 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
991 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
992
993 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
994 wordtmp &= 0xf;
995 wordtmp |= 0xF5B1;
996 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
997
998 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
999 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1000 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1001 /*low address*/
1002 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1003 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1004 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1005 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1006 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1007 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1008 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1009 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1010 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1011 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1012 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1013 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1014 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1015 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1016 rtl_write_dword(rtlpriv, REG_RX_DESA,
1017 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1018
1019 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1020
1021 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1022
1023 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1024
1025 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1026 _rtl8821ae_gen_refresh_led_state(hw);
1027
1028 return true;
1029 }
1030
1031 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1032 {
1033 struct rtl_priv *rtlpriv = rtl_priv(hw);
1034 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1035 u32 reg_rrsr;
1036
1037 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1038
1039 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1040 /* ARFB table 9 for 11ac 5G 2SS */
1041 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1042 /* ARFB table 10 for 11ac 5G 1SS */
1043 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1044 /* ARFB table 11 for 11ac 24G 1SS */
1045 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1046 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1047 /* ARFB table 12 for 11ac 24G 1SS */
1048 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1049 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1050 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1051 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1052 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1053
1054 /*Set retry limit*/
1055 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1056
1057 /* Set Data / Response auto rate fallack retry count*/
1058 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1059 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1060 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1061 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1062
1063 rtlpci->reg_bcn_ctrl_val = 0x1d;
1064 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1065
1066 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1067 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1068
1069 /* AGGR_BK_TIME Reg51A 0x16 */
1070 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1071
1072 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1073 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1074
1075 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1076 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1077 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1078 }
1079
1080 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1081 {
1082 u16 ret = 0;
1083 u8 tmp = 0, count = 0;
1084
1085 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1086 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1087 count = 0;
1088 while (tmp && count < 20) {
1089 udelay(10);
1090 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1091 count++;
1092 }
1093 if (0 == tmp)
1094 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1095
1096 return ret;
1097 }
1098
1099 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1100 {
1101 u8 tmp = 0, count = 0;
1102
1103 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1104 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1105 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1106 count = 0;
1107 while (tmp && count < 20) {
1108 udelay(10);
1109 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1110 count++;
1111 }
1112 }
1113
1114 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1115 {
1116 u16 read_addr = addr & 0xfffc;
1117 u8 tmp = 0, count = 0, ret = 0;
1118
1119 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1120 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1121 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1122 count = 0;
1123 while (tmp && count < 20) {
1124 udelay(10);
1125 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1126 count++;
1127 }
1128 if (0 == tmp) {
1129 read_addr = REG_DBI_RDATA + addr % 4;
1130 ret = rtl_read_word(rtlpriv, read_addr);
1131 }
1132 return ret;
1133 }
1134
1135 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1136 {
1137 u8 tmp = 0, count = 0;
1138 u16 wrtie_addr, remainder = addr % 4;
1139
1140 wrtie_addr = REG_DBI_WDATA + remainder;
1141 rtl_write_byte(rtlpriv, wrtie_addr, data);
1142
1143 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1144 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1145
1146 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1147
1148 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1149 count = 0;
1150 while (tmp && count < 20) {
1151 udelay(10);
1152 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1153 count++;
1154 }
1155 }
1156
1157 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1158 {
1159 struct rtl_priv *rtlpriv = rtl_priv(hw);
1160 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1161 u8 tmp;
1162
1163 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1164 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1165 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1166
1167 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1168 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1169 }
1170
1171 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1172 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1173
1174 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1175 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1176
1177 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1178 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1179 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1180 }
1181 }
1182
1183 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1184 {
1185 struct rtl_priv *rtlpriv = rtl_priv(hw);
1186 u8 sec_reg_value;
1187 u8 tmp;
1188
1189 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1190 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1191 rtlpriv->sec.pairwise_enc_algorithm,
1192 rtlpriv->sec.group_enc_algorithm);
1193
1194 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1195 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1196 "not open hw encryption\n");
1197 return;
1198 }
1199
1200 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1201
1202 if (rtlpriv->sec.use_defaultkey) {
1203 sec_reg_value |= SCR_TXUSEDK;
1204 sec_reg_value |= SCR_RXUSEDK;
1205 }
1206
1207 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1208
1209 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1210 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1211
1212 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1213 "The SECR-value %x\n", sec_reg_value);
1214
1215 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1216 }
1217
1218 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1219 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1220 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1221 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1222 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1223 /* ----------------------------------------------------------- */
1224
1225 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1226 {
1227 struct rtl_priv *rtlpriv = rtl_priv(hw);
1228 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1229 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1230 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1231
1232 rtlpriv->cfg->ops->set_hw_reg(hw,
1233 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1234
1235 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1236 "Initialize MacId media status: from %d to %d\n",
1237 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1238 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1239 }
1240
1241 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1242 {
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 u8 tmp;
1245
1246 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1247 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1248 if (!(tmp & BIT(2))) {
1249 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1250 mdelay(100);
1251 }
1252
1253 /* read reg 0x350 Bit[25] if 1 : RX hang */
1254 /* read reg 0x350 Bit[24] if 1 : TX hang */
1255 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1256 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1257 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1258 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1259 return true;
1260 } else {
1261 return false;
1262 }
1263 }
1264
1265 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1266 bool mac_power_on,
1267 bool in_watchdog)
1268 {
1269 struct rtl_priv *rtlpriv = rtl_priv(hw);
1270 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1271 u8 tmp;
1272 bool release_mac_rx_pause;
1273 u8 backup_pcie_dma_pause;
1274
1275 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1276
1277 /* 1. Disable register write lock. 0x1c[1] = 0 */
1278 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1279 tmp &= ~(BIT(1));
1280 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1281 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1282 /* write 0xCC bit[2] = 1'b1 */
1283 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1284 tmp |= BIT(2);
1285 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1286 }
1287
1288 /* 2. Check and pause TRX DMA */
1289 /* write 0x284 bit[18] = 1'b1 */
1290 /* write 0x301 = 0xFF */
1291 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1292 if (tmp & BIT(2)) {
1293 /* Already pause before the function for another purpose. */
1294 release_mac_rx_pause = false;
1295 } else {
1296 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1297 release_mac_rx_pause = true;
1298 }
1299 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1300 if (backup_pcie_dma_pause != 0xFF)
1301 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1302
1303 if (mac_power_on) {
1304 /* 3. reset TRX function */
1305 /* write 0x100 = 0x00 */
1306 rtl_write_byte(rtlpriv, REG_CR, 0);
1307 }
1308
1309 /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1310 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1311 tmp &= ~(BIT(0));
1312 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1313
1314 /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1315 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1316 tmp |= BIT(0);
1317 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1318
1319 if (mac_power_on) {
1320 /* 6. enable TRX function */
1321 /* write 0x100 = 0xFF */
1322 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1323
1324 /* We should init LLT & RQPN and
1325 * prepare Tx/Rx descrptor address later
1326 * because MAC function is reset.*/
1327 }
1328
1329 /* 7. Restore PCIe autoload down bit */
1330 /* 8812AE does not has the defination. */
1331 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1332 /* write 0xF8 bit[17] = 1'b1 */
1333 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1334 tmp |= BIT(1);
1335 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1336 }
1337
1338 /* In MAC power on state, BB and RF maybe in ON state,
1339 * if we release TRx DMA here.
1340 * it will cause packets to be started to Tx/Rx,
1341 * so we release Tx/Rx DMA later.*/
1342 if (!mac_power_on/* || in_watchdog*/) {
1343 /* 8. release TRX DMA */
1344 /* write 0x284 bit[18] = 1'b0 */
1345 /* write 0x301 = 0x00 */
1346 if (release_mac_rx_pause) {
1347 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1348 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1349 tmp & (~BIT(2)));
1350 }
1351 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1352 backup_pcie_dma_pause);
1353 }
1354
1355 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1356 /* 9. lock system register */
1357 /* write 0xCC bit[2] = 1'b0 */
1358 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1359 tmp &= ~(BIT(2));
1360 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1361 }
1362 return true;
1363 }
1364
1365 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1366 {
1367 struct rtl_priv *rtlpriv = rtl_priv(hw);
1368 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1369 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1370 u8 fw_reason = 0;
1371 struct timeval ts;
1372
1373 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1374
1375 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1376 fw_reason);
1377
1378 ppsc->wakeup_reason = 0;
1379
1380 rtlhal->last_suspend_sec = ts.tv_sec;
1381
1382 switch (fw_reason) {
1383 case FW_WOW_V2_PTK_UPDATE_EVENT:
1384 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1385 do_gettimeofday(&ts);
1386 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1387 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1388 "It's a WOL PTK Key update event!\n");
1389 break;
1390 case FW_WOW_V2_GTK_UPDATE_EVENT:
1391 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1392 do_gettimeofday(&ts);
1393 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1394 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1395 "It's a WOL GTK Key update event!\n");
1396 break;
1397 case FW_WOW_V2_DISASSOC_EVENT:
1398 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1399 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1400 "It's a disassociation event!\n");
1401 break;
1402 case FW_WOW_V2_DEAUTH_EVENT:
1403 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1404 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1405 "It's a deauth event!\n");
1406 break;
1407 case FW_WOW_V2_FW_DISCONNECT_EVENT:
1408 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1409 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1410 "It's a Fw disconnect decision (AP lost) event!\n");
1411 break;
1412 case FW_WOW_V2_MAGIC_PKT_EVENT:
1413 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1414 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1415 "It's a magic packet event!\n");
1416 break;
1417 case FW_WOW_V2_UNICAST_PKT_EVENT:
1418 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1419 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1420 "It's an unicast packet event!\n");
1421 break;
1422 case FW_WOW_V2_PATTERN_PKT_EVENT:
1423 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1424 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1425 "It's a pattern match event!\n");
1426 break;
1427 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1428 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1429 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1430 "It's an RTD3 Ssid match event!\n");
1431 break;
1432 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1433 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1434 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1435 "It's an RealWoW wake packet event!\n");
1436 break;
1437 case FW_WOW_V2_REALWOW_V2_ACKLOST:
1438 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1439 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1440 "It's an RealWoW ack lost event!\n");
1441 break;
1442 default:
1443 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1444 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1445 fw_reason);
1446 break;
1447 }
1448 }
1449
1450 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1451 {
1452 struct rtl_priv *rtlpriv = rtl_priv(hw);
1453 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1454
1455 /*low address*/
1456 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1457 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1458 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1459 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1460 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1461 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1462 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1463 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1464 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1465 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1466 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1467 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1468 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1469 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1470 rtl_write_dword(rtlpriv, REG_RX_DESA,
1471 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1472 }
1473
1474 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1475 {
1476 bool status = true;
1477 u32 i;
1478 u32 txpktbuf_bndy = boundary;
1479 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1480
1481 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1482 status = _rtl8821ae_llt_write(hw, i , i + 1);
1483 if (!status)
1484 return status;
1485 }
1486
1487 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1488 if (!status)
1489 return status;
1490
1491 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1492 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1493 if (!status)
1494 return status;
1495 }
1496
1497 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1498 txpktbuf_bndy);
1499 if (!status)
1500 return status;
1501
1502 return status;
1503 }
1504
1505 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1506 u16 npq_rqpn_value, u32 rqpn_val)
1507 {
1508 struct rtl_priv *rtlpriv = rtl_priv(hw);
1509 u8 tmp;
1510 bool ret = true;
1511 u16 count = 0, tmp16;
1512 bool support_remote_wakeup;
1513
1514 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1515 (u8 *)(&support_remote_wakeup));
1516
1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1518 "boundary=0x%#X, NPQ_RQPNValue=0x%#X, RQPNValue=0x%#X\n",
1519 boundary, npq_rqpn_value, rqpn_val);
1520
1521 /* stop PCIe DMA
1522 * 1. 0x301[7:0] = 0xFE */
1523 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1524
1525 /* wait TXFF empty
1526 * 2. polling till 0x41A[15:0]=0x07FF */
1527 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1528 while ((tmp16 & 0x07FF) != 0x07FF) {
1529 udelay(100);
1530 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1531 count++;
1532 if ((count % 200) == 0) {
1533 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1534 "Tx queue is not empty for 20ms!\n");
1535 }
1536 if (count >= 1000) {
1537 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1538 "Wait for Tx FIFO empty timeout!\n");
1539 break;
1540 }
1541 }
1542
1543 /* TX pause
1544 * 3. reg 0x522=0xFF */
1545 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1546
1547 /* Wait TX State Machine OK
1548 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1549 count = 0;
1550 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1551 udelay(100);
1552 count++;
1553 if (count >= 500) {
1554 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1555 "Wait for TX State Machine ready timeout !!\n");
1556 break;
1557 }
1558 }
1559
1560 /* stop RX DMA path
1561 * 5. 0x284[18] = 1
1562 * 6. wait till 0x284[17] == 1
1563 * wait RX DMA idle */
1564 count = 0;
1565 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1566 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1567 do {
1568 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1569 udelay(10);
1570 count++;
1571 } while (!(tmp & BIT(1)) && count < 100);
1572
1573 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1574 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1575 count, tmp);
1576
1577 /* reset BB
1578 * 7. 0x02 [0] = 0 */
1579 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1580 tmp &= ~(BIT(0));
1581 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1582
1583 /* Reset TRX MAC
1584 * 8. 0x100 = 0x00
1585 * Delay (1ms) */
1586 rtl_write_byte(rtlpriv, REG_CR, 0x00);
1587 udelay(1000);
1588
1589 /* Disable MAC Security Engine
1590 * 9. 0x100 bit[9]=0 */
1591 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1592 tmp &= ~(BIT(1));
1593 rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1594
1595 /* To avoid DD-Tim Circuit hang
1596 * 10. 0x553 bit[5]=1 */
1597 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1598 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1599
1600 /* Enable MAC Security Engine
1601 * 11. 0x100 bit[9]=1 */
1602 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1603 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1604
1605 /* Enable TRX MAC
1606 * 12. 0x100 = 0xFF
1607 * Delay (1ms) */
1608 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1609 udelay(1000);
1610
1611 /* Enable BB
1612 * 13. 0x02 [0] = 1 */
1613 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1614 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1615
1616 /* beacon setting
1617 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1618 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1619 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1620 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1621
1622 /* 16. WMAC_LBK_BF_HD 0x45D[7:0]
1623 * WMAC_LBK_BF_HD */
1624 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1625 (u8)boundary);
1626
1627 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1628
1629 /* init LLT
1630 * 17. init LLT */
1631 if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1632 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1633 "Failed to init LLT table!\n");
1634 return false;
1635 }
1636
1637 /* reallocate RQPN
1638 * 18. reallocate RQPN and init LLT */
1639 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1640 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1641
1642 /* release Tx pause
1643 * 19. 0x522=0x00 */
1644 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1645
1646 /* enable PCIE DMA
1647 * 20. 0x301[7:0] = 0x00
1648 * 21. 0x284[18] = 0 */
1649 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1650 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1651 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1652
1653 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1654 return ret;
1655 }
1656
1657 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1658 {
1659 struct rtl_priv *rtlpriv = rtl_priv(hw);
1660 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1661 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1662
1663 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1664 /* Re-download normal Fw. */
1665 rtl8821ae_set_fw_related_for_wowlan(hw, false);
1666 #endif
1667
1668 /* Re-Initialize LLT table. */
1669 if (rtlhal->re_init_llt_table) {
1670 u32 rqpn = 0x80e70808;
1671 u8 rqpn_npq = 0, boundary = 0xF8;
1672 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1673 rqpn = 0x80e90808;
1674 boundary = 0xFA;
1675 }
1676 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1677 rtlhal->re_init_llt_table = false;
1678 }
1679
1680 ppsc->rfpwr_state = ERFON;
1681 }
1682
1683 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1684 {
1685 u8 tmp = 0;
1686 struct rtl_priv *rtlpriv = rtl_priv(hw);
1687
1688 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1689
1690 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1691 if (!(tmp & (BIT(2) | BIT(3)))) {
1692 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1693 "0x160(%#x)return!!\n", tmp);
1694 return;
1695 }
1696
1697 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1698 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1699
1700 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1701 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1702
1703 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1704 }
1705
1706 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1707 {
1708 u8 tmp = 0;
1709 struct rtl_priv *rtlpriv = rtl_priv(hw);
1710
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1712
1713 /* Check 0x98[10] */
1714 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1715 if (!(tmp & BIT(2))) {
1716 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1717 "<---0x99(%#x) return!!\n", tmp);
1718 return;
1719 }
1720
1721 /* LTR idle latency, 0x90 for 144us */
1722 rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1723
1724 /* LTR active latency, 0x3c for 60us */
1725 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1726
1727 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1728 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1729
1730 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1731 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1732 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1733
1734 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1735 }
1736
1737 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1738 {
1739 struct rtl_priv *rtlpriv = rtl_priv(hw);
1740 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1741 bool init_finished = true;
1742 u8 tmp = 0;
1743
1744 /* Get Fw wake up reason. */
1745 _rtl8821ae_get_wakeup_reason(hw);
1746
1747 /* Patch Pcie Rx DMA hang after S3/S4 several times.
1748 * The root cause has not be found. */
1749 if (_rtl8821ae_check_pcie_dma_hang(hw))
1750 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1751
1752 /* Prepare Tx/Rx Desc Hw address. */
1753 _rtl8821ae_init_trx_desc_hw_address(hw);
1754
1755 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1756 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1757 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1758
1759 /* Check wake up event.
1760 * We should check wake packet bit before disable wowlan by H2C or
1761 * Fw will clear the bit. */
1762 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1763 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1764 "Read REG_FTISR 0x13f = %#X\n", tmp);
1765
1766 /* Set the WoWLAN related function control disable. */
1767 rtl8821ae_set_fw_wowlan_mode(hw, false);
1768 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1769
1770 if (rtlhal->hw_rof_enable) {
1771 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1772 if (tmp & BIT(1)) {
1773 /* Clear GPIO9 ISR */
1774 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1775 init_finished = false;
1776 } else {
1777 init_finished = true;
1778 }
1779 }
1780
1781 if (init_finished) {
1782 _rtl8821ae_simple_initialize_adapter(hw);
1783
1784 /* Release Pcie Interface Tx DMA. */
1785 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1786 /* Release Pcie RX DMA */
1787 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1788
1789 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1790 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1791
1792 _rtl8821ae_enable_l1off(hw);
1793 _rtl8821ae_enable_ltr(hw);
1794 }
1795
1796 return init_finished;
1797 }
1798
1799 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1800 {
1801 /* BB OFDM RX Path_A */
1802 rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1803 /* BB OFDM TX Path_A */
1804 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1805 /* BB CCK R/Rx Path_A */
1806 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1807 /* MCS support */
1808 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1809 /* RF Path_B HSSI OFF */
1810 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1811 /* RF Path_B Power Down */
1812 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1813 /* ADDA Path_B OFF */
1814 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1815 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1816 }
1817
1818 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1819 {
1820 struct rtl_priv *rtlpriv = rtl_priv(hw);
1821 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1822 u8 u1b_tmp;
1823
1824 rtlhal->mac_func_enable = false;
1825
1826 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1827 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1828 /* 1. Run LPS WL RFOFF flow */
1829 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1830 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1831 */
1832 rtl_hal_pwrseqcmdparsing(rtlpriv,
1833 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1834 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1835 }
1836 /* 2. 0x1F[7:0] = 0 */
1837 /* turn off RF */
1838 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1839 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1840 rtlhal->fw_ready) {
1841 rtl8821ae_firmware_selfreset(hw);
1842 }
1843
1844 /* Reset MCU. Suggested by Filen. */
1845 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1846 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1847
1848 /* g. MCUFWDL 0x80[1:0]=0 */
1849 /* reset MCU ready status */
1850 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1851
1852 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1853 /* HW card disable configuration. */
1854 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1855 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1856 } else {
1857 /* HW card disable configuration. */
1858 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1859 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1860 }
1861
1862 /* Reset MCU IO Wrapper */
1863 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1864 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1865 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1866 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1867
1868 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1869 /* lock ISO/CLK/Power control register */
1870 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1871 }
1872
1873 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1874 {
1875 struct rtl_priv *rtlpriv = rtl_priv(hw);
1876 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1877 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1878 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1879 bool rtstatus = true;
1880 int err;
1881 u8 tmp_u1b;
1882 bool support_remote_wakeup;
1883 u32 nav_upper = WIFI_NAV_UPPER_US;
1884
1885 rtlhal->being_init_adapter = true;
1886 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1887 (u8 *)(&support_remote_wakeup));
1888 rtlpriv->intf_ops->disable_aspm(hw);
1889
1890 /*YP wowlan not considered*/
1891
1892 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1893 if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1894 rtlhal->mac_func_enable = true;
1895 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1896 "MAC has already power on.\n");
1897 } else {
1898 rtlhal->mac_func_enable = false;
1899 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1900 }
1901
1902 if (support_remote_wakeup &&
1903 rtlhal->wake_from_pnp_sleep &&
1904 rtlhal->mac_func_enable) {
1905 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1906 rtlhal->being_init_adapter = false;
1907 return 0;
1908 }
1909 }
1910
1911 if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1912 _rtl8821ae_reset_pcie_interface_dma(hw,
1913 rtlhal->mac_func_enable,
1914 false);
1915 rtlhal->mac_func_enable = false;
1916 }
1917
1918 /* Reset MAC/BB/RF status if it is not powered off
1919 * before calling initialize Hw flow to prevent
1920 * from interface and MAC status mismatch.
1921 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1922 if (rtlhal->mac_func_enable) {
1923 _rtl8821ae_poweroff_adapter(hw);
1924 rtlhal->mac_func_enable = false;
1925 }
1926
1927 rtstatus = _rtl8821ae_init_mac(hw);
1928 if (rtstatus != true) {
1929 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1930 err = 1;
1931 return err;
1932 }
1933
1934 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1935 tmp_u1b &= 0x7F;
1936 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1937
1938 err = rtl8821ae_download_fw(hw, false);
1939 if (err) {
1940 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1941 "Failed to download FW. Init HW without FW now\n");
1942 err = 1;
1943 rtlhal->fw_ready = false;
1944 return err;
1945 } else {
1946 rtlhal->fw_ready = true;
1947 }
1948 ppsc->fw_current_inpsmode = false;
1949 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1950 rtlhal->fw_clk_change_in_progress = false;
1951 rtlhal->allow_sw_to_change_hwclc = false;
1952 rtlhal->last_hmeboxnum = 0;
1953
1954 /*SIC_Init(Adapter);
1955 if(rtlhal->AMPDUBurstMode)
1956 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1957
1958 rtl8821ae_phy_mac_config(hw);
1959 /* because last function modify RCR, so we update
1960 * rcr var here, or TP will unstable for receive_config
1961 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1962 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1963 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1964 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1965 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1966 rtl8821ae_phy_bb_config(hw);
1967
1968 rtl8821ae_phy_rf_config(hw);
1969
1970 if (rtlpriv->phy.rf_type == RF_1T1R &&
1971 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1972 _rtl8812ae_bb8812_config_1t(hw);
1973
1974 _rtl8821ae_hw_configure(hw);
1975
1976 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1977
1978 /*set wireless mode*/
1979
1980 rtlhal->mac_func_enable = true;
1981
1982 rtl_cam_reset_all_entry(hw);
1983
1984 rtl8821ae_enable_hw_security_config(hw);
1985
1986 ppsc->rfpwr_state = ERFON;
1987
1988 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1989 _rtl8821ae_enable_aspm_back_door(hw);
1990 rtlpriv->intf_ops->enable_aspm(hw);
1991
1992 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1993 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1994 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1995
1996 rtl8821ae_bt_hw_init(hw);
1997 rtlpriv->rtlhal.being_init_adapter = false;
1998
1999 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2000
2001 /* rtl8821ae_dm_check_txpower_tracking(hw); */
2002 /* rtl8821ae_phy_lc_calibrate(hw); */
2003 if (support_remote_wakeup)
2004 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2005
2006 /* Release Rx DMA*/
2007 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2008 if (tmp_u1b & BIT(2)) {
2009 /* Release Rx DMA if needed*/
2010 tmp_u1b &= ~BIT(2);
2011 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2012 }
2013
2014 /* Release Tx/Rx PCIE DMA if*/
2015 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2016
2017 rtl8821ae_dm_init(hw);
2018 rtl8821ae_macid_initialize_mediastatus(hw);
2019
2020 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2021 return err;
2022 }
2023
2024 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2025 {
2026 struct rtl_priv *rtlpriv = rtl_priv(hw);
2027 struct rtl_phy *rtlphy = &rtlpriv->phy;
2028 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2029 enum version_8821ae version = VERSION_UNKNOWN;
2030 u32 value32;
2031
2032 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2033 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2034 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2035
2036 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2037 rtlphy->rf_type = RF_2T2R;
2038 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2039 rtlphy->rf_type = RF_1T1R;
2040
2041 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2042 "RF_Type is %x!!\n", rtlphy->rf_type);
2043
2044 if (value32 & TRP_VAUX_EN) {
2045 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2046 if (rtlphy->rf_type == RF_2T2R)
2047 version = VERSION_TEST_CHIP_2T2R_8812;
2048 else
2049 version = VERSION_TEST_CHIP_1T1R_8812;
2050 } else
2051 version = VERSION_TEST_CHIP_8821;
2052 } else {
2053 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2054 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2055
2056 if (rtlphy->rf_type == RF_2T2R)
2057 version =
2058 (enum version_8821ae)(CHIP_8812
2059 | NORMAL_CHIP |
2060 RF_TYPE_2T2R);
2061 else
2062 version = (enum version_8821ae)(CHIP_8812
2063 | NORMAL_CHIP);
2064
2065 version = (enum version_8821ae)(version | (rtl_id << 12));
2066 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2067 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2068
2069 version = (enum version_8821ae)(CHIP_8821
2070 | NORMAL_CHIP | rtl_id);
2071 }
2072 }
2073
2074 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2075 /*WL_HWROF_EN.*/
2076 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2077 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2078 }
2079
2080 switch (version) {
2081 case VERSION_TEST_CHIP_1T1R_8812:
2082 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2083 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2084 break;
2085 case VERSION_TEST_CHIP_2T2R_8812:
2086 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2087 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2088 break;
2089 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2090 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2092 break;
2093 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2094 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2096 break;
2097 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2098 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2099 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2100 break;
2101 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2104 break;
2105 case VERSION_TEST_CHIP_8821:
2106 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2108 break;
2109 case VERSION_NORMAL_TSMC_CHIP_8821:
2110 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2112 break;
2113 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2114 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2115 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2116 break;
2117 default:
2118 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2119 "Chip Version ID: Unknow (0x%X)\n", version);
2120 break;
2121 }
2122
2123 return version;
2124 }
2125
2126 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2127 enum nl80211_iftype type)
2128 {
2129 struct rtl_priv *rtlpriv = rtl_priv(hw);
2130 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2131 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2132 bt_msr &= 0xfc;
2133
2134 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2135 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2136 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2137
2138 if (type == NL80211_IFTYPE_UNSPECIFIED ||
2139 type == NL80211_IFTYPE_STATION) {
2140 _rtl8821ae_stop_tx_beacon(hw);
2141 _rtl8821ae_enable_bcn_sub_func(hw);
2142 } else if (type == NL80211_IFTYPE_ADHOC ||
2143 type == NL80211_IFTYPE_AP) {
2144 _rtl8821ae_resume_tx_beacon(hw);
2145 _rtl8821ae_disable_bcn_sub_func(hw);
2146 } else {
2147 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2148 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2149 type);
2150 }
2151
2152 switch (type) {
2153 case NL80211_IFTYPE_UNSPECIFIED:
2154 bt_msr |= MSR_NOLINK;
2155 ledaction = LED_CTL_LINK;
2156 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2157 "Set Network type to NO LINK!\n");
2158 break;
2159 case NL80211_IFTYPE_ADHOC:
2160 bt_msr |= MSR_ADHOC;
2161 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2162 "Set Network type to Ad Hoc!\n");
2163 break;
2164 case NL80211_IFTYPE_STATION:
2165 bt_msr |= MSR_INFRA;
2166 ledaction = LED_CTL_LINK;
2167 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2168 "Set Network type to STA!\n");
2169 break;
2170 case NL80211_IFTYPE_AP:
2171 bt_msr |= MSR_AP;
2172 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2173 "Set Network type to AP!\n");
2174 break;
2175 default:
2176 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2177 "Network type %d not support!\n", type);
2178 return 1;
2179 }
2180
2181 rtl_write_byte(rtlpriv, (MSR), bt_msr);
2182 rtlpriv->cfg->ops->led_control(hw, ledaction);
2183 if ((bt_msr & 0xfc) == MSR_AP)
2184 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2185 else
2186 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2187
2188 return 0;
2189 }
2190
2191 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2192 {
2193 struct rtl_priv *rtlpriv = rtl_priv(hw);
2194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2195 u32 reg_rcr = rtlpci->receive_config;
2196
2197 if (rtlpriv->psc.rfpwr_state != ERFON)
2198 return;
2199
2200 if (check_bssid) {
2201 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2202 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2203 (u8 *)(&reg_rcr));
2204 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2205 } else if (!check_bssid) {
2206 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2207 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2208 rtlpriv->cfg->ops->set_hw_reg(hw,
2209 HW_VAR_RCR, (u8 *)(&reg_rcr));
2210 }
2211 }
2212
2213 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2214 {
2215 struct rtl_priv *rtlpriv = rtl_priv(hw);
2216
2217 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2218
2219 if (_rtl8821ae_set_media_status(hw, type))
2220 return -EOPNOTSUPP;
2221
2222 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2223 if (type != NL80211_IFTYPE_AP)
2224 rtl8821ae_set_check_bssid(hw, true);
2225 } else {
2226 rtl8821ae_set_check_bssid(hw, false);
2227 }
2228
2229 return 0;
2230 }
2231
2232 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2233 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2234 {
2235 struct rtl_priv *rtlpriv = rtl_priv(hw);
2236 rtl8821ae_dm_init_edca_turbo(hw);
2237 switch (aci) {
2238 case AC1_BK:
2239 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2240 break;
2241 case AC0_BE:
2242 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2243 break;
2244 case AC2_VI:
2245 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2246 break;
2247 case AC3_VO:
2248 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2249 break;
2250 default:
2251 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2252 break;
2253 }
2254 }
2255
2256 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2257 {
2258 struct rtl_priv *rtlpriv = rtl_priv(hw);
2259 u32 tmp;
2260 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2261 /*printk("clear interrupt first:\n");
2262 printk("0x%x = 0x%08x\n",REG_HISR, tmp);*/
2263 rtl_write_dword(rtlpriv, REG_HISR, tmp);
2264
2265 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2266 /*printk("0x%x = 0x%08x\n",REG_HISRE, tmp);*/
2267 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2268
2269 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2270 /*printk("0x%x = 0x%08x\n",REG_HSISR, tmp);*/
2271 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2272 }
2273
2274 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2275 {
2276 struct rtl_priv *rtlpriv = rtl_priv(hw);
2277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2278
2279 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2280
2281 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2282 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2283 rtlpci->irq_enabled = true;
2284 /* there are some C2H CMDs have been sent before
2285 system interrupt is enabled, e.g., C2H, CPWM.
2286 *So we need to clear all C2H events that FW has
2287 notified, otherwise FW won't schedule any commands anymore.
2288 */
2289 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2290 /*enable system interrupt*/
2291 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2292 }
2293
2294 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2295 {
2296 struct rtl_priv *rtlpriv = rtl_priv(hw);
2297 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2298
2299 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2300 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2301 rtlpci->irq_enabled = false;
2302 /*synchronize_irq(rtlpci->pdev->irq);*/
2303 }
2304
2305 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2306 {
2307 struct rtl_priv *rtlpriv = rtl_priv(hw);
2308 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2309 u16 cap_hdr;
2310 u8 cap_pointer;
2311 u8 cap_id = 0xff;
2312 u8 pmcs_reg;
2313 u8 cnt = 0;
2314
2315 /* Get the Capability pointer first,
2316 * the Capability Pointer is located at
2317 * offset 0x34 from the Function Header */
2318
2319 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2320 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2321 "PCI configration 0x34 = 0x%2x\n", cap_pointer);
2322
2323 do {
2324 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2325 cap_id = cap_hdr & 0xFF;
2326
2327 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2328 "in pci configration, cap_pointer%x = %x\n",
2329 cap_pointer, cap_id);
2330
2331 if (cap_id == 0x01) {
2332 break;
2333 } else {
2334 /* point to next Capability */
2335 cap_pointer = (cap_hdr >> 8) & 0xFF;
2336 /* 0: end of pci capability, 0xff: invalid value */
2337 if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2338 cap_id = 0xff;
2339 break;
2340 }
2341 }
2342 } while (cnt++ < 200);
2343
2344 if (cap_id == 0x01) {
2345 /* Get the PM CSR (Control/Status Register),
2346 * The PME_Status is located at PM Capatibility offset 5, bit 7
2347 */
2348 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2349
2350 if (pmcs_reg & BIT(7)) {
2351 /* PME event occured, clear the PM_Status by write 1 */
2352 pmcs_reg = pmcs_reg | BIT(7);
2353
2354 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2355 pmcs_reg);
2356 /* Read it back to check */
2357 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2358 &pmcs_reg);
2359 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2360 "Clear PME status 0x%2x to 0x%2x\n",
2361 cap_pointer + 5, pmcs_reg);
2362 } else {
2363 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2364 "PME status(0x%2x) = 0x%2x\n",
2365 cap_pointer + 5, pmcs_reg);
2366 }
2367 } else {
2368 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2369 "Cannot find PME Capability\n");
2370 }
2371 }
2372
2373 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2374 {
2375 struct rtl_priv *rtlpriv = rtl_priv(hw);
2376 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2377 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2378 struct rtl_mac *mac = rtl_mac(rtlpriv);
2379 enum nl80211_iftype opmode;
2380 bool support_remote_wakeup;
2381 u8 tmp;
2382 u32 count = 0;
2383
2384 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2385 (u8 *)(&support_remote_wakeup));
2386
2387 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2388
2389 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2390 || !rtlhal->enter_pnp_sleep) {
2391 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2392 mac->link_state = MAC80211_NOLINK;
2393 opmode = NL80211_IFTYPE_UNSPECIFIED;
2394 _rtl8821ae_set_media_status(hw, opmode);
2395 _rtl8821ae_poweroff_adapter(hw);
2396 } else {
2397 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2398 /* 3 <1> Prepare for configuring wowlan related infomations */
2399 /* Clear Fw WoWLAN event. */
2400 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2401
2402 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2403 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2404 #endif
2405 /* Dynamically adjust Tx packet boundary
2406 * for download reserved page packet.
2407 * reserve 30 pages for rsvd page */
2408 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2409 rtlhal->re_init_llt_table = true;
2410
2411 /* 3 <2> Set Fw releted H2C cmd. */
2412
2413 /* Set WoWLAN related security information. */
2414 rtl8821ae_set_fw_global_info_cmd(hw);
2415
2416 _rtl8821ae_download_rsvd_page(hw, true);
2417
2418 /* Just enable AOAC related functions when we connect to AP. */
2419 printk("mac->link_state = %d\n", mac->link_state);
2420 if (mac->link_state >= MAC80211_LINKED &&
2421 mac->opmode == NL80211_IFTYPE_STATION) {
2422 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2423 rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2424 RT_MEDIA_CONNECT);
2425
2426 rtl8821ae_set_fw_wowlan_mode(hw, true);
2427 /* Enable Fw Keep alive mechanism. */
2428 rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2429
2430 /* Enable disconnect decision control. */
2431 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2432 }
2433
2434 /* 3 <3> Hw Configutations */
2435
2436 /* Wait untill Rx DMA Finished before host sleep.
2437 * FW Pause Rx DMA may happens when received packet doing dma.
2438 */
2439 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2440
2441 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2442 count = 0;
2443 while (!(tmp & BIT(1)) && (count++ < 100)) {
2444 udelay(10);
2445 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2446 }
2447 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2448 "Wait Rx DMA Finished before host sleep. count=%d\n",
2449 count);
2450
2451 /* reset trx ring */
2452 rtlpriv->intf_ops->reset_trx_ring(hw);
2453
2454 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2455
2456 _rtl8821ae_clear_pci_pme_status(hw);
2457 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2458 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2459 /* prevent 8051 to be reset by PERST */
2460 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2461 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2462 }
2463
2464 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2465 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2466 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2467 /* For wowlan+LPS+32k. */
2468 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2469 /* Set the WoWLAN related function control enable.
2470 * It should be the last H2C cmd in the WoWLAN flow. */
2471 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2472
2473 /* Stop Pcie Interface Tx DMA. */
2474 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2475 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2476
2477 /* Wait for TxDMA idle. */
2478 count = 0;
2479 do {
2480 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2481 udelay(10);
2482 count++;
2483 } while ((tmp != 0) && (count < 100));
2484 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2485 "Wait Tx DMA Finished before host sleep. count=%d\n",
2486 count);
2487
2488 if (rtlhal->hw_rof_enable) {
2489 printk("hw_rof_enable\n");
2490 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2491 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2492 }
2493 }
2494 /* after power off we should do iqk again */
2495 rtlpriv->phy.iqk_initialized = false;
2496 }
2497
2498 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2499 u32 *p_inta, u32 *p_intb)
2500 {
2501 struct rtl_priv *rtlpriv = rtl_priv(hw);
2502 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2503
2504 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2505 rtl_write_dword(rtlpriv, ISR, *p_inta);
2506
2507 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2508 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2509 }
2510
2511 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2512 {
2513 struct rtl_priv *rtlpriv = rtl_priv(hw);
2514 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2516 u16 bcn_interval, atim_window;
2517
2518 bcn_interval = mac->beacon_interval;
2519 atim_window = 2; /*FIX MERGE */
2520 rtl8821ae_disable_interrupt(hw);
2521 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2522 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2523 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2524 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2525 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2526 rtl_write_byte(rtlpriv, 0x606, 0x30);
2527 rtlpci->reg_bcn_ctrl_val |= BIT(3);
2528 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2529 rtl8821ae_enable_interrupt(hw);
2530 }
2531
2532 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2533 {
2534 struct rtl_priv *rtlpriv = rtl_priv(hw);
2535 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2536 u16 bcn_interval = mac->beacon_interval;
2537
2538 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2539 "beacon_interval:%d\n", bcn_interval);
2540 rtl8821ae_disable_interrupt(hw);
2541 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2542 rtl8821ae_enable_interrupt(hw);
2543 }
2544
2545 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2546 u32 add_msr, u32 rm_msr)
2547 {
2548 struct rtl_priv *rtlpriv = rtl_priv(hw);
2549 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2550
2551 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2552 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2553
2554 if (add_msr)
2555 rtlpci->irq_mask[0] |= add_msr;
2556 if (rm_msr)
2557 rtlpci->irq_mask[0] &= (~rm_msr);
2558 rtl8821ae_disable_interrupt(hw);
2559 rtl8821ae_enable_interrupt(hw);
2560 }
2561
2562 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2563 {
2564 u8 group = 0;
2565
2566 if (chnl <= 14) {
2567 if (1 <= chnl && chnl <= 2)
2568 group = 0;
2569 else if (3 <= chnl && chnl <= 5)
2570 group = 1;
2571 else if (6 <= chnl && chnl <= 8)
2572 group = 2;
2573 else if (9 <= chnl && chnl <= 11)
2574 group = 3;
2575 else /*if (12 <= chnl && chnl <= 14)*/
2576 group = 4;
2577 } else {
2578 if (36 <= chnl && chnl <= 42)
2579 group = 0;
2580 else if (44 <= chnl && chnl <= 48)
2581 group = 1;
2582 else if (50 <= chnl && chnl <= 58)
2583 group = 2;
2584 else if (60 <= chnl && chnl <= 64)
2585 group = 3;
2586 else if (100 <= chnl && chnl <= 106)
2587 group = 4;
2588 else if (108 <= chnl && chnl <= 114)
2589 group = 5;
2590 else if (116 <= chnl && chnl <= 122)
2591 group = 6;
2592 else if (124 <= chnl && chnl <= 130)
2593 group = 7;
2594 else if (132 <= chnl && chnl <= 138)
2595 group = 8;
2596 else if (140 <= chnl && chnl <= 144)
2597 group = 9;
2598 else if (149 <= chnl && chnl <= 155)
2599 group = 10;
2600 else if (157 <= chnl && chnl <= 161)
2601 group = 11;
2602 else if (165 <= chnl && chnl <= 171)
2603 group = 12;
2604 else if (173 <= chnl && chnl <= 177)
2605 group = 13;
2606 else
2607 /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2608 "5G, Channel %d in Group not found\n",chnl);*/
2609 RT_ASSERT(!COMP_EFUSE,
2610 "5G, Channel %d in Group not found\n", chnl);
2611 }
2612 return group;
2613 }
2614
2615 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2616 struct txpower_info_2g *pwrinfo24g,
2617 struct txpower_info_5g *pwrinfo5g,
2618 bool autoload_fail,
2619 u8 *hwinfo)
2620 {
2621 struct rtl_priv *rtlpriv = rtl_priv(hw);
2622 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2623
2624 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2625 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2626 (eeAddr+1), hwinfo[eeAddr+1]);
2627 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/
2628 autoload_fail = true;
2629
2630 if (autoload_fail) {
2631 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2632 "auto load fail : Use Default value!\n");
2633 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2634 /*2.4G default value*/
2635 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2636 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2637 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2638 }
2639 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2640 if (TxCount == 0) {
2641 pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2642 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2643 } else {
2644 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2645 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2646 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2647 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2648 }
2649 }
2650 /*5G default value*/
2651 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2652 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2653
2654 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2655 if (TxCount == 0) {
2656 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2657 pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2658 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2659 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2660 } else {
2661 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2662 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2663 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2664 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2665 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2666 }
2667 }
2668 }
2669 return;
2670 }
2671
2672 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2673
2674 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2675 /*2.4G default value*/
2676 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2677 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2678 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2679 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2680 }
2681 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2682 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2683 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2684 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2685 }
2686 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2687 if (TxCount == 0) {
2688 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2689 /*bit sign number to 8 bit sign number*/
2690 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2691 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2692 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2693 /*bit sign number to 8 bit sign number*/
2694 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2695 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2696 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2697
2698 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2699 eeAddr++;
2700 } else {
2701 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2702 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2703 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2704
2705 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2706 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2707 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2708
2709 eeAddr++;
2710
2711 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2712 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2713 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2714
2715 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2716 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2717 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2718
2719 eeAddr++;
2720 }
2721 }
2722
2723 /*5G default value*/
2724 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2725 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2726 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2727 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2728 }
2729
2730 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2731 if (TxCount == 0) {
2732 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2733
2734 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2735 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2736 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2737
2738 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2739 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2740 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2741
2742 eeAddr++;
2743 } else {
2744 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2745 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2746 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2747
2748 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2749 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2750 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2751
2752 eeAddr++;
2753 }
2754 }
2755
2756 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4;
2757 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f);
2758
2759 eeAddr++;
2760
2761 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2762
2763 eeAddr++;
2764
2765 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2766 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2767 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2768 }
2769 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2770 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2771 /* 4bit sign number to 8 bit sign number */
2772 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2773 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2774 /* 4bit sign number to 8 bit sign number */
2775 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2776 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2777 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2778
2779 eeAddr++;
2780 }
2781 }
2782 }
2783 #if 0
2784 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2785 bool autoload_fail,
2786 u8 *hwinfo)
2787 {
2788 struct rtl_priv *rtlpriv = rtl_priv(hw);
2789 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2790 struct txpower_info_2g pwrinfo24g;
2791 struct txpower_info_5g pwrinfo5g;
2792 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2793 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2794 56, 58, 60, 62, 64, 100, 102, 104, 106,
2795 108, 110, 112, 114, 116, 118, 120, 122,
2796 124, 126, 128, 130, 132, 134, 136, 138,
2797 140, 142, 144, 149, 151, 153, 155, 157,
2798 159, 161, 163, 165, 167, 168, 169, 171, 173, 175, 177};
2799 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2800 u8 rf_path, index;
2801 u8 i;
2802
2803 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2804 &pwrinfo5g, autoload_fail, hwinfo);
2805
2806 for (rf_path = 0; rf_path < 2; rf_path++) {
2807 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2808 index = _rtl8821ae_get_chnl_group(i + 1);
2809
2810 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2811 rtlefuse->txpwrlevel_cck[rf_path][i] =
2812 pwrinfo24g.index_cck_base[rf_path][5];
2813 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2814 pwrinfo24g.index_bw40_base[rf_path][index];
2815 } else {
2816 rtlefuse->txpwrlevel_cck[rf_path][i] =
2817 pwrinfo24g.index_cck_base[rf_path][index];
2818 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2819 pwrinfo24g.index_bw40_base[rf_path][index];
2820 }
2821 }
2822
2823 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2824 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2825 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2826 pwrinfo5g.index_bw40_base[rf_path][index];
2827 }
2828 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2829 u8 upper, lower;
2830 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2831 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2832 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2833
2834 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2835 }
2836 for (i = 0; i < MAX_TX_COUNT; i++) {
2837 rtlefuse->txpwr_cckdiff[rf_path][i] =
2838 pwrinfo24g.cck_diff[rf_path][i];
2839 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2840 pwrinfo24g.ofdm_diff[rf_path][i];
2841 rtlefuse->txpwr_ht20diff[rf_path][i] =
2842 pwrinfo24g.bw20_diff[rf_path][i];
2843 rtlefuse->txpwr_ht40diff[rf_path][i] =
2844 pwrinfo24g.bw40_diff[rf_path][i];
2845
2846 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2847 pwrinfo5g.ofdm_diff[rf_path][i];
2848 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2849 pwrinfo5g.bw20_diff[rf_path][i];
2850 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2851 pwrinfo5g.bw40_diff[rf_path][i];
2852 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2853 pwrinfo5g.bw80_diff[rf_path][i];
2854 }
2855 }
2856
2857 if (!autoload_fail) {
2858 rtlefuse->eeprom_regulatory =
2859 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2860 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2861 rtlefuse->eeprom_regulatory = 0;
2862 } else {
2863 rtlefuse->eeprom_regulatory = 0;
2864 }
2865
2866 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2867 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2868 }
2869 #endif
2870 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2871 bool autoload_fail,
2872 u8 *hwinfo)
2873 {
2874 struct rtl_priv *rtlpriv = rtl_priv(hw);
2875 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2876 struct txpower_info_2g pwrinfo24g;
2877 struct txpower_info_5g pwrinfo5g;
2878 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2879 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2880 56, 58, 60, 62, 64, 100, 102, 104, 106,
2881 108, 110, 112, 114, 116, 118, 120, 122,
2882 124, 126, 128, 130, 132, 134, 136, 138,
2883 140, 142, 144, 149, 151, 153, 155, 157,
2884 159, 161, 163, 165, 167, 168, 169, 171,
2885 173, 175, 177};
2886 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2887 42, 58, 106, 122, 138, 155, 171};
2888 u8 rf_path, index;
2889 u8 i;
2890
2891 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2892 &pwrinfo5g, autoload_fail, hwinfo);
2893
2894 for (rf_path = 0; rf_path < 2; rf_path++) {
2895 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2896 index = _rtl8821ae_get_chnl_group(i + 1);
2897
2898 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2899 rtlefuse->txpwrlevel_cck[rf_path][i] =
2900 pwrinfo24g.index_cck_base[rf_path][5];
2901 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2902 pwrinfo24g.index_bw40_base[rf_path][index];
2903 } else {
2904 rtlefuse->txpwrlevel_cck[rf_path][i] =
2905 pwrinfo24g.index_cck_base[rf_path][index];
2906 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2907 pwrinfo24g.index_bw40_base[rf_path][index];
2908 }
2909 }
2910
2911 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2912 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2913 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2914 pwrinfo5g.index_bw40_base[rf_path][index];
2915 }
2916 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2917 u8 upper, lower;
2918 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2919 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2920 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2921
2922 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2923 }
2924 for (i = 0; i < MAX_TX_COUNT; i++) {
2925 rtlefuse->txpwr_cckdiff[rf_path][i] =
2926 pwrinfo24g.cck_diff[rf_path][i];
2927 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2928 pwrinfo24g.ofdm_diff[rf_path][i];
2929 rtlefuse->txpwr_ht20diff[rf_path][i] =
2930 pwrinfo24g.bw20_diff[rf_path][i];
2931 rtlefuse->txpwr_ht40diff[rf_path][i] =
2932 pwrinfo24g.bw40_diff[rf_path][i];
2933
2934 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2935 pwrinfo5g.ofdm_diff[rf_path][i];
2936 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2937 pwrinfo5g.bw20_diff[rf_path][i];
2938 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2939 pwrinfo5g.bw40_diff[rf_path][i];
2940 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2941 pwrinfo5g.bw80_diff[rf_path][i];
2942 }
2943 }
2944 /*bit0~2*/
2945 if (!autoload_fail) {
2946 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2947 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2948 rtlefuse->eeprom_regulatory = 0;
2949 } else {
2950 rtlefuse->eeprom_regulatory = 0;
2951 }
2952
2953 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2954 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2955 }
2956
2957 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2958 bool autoload_fail)
2959 {
2960 struct rtl_priv *rtlpriv = rtl_priv(hw);
2961 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2962
2963 if (!autoload_fail) {
2964 rtlhal->pa_type_2g = hwinfo[0xBC];
2965 rtlhal->lna_type_2g = hwinfo[0xBD];
2966 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2967 rtlhal->pa_type_2g = 0;
2968 rtlhal->lna_type_2g = 0;
2969 }
2970 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2971 (rtlhal->pa_type_2g & BIT(4))) ?
2972 1 : 0;
2973 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2974 (rtlhal->lna_type_2g & BIT(3))) ?
2975 1 : 0;
2976
2977 rtlhal->pa_type_5g = hwinfo[0xBC];
2978 rtlhal->lna_type_5g = hwinfo[0xBF];
2979 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2980 rtlhal->pa_type_5g = 0;
2981 rtlhal->lna_type_5g = 0;
2982 }
2983 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2984 (rtlhal->pa_type_5g & BIT(0))) ?
2985 1 : 0;
2986 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2987 (rtlhal->lna_type_5g & BIT(3))) ?
2988 1 : 0;
2989 } else {
2990 rtlhal->external_pa_2g = 0;
2991 rtlhal->external_lna_2g = 0;
2992 rtlhal->external_pa_5g = 0;
2993 rtlhal->external_lna_5g = 0;
2994 }
2995 }
2996
2997 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2998 bool autoload_fail)
2999 {
3000 struct rtl_priv *rtlpriv = rtl_priv(hw);
3001 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3002
3003 if (!autoload_fail) {
3004 rtlhal->pa_type_2g = hwinfo[0xBC];
3005 rtlhal->lna_type_2g = hwinfo[0xBD];
3006 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
3007 rtlhal->pa_type_2g = 0;
3008 rtlhal->lna_type_2g = 0;
3009 }
3010 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
3011 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
3012
3013 rtlhal->pa_type_5g = hwinfo[0xBC];
3014 rtlhal->lna_type_5g = hwinfo[0xBF];
3015 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3016 rtlhal->pa_type_5g = 0;
3017 rtlhal->lna_type_5g = 0;
3018 }
3019 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3020 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3021 } else {
3022 rtlhal->external_pa_2g = 0;
3023 rtlhal->external_lna_2g = 0;
3024 rtlhal->external_pa_5g = 0;
3025 rtlhal->external_lna_5g = 0;
3026 }
3027 }
3028
3029 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3030 bool autoload_fail)
3031 {
3032 struct rtl_priv *rtlpriv = rtl_priv(hw);
3033 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3034
3035 if (!autoload_fail) {
3036 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3037 if (rtlhal->external_lna_5g) {
3038 if (rtlhal->external_pa_5g) {
3039 if (rtlhal->external_lna_2g &&
3040 rtlhal->external_pa_2g)
3041 rtlhal->rfe_type = 3;
3042 else
3043 rtlhal->rfe_type = 0;
3044 } else {
3045 rtlhal->rfe_type = 2;
3046 }
3047 } else {
3048 rtlhal->rfe_type = 4;
3049 }
3050 } else {
3051 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3052
3053 if (rtlhal->rfe_type == 4 &&
3054 (rtlhal->external_pa_5g ||
3055 rtlhal->external_pa_2g ||
3056 rtlhal->external_lna_5g ||
3057 rtlhal->external_lna_2g)) {
3058 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3059 rtlhal->rfe_type = 2;
3060 }
3061 }
3062 } else {
3063 rtlhal->rfe_type = 0x04;
3064 }
3065
3066 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3067 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3068 }
3069
3070 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3071 bool auto_load_fail, u8 *hwinfo)
3072 {
3073 struct rtl_priv *rtlpriv = rtl_priv(hw);
3074 u8 value;
3075
3076 if (!auto_load_fail) {
3077 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3078 if (((value & 0xe0) >> 5) == 0x1)
3079 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3080 else
3081 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3082 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3083
3084 value = hwinfo[EEPROM_RF_BT_SETTING];
3085 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3086 } else {
3087 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3088 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3089 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3090 }
3091 /*move BT_InitHalVars() to init_sw_vars*/
3092 }
3093
3094 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3095 bool auto_load_fail, u8 *hwinfo)
3096 {
3097 struct rtl_priv *rtlpriv = rtl_priv(hw);
3098 u8 value;
3099 u32 tmpu_32;
3100
3101 if (!auto_load_fail) {
3102 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3103 if (tmpu_32 & BIT(18))
3104 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3105 else
3106 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3107 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3108
3109 value = hwinfo[EEPROM_RF_BT_SETTING];
3110 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3111 } else {
3112 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3113 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3114 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3115 }
3116 /*move BT_InitHalVars() to init_sw_vars*/
3117 }
3118
3119 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3120 {
3121 struct rtl_priv *rtlpriv = rtl_priv(hw);
3122 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3124 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3125 u16 i, usvalue;
3126 u8 hwinfo[HWSET_MAX_SIZE];
3127 u16 eeprom_id;
3128
3129 if (b_pseudo_test) {
3130 ;/* need add */
3131 }
3132
3133 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
3134 rtl_efuse_shadow_map_update(hw);
3135 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
3136 HWSET_MAX_SIZE);
3137 } else if (rtlefuse->epromtype == EEPROM_93C46) {
3138 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3139 "RTL819X Not boot from eeprom, check it !!");
3140 }
3141
3142 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
3143 hwinfo, HWSET_MAX_SIZE);
3144
3145 eeprom_id = *((u16 *)&hwinfo[0]);
3146 if (eeprom_id != RTL_EEPROM_ID) {
3147 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3148 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
3149 rtlefuse->autoload_failflag = true;
3150 } else {
3151 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3152 rtlefuse->autoload_failflag = false;
3153 }
3154
3155 if (rtlefuse->autoload_failflag) {
3156 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3157 "RTL8812AE autoload_failflag, check it !!");
3158 return;
3159 }
3160
3161 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
3162 if (rtlefuse->eeprom_version == 0xff)
3163 rtlefuse->eeprom_version = 0;
3164
3165 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3166 "EEPROM version: 0x%2x\n", rtlefuse->eeprom_version);
3167
3168 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
3169 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
3170 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
3171 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
3172 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3173 "EEPROMId = 0x%4x\n", eeprom_id);
3174 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3175 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
3176 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3177 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
3178 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3179 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
3180 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3181 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
3182
3183 /*customer ID*/
3184 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
3185 if (rtlefuse->eeprom_oemid == 0xFF)
3186 rtlefuse->eeprom_oemid = 0;
3187
3188 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3189 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
3190
3191 for (i = 0; i < 6; i += 2) {
3192 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
3193 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
3194 }
3195
3196 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3197 "dev_addr: %pM\n", rtlefuse->dev_addr);
3198
3199 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3200 hwinfo);
3201
3202 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3203 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3204 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3205 rtlefuse->autoload_failflag, hwinfo);
3206 } else {
3207 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3208 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3209 rtlefuse->autoload_failflag, hwinfo);
3210 }
3211
3212 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3213 /*board type*/
3214 rtlefuse->board_type = ODM_BOARD_DEFAULT;
3215 if (rtlhal->external_lna_2g != 0)
3216 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3217 if (rtlhal->external_lna_5g != 0)
3218 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3219 if (rtlhal->external_pa_2g != 0)
3220 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3221 if (rtlhal->external_pa_5g != 0)
3222 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3223
3224 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3225 rtlefuse->board_type |= ODM_BOARD_BT;
3226
3227 rtlhal->board_type = rtlefuse->board_type;
3228 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3229 "board_type = 0x%x\n", rtlefuse->board_type);
3230
3231 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3232 if (rtlefuse->eeprom_channelplan == 0xff)
3233 rtlefuse->eeprom_channelplan = 0x7F;
3234
3235 /* set channel paln to world wide 13 */
3236 /* rtlefuse->channel_plan = (u8)rtlefuse->eeprom_channelplan; */
3237
3238 /*parse xtal*/
3239 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3240 if (rtlefuse->crystalcap == 0xFF)
3241 rtlefuse->crystalcap = 0x20;
3242
3243 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3244 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3245 rtlefuse->autoload_failflag) {
3246 rtlefuse->apk_thermalmeterignore = true;
3247 rtlefuse->eeprom_thermalmeter = 0xff;
3248 }
3249
3250 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3251 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3252 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3253
3254 if (!rtlefuse->autoload_failflag) {
3255 rtlefuse->antenna_div_cfg =
3256 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3257 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3258 rtlefuse->antenna_div_cfg = 0;
3259
3260 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3261 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3262 rtlefuse->antenna_div_cfg = 0;
3263
3264 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3265 if (rtlefuse->antenna_div_type == 0xff)
3266 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3267 } else {
3268 rtlefuse->antenna_div_cfg = 0;
3269 rtlefuse->antenna_div_type = 0;
3270 }
3271
3272 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3273 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3274 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3275
3276 pcipriv->ledctl.led_opendrain = true;
3277
3278 if (rtlhal->oem_id == RT_CID_DEFAULT) {
3279 switch (rtlefuse->eeprom_oemid) {
3280 case RT_CID_DEFAULT:
3281 break;
3282 case EEPROM_CID_TOSHIBA:
3283 rtlhal->oem_id = RT_CID_TOSHIBA;
3284 break;
3285 case EEPROM_CID_CCX:
3286 rtlhal->oem_id = RT_CID_CCX;
3287 break;
3288 case EEPROM_CID_QMI:
3289 rtlhal->oem_id = RT_CID_819X_QMI;
3290 break;
3291 case EEPROM_CID_WHQL:
3292 break;
3293 default:
3294 break;
3295 }
3296 }
3297 }
3298
3299 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3300 {
3301 struct rtl_priv *rtlpriv = rtl_priv(hw);
3302 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3303 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3304
3305 pcipriv->ledctl.led_opendrain = true;
3306 switch (rtlhal->oem_id) {
3307 case RT_CID_819X_HP:
3308 pcipriv->ledctl.led_opendrain = true;
3309 break;
3310 case RT_CID_819X_LENOVO:
3311 case RT_CID_DEFAULT:
3312 case RT_CID_TOSHIBA:
3313 case RT_CID_CCX:
3314 case RT_CID_819X_ACER:
3315 case RT_CID_WHQL:
3316 default:
3317 break;
3318 }
3319 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3320 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3321 }*/
3322
3323 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3324 {
3325 struct rtl_priv *rtlpriv = rtl_priv(hw);
3326 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3327 struct rtl_phy *rtlphy = &rtlpriv->phy;
3328 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3329 u8 tmp_u1b;
3330
3331 rtlhal->version = _rtl8821ae_read_chip_version(hw);
3332 if (get_rf_type(rtlphy) == RF_1T1R)
3333 rtlpriv->dm.rfpath_rxenable[0] = true;
3334 else
3335 rtlpriv->dm.rfpath_rxenable[0] =
3336 rtlpriv->dm.rfpath_rxenable[1] = true;
3337 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3338 rtlhal->version);
3339
3340 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3341 if (tmp_u1b & BIT(4)) {
3342 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3343 rtlefuse->epromtype = EEPROM_93C46;
3344 } else {
3345 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3346 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3347 }
3348
3349 if (tmp_u1b & BIT(5)) {
3350 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3351 rtlefuse->autoload_failflag = false;
3352 _rtl8821ae_read_adapter_info(hw, false);
3353 } else {
3354 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3355 }
3356 /*hal_ReadRFType_8812A()*/
3357 /* _rtl8821ae_hal_customized_behavior(hw); */
3358 }
3359
3360 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3361 struct ieee80211_sta *sta)
3362 {
3363 struct rtl_priv *rtlpriv = rtl_priv(hw);
3364 struct rtl_phy *rtlphy = &rtlpriv->phy;
3365 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3366 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3367 u32 ratr_value;
3368 u8 ratr_index = 0;
3369 u8 b_nmode = mac->ht_enable;
3370 u8 mimo_ps = IEEE80211_SMPS_OFF;
3371 u16 shortgi_rate;
3372 u32 tmp_ratr_value;
3373 u8 curtxbw_40mhz = mac->bw_40;
3374 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3375 1 : 0;
3376 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3377 1 : 0;
3378 enum wireless_mode wirelessmode = mac->mode;
3379
3380 if (rtlhal->current_bandtype == BAND_ON_5G)
3381 ratr_value = sta->supp_rates[1] << 4;
3382 else
3383 ratr_value = sta->supp_rates[0];
3384 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3385 ratr_value = 0xfff;
3386 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3387 sta->ht_cap.mcs.rx_mask[0] << 12);
3388 switch (wirelessmode) {
3389 case WIRELESS_MODE_B:
3390 if (ratr_value & 0x0000000c)
3391 ratr_value &= 0x0000000d;
3392 else
3393 ratr_value &= 0x0000000f;
3394 break;
3395 case WIRELESS_MODE_G:
3396 ratr_value &= 0x00000FF5;
3397 break;
3398 case WIRELESS_MODE_N_24G:
3399 case WIRELESS_MODE_N_5G:
3400 b_nmode = 1;
3401 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3402 ratr_value &= 0x0007F005;
3403 } else {
3404 u32 ratr_mask;
3405
3406 if (get_rf_type(rtlphy) == RF_1T2R ||
3407 get_rf_type(rtlphy) == RF_1T1R)
3408 ratr_mask = 0x000ff005;
3409 else
3410 ratr_mask = 0x0f0ff005;
3411
3412 ratr_value &= ratr_mask;
3413 }
3414 break;
3415 default:
3416 if (rtlphy->rf_type == RF_1T2R)
3417 ratr_value &= 0x000ff0ff;
3418 else
3419 ratr_value &= 0x0f0ff0ff;
3420
3421 break;
3422 }
3423
3424 if ((rtlpriv->btcoexist.bt_coexistence) &&
3425 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3426 (rtlpriv->btcoexist.bt_cur_state) &&
3427 (rtlpriv->btcoexist.bt_ant_isolation) &&
3428 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3429 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3430 ratr_value &= 0x0fffcfc0;
3431 else
3432 ratr_value &= 0x0FFFFFFF;
3433
3434 if (b_nmode && ((curtxbw_40mhz &&
3435 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3436 b_curshortgi_20mhz))) {
3437 ratr_value |= 0x10000000;
3438 tmp_ratr_value = (ratr_value >> 12);
3439
3440 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3441 if ((1 << shortgi_rate) & tmp_ratr_value)
3442 break;
3443 }
3444
3445 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3446 (shortgi_rate << 4) | (shortgi_rate);
3447 }
3448
3449 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3450
3451 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3452 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3453 }
3454
3455 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3456 struct ieee80211_hw *hw, u8 rate_index,
3457 enum wireless_mode wirelessmode)
3458 {
3459 struct rtl_priv *rtlpriv = rtl_priv(hw);
3460 struct rtl_phy *rtlphy = &rtlpriv->phy;
3461 u8 ret = 0;
3462 switch (rate_index) {
3463 case RATR_INX_WIRELESS_NGB:
3464 if (rtlphy->rf_type == RF_1T1R)
3465 ret = 1;
3466 else
3467 ret = 0;
3468 ; break;
3469 case RATR_INX_WIRELESS_N:
3470 case RATR_INX_WIRELESS_NG:
3471 if (rtlphy->rf_type == RF_1T1R)
3472 ret = 5;
3473 else
3474 ret = 4;
3475 ; break;
3476 case RATR_INX_WIRELESS_NB:
3477 if (rtlphy->rf_type == RF_1T1R)
3478 ret = 3;
3479 else
3480 ret = 2;
3481 ; break;
3482 case RATR_INX_WIRELESS_GB:
3483 ret = 6;
3484 break;
3485 case RATR_INX_WIRELESS_G:
3486 ret = 7;
3487 break;
3488 case RATR_INX_WIRELESS_B:
3489 ret = 8;
3490 break;
3491 case RATR_INX_WIRELESS_MC:
3492 if ((wirelessmode == WIRELESS_MODE_B)
3493 || (wirelessmode == WIRELESS_MODE_G)
3494 || (wirelessmode == WIRELESS_MODE_N_24G)
3495 || (wirelessmode == WIRELESS_MODE_AC_24G))
3496 ret = 6;
3497 else
3498 ret = 7;
3499 case RATR_INX_WIRELESS_AC_5N:
3500 if (rtlphy->rf_type == RF_1T1R)
3501 ret = 10;
3502 else
3503 ret = 9;
3504 break;
3505 case RATR_INX_WIRELESS_AC_24N:
3506 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3507 if (rtlphy->rf_type == RF_1T1R)
3508 ret = 10;
3509 else
3510 ret = 9;
3511 } else {
3512 if (rtlphy->rf_type == RF_1T1R)
3513 ret = 11;
3514 else
3515 ret = 12;
3516 }
3517 break;
3518 default:
3519 ret = 0; break;
3520 }
3521 return ret;
3522 }
3523
3524 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3525 {
3526 u8 i, j, tmp_rate;
3527 u32 rate_bitmap = 0;
3528
3529 for (i = j = 0; i < 4; i += 2, j += 10) {
3530 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3531
3532 switch (tmp_rate) {
3533 case 2:
3534 rate_bitmap = rate_bitmap | (0x03ff << j);
3535 break;
3536 case 1:
3537 rate_bitmap = rate_bitmap | (0x01ff << j);
3538 break;
3539 case 0:
3540 rate_bitmap = rate_bitmap | (0x00ff << j);
3541 break;
3542 default:
3543 break;
3544 }
3545 }
3546
3547 return rate_bitmap;
3548 }
3549
3550 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3551 enum wireless_mode wirelessmode,
3552 u32 ratr_bitmap)
3553 {
3554 struct rtl_priv *rtlpriv = rtl_priv(hw);
3555 struct rtl_phy *rtlphy = &rtlpriv->phy;
3556 u32 ret_bitmap = ratr_bitmap;
3557
3558 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3559 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3560 ret_bitmap = ratr_bitmap;
3561 else if (wirelessmode == WIRELESS_MODE_AC_5G
3562 || wirelessmode == WIRELESS_MODE_AC_24G) {
3563 if (rtlphy->rf_type == RF_1T1R)
3564 ret_bitmap = ratr_bitmap & (~BIT21);
3565 else
3566 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3567 }
3568
3569 return ret_bitmap;
3570 }
3571
3572 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3573 u32 ratr_bitmap)
3574 {
3575 u8 ret = 0;
3576 if (wirelessmode < WIRELESS_MODE_N_24G)
3577 ret = 0;
3578 else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3579 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
3580 ret = 3;
3581 else /* Mix, 1SS */
3582 ret = 2;
3583 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3584 ret = 1;
3585 } /* VHT */
3586
3587 return ret << 4;
3588 }
3589
3590 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3591 u8 mac_id, struct rtl_sta_info *sta_entry,
3592 enum wireless_mode wirelessmode)
3593 {
3594 u8 b_ldpc = 0;
3595 /*not support ldpc, do not open*/
3596 return b_ldpc << 2;
3597 }
3598
3599 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3600 enum wireless_mode wirelessmode,
3601 u32 ratr_bitmap)
3602 {
3603 struct rtl_priv *rtlpriv = rtl_priv(hw);
3604 struct rtl_phy *rtlphy = &rtlpriv->phy;
3605 u8 rf_type = RF_1T1R;
3606
3607 if (rtlphy->rf_type == RF_1T1R)
3608 rf_type = RF_1T1R;
3609 else if (wirelessmode == WIRELESS_MODE_AC_5G
3610 || wirelessmode == WIRELESS_MODE_AC_24G
3611 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3612 if (ratr_bitmap & 0xffc00000)
3613 rf_type = RF_2T2R;
3614 } else if (wirelessmode == WIRELESS_MODE_N_5G
3615 || wirelessmode == WIRELESS_MODE_N_24G) {
3616 if (ratr_bitmap & 0xfff00000)
3617 rf_type = RF_2T2R;
3618 }
3619
3620 return rf_type;
3621 }
3622
3623 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3624 u8 mac_id)
3625 {
3626 bool b_short_gi = false;
3627 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3628 1 : 0;
3629 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3630 1 : 0;
3631 u8 b_curshortgi_80mhz = 0;
3632 b_curshortgi_80mhz = (sta->vht_cap.cap &
3633 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3634
3635 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3636 b_short_gi = false;
3637
3638 if (b_curshortgi_40mhz || b_curshortgi_80mhz
3639 || b_curshortgi_20mhz)
3640 b_short_gi = true;
3641
3642 return b_short_gi;
3643 }
3644
3645 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3646 struct ieee80211_sta *sta, u8 rssi_level)
3647 {
3648 struct rtl_priv *rtlpriv = rtl_priv(hw);
3649 struct rtl_phy *rtlphy = &rtlpriv->phy;
3650 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3651 struct rtl_sta_info *sta_entry = NULL;
3652 u32 ratr_bitmap;
3653 u8 ratr_index;
3654 enum wireless_mode wirelessmode = 0;
3655 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3656 ? 1 : 0;
3657 bool b_shortgi = false;
3658 u8 rate_mask[7];
3659 u8 macid = 0;
3660 u8 mimo_ps = IEEE80211_SMPS_OFF;
3661 u8 rf_type;
3662
3663 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3664 wirelessmode = sta_entry->wireless_mode;
3665
3666 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3667 "wireless mode = 0x%x\n", wirelessmode);
3668 if (mac->opmode == NL80211_IFTYPE_STATION ||
3669 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3670 curtxbw_40mhz = mac->bw_40;
3671 } else if (mac->opmode == NL80211_IFTYPE_AP ||
3672 mac->opmode == NL80211_IFTYPE_ADHOC)
3673 macid = sta->aid + 1;
3674 if (wirelessmode == WIRELESS_MODE_N_5G ||
3675 wirelessmode == WIRELESS_MODE_AC_5G)
3676 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ];
3677 else
3678 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3679
3680 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3681 ratr_bitmap = 0xfff;
3682
3683 if (wirelessmode == WIRELESS_MODE_N_24G
3684 || wirelessmode == WIRELESS_MODE_N_5G)
3685 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3686 sta->ht_cap.mcs.rx_mask[0] << 12);
3687 else if (wirelessmode == WIRELESS_MODE_AC_24G
3688 || wirelessmode == WIRELESS_MODE_AC_5G
3689 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3690 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3691 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3692
3693 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3694 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3695
3696 /*mac id owner*/
3697 switch (wirelessmode) {
3698 case WIRELESS_MODE_B:
3699 ratr_index = RATR_INX_WIRELESS_B;
3700 if (ratr_bitmap & 0x0000000c)
3701 ratr_bitmap &= 0x0000000d;
3702 else
3703 ratr_bitmap &= 0x0000000f;
3704 break;
3705 case WIRELESS_MODE_G:
3706 ratr_index = RATR_INX_WIRELESS_GB;
3707
3708 if (rssi_level == 1)
3709 ratr_bitmap &= 0x00000f00;
3710 else if (rssi_level == 2)
3711 ratr_bitmap &= 0x00000ff0;
3712 else
3713 ratr_bitmap &= 0x00000ff5;
3714 break;
3715 case WIRELESS_MODE_A:
3716 ratr_index = RATR_INX_WIRELESS_G;
3717 ratr_bitmap &= 0x00000ff0;
3718 break;
3719 case WIRELESS_MODE_N_24G:
3720 case WIRELESS_MODE_N_5G:
3721 if (wirelessmode == WIRELESS_MODE_N_24G)
3722 ratr_index = RATR_INX_WIRELESS_NGB;
3723 else
3724 ratr_index = RATR_INX_WIRELESS_NG;
3725
3726 if (mimo_ps == IEEE80211_SMPS_STATIC
3727 || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3728 if (rssi_level == 1)
3729 ratr_bitmap &= 0x000f0000;
3730 else if (rssi_level == 2)
3731 ratr_bitmap &= 0x000ff000;
3732 else
3733 ratr_bitmap &= 0x000ff005;
3734 } else {
3735 if (rf_type == RF_1T1R) {
3736 if (curtxbw_40mhz) {
3737 if (rssi_level == 1)
3738 ratr_bitmap &= 0x000f0000;
3739 else if (rssi_level == 2)
3740 ratr_bitmap &= 0x000ff000;
3741 else
3742 ratr_bitmap &= 0x000ff015;
3743 } else {
3744 if (rssi_level == 1)
3745 ratr_bitmap &= 0x000f0000;
3746 else if (rssi_level == 2)
3747 ratr_bitmap &= 0x000ff000;
3748 else
3749 ratr_bitmap &= 0x000ff005;
3750 }
3751 } else {
3752 if (curtxbw_40mhz) {
3753 if (rssi_level == 1)
3754 ratr_bitmap &= 0x0fff0000;
3755 else if (rssi_level == 2)
3756 ratr_bitmap &= 0x0ffff000;
3757 else
3758 ratr_bitmap &= 0x0ffff015;
3759 } else {
3760 if (rssi_level == 1)
3761 ratr_bitmap &= 0x0fff0000;
3762 else if (rssi_level == 2)
3763 ratr_bitmap &= 0x0ffff000;
3764 else
3765 ratr_bitmap &= 0x0ffff005;
3766 }
3767 }
3768 }
3769 break;
3770
3771 case WIRELESS_MODE_AC_24G:
3772 ratr_index = RATR_INX_WIRELESS_AC_24N;
3773 if (rssi_level == 1)
3774 ratr_bitmap &= 0xfc3f0000;
3775 else if (rssi_level == 2)
3776 ratr_bitmap &= 0xfffff000;
3777 else
3778 ratr_bitmap &= 0xffffffff;
3779 break;
3780
3781 case WIRELESS_MODE_AC_5G:
3782 ratr_index = RATR_INX_WIRELESS_AC_5N;
3783
3784 if (rf_type == RF_1T1R) {
3785 if (rssi_level == 1) /*add by Gary for ac-series*/
3786 ratr_bitmap &= 0x003f8000;
3787 else if (rssi_level == 2)
3788 ratr_bitmap &= 0x003ff000;
3789 else
3790 ratr_bitmap &= 0x003ff010;
3791 } else {
3792 if (rssi_level == 1)
3793 ratr_bitmap &= 0xfe3f8000;
3794 else if (rssi_level == 2)
3795 ratr_bitmap &= 0xfffff000;
3796 else
3797 ratr_bitmap &= 0xfffff010;
3798 }
3799 break;
3800
3801 default:
3802 ratr_index = RATR_INX_WIRELESS_NGB;
3803
3804 if (rf_type == RF_1T2R)
3805 ratr_bitmap &= 0x000ff0ff;
3806 else
3807 ratr_bitmap &= 0x0f8ff0ff;
3808 break;
3809 }
3810
3811 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3812 sta_entry->ratr_index = ratr_index;
3813 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3814 ratr_bitmap);
3815
3816 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3817 "ratr_bitmap :%x\n", ratr_bitmap);
3818
3819 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3820 (ratr_index << 28)); */
3821
3822 rate_mask[0] = macid;
3823 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3824 rate_mask[2] = rtlphy->current_chan_bw
3825 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3826 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3827
3828 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3829 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3830 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3831 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3832
3833 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3834 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3835 ratr_index, ratr_bitmap,
3836 rate_mask[0], rate_mask[1],
3837 rate_mask[2], rate_mask[3],
3838 rate_mask[4], rate_mask[5],
3839 rate_mask[6]);
3840 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3841 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3842 }
3843
3844 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3845 struct ieee80211_sta *sta, u8 rssi_level)
3846 {
3847 struct rtl_priv *rtlpriv = rtl_priv(hw);
3848 if (rtlpriv->dm.useramask)
3849 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3850 else
3851 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3852 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only");*/
3853 rtl8821ae_update_hal_rate_table(hw, sta);
3854 }
3855
3856 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3857 {
3858 struct rtl_priv *rtlpriv = rtl_priv(hw);
3859 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3860 u8 wireless_mode = mac->mode;
3861 u8 sifs_timer, r2t_sifs;
3862
3863 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3864 (u8 *)&mac->slot_time);
3865 if (wireless_mode == WIRELESS_MODE_G)
3866 sifs_timer = 0x0a;
3867 else
3868 sifs_timer = 0x0e;
3869 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3870
3871 r2t_sifs = 0xa;
3872
3873 if (wireless_mode == WIRELESS_MODE_AC_5G &&
3874 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3875 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3876 if (mac->vendor == PEER_ATH)
3877 r2t_sifs = 0x8;
3878 else
3879 r2t_sifs = 0xa;
3880 } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3881 r2t_sifs = 0xa;
3882 }
3883
3884 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3885 }
3886
3887 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3888 {
3889 struct rtl_priv *rtlpriv = rtl_priv(hw);
3890 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3891 struct rtl_phy *rtlphy = &rtlpriv->phy;
3892 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3893 u8 u1tmp = 0;
3894 bool b_actuallyset = false;
3895
3896 if (rtlpriv->rtlhal.being_init_adapter)
3897 return false;
3898
3899 if (ppsc->swrf_processing)
3900 return false;
3901
3902 spin_lock(&rtlpriv->locks.rf_ps_lock);
3903 if (ppsc->rfchange_inprogress) {
3904 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3905 return false;
3906 } else {
3907 ppsc->rfchange_inprogress = true;
3908 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3909 }
3910
3911 cur_rfstate = ppsc->rfpwr_state;
3912
3913 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3914 rtl_read_byte(rtlpriv,
3915 REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3916
3917 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3918
3919 if (rtlphy->polarity_ctl)
3920 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3921 else
3922 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3923
3924 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3925 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3926 "GPIOChangeRF - HW Radio ON, RF ON\n");
3927
3928 e_rfpowerstate_toset = ERFON;
3929 ppsc->hwradiooff = false;
3930 b_actuallyset = true;
3931 } else if ((!ppsc->hwradiooff)
3932 && (e_rfpowerstate_toset == ERFOFF)) {
3933 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3934 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
3935
3936 e_rfpowerstate_toset = ERFOFF;
3937 ppsc->hwradiooff = true;
3938 b_actuallyset = true;
3939 }
3940
3941 if (b_actuallyset) {
3942 spin_lock(&rtlpriv->locks.rf_ps_lock);
3943 ppsc->rfchange_inprogress = false;
3944 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3945 } else {
3946 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3947 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3948
3949 spin_lock(&rtlpriv->locks.rf_ps_lock);
3950 ppsc->rfchange_inprogress = false;
3951 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3952 }
3953
3954 *valid = 1;
3955 return !ppsc->hwradiooff;
3956 }
3957
3958 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3959 u8 *p_macaddr, bool is_group, u8 enc_algo,
3960 bool is_wepkey, bool clear_all)
3961 {
3962 struct rtl_priv *rtlpriv = rtl_priv(hw);
3963 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3964 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3965 u8 *macaddr = p_macaddr;
3966 u32 entry_id = 0;
3967 bool is_pairwise = false;
3968
3969 static u8 cam_const_addr[4][6] = {
3970 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3971 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3972 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3973 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3974 };
3975 static u8 cam_const_broad[] = {
3976 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3977 };
3978
3979 if (clear_all) {
3980 u8 idx = 0;
3981 u8 cam_offset = 0;
3982 u8 clear_number = 5;
3983
3984 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3985
3986 for (idx = 0; idx < clear_number; idx++) {
3987 rtl_cam_mark_invalid(hw, cam_offset + idx);
3988 rtl_cam_empty_entry(hw, cam_offset + idx);
3989
3990 if (idx < 5) {
3991 memset(rtlpriv->sec.key_buf[idx], 0,
3992 MAX_KEY_LEN);
3993 rtlpriv->sec.key_len[idx] = 0;
3994 }
3995 }
3996 } else {
3997 switch (enc_algo) {
3998 case WEP40_ENCRYPTION:
3999 enc_algo = CAM_WEP40;
4000 break;
4001 case WEP104_ENCRYPTION:
4002 enc_algo = CAM_WEP104;
4003 break;
4004 case TKIP_ENCRYPTION:
4005 enc_algo = CAM_TKIP;
4006 break;
4007 case AESCCMP_ENCRYPTION:
4008 enc_algo = CAM_AES;
4009 break;
4010 default:
4011 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
4012 "switch case not process\n");
4013 enc_algo = CAM_TKIP;
4014 break;
4015 }
4016
4017 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
4018 macaddr = cam_const_addr[key_index];
4019 entry_id = key_index;
4020 } else {
4021 if (is_group) {
4022 macaddr = cam_const_broad;
4023 entry_id = key_index;
4024 } else {
4025 if (mac->opmode == NL80211_IFTYPE_AP) {
4026 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
4027 if (entry_id >= TOTAL_CAM_ENTRY) {
4028 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
4029 "Can not find free hwsecurity cam entry\n");
4030 return;
4031 }
4032 } else {
4033 entry_id = CAM_PAIRWISE_KEY_POSITION;
4034 }
4035
4036 key_index = PAIRWISE_KEYIDX;
4037 is_pairwise = true;
4038 }
4039 }
4040
4041 if (rtlpriv->sec.key_len[key_index] == 0) {
4042 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4043 "delete one entry, entry_id is %d\n",
4044 entry_id);
4045 if (mac->opmode == NL80211_IFTYPE_AP)
4046 rtl_cam_del_entry(hw, p_macaddr);
4047 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
4048 } else {
4049 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4050 "add one entry\n");
4051 if (is_pairwise) {
4052 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4053 "set Pairwise key\n");
4054
4055 rtl_cam_add_one_entry(hw, macaddr, key_index,
4056 entry_id, enc_algo,
4057 CAM_CONFIG_NO_USEDK,
4058 rtlpriv->sec.key_buf[key_index]);
4059 } else {
4060 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4061 "set group key\n");
4062
4063 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
4064 rtl_cam_add_one_entry(hw,
4065 rtlefuse->dev_addr,
4066 PAIRWISE_KEYIDX,
4067 CAM_PAIRWISE_KEY_POSITION,
4068 enc_algo,
4069 CAM_CONFIG_NO_USEDK,
4070 rtlpriv->sec.key_buf
4071 [entry_id]);
4072 }
4073
4074 rtl_cam_add_one_entry(hw, macaddr, key_index,
4075 entry_id, enc_algo,
4076 CAM_CONFIG_NO_USEDK,
4077 rtlpriv->sec.key_buf[entry_id]);
4078 }
4079 }
4080 }
4081 }
4082
4083 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4084 {
4085 struct rtl_priv *rtlpriv = rtl_priv(hw);
4086
4087 /* 0:Low, 1:High, 2:From Efuse. */
4088 rtlpriv->btcoexist.reg_bt_iso = 2;
4089 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4090 rtlpriv->btcoexist.reg_bt_sco = 3;
4091 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4092 rtlpriv->btcoexist.reg_bt_sco = 0;
4093 }
4094
4095 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4096 {
4097 struct rtl_priv *rtlpriv = rtl_priv(hw);
4098
4099 if (rtlpriv->cfg->ops->get_btc_status())
4100 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4101 }
4102
4103 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4104 {
4105 }
4106
4107 void rtl8821ae_resume(struct ieee80211_hw *hw)
4108 {
4109 }
4110
4111 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4112 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4113 bool allow_all_da, bool write_into_reg)
4114 {
4115 struct rtl_priv *rtlpriv = rtl_priv(hw);
4116 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4117
4118 if (allow_all_da) /* Set BIT0 */
4119 rtlpci->receive_config |= RCR_AAP;
4120 else /* Clear BIT0 */
4121 rtlpci->receive_config &= ~RCR_AAP;
4122
4123 if (write_into_reg)
4124 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4125
4126 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4127 "receive_config=0x%08X, write_into_reg=%d\n",
4128 rtlpci->receive_config, write_into_reg);
4129 }
4130
4131 /* WKFMCAMAddAllEntry8812 */
4132 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4133 struct rtl_wow_pattern *rtl_pattern,
4134 u8 index)
4135 {
4136 struct rtl_priv *rtlpriv = rtl_priv(hw);
4137 u32 cam = 0;
4138 u8 addr = 0;
4139 u16 rxbuf_addr;
4140 u8 tmp, count = 0;
4141 u16 cam_start;
4142 u16 offset;
4143
4144 /* Count the WFCAM entry start offset. */
4145
4146 /* RX page size = 128 byte */
4147 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4148 /* We should start from the boundry */
4149 cam_start = offset * 128;
4150
4151 /* Enable Rx packet buffer access. */
4152 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4153 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4154 /* Set Rx packet buffer offset.
4155 * RxBufer pointer increases 1,
4156 * we can access 8 bytes in Rx packet buffer.
4157 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE
4158 * RxBufer addr = (CAM start offset +
4159 * per entry offset of a WKFM CAM)/8
4160 * * index: The index of the wake up frame mask
4161 * * WKFMCAM_SIZE: the total size of one WKFM CAM
4162 * * per entry offset of a WKFM CAM: Addr*4 bytes
4163 */
4164 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4165 /* Set R/W start offset */
4166 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4167
4168 if (addr == 0) {
4169 cam = BIT(31) | rtl_pattern->crc;
4170
4171 if (rtl_pattern->type == UNICAST_PATTERN)
4172 cam |= BIT(24);
4173 else if (rtl_pattern->type == MULTICAST_PATTERN)
4174 cam |= BIT(25);
4175 else if (rtl_pattern->type == BROADCAST_PATTERN)
4176 cam |= BIT(26);
4177
4178 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4179 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4180 "WRITE entry[%d] 0x%x: %x\n", addr,
4181 REG_PKTBUF_DBG_DATA_L, cam);
4182
4183 /* Write to Rx packet buffer. */
4184 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4185 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4186 cam = rtl_pattern->mask[addr - 2];
4187
4188 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4189 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4190 "WRITE entry[%d] 0x%x: %x\n", addr,
4191 REG_PKTBUF_DBG_DATA_L, cam);
4192
4193 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4194 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4195 cam = rtl_pattern->mask[addr - 2];
4196
4197 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4198 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4199 "WRITE entry[%d] 0x%x: %x\n", addr,
4200 REG_PKTBUF_DBG_DATA_H, cam);
4201
4202 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4203 }
4204
4205 count = 0;
4206 do {
4207 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4208 udelay(2);
4209 count++;
4210 } while (tmp && count < 100);
4211
4212 RT_ASSERT((count < 100),
4213 "Write wake up frame mask FAIL %d value!\n", tmp);
4214 }
4215 /* Disable Rx packet buffer access. */
4216 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4217 DISABLE_TRXPKT_BUF_ACCESS);
4218 }
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