1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
36 #include "../btcoexist/halbt_precomp.h"
40 #define READ_NEXT_PAIR(array_table, v1, v2, i) \
43 v1 = array_table[i]; \
44 v2 = array_table[i+1]; \
47 static u32
_rtl8821ae_phy_rf_serial_read(struct ieee80211_hw
*hw
,
48 enum radio_path rfpath
, u32 offset
);
49 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw
*hw
,
50 enum radio_path rfpath
, u32 offset
,
52 static u32
_rtl8821ae_phy_calculate_bit_shift(u32 bitmask
);
53 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw
*hw
);
54 /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/
55 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw
*hw
);
56 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw
*hw
,
58 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw
*hw
,
60 static void phy_init_bb_rf_register_definition(struct ieee80211_hw
*hw
);
62 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw
*hw
,
63 enum wireless_mode wirelessmode
,
65 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw
*hw
);
66 static void rtl8821ae_phy_set_io(struct ieee80211_hw
*hw
);
68 static void rtl8812ae_fixspur(struct ieee80211_hw
*hw
,
69 enum ht_channel_width band_width
, u8 channel
)
71 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
73 /*C cut Item12 ADC FIFO CLOCK*/
74 if (IS_VENDOR_8812A_C_CUT(rtlhal
->version
)) {
75 if (band_width
== HT_CHANNEL_WIDTH_20_40
&& channel
== 11)
76 rtl_set_bbreg(hw
, RRFMOD
, 0xC00, 0x3);
77 /* 0x8AC[11:10] = 2'b11*/
79 rtl_set_bbreg(hw
, RRFMOD
, 0xC00, 0x2);
80 /* 0x8AC[11:10] = 2'b10*/
82 /* <20120914, Kordan> A workarould to resolve
83 * 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)
85 if (band_width
== HT_CHANNEL_WIDTH_20
&&
86 (channel
== 13 || channel
== 14)) {
87 rtl_set_bbreg(hw
, RRFMOD
, 0x300, 0x3);
88 /*0x8AC[9:8] = 2'b11*/
89 rtl_set_bbreg(hw
, RADC_BUF_CLK
, BIT(30), 1);
91 } else if (band_width
== HT_CHANNEL_WIDTH_20_40
&&
93 rtl_set_bbreg(hw
, RADC_BUF_CLK
, BIT(30), 1);
95 } else if (band_width
!= HT_CHANNEL_WIDTH_80
) {
96 rtl_set_bbreg(hw
, RRFMOD
, 0x300, 0x2);
97 /*0x8AC[9:8] = 2'b10*/
98 rtl_set_bbreg(hw
, RADC_BUF_CLK
, BIT(30), 0);
101 } else if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
102 /* <20120914, Kordan> A workarould to resolve
103 * 2480Mhz spur by setting ADC clock as 160M.
105 if (band_width
== HT_CHANNEL_WIDTH_20
&&
106 (channel
== 13 || channel
== 14))
107 rtl_set_bbreg(hw
, RRFMOD
, 0x300, 0x3);
109 else if (channel
<= 14) /*2.4G only*/
110 rtl_set_bbreg(hw
, RRFMOD
, 0x300, 0x2);
115 u32
rtl8821ae_phy_query_bb_reg(struct ieee80211_hw
*hw
, u32 regaddr
,
118 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
119 u32 returnvalue
, originalvalue
, bitshift
;
121 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
122 "regaddr(%#x), bitmask(%#x)\n",
124 originalvalue
= rtl_read_dword(rtlpriv
, regaddr
);
125 bitshift
= _rtl8821ae_phy_calculate_bit_shift(bitmask
);
126 returnvalue
= (originalvalue
& bitmask
) >> bitshift
;
128 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
129 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
130 bitmask
, regaddr
, originalvalue
);
134 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw
*hw
,
135 u32 regaddr
, u32 bitmask
, u32 data
)
137 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
138 u32 originalvalue
, bitshift
;
140 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
141 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
142 regaddr
, bitmask
, data
);
144 if (bitmask
!= MASKDWORD
) {
145 originalvalue
= rtl_read_dword(rtlpriv
, regaddr
);
146 bitshift
= _rtl8821ae_phy_calculate_bit_shift(bitmask
);
147 data
= ((originalvalue
& (~bitmask
)) |
148 ((data
<< bitshift
) & bitmask
));
151 rtl_write_dword(rtlpriv
, regaddr
, data
);
153 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
154 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
155 regaddr
, bitmask
, data
);
158 u32
rtl8821ae_phy_query_rf_reg(struct ieee80211_hw
*hw
,
159 enum radio_path rfpath
, u32 regaddr
,
162 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
163 u32 original_value
, readback_value
, bitshift
;
166 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
167 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
168 regaddr
, rfpath
, bitmask
);
170 spin_lock_irqsave(&rtlpriv
->locks
.rf_lock
, flags
);
172 original_value
= _rtl8821ae_phy_rf_serial_read(hw
, rfpath
, regaddr
);
173 bitshift
= _rtl8821ae_phy_calculate_bit_shift(bitmask
);
174 readback_value
= (original_value
& bitmask
) >> bitshift
;
176 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_lock
, flags
);
178 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
179 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
180 regaddr
, rfpath
, bitmask
, original_value
);
182 return readback_value
;
185 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw
*hw
,
186 enum radio_path rfpath
,
187 u32 regaddr
, u32 bitmask
, u32 data
)
189 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
190 u32 original_value
, bitshift
;
193 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
194 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
195 regaddr
, bitmask
, data
, rfpath
);
197 spin_lock_irqsave(&rtlpriv
->locks
.rf_lock
, flags
);
199 if (bitmask
!= RFREG_OFFSET_MASK
) {
201 _rtl8821ae_phy_rf_serial_read(hw
, rfpath
, regaddr
);
202 bitshift
= _rtl8821ae_phy_calculate_bit_shift(bitmask
);
203 data
= ((original_value
& (~bitmask
)) | (data
<< bitshift
));
206 _rtl8821ae_phy_rf_serial_write(hw
, rfpath
, regaddr
, data
);
208 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_lock
, flags
);
210 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
211 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
212 regaddr
, bitmask
, data
, rfpath
);
215 static u32
_rtl8821ae_phy_rf_serial_read(struct ieee80211_hw
*hw
,
216 enum radio_path rfpath
, u32 offset
)
218 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
219 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
220 bool is_pi_mode
= false;
223 /* 2009/06/17 MH We can not execute IO for power
224 save or other accident mode.*/
225 if (RT_CANNOT_IO(hw
)) {
226 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "return all one\n");
229 /* <20120809, Kordan> CCA OFF(when entering),
230 asked by James to avoid reading the wrong value.
231 <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
233 !((rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) ||
234 (IS_VENDOR_8812A_C_CUT(rtlhal
->version
))))
235 rtl_set_bbreg(hw
, RCCAONSEC
, 0x8, 1);
238 if (rfpath
== RF90_PATH_A
)
239 is_pi_mode
= (bool)rtl_get_bbreg(hw
, 0xC00, 0x4);
240 else if (rfpath
== RF90_PATH_B
)
241 is_pi_mode
= (bool)rtl_get_bbreg(hw
, 0xE00, 0x4);
243 rtl_set_bbreg(hw
, RHSSIREAD_8821AE
, 0xff, offset
);
245 if ((rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) ||
246 (IS_VENDOR_8812A_C_CUT(rtlhal
->version
)))
250 if (rfpath
== RF90_PATH_A
)
252 rtl_get_bbreg(hw
, RA_PIREAD_8821A
, BLSSIREADBACKDATA
);
253 else if (rfpath
== RF90_PATH_B
)
255 rtl_get_bbreg(hw
, RB_PIREAD_8821A
, BLSSIREADBACKDATA
);
257 if (rfpath
== RF90_PATH_A
)
259 rtl_get_bbreg(hw
, RA_SIREAD_8821A
, BLSSIREADBACKDATA
);
260 else if (rfpath
== RF90_PATH_B
)
262 rtl_get_bbreg(hw
, RB_SIREAD_8821A
, BLSSIREADBACKDATA
);
265 /*<20120809, Kordan> CCA ON(when exiting),
266 * asked by James to avoid reading the wrong value.
267 * <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!
270 !((rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) ||
271 (IS_VENDOR_8812A_C_CUT(rtlhal
->version
))))
272 rtl_set_bbreg(hw
, RCCAONSEC
, 0x8, 0);
276 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw
*hw
,
277 enum radio_path rfpath
, u32 offset
,
280 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
281 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
282 struct bb_reg_def
*pphyreg
= &rtlphy
->phyreg_def
[rfpath
];
286 if (RT_CANNOT_IO(hw
)) {
287 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "stop\n");
292 data_and_addr
= ((newoffset
<< 20) |
293 (data
& 0x000fffff)) & 0x0fffffff;
294 rtl_set_bbreg(hw
, pphyreg
->rf3wire_offset
, MASKDWORD
, data_and_addr
);
295 RT_TRACE(rtlpriv
, COMP_RF
, DBG_TRACE
,
296 "RFW-%d Addr[0x%x]=0x%x\n",
297 rfpath
, pphyreg
->rf3wire_offset
, data_and_addr
);
300 static u32
_rtl8821ae_phy_calculate_bit_shift(u32 bitmask
)
304 for (i
= 0; i
<= 31; i
++) {
305 if (((bitmask
>> i
) & 0x1) == 1)
311 bool rtl8821ae_phy_mac_config(struct ieee80211_hw
*hw
)
315 rtstatus
= _rtl8821ae_phy_config_mac_with_headerfile(hw
);
320 bool rtl8821ae_phy_bb_config(struct ieee80211_hw
*hw
)
322 bool rtstatus
= true;
323 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
324 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
325 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
326 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
330 phy_init_bb_rf_register_definition(hw
);
332 regval
= rtl_read_byte(rtlpriv
, REG_SYS_FUNC_EN
);
334 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, regval
);
335 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
,
336 regval
| FEN_BB_GLB_RSTN
| FEN_BBRSTB
);
338 rtl_write_byte(rtlpriv
, REG_RF_CTRL
, 0x7);
339 rtl_write_byte(rtlpriv
, REG_OPT_CTRL
+ 2, 0x7);
341 rtstatus
= _rtl8821ae_phy_bb8821a_config_parafile(hw
);
343 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
344 crystal_cap
= rtlefuse
->crystalcap
& 0x3F;
345 rtl_set_bbreg(hw
, REG_MAC_PHY_CTRL
, 0x7FF80000,
346 (crystal_cap
| (crystal_cap
<< 6)));
348 crystal_cap
= rtlefuse
->crystalcap
& 0x3F;
349 rtl_set_bbreg(hw
, REG_MAC_PHY_CTRL
, 0xFFF000,
350 (crystal_cap
| (crystal_cap
<< 6)));
352 rtlphy
->reg_837
= rtl_read_byte(rtlpriv
, 0x837);
357 bool rtl8821ae_phy_rf_config(struct ieee80211_hw
*hw
)
359 return rtl8821ae_phy_rf6052_config(hw
);
362 u32
phy_get_tx_swing_8812A(struct ieee80211_hw
*hw
, u8 band
,
365 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
366 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
367 struct rtl_dm
*rtldm
= rtl_dm(rtlpriv
);
368 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
369 char reg_swing_2g
= -1;/* 0xff; */
370 char reg_swing_5g
= -1;/* 0xff; */
371 char swing_2g
= -1 * reg_swing_2g
;
372 char swing_5g
= -1 * reg_swing_5g
;
374 const char auto_temp
= -1;
376 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
,
377 "===> PHY_GetTxBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d,autoload_failflag=%d.\n",
378 (int)swing_2g
, (int)swing_5g
,
379 (int)rtlefuse
->autoload_failflag
);
381 if (rtlefuse
->autoload_failflag
) {
382 if (band
== BAND_ON_2_4G
) {
383 rtldm
->swing_diff_2g
= swing_2g
;
385 out
= 0x200; /* 0 dB */
386 } else if (swing_2g
== -3) {
387 out
= 0x16A; /* -3 dB */
388 } else if (swing_2g
== -6) {
389 out
= 0x101; /* -6 dB */
390 } else if (swing_2g
== -9) {
391 out
= 0x0B6; /* -9 dB */
393 rtldm
->swing_diff_2g
= 0;
396 } else if (band
== BAND_ON_5G
) {
397 rtldm
->swing_diff_5g
= swing_5g
;
399 out
= 0x200; /* 0 dB */
400 } else if (swing_5g
== -3) {
401 out
= 0x16A; /* -3 dB */
402 } else if (swing_5g
== -6) {
403 out
= 0x101; /* -6 dB */
404 } else if (swing_5g
== -9) {
405 out
= 0x0B6; /* -9 dB */
407 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
408 rtldm
->swing_diff_5g
= -3;
411 rtldm
->swing_diff_5g
= 0;
416 rtldm
->swing_diff_2g
= -3;
417 rtldm
->swing_diff_5g
= -3;
418 out
= 0x16A; /* -3 dB */
421 u32 swing
= 0, swing_a
= 0, swing_b
= 0;
423 if (band
== BAND_ON_2_4G
) {
424 if (reg_swing_2g
== auto_temp
) {
425 efuse_shadow_read(hw
, 1, 0xC6, (u32
*)&swing
);
426 swing
= (swing
== 0xFF) ? 0x00 : swing
;
427 } else if (swing_2g
== 0) {
428 swing
= 0x00; /* 0 dB */
429 } else if (swing_2g
== -3) {
430 swing
= 0x05; /* -3 dB */
431 } else if (swing_2g
== -6) {
432 swing
= 0x0A; /* -6 dB */
433 } else if (swing_2g
== -9) {
434 swing
= 0xFF; /* -9 dB */
439 if (reg_swing_5g
== auto_temp
) {
440 efuse_shadow_read(hw
, 1, 0xC7, (u32
*)&swing
);
441 swing
= (swing
== 0xFF) ? 0x00 : swing
;
442 } else if (swing_5g
== 0) {
443 swing
= 0x00; /* 0 dB */
444 } else if (swing_5g
== -3) {
445 swing
= 0x05; /* -3 dB */
446 } else if (swing_5g
== -6) {
447 swing
= 0x0A; /* -6 dB */
448 } else if (swing_5g
== -9) {
449 swing
= 0xFF; /* -9 dB */
455 swing_a
= (swing
& 0x3) >> 0; /* 0xC6/C7[1:0] */
456 swing_b
= (swing
& 0xC) >> 2; /* 0xC6/C7[3:2] */
457 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
,
458 "===> PHY_GetTxBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n",
462 if (swing_a
== 0x0) {
463 if (band
== BAND_ON_2_4G
)
464 rtldm
->swing_diff_2g
= 0;
466 rtldm
->swing_diff_5g
= 0;
467 out
= 0x200; /* 0 dB */
468 } else if (swing_a
== 0x1) {
469 if (band
== BAND_ON_2_4G
)
470 rtldm
->swing_diff_2g
= -3;
472 rtldm
->swing_diff_5g
= -3;
473 out
= 0x16A; /* -3 dB */
474 } else if (swing_a
== 0x2) {
475 if (band
== BAND_ON_2_4G
)
476 rtldm
->swing_diff_2g
= -6;
478 rtldm
->swing_diff_5g
= -6;
479 out
= 0x101; /* -6 dB */
480 } else if (swing_a
== 0x3) {
481 if (band
== BAND_ON_2_4G
)
482 rtldm
->swing_diff_2g
= -9;
484 rtldm
->swing_diff_5g
= -9;
485 out
= 0x0B6; /* -9 dB */
488 if (swing_b
== 0x0) {
489 if (band
== BAND_ON_2_4G
)
490 rtldm
->swing_diff_2g
= 0;
492 rtldm
->swing_diff_5g
= 0;
493 out
= 0x200; /* 0 dB */
494 } else if (swing_b
== 0x1) {
495 if (band
== BAND_ON_2_4G
)
496 rtldm
->swing_diff_2g
= -3;
498 rtldm
->swing_diff_5g
= -3;
499 out
= 0x16A; /* -3 dB */
500 } else if (swing_b
== 0x2) {
501 if (band
== BAND_ON_2_4G
)
502 rtldm
->swing_diff_2g
= -6;
504 rtldm
->swing_diff_5g
= -6;
505 out
= 0x101; /* -6 dB */
506 } else if (swing_b
== 0x3) {
507 if (band
== BAND_ON_2_4G
)
508 rtldm
->swing_diff_2g
= -9;
510 rtldm
->swing_diff_5g
= -9;
511 out
= 0x0B6; /* -9 dB */
515 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
,
516 "<=== PHY_GetTxBBSwing_8812A, out = 0x%X\n", out
);
520 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw
*hw
, u8 band
)
522 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
523 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
524 struct rtl_dm
*rtldm
= rtl_dm(rtlpriv
);
525 u8 current_band
= rtlhal
->current_bandtype
;
527 char bb_diff_between_band
;
529 txpath
= rtl8821ae_phy_query_bb_reg(hw
, RTXPATH
, 0xf0);
530 rxpath
= rtl8821ae_phy_query_bb_reg(hw
, RCCK_RX
, 0x0f000000);
531 rtlhal
->current_bandtype
= (enum band_type
) band
;
532 /* reconfig BB/RF according to wireless mode */
533 if (rtlhal
->current_bandtype
== BAND_ON_2_4G
) {
535 rtl_set_bbreg(hw
, ROFDMCCKEN
, BOFDMEN
|BCCKEN
, 0x03);
537 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
538 /* 0xCB0[15:12] = 0x7 (LNA_On)*/
539 rtl_set_bbreg(hw
, RA_RFE_PINMUX
, 0xF000, 0x7);
540 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
541 rtl_set_bbreg(hw
, RA_RFE_PINMUX
, 0xF0, 0x7);
544 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
546 rtl_set_bbreg(hw
, 0x834, 0x3, 0x1);
549 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
550 /* 0xC1C[11:8] = 0 */
551 rtl_set_bbreg(hw
, RA_TXSCALE
, 0xF00, 0);
553 /* 0x82C[1:0] = 2b'00 */
554 rtl_set_bbreg(hw
, 0x82c, 0x3, 0);
556 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
557 rtl_set_bbreg(hw
, RA_RFE_PINMUX
, BMASKDWORD
,
559 rtl_set_bbreg(hw
, RB_RFE_PINMUX
, BMASKDWORD
,
561 rtl_set_bbreg(hw
, RA_RFE_INV
, 0x3ff00000, 0x000);
562 rtl_set_bbreg(hw
, RB_RFE_INV
, 0x3ff00000, 0x000);
565 rtl_set_bbreg(hw
, RTXPATH
, 0xf0, 0x1);
566 rtl_set_bbreg(hw
, RCCK_RX
, 0x0f000000, 0x1);
568 rtl_write_byte(rtlpriv
, REG_CCK_CHECK
, 0x0);
569 } else {/* 5G band */
572 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
573 /*0xCB0[15:12] = 0x5 (LNA_On)*/
574 rtl_set_bbreg(hw
, RA_RFE_PINMUX
, 0xF000, 0x5);
575 /*0xCB0[7:4] = 0x4 (PAPE_A)*/
576 rtl_set_bbreg(hw
, RA_RFE_PINMUX
, 0xF0, 0x4);
579 rtl_write_byte(rtlpriv
, REG_CCK_CHECK
, 0x80);
582 reg_41a
= rtl_read_word(rtlpriv
, REG_TXPKT_EMPTY
);
583 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
,
584 "Reg41A value %d", reg_41a
);
586 while ((reg_41a
!= 0x30) && (count
< 50)) {
588 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
, "Delay 50us\n");
590 reg_41a
= rtl_read_word(rtlpriv
, REG_TXPKT_EMPTY
);
593 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
,
594 "Reg41A value %d", reg_41a
);
597 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
598 "PHY_SwitchWirelessBand8812(): Switch to 5G Band. Count = %d reg41A=0x%x\n",
601 /* 2012/02/01, Sinda add registry to switch workaround
602 without long-run verification for scan issue. */
603 rtl_set_bbreg(hw
, ROFDMCCKEN
, BOFDMEN
|BCCKEN
, 0x03);
605 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
607 rtl_set_bbreg(hw
, 0x834, 0x3, 0x2);
610 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
611 /* AGC table select */
613 rtl_set_bbreg(hw
, RA_TXSCALE
, 0xF00, 1);
615 /* 0x82C[1:0] = 2'b00 */
616 rtl_set_bbreg(hw
, 0x82c, 0x3, 1);
618 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
619 rtl_set_bbreg(hw
, RA_RFE_PINMUX
, BMASKDWORD
,
621 rtl_set_bbreg(hw
, RB_RFE_PINMUX
, BMASKDWORD
,
623 rtl_set_bbreg(hw
, RA_RFE_INV
, 0x3ff00000, 0x010);
624 rtl_set_bbreg(hw
, RB_RFE_INV
, 0x3ff00000, 0x010);
627 rtl_set_bbreg(hw
, RTXPATH
, 0xf0, 0);
628 rtl_set_bbreg(hw
, RCCK_RX
, 0x0f000000, 0xf);
630 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
,
631 "==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n",
632 rtlpriv
->dm
.ofdm_index
[RF90_PATH_A
]);
635 if ((rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) ||
636 (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
)) {
638 rtl_set_bbreg(hw
, RA_TXSCALE
, 0xFFE00000,
639 phy_get_tx_swing_8812A(hw
, band
, RF90_PATH_A
));
641 rtl_set_bbreg(hw
, RB_TXSCALE
, 0xFFE00000,
642 phy_get_tx_swing_8812A(hw
, band
, RF90_PATH_B
));
644 /* <20121005, Kordan> When TxPowerTrack is ON,
645 * we should take care of the change of BB swing.
646 * That is, reset all info to trigger Tx power tracking.
648 if (band
!= current_band
) {
649 bb_diff_between_band
=
650 (rtldm
->swing_diff_2g
- rtldm
->swing_diff_5g
);
651 bb_diff_between_band
= (band
== BAND_ON_2_4G
) ?
652 bb_diff_between_band
:
653 (-1 * bb_diff_between_band
);
654 rtldm
->default_ofdm_index
+= bb_diff_between_band
* 2;
656 rtl8821ae_dm_clear_txpower_tracking_state(hw
);
659 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
,
660 "<==rtl8821ae_phy_switch_wirelessband():Switch Band OK.\n");
664 static bool _rtl8821ae_check_condition(struct ieee80211_hw
*hw
,
667 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
668 u32 _board
= rtlefuse
->board_type
; /*need efuse define*/
669 u32 _interface
= 0x01; /* ODM_ITRF_PCIE */
670 u32 _platform
= 0x08;/* ODM_WIN */
671 u32 cond
= condition
;
673 if (condition
== 0xCDCDCDCD)
676 cond
= condition
& 0xFF;
677 if ((_board
!= cond
) && cond
!= 0xFF)
680 cond
= condition
& 0xFF00;
682 if ((_interface
& cond
) == 0 && cond
!= 0x07)
685 cond
= condition
& 0xFF0000;
687 if ((_platform
& cond
) == 0 && cond
!= 0x0F)
692 static void _rtl8821ae_config_rf_reg(struct ieee80211_hw
*hw
,
694 enum radio_path rfpath
, u32 regaddr
)
696 if (addr
== 0xfe || addr
== 0xffe) {
697 /* In order not to disturb BT music when
698 * wifi init.(1ant NIC only)
702 rtl_set_rfreg(hw
, rfpath
, regaddr
, RFREG_OFFSET_MASK
, data
);
707 static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw
*hw
,
710 u32 content
= 0x1000; /*RF Content: radio_a_txt*/
711 u32 maskforphyset
= (u32
)(content
& 0xE000);
713 _rtl8821ae_config_rf_reg(hw
, addr
, data
,
714 RF90_PATH_A
, addr
| maskforphyset
);
717 static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw
*hw
,
720 u32 content
= 0x1001; /*RF Content: radio_b_txt*/
721 u32 maskforphyset
= (u32
)(content
& 0xE000);
723 _rtl8821ae_config_rf_reg(hw
, addr
, data
,
724 RF90_PATH_B
, addr
| maskforphyset
);
727 static void _rtl8821ae_config_bb_reg(struct ieee80211_hw
*hw
,
732 else if (addr
== 0xfd)
734 else if (addr
== 0xfc)
736 else if (addr
== 0xfb)
738 else if (addr
== 0xfa)
740 else if (addr
== 0xf9)
743 rtl_set_bbreg(hw
, addr
, MASKDWORD
, data
);
748 static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw
*hw
)
750 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
751 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
752 u8 band
, rfpath
, txnum
, rate_section
;
754 for (band
= BAND_ON_2_4G
; band
<= BAND_ON_5G
; ++band
)
755 for (rfpath
= 0; rfpath
< TX_PWR_BY_RATE_NUM_RF
; ++rfpath
)
756 for (txnum
= 0; txnum
< TX_PWR_BY_RATE_NUM_RF
; ++txnum
)
757 for (rate_section
= 0;
758 rate_section
< TX_PWR_BY_RATE_NUM_SECTION
;
760 rtlphy
->tx_power_by_rate_offset
[band
]
761 [rfpath
][txnum
][rate_section
] = 0;
764 static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw
*hw
,
769 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
770 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
772 if (path
> RF90_PATH_D
) {
773 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
774 "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path
);
778 if (band
== BAND_ON_2_4G
) {
779 switch (rate_section
) {
781 rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][0] = value
;
784 rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][1] = value
;
787 rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][2] = value
;
790 rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][3] = value
;
792 case VHT_1SSMCS0_1SSMCS9
:
793 rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][4] = value
;
795 case VHT_2SSMCS0_2SSMCS9
:
796 rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][5] = value
;
799 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
800 "Invalid RateSection %d in Band 2.4G,Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
801 rate_section
, path
, txnum
);
804 } else if (band
== BAND_ON_5G
) {
805 switch (rate_section
) {
807 rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][0] = value
;
810 rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][1] = value
;
813 rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][2] = value
;
815 case VHT_1SSMCS0_1SSMCS9
:
816 rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][3] = value
;
818 case VHT_2SSMCS0_2SSMCS9
:
819 rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][4] = value
;
822 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
823 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
824 rate_section
, path
, txnum
);
828 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
829 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band
);
833 static u8
_rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw
*hw
,
835 u8 txnum
, u8 rate_section
)
837 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
838 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
841 if (path
> RF90_PATH_D
) {
842 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
843 "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
848 if (band
== BAND_ON_2_4G
) {
849 switch (rate_section
) {
851 value
= rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][0];
854 value
= rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][1];
857 value
= rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][2];
860 value
= rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][3];
862 case VHT_1SSMCS0_1SSMCS9
:
863 value
= rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][4];
865 case VHT_2SSMCS0_2SSMCS9
:
866 value
= rtlphy
->txpwr_by_rate_base_24g
[path
][txnum
][5];
869 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
870 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
871 rate_section
, path
, txnum
);
874 } else if (band
== BAND_ON_5G
) {
875 switch (rate_section
) {
877 value
= rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][0];
880 value
= rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][1];
883 value
= rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][2];
885 case VHT_1SSMCS0_1SSMCS9
:
886 value
= rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][3];
888 case VHT_2SSMCS0_2SSMCS9
:
889 value
= rtlphy
->txpwr_by_rate_base_5g
[path
][txnum
][4];
892 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
893 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
894 rate_section
, path
, txnum
);
898 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
899 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band
);
905 static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw
*hw
)
907 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
908 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
910 u8 base
= 0, path
= 0;
912 for (path
= RF90_PATH_A
; path
<= RF90_PATH_B
; ++path
) {
913 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][path
][RF_1TX
][0] >> 24) & 0xFF;
914 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
915 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_2_4G
, path
, CCK
, RF_1TX
, base
);
917 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][path
][RF_1TX
][2] >> 24) & 0xFF;
918 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
919 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_2_4G
, path
, OFDM
, RF_1TX
, base
);
921 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][path
][RF_1TX
][4] >> 24) & 0xFF;
922 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
923 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_2_4G
, path
, HT_MCS0_MCS7
, RF_1TX
, base
);
925 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][path
][RF_2TX
][6] >> 24) & 0xFF;
926 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
927 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_2_4G
, path
, HT_MCS8_MCS15
, RF_2TX
, base
);
929 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][path
][RF_1TX
][8] >> 24) & 0xFF;
930 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
931 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_2_4G
, path
, VHT_1SSMCS0_1SSMCS9
, RF_1TX
, base
);
933 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][path
][RF_2TX
][11] >> 8) & 0xFF;
934 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
935 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_2_4G
, path
, VHT_2SSMCS0_2SSMCS9
, RF_2TX
, base
);
937 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][path
][RF_1TX
][2] >> 24) & 0xFF;
938 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
939 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_5G
, path
, OFDM
, RF_1TX
, base
);
941 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][path
][RF_1TX
][4] >> 24) & 0xFF;
942 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
943 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_5G
, path
, HT_MCS0_MCS7
, RF_1TX
, base
);
945 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][path
][RF_2TX
][6] >> 24) & 0xFF;
946 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
947 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_5G
, path
, HT_MCS8_MCS15
, RF_2TX
, base
);
949 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][path
][RF_1TX
][8] >> 24) & 0xFF;
950 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
951 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_5G
, path
, VHT_1SSMCS0_1SSMCS9
, RF_1TX
, base
);
953 rawValue
= (u16
)(rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][path
][RF_2TX
][11] >> 8) & 0xFF;
954 base
= (rawValue
>> 4) * 10 + (rawValue
& 0xF);
955 _rtl8821ae_phy_set_txpower_by_rate_base(hw
, BAND_ON_5G
, path
, VHT_2SSMCS0_2SSMCS9
, RF_2TX
, base
);
959 static void _phy_convert_txpower_dbm_to_relative_value(u32
*data
, u8 start
,
966 for (i
= 3; i
>= 0; --i
) {
967 if (i
>= start
&& i
<= end
) {
968 /* Get the exact value */
969 temp_value
= (u8
)(*data
>> (i
* 8)) & 0xF;
970 temp_value
+= ((u8
)((*data
>> (i
* 8 + 4)) & 0xF)) * 10;
972 /* Change the value to a relative value */
973 temp_value
= (temp_value
> base_val
) ? temp_value
-
974 base_val
: base_val
- temp_value
;
976 temp_value
= (u8
)(*data
>> (i
* 8)) & 0xFF;
979 temp_data
|= temp_value
;
984 static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw
*hw
)
986 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
987 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
988 u8 regulation
, bw
, channel
, rate_section
;
989 char temp_pwrlmt
= 0;
991 for (regulation
= 0; regulation
< MAX_REGULATION_NUM
; ++regulation
) {
992 for (bw
= 0; bw
< MAX_5G_BANDWITH_NUM
; ++bw
) {
993 for (channel
= 0; channel
< CHANNEL_MAX_NUMBER_5G
; ++channel
) {
994 for (rate_section
= 0; rate_section
< MAX_RATE_SECTION_NUM
; ++rate_section
) {
995 temp_pwrlmt
= rtlphy
->txpwr_limit_5g
[regulation
]
996 [bw
][rate_section
][channel
][RF90_PATH_A
];
997 if (temp_pwrlmt
== MAX_POWER_INDEX
) {
998 if (bw
== 0 || bw
== 1) { /*5G 20M 40M VHT and HT can cross reference*/
999 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1000 "No power limit table of the specified band %d, bandwidth %d, ratesection %d, channel %d, rf path %d\n",
1001 1, bw
, rate_section
, channel
, RF90_PATH_A
);
1002 if (rate_section
== 2) {
1003 rtlphy
->txpwr_limit_5g
[regulation
][bw
][2][channel
][RF90_PATH_A
] =
1004 rtlphy
->txpwr_limit_5g
[regulation
][bw
][4][channel
][RF90_PATH_A
];
1005 } else if (rate_section
== 4) {
1006 rtlphy
->txpwr_limit_5g
[regulation
][bw
][4][channel
][RF90_PATH_A
] =
1007 rtlphy
->txpwr_limit_5g
[regulation
][bw
][2][channel
][RF90_PATH_A
];
1008 } else if (rate_section
== 3) {
1009 rtlphy
->txpwr_limit_5g
[regulation
][bw
][3][channel
][RF90_PATH_A
] =
1010 rtlphy
->txpwr_limit_5g
[regulation
][bw
][5][channel
][RF90_PATH_A
];
1011 } else if (rate_section
== 5) {
1012 rtlphy
->txpwr_limit_5g
[regulation
][bw
][5][channel
][RF90_PATH_A
] =
1013 rtlphy
->txpwr_limit_5g
[regulation
][bw
][3][channel
][RF90_PATH_A
];
1016 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "use other value %d", temp_pwrlmt
);
1025 static u8
_rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw
*hw
,
1026 enum band_type band
, u8 rate
)
1028 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1030 if (band
== BAND_ON_2_4G
) {
1073 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1074 "Wrong rate 0x%x to obtain index in 2.4G in PHY_GetTxPowerByRateBaseIndex()\n",
1078 } else if (band
== BAND_ON_5G
) {
1113 case MGN_VHT1SS_MCS0
:
1114 case MGN_VHT1SS_MCS1
:
1115 case MGN_VHT1SS_MCS2
:
1116 case MGN_VHT1SS_MCS3
:
1117 case MGN_VHT1SS_MCS4
:
1118 case MGN_VHT1SS_MCS5
:
1119 case MGN_VHT1SS_MCS6
:
1120 case MGN_VHT1SS_MCS7
:
1121 case MGN_VHT1SS_MCS8
:
1122 case MGN_VHT1SS_MCS9
:
1126 case MGN_VHT2SS_MCS0
:
1127 case MGN_VHT2SS_MCS1
:
1128 case MGN_VHT2SS_MCS2
:
1129 case MGN_VHT2SS_MCS3
:
1130 case MGN_VHT2SS_MCS4
:
1131 case MGN_VHT2SS_MCS5
:
1132 case MGN_VHT2SS_MCS6
:
1133 case MGN_VHT2SS_MCS7
:
1134 case MGN_VHT2SS_MCS8
:
1135 case MGN_VHT2SS_MCS9
:
1140 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1141 "Wrong rate 0x%x to obtain index in 5G in PHY_GetTxPowerByRateBaseIndex()\n",
1150 static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw
*hw
)
1152 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1153 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
1154 u8 bw40_pwr_base_dbm2_4G
, bw40_pwr_base_dbm5G
;
1155 u8 regulation
, bw
, channel
, rate_section
;
1156 u8 base_index2_4G
= 0;
1157 u8 base_index5G
= 0;
1158 char temp_value
= 0, temp_pwrlmt
= 0;
1161 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1162 "=====> _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n");
1164 _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw
);
1166 for (regulation
= 0; regulation
< MAX_REGULATION_NUM
; ++regulation
) {
1167 for (bw
= 0; bw
< MAX_2_4G_BANDWITH_NUM
; ++bw
) {
1168 for (channel
= 0; channel
< CHANNEL_MAX_NUMBER_2G
; ++channel
) {
1169 for (rate_section
= 0; rate_section
< MAX_RATE_SECTION_NUM
; ++rate_section
) {
1170 /* obtain the base dBm values in 2.4G band
1171 CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15*/
1172 if (rate_section
== 0) { /*CCK*/
1174 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1175 BAND_ON_2_4G
, MGN_11M
);
1176 } else if (rate_section
== 1) { /*OFDM*/
1178 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1179 BAND_ON_2_4G
, MGN_54M
);
1180 } else if (rate_section
== 2) { /*HT IT*/
1182 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1183 BAND_ON_2_4G
, MGN_MCS7
);
1184 } else if (rate_section
== 3) { /*HT 2T*/
1186 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1187 BAND_ON_2_4G
, MGN_MCS15
);
1190 temp_pwrlmt
= rtlphy
->txpwr_limit_2_4g
[regulation
]
1191 [bw
][rate_section
][channel
][RF90_PATH_A
];
1193 for (rf_path
= RF90_PATH_A
;
1194 rf_path
< MAX_RF_PATH_NUM
;
1196 if (rate_section
== 3)
1197 bw40_pwr_base_dbm2_4G
=
1198 rtlphy
->txpwr_by_rate_base_24g
[rf_path
][RF_2TX
][base_index2_4G
];
1200 bw40_pwr_base_dbm2_4G
=
1201 rtlphy
->txpwr_by_rate_base_24g
[rf_path
][RF_1TX
][base_index2_4G
];
1203 if (temp_pwrlmt
!= MAX_POWER_INDEX
) {
1204 temp_value
= temp_pwrlmt
- bw40_pwr_base_dbm2_4G
;
1205 rtlphy
->txpwr_limit_2_4g
[regulation
]
1206 [bw
][rate_section
][channel
][rf_path
] =
1210 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1211 "TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfPath %d] %d)\n",
1212 regulation
, bw
, rate_section
, channel
,
1213 rtlphy
->txpwr_limit_2_4g
[regulation
][bw
]
1214 [rate_section
][channel
][rf_path
], (temp_pwrlmt
== 63)
1215 ? 0 : temp_pwrlmt
/2, channel
, rf_path
,
1216 bw40_pwr_base_dbm2_4G
);
1222 for (regulation
= 0; regulation
< MAX_REGULATION_NUM
; ++regulation
) {
1223 for (bw
= 0; bw
< MAX_5G_BANDWITH_NUM
; ++bw
) {
1224 for (channel
= 0; channel
< CHANNEL_MAX_NUMBER_5G
; ++channel
) {
1225 for (rate_section
= 0; rate_section
< MAX_RATE_SECTION_NUM
; ++rate_section
) {
1226 /* obtain the base dBm values in 5G band
1227 OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15,
1228 VHT => 1SSMCS7, VHT 2T => 2SSMCS7*/
1229 if (rate_section
== 1) { /*OFDM*/
1231 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1232 BAND_ON_5G
, MGN_54M
);
1233 } else if (rate_section
== 2) { /*HT 1T*/
1235 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1236 BAND_ON_5G
, MGN_MCS7
);
1237 } else if (rate_section
== 3) { /*HT 2T*/
1239 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1240 BAND_ON_5G
, MGN_MCS15
);
1241 } else if (rate_section
== 4) { /*VHT 1T*/
1243 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1244 BAND_ON_5G
, MGN_VHT1SS_MCS7
);
1245 } else if (rate_section
== 5) { /*VHT 2T*/
1247 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw
,
1248 BAND_ON_5G
, MGN_VHT2SS_MCS7
);
1251 temp_pwrlmt
= rtlphy
->txpwr_limit_5g
[regulation
]
1252 [bw
][rate_section
][channel
]
1255 for (rf_path
= RF90_PATH_A
;
1256 rf_path
< MAX_RF_PATH_NUM
;
1258 if (rate_section
== 3 || rate_section
== 5)
1259 bw40_pwr_base_dbm5G
=
1260 rtlphy
->txpwr_by_rate_base_5g
[rf_path
]
1261 [RF_2TX
][base_index5G
];
1263 bw40_pwr_base_dbm5G
=
1264 rtlphy
->txpwr_by_rate_base_5g
[rf_path
]
1265 [RF_1TX
][base_index5G
];
1267 if (temp_pwrlmt
!= MAX_POWER_INDEX
) {
1269 temp_pwrlmt
- bw40_pwr_base_dbm5G
;
1270 rtlphy
->txpwr_limit_5g
[regulation
]
1271 [bw
][rate_section
][channel
]
1272 [rf_path
] = temp_value
;
1275 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1276 "TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfPath %d] %d)\n",
1277 regulation
, bw
, rate_section
,
1278 channel
, rtlphy
->txpwr_limit_5g
[regulation
]
1279 [bw
][rate_section
][channel
][rf_path
],
1280 temp_pwrlmt
, channel
, rf_path
, bw40_pwr_base_dbm5G
);
1286 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1287 "<===== _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n");
1290 static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw
*hw
)
1292 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1293 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
1296 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1297 "=====> _rtl8821ae_phy_init_txpower_limit()!\n");
1299 for (i
= 0; i
< MAX_REGULATION_NUM
; ++i
) {
1300 for (j
= 0; j
< MAX_2_4G_BANDWITH_NUM
; ++j
)
1301 for (k
= 0; k
< MAX_RATE_SECTION_NUM
; ++k
)
1302 for (m
= 0; m
< CHANNEL_MAX_NUMBER_2G
; ++m
)
1303 for (l
= 0; l
< MAX_RF_PATH_NUM
; ++l
)
1304 rtlphy
->txpwr_limit_2_4g
1308 for (i
= 0; i
< MAX_REGULATION_NUM
; ++i
) {
1309 for (j
= 0; j
< MAX_5G_BANDWITH_NUM
; ++j
)
1310 for (k
= 0; k
< MAX_RATE_SECTION_NUM
; ++k
)
1311 for (m
= 0; m
< CHANNEL_MAX_NUMBER_5G
; ++m
)
1312 for (l
= 0; l
< MAX_RF_PATH_NUM
; ++l
)
1313 rtlphy
->txpwr_limit_5g
1318 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1319 "<===== _rtl8821ae_phy_init_txpower_limit()!\n");
1322 static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw
*hw
)
1324 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1325 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
1326 u8 base
= 0, rfPath
= 0;
1328 for (rfPath
= RF90_PATH_A
; rfPath
<= RF90_PATH_B
; ++rfPath
) {
1329 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_2_4G
, rfPath
, RF_1TX
, CCK
);
1330 _phy_convert_txpower_dbm_to_relative_value(
1331 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][0],
1334 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_2_4G
, rfPath
, RF_1TX
, OFDM
);
1335 _phy_convert_txpower_dbm_to_relative_value(
1336 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][1],
1338 _phy_convert_txpower_dbm_to_relative_value(
1339 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][2],
1342 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_2_4G
, rfPath
, RF_1TX
, HT_MCS0_MCS7
);
1343 _phy_convert_txpower_dbm_to_relative_value(
1344 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][3],
1346 _phy_convert_txpower_dbm_to_relative_value(
1347 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][4],
1350 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_2_4G
, rfPath
, RF_2TX
, HT_MCS8_MCS15
);
1352 _phy_convert_txpower_dbm_to_relative_value(
1353 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_2TX
][5],
1356 _phy_convert_txpower_dbm_to_relative_value(
1357 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_2TX
][6],
1360 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_2_4G
, rfPath
, RF_1TX
, VHT_1SSMCS0_1SSMCS9
);
1361 _phy_convert_txpower_dbm_to_relative_value(
1362 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][7],
1364 _phy_convert_txpower_dbm_to_relative_value(
1365 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][8],
1367 _phy_convert_txpower_dbm_to_relative_value(
1368 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][9],
1371 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_2_4G
, rfPath
, RF_2TX
, VHT_2SSMCS0_2SSMCS9
);
1372 _phy_convert_txpower_dbm_to_relative_value(
1373 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_1TX
][9],
1375 _phy_convert_txpower_dbm_to_relative_value(
1376 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_2TX
][10],
1378 _phy_convert_txpower_dbm_to_relative_value(
1379 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_2_4G
][rfPath
][RF_2TX
][11],
1382 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_5G
, rfPath
, RF_1TX
, OFDM
);
1383 _phy_convert_txpower_dbm_to_relative_value(
1384 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][1],
1386 _phy_convert_txpower_dbm_to_relative_value(
1387 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][2],
1390 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_5G
, rfPath
, RF_1TX
, HT_MCS0_MCS7
);
1391 _phy_convert_txpower_dbm_to_relative_value(
1392 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][3],
1394 _phy_convert_txpower_dbm_to_relative_value(
1395 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][4],
1398 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_5G
, rfPath
, RF_2TX
, HT_MCS8_MCS15
);
1399 _phy_convert_txpower_dbm_to_relative_value(
1400 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_2TX
][5],
1402 _phy_convert_txpower_dbm_to_relative_value(
1403 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_2TX
][6],
1406 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_5G
, rfPath
, RF_1TX
, VHT_1SSMCS0_1SSMCS9
);
1407 _phy_convert_txpower_dbm_to_relative_value(
1408 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][7],
1410 _phy_convert_txpower_dbm_to_relative_value(
1411 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][8],
1413 _phy_convert_txpower_dbm_to_relative_value(
1414 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][9],
1417 base
= _rtl8821ae_phy_get_txpower_by_rate_base(hw
, BAND_ON_5G
, rfPath
, RF_2TX
, VHT_2SSMCS0_2SSMCS9
);
1418 _phy_convert_txpower_dbm_to_relative_value(
1419 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_1TX
][9],
1421 _phy_convert_txpower_dbm_to_relative_value(
1422 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_2TX
][10],
1424 _phy_convert_txpower_dbm_to_relative_value(
1425 &rtlphy
->tx_power_by_rate_offset
[BAND_ON_5G
][rfPath
][RF_2TX
][11],
1429 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_TRACE
,
1430 "<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n");
1433 static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw
*hw
)
1435 _rtl8821ae_phy_store_txpower_by_rate_base(hw
);
1436 _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw
);
1439 /* string is in decimal */
1440 static bool _rtl8812ae_get_integer_from_string(char *str
, u8
*pint
)
1445 while (str
[i
] != '\0') {
1446 if (str
[i
] >= '0' && str
[i
] <= '9') {
1448 *pint
+= (str
[i
] - '0');
1458 static bool _rtl8812ae_eq_n_byte(u8
*str1
, u8
*str2
, u32 num
)
1464 if (str1
[num
] != str2
[num
])
1470 static char _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw
*hw
,
1471 u8 band
, u8 channel
)
1473 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1474 char channel_index
= -1;
1475 u8 channel_5g
[CHANNEL_MAX_NUMBER_5G
] = {
1476 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
1477 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
1478 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 149,
1479 151, 153, 155, 157, 159, 161, 163, 165, 167, 168, 169, 171,
1482 if (band
== BAND_ON_2_4G
)
1483 channel_index
= channel
- 1;
1484 else if (band
== BAND_ON_5G
) {
1485 for (i
= 0; i
< sizeof(channel_5g
)/sizeof(u8
); ++i
) {
1486 if (channel_5g
[i
] == channel
)
1490 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
, "Invalid Band %d in %s",
1493 if (channel_index
== -1)
1494 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
1495 "Invalid Channel %d of Band %d in %s", channel
,
1498 return channel_index
;
1501 static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw
*hw
, u8
*pregulation
,
1502 u8
*pband
, u8
*pbandwidth
,
1503 u8
*prate_section
, u8
*prf_path
,
1504 u8
*pchannel
, u8
*ppower_limit
)
1506 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1507 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
1508 u8 regulation
= 0, bandwidth
= 0, rate_section
= 0, channel
;
1510 char power_limit
= 0, prev_power_limit
, ret
;
1512 if (!_rtl8812ae_get_integer_from_string((char *)pchannel
, &channel
) ||
1513 !_rtl8812ae_get_integer_from_string((char *)ppower_limit
,
1515 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1516 "Illegal index of pwr_lmt table [chnl %d][val %d]\n",
1517 channel
, power_limit
);
1520 power_limit
= power_limit
> MAX_POWER_INDEX
?
1521 MAX_POWER_INDEX
: power_limit
;
1523 if (_rtl8812ae_eq_n_byte(pregulation
, (u8
*)("FCC"), 3))
1525 else if (_rtl8812ae_eq_n_byte(pregulation
, (u8
*)("MKK"), 3))
1527 else if (_rtl8812ae_eq_n_byte(pregulation
, (u8
*)("ETSI"), 4))
1529 else if (_rtl8812ae_eq_n_byte(pregulation
, (u8
*)("WW13"), 4))
1532 if (_rtl8812ae_eq_n_byte(prate_section
, (u8
*)("CCK"), 3))
1534 else if (_rtl8812ae_eq_n_byte(prate_section
, (u8
*)("OFDM"), 4))
1536 else if (_rtl8812ae_eq_n_byte(prate_section
, (u8
*)("HT"), 2) &&
1537 _rtl8812ae_eq_n_byte(prf_path
, (u8
*)("1T"), 2))
1539 else if (_rtl8812ae_eq_n_byte(prate_section
, (u8
*)("HT"), 2) &&
1540 _rtl8812ae_eq_n_byte(prf_path
, (u8
*)("2T"), 2))
1542 else if (_rtl8812ae_eq_n_byte(prate_section
, (u8
*)("VHT"), 3) &&
1543 _rtl8812ae_eq_n_byte(prf_path
, (u8
*)("1T"), 2))
1545 else if (_rtl8812ae_eq_n_byte(prate_section
, (u8
*)("VHT"), 3) &&
1546 _rtl8812ae_eq_n_byte(prf_path
, (u8
*)("2T"), 2))
1549 if (_rtl8812ae_eq_n_byte(pbandwidth
, (u8
*)("20M"), 3))
1551 else if (_rtl8812ae_eq_n_byte(pbandwidth
, (u8
*)("40M"), 3))
1553 else if (_rtl8812ae_eq_n_byte(pbandwidth
, (u8
*)("80M"), 3))
1555 else if (_rtl8812ae_eq_n_byte(pbandwidth
, (u8
*)("160M"), 4))
1558 if (_rtl8812ae_eq_n_byte(pband
, (u8
*)("2.4G"), 4)) {
1559 ret
= _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw
,
1566 channel_index
= ret
;
1568 prev_power_limit
= rtlphy
->txpwr_limit_2_4g
[regulation
]
1569 [bandwidth
][rate_section
]
1570 [channel_index
][RF90_PATH_A
];
1572 if (power_limit
< prev_power_limit
)
1573 rtlphy
->txpwr_limit_2_4g
[regulation
][bandwidth
]
1574 [rate_section
][channel_index
][RF90_PATH_A
] =
1577 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1578 "2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n",
1579 regulation
, bandwidth
, rate_section
, channel_index
,
1580 rtlphy
->txpwr_limit_2_4g
[regulation
][bandwidth
]
1581 [rate_section
][channel_index
][RF90_PATH_A
]);
1582 } else if (_rtl8812ae_eq_n_byte(pband
, (u8
*)("5G"), 2)) {
1583 ret
= _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw
,
1590 channel_index
= ret
;
1592 prev_power_limit
= rtlphy
->txpwr_limit_5g
[regulation
][bandwidth
]
1593 [rate_section
][channel_index
]
1596 if (power_limit
< prev_power_limit
)
1597 rtlphy
->txpwr_limit_5g
[regulation
][bandwidth
]
1598 [rate_section
][channel_index
][RF90_PATH_A
] = power_limit
;
1600 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1601 "5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n",
1602 regulation
, bandwidth
, rate_section
, channel
,
1603 rtlphy
->txpwr_limit_5g
[regulation
][bandwidth
]
1604 [rate_section
][channel_index
][RF90_PATH_A
]);
1606 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1607 "Cannot recognize the band info in %s\n", pband
);
1612 static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw
*hw
,
1613 u8
*regulation
, u8
*band
,
1614 u8
*bandwidth
, u8
*rate_section
,
1615 u8
*rf_path
, u8
*channel
,
1618 _rtl8812ae_phy_set_txpower_limit(hw
, regulation
, band
, bandwidth
,
1619 rate_section
, rf_path
, channel
,
1623 static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw
*hw
)
1625 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1626 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
1631 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
1632 array_len
= RTL8812AE_TXPWR_LMT_ARRAY_LEN
;
1633 array
= RTL8812AE_TXPWR_LMT
;
1635 array_len
= RTL8821AE_TXPWR_LMT_ARRAY_LEN
;
1636 array
= RTL8821AE_TXPWR_LMT
;
1639 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1642 for (i
= 0; i
< array_len
; i
+= 7) {
1643 u8
*regulation
= array
[i
];
1644 u8
*band
= array
[i
+1];
1645 u8
*bandwidth
= array
[i
+2];
1646 u8
*rate
= array
[i
+3];
1647 u8
*rf_path
= array
[i
+4];
1648 u8
*chnl
= array
[i
+5];
1649 u8
*val
= array
[i
+6];
1651 _rtl8812ae_phy_config_bb_txpwr_lmt(hw
, regulation
, band
,
1652 bandwidth
, rate
, rf_path
,
1657 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw
*hw
)
1659 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1660 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
1661 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1664 _rtl8821ae_phy_init_txpower_limit(hw
);
1666 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1667 if (rtlefuse
->eeprom_regulatory
!= 2)
1668 _rtl8821ae_phy_read_and_config_txpwr_lmt(hw
);
1670 rtstatus
= _rtl8821ae_phy_config_bb_with_headerfile(hw
,
1671 BASEBAND_CONFIG_PHY_REG
);
1672 if (rtstatus
!= true) {
1673 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Write BB Reg Fail!!");
1676 _rtl8821ae_phy_init_tx_power_by_rate(hw
);
1677 if (rtlefuse
->autoload_failflag
== false) {
1678 rtstatus
= _rtl8821ae_phy_config_bb_with_pgheaderfile(hw
,
1679 BASEBAND_CONFIG_PHY_REG
);
1681 if (rtstatus
!= true) {
1682 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "BB_PG Reg Fail!!");
1686 _rtl8821ae_phy_txpower_by_rate_configuration(hw
);
1688 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1689 if (rtlefuse
->eeprom_regulatory
!= 2)
1690 _rtl8812ae_phy_convert_txpower_limit_to_power_index(hw
);
1692 rtstatus
= _rtl8821ae_phy_config_bb_with_headerfile(hw
,
1693 BASEBAND_CONFIG_AGC_TAB
);
1695 if (rtstatus
!= true) {
1696 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "AGC Table Fail\n");
1699 rtlphy
->cck_high_power
= (bool)(rtl_get_bbreg(hw
,
1700 RFPGA0_XA_HSSIPARAMETER2
, 0x200));
1704 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw
*hw
)
1706 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1707 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
1712 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "Read MAC_REG_Array\n");
1713 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
1714 arraylength
= RTL8821AEMAC_1T_ARRAYLEN
;
1715 ptrarray
= RTL8821AE_MAC_REG_ARRAY
;
1717 arraylength
= RTL8812AEMAC_1T_ARRAYLEN
;
1718 ptrarray
= RTL8812AE_MAC_REG_ARRAY
;
1720 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1721 "Img: MAC_REG_ARRAY LEN %d\n", arraylength
);
1722 for (i
= 0; i
< arraylength
; i
+= 2) {
1724 v2
= (u8
)ptrarray
[i
+ 1];
1725 if (v1
< 0xCDCDCDCD) {
1726 rtl_write_byte(rtlpriv
, v1
, (u8
)v2
);
1729 if (!_rtl8821ae_check_condition(hw
, v1
)) {
1730 /*Discard the following (offset, data) pairs*/
1731 READ_NEXT_PAIR(ptrarray
, v1
, v2
, i
);
1732 while (v2
!= 0xDEAD &&
1734 v2
!= 0xCDCD && i
< arraylength
- 2) {
1735 READ_NEXT_PAIR(ptrarray
, v1
, v2
, i
);
1737 i
-= 2; /* prevent from for-loop += 2*/
1738 } else {/*Configure matched pairs and skip to end of if-else.*/
1739 READ_NEXT_PAIR(ptrarray
, v1
, v2
, i
);
1740 while (v2
!= 0xDEAD &&
1742 v2
!= 0xCDCD && i
< arraylength
- 2) {
1743 rtl_write_byte(rtlpriv
, v1
, v2
);
1744 READ_NEXT_PAIR(ptrarray
, v1
, v2
, i
);
1747 while (v2
!= 0xDEAD && i
< arraylength
- 2)
1748 READ_NEXT_PAIR(ptrarray
, v1
, v2
, i
);
1755 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw
*hw
,
1758 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1759 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
1765 if (configtype
== BASEBAND_CONFIG_PHY_REG
) {
1766 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
1767 arraylen
= RTL8812AEPHY_REG_1TARRAYLEN
;
1768 array_table
= RTL8812AE_PHY_REG_ARRAY
;
1770 arraylen
= RTL8821AEPHY_REG_1TARRAYLEN
;
1771 array_table
= RTL8821AE_PHY_REG_ARRAY
;
1774 for (i
= 0; i
< arraylen
; i
+= 2) {
1775 v1
= array_table
[i
];
1776 v2
= array_table
[i
+ 1];
1777 if (v1
< 0xCDCDCDCD) {
1778 _rtl8821ae_config_bb_reg(hw
, v1
, v2
);
1780 } else {/*This line is the start line of branch.*/
1781 if (!_rtl8821ae_check_condition(hw
, v1
)) {
1782 /*Discard the following (offset, data) pairs*/
1783 READ_NEXT_PAIR(array_table
, v1
, v2
, i
);
1784 while (v2
!= 0xDEAD &&
1788 READ_NEXT_PAIR(array_table
, v1
,
1792 i
-= 2; /* prevent from for-loop += 2*/
1793 } else {/*Configure matched pairs and skip to end of if-else.*/
1794 READ_NEXT_PAIR(array_table
, v1
, v2
, i
);
1795 while (v2
!= 0xDEAD &&
1799 _rtl8821ae_config_bb_reg(hw
, v1
,
1801 READ_NEXT_PAIR(array_table
, v1
,
1805 while (v2
!= 0xDEAD &&
1807 READ_NEXT_PAIR(array_table
, v1
,
1813 } else if (configtype
== BASEBAND_CONFIG_AGC_TAB
) {
1814 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
1815 arraylen
= RTL8812AEAGCTAB_1TARRAYLEN
;
1816 array_table
= RTL8812AE_AGC_TAB_ARRAY
;
1818 arraylen
= RTL8821AEAGCTAB_1TARRAYLEN
;
1819 array_table
= RTL8821AE_AGC_TAB_ARRAY
;
1822 for (i
= 0; i
< arraylen
; i
= i
+ 2) {
1823 v1
= array_table
[i
];
1824 v2
= array_table
[i
+1];
1825 if (v1
< 0xCDCDCDCD) {
1826 rtl_set_bbreg(hw
, v1
, MASKDWORD
, v2
);
1829 } else {/*This line is the start line of branch.*/
1830 if (!_rtl8821ae_check_condition(hw
, v1
)) {
1831 /*Discard the following (offset, data) pairs*/
1832 READ_NEXT_PAIR(array_table
, v1
, v2
, i
);
1833 while (v2
!= 0xDEAD &&
1837 READ_NEXT_PAIR(array_table
, v1
,
1840 i
-= 2; /* prevent from for-loop += 2*/
1841 } else {/*Configure matched pairs and skip to end of if-else.*/
1842 READ_NEXT_PAIR(array_table
, v1
, v2
, i
);
1843 while (v2
!= 0xDEAD &&
1847 rtl_set_bbreg(hw
, v1
, MASKDWORD
,
1850 READ_NEXT_PAIR(array_table
, v1
,
1854 while (v2
!= 0xDEAD &&
1856 READ_NEXT_PAIR(array_table
, v1
,
1860 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1861 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
1862 array_table
[i
], array_table
[i
+ 1]);
1869 static u8
_rtl8821ae_get_rate_section_index(u32 regaddr
)
1873 if (regaddr
>= 0xC20 && regaddr
<= 0xC4C)
1874 index
= (u8
)((regaddr
- 0xC20) / 4);
1875 else if (regaddr
>= 0xE20 && regaddr
<= 0xE4C)
1876 index
= (u8
)((regaddr
- 0xE20) / 4);
1878 RT_ASSERT(!COMP_INIT
,
1879 "Invalid RegAddr 0x%x\n", regaddr
);
1883 static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw
*hw
,
1884 u32 band
, u32 rfpath
,
1885 u32 txnum
, u32 regaddr
,
1886 u32 bitmask
, u32 data
)
1888 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1889 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
1890 u8 rate_section
= _rtl8821ae_get_rate_section_index(regaddr
);
1892 if (band
!= BAND_ON_2_4G
&& band
!= BAND_ON_5G
) {
1893 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_WARNING
, "Invalid Band %d\n", band
);
1894 band
= BAND_ON_2_4G
;
1896 if (rfpath
>= MAX_RF_PATH
) {
1897 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_WARNING
, "Invalid RfPath %d\n", rfpath
);
1898 rfpath
= MAX_RF_PATH
- 1;
1900 if (txnum
>= MAX_RF_PATH
) {
1901 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_WARNING
, "Invalid TxNum %d\n", txnum
);
1902 txnum
= MAX_RF_PATH
- 1;
1904 rtlphy
->tx_power_by_rate_offset
[band
][rfpath
][txnum
][rate_section
] = data
;
1905 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1906 "TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n",
1907 band
, rfpath
, txnum
, rate_section
,
1908 rtlphy
->tx_power_by_rate_offset
[band
][rfpath
][txnum
][rate_section
]);
1911 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw
*hw
,
1914 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1915 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
1919 u32 v1
, v2
, v3
, v4
, v5
, v6
;
1921 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
) {
1922 arraylen
= RTL8812AEPHY_REG_ARRAY_PGLEN
;
1923 array
= RTL8812AE_PHY_REG_ARRAY_PG
;
1925 arraylen
= RTL8821AEPHY_REG_ARRAY_PGLEN
;
1926 array
= RTL8821AE_PHY_REG_ARRAY_PG
;
1929 if (configtype
!= BASEBAND_CONFIG_PHY_REG
) {
1930 RT_TRACE(rtlpriv
, COMP_SEND
, DBG_TRACE
,
1931 "configtype != BaseBand_Config_PHY_REG\n");
1934 for (i
= 0; i
< arraylen
; i
+= 6) {
1942 if (v1
< 0xCDCDCDCD) {
1943 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8812AE
&&
1944 (v4
== 0xfe || v4
== 0xffe)) {
1949 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
1952 else if (v4
== 0xfd)
1954 else if (v4
== 0xfc)
1956 else if (v4
== 0xfb)
1958 else if (v4
== 0xfa)
1960 else if (v4
== 0xf9)
1963 _rtl8821ae_store_tx_power_by_rate(hw
, v1
, v2
, v3
,
1967 /*don't need the hw_body*/
1968 if (!_rtl8821ae_check_condition(hw
, v1
)) {
1969 i
+= 2; /* skip the pair of expression*/
1973 while (v2
!= 0xDEAD) {
1986 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw
*hw
,
1987 enum radio_path rfpath
)
1990 bool rtstatus
= true;
1991 u32
*radioa_array_table_a
, *radioa_array_table_b
;
1992 u16 radioa_arraylen_a
, radioa_arraylen_b
;
1993 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1996 radioa_arraylen_a
= RTL8812AE_RADIOA_1TARRAYLEN
;
1997 radioa_array_table_a
= RTL8812AE_RADIOA_ARRAY
;
1998 radioa_arraylen_b
= RTL8812AE_RADIOB_1TARRAYLEN
;
1999 radioa_array_table_b
= RTL8812AE_RADIOB_ARRAY
;
2000 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
2001 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen_a
);
2002 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Radio No %x\n", rfpath
);
2006 for (i
= 0; i
< radioa_arraylen_a
; i
= i
+ 2) {
2007 v1
= radioa_array_table_a
[i
];
2008 v2
= radioa_array_table_a
[i
+1];
2009 if (v1
< 0xcdcdcdcd) {
2010 _rtl8821ae_config_rf_radio_a(hw
, v1
, v2
);
2012 } else{/*This line is the start line of branch.*/
2013 if (!_rtl8821ae_check_condition(hw
, v1
)) {
2014 /*Discard the following (offset, data) pairs*/
2015 READ_NEXT_PAIR(radioa_array_table_a
, v1
, v2
, i
);
2016 while (v2
!= 0xDEAD &&
2018 v2
!= 0xCDCD && i
< radioa_arraylen_a
-2)
2019 READ_NEXT_PAIR(radioa_array_table_a
, v1
, v2
, i
);
2021 i
-= 2; /* prevent from for-loop += 2*/
2022 } else {/*Configure matched pairs and skip to end of if-else.*/
2023 READ_NEXT_PAIR(radioa_array_table_a
, v1
, v2
, i
);
2024 while (v2
!= 0xDEAD &&
2026 v2
!= 0xCDCD && i
< radioa_arraylen_a
- 2) {
2027 _rtl8821ae_config_rf_radio_a(hw
, v1
, v2
);
2028 READ_NEXT_PAIR(radioa_array_table_a
, v1
, v2
, i
);
2031 while (v2
!= 0xDEAD && i
< radioa_arraylen_a
-2)
2032 READ_NEXT_PAIR(radioa_array_table_a
, v1
, v2
, i
);
2039 for (i
= 0; i
< radioa_arraylen_b
; i
= i
+ 2) {
2040 v1
= radioa_array_table_b
[i
];
2041 v2
= radioa_array_table_b
[i
+1];
2042 if (v1
< 0xcdcdcdcd) {
2043 _rtl8821ae_config_rf_radio_b(hw
, v1
, v2
);
2045 } else{/*This line is the start line of branch.*/
2046 if (!_rtl8821ae_check_condition(hw
, v1
)) {
2047 /*Discard the following (offset, data) pairs*/
2048 READ_NEXT_PAIR(radioa_array_table_b
, v1
, v2
, i
);
2049 while (v2
!= 0xDEAD &&
2051 v2
!= 0xCDCD && i
< radioa_arraylen_b
-2)
2052 READ_NEXT_PAIR(radioa_array_table_b
, v1
, v2
, i
);
2054 i
-= 2; /* prevent from for-loop += 2*/
2055 } else {/*Configure matched pairs and skip to end of if-else.*/
2056 READ_NEXT_PAIR(radioa_array_table_b
, v1
, v2
, i
);
2057 while (v2
!= 0xDEAD &&
2059 v2
!= 0xCDCD && i
< radioa_arraylen_b
-2) {
2060 _rtl8821ae_config_rf_radio_b(hw
, v1
, v2
);
2061 READ_NEXT_PAIR(radioa_array_table_b
, v1
, v2
, i
);
2064 while (v2
!= 0xDEAD && i
< radioa_arraylen_b
-2)
2065 READ_NEXT_PAIR(radioa_array_table_b
, v1
, v2
, i
);
2071 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2072 "switch case not process\n");
2075 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2076 "switch case not process\n");
2082 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw
*hw
,
2083 enum radio_path rfpath
)
2085 #define READ_NEXT_RF_PAIR(v1, v2, i) \
2088 v1 = radioa_array_table[i]; \
2089 v2 = radioa_array_table[i+1]; \
2094 bool rtstatus
= true;
2095 u32
*radioa_array_table
;
2096 u16 radioa_arraylen
;
2097 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2098 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */
2101 radioa_arraylen
= RTL8821AE_RADIOA_1TARRAYLEN
;
2102 radioa_array_table
= RTL8821AE_RADIOA_ARRAY
;
2103 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
2104 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen
);
2105 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Radio No %x\n", rfpath
);
2109 for (i
= 0; i
< radioa_arraylen
; i
= i
+ 2) {
2110 v1
= radioa_array_table
[i
];
2111 v2
= radioa_array_table
[i
+1];
2112 if (v1
< 0xcdcdcdcd)
2113 _rtl8821ae_config_rf_radio_a(hw
, v1
, v2
);
2114 else{/*This line is the start line of branch.*/
2115 if (!_rtl8821ae_check_condition(hw
, v1
)) {
2116 /*Discard the following (offset, data) pairs*/
2117 READ_NEXT_RF_PAIR(v1
, v2
, i
);
2118 while (v2
!= 0xDEAD &&
2120 v2
!= 0xCDCD && i
< radioa_arraylen
- 2)
2121 READ_NEXT_RF_PAIR(v1
, v2
, i
);
2123 i
-= 2; /* prevent from for-loop += 2*/
2124 } else {/*Configure matched pairs and skip to end of if-else.*/
2125 READ_NEXT_RF_PAIR(v1
, v2
, i
);
2126 while (v2
!= 0xDEAD &&
2128 v2
!= 0xCDCD && i
< radioa_arraylen
- 2) {
2129 _rtl8821ae_config_rf_radio_a(hw
, v1
, v2
);
2130 READ_NEXT_RF_PAIR(v1
, v2
, i
);
2133 while (v2
!= 0xDEAD && i
< radioa_arraylen
- 2)
2134 READ_NEXT_RF_PAIR(v1
, v2
, i
);
2141 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2142 "switch case not process\n");
2145 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2146 "switch case not process\n");
2149 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2150 "switch case not process\n");
2156 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw
*hw
)
2158 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2159 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
2161 rtlphy
->default_initialgain
[0] =
2162 (u8
)rtl_get_bbreg(hw
, ROFDM0_XAAGCCORE1
, MASKBYTE0
);
2163 rtlphy
->default_initialgain
[1] =
2164 (u8
)rtl_get_bbreg(hw
, ROFDM0_XBAGCCORE1
, MASKBYTE0
);
2165 rtlphy
->default_initialgain
[2] =
2166 (u8
)rtl_get_bbreg(hw
, ROFDM0_XCAGCCORE1
, MASKBYTE0
);
2167 rtlphy
->default_initialgain
[3] =
2168 (u8
)rtl_get_bbreg(hw
, ROFDM0_XDAGCCORE1
, MASKBYTE0
);
2170 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
2171 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
2172 rtlphy
->default_initialgain
[0],
2173 rtlphy
->default_initialgain
[1],
2174 rtlphy
->default_initialgain
[2],
2175 rtlphy
->default_initialgain
[3]);
2177 rtlphy
->framesync
= (u8
)rtl_get_bbreg(hw
,
2178 ROFDM0_RXDETECTOR3
, MASKBYTE0
);
2179 rtlphy
->framesync_c34
= rtl_get_bbreg(hw
,
2180 ROFDM0_RXDETECTOR2
, MASKDWORD
);
2182 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
2183 "Default framesync (0x%x) = 0x%x\n",
2184 ROFDM0_RXDETECTOR3
, rtlphy
->framesync
);
2187 static void phy_init_bb_rf_register_definition(struct ieee80211_hw
*hw
)
2189 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2190 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
2192 rtlphy
->phyreg_def
[RF90_PATH_A
].rfintfs
= RFPGA0_XAB_RFINTERFACESW
;
2193 rtlphy
->phyreg_def
[RF90_PATH_B
].rfintfs
= RFPGA0_XAB_RFINTERFACESW
;
2195 rtlphy
->phyreg_def
[RF90_PATH_A
].rfintfo
= RFPGA0_XA_RFINTERFACEOE
;
2196 rtlphy
->phyreg_def
[RF90_PATH_B
].rfintfo
= RFPGA0_XB_RFINTERFACEOE
;
2198 rtlphy
->phyreg_def
[RF90_PATH_A
].rfintfe
= RFPGA0_XA_RFINTERFACEOE
;
2199 rtlphy
->phyreg_def
[RF90_PATH_B
].rfintfe
= RFPGA0_XB_RFINTERFACEOE
;
2201 rtlphy
->phyreg_def
[RF90_PATH_A
].rf3wire_offset
= RA_LSSIWRITE_8821A
;
2202 rtlphy
->phyreg_def
[RF90_PATH_B
].rf3wire_offset
= RB_LSSIWRITE_8821A
;
2204 rtlphy
->phyreg_def
[RF90_PATH_A
].rfhssi_para2
= RHSSIREAD_8821AE
;
2205 rtlphy
->phyreg_def
[RF90_PATH_B
].rfhssi_para2
= RHSSIREAD_8821AE
;
2207 rtlphy
->phyreg_def
[RF90_PATH_A
].rf_rb
= RA_SIREAD_8821A
;
2208 rtlphy
->phyreg_def
[RF90_PATH_B
].rf_rb
= RB_SIREAD_8821A
;
2210 rtlphy
->phyreg_def
[RF90_PATH_A
].rf_rbpi
= RA_PIREAD_8821A
;
2211 rtlphy
->phyreg_def
[RF90_PATH_B
].rf_rbpi
= RB_PIREAD_8821A
;
2214 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw
*hw
, long *powerlevel
)
2216 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2217 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
2221 txpwr_level
= rtlphy
->cur_cck_txpwridx
;
2222 txpwr_dbm
= _rtl8821ae_phy_txpwr_idx_to_dbm(hw
,
2223 WIRELESS_MODE_B
, txpwr_level
);
2224 txpwr_level
= rtlphy
->cur_ofdm24g_txpwridx
;
2225 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw
,
2227 txpwr_level
) > txpwr_dbm
)
2229 _rtl8821ae_phy_txpwr_idx_to_dbm(hw
, WIRELESS_MODE_G
,
2231 txpwr_level
= rtlphy
->cur_ofdm24g_txpwridx
;
2232 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw
,
2233 WIRELESS_MODE_N_24G
,
2234 txpwr_level
) > txpwr_dbm
)
2236 _rtl8821ae_phy_txpwr_idx_to_dbm(hw
, WIRELESS_MODE_N_24G
,
2238 *powerlevel
= txpwr_dbm
;
2241 static bool _rtl8821ae_phy_get_chnl_index(u8 channel
, u8
*chnl_index
)
2243 u8 channel_5g
[CHANNEL_MAX_NUMBER_5G
] = {
2244 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62,
2245 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118,
2246 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140,
2247 142, 144, 149, 151, 153, 155, 157, 159, 161, 163, 165,
2248 167, 168, 169, 171, 173, 175, 177
2253 if (channel
<= 14) {
2255 *chnl_index
= channel
- 1;
2259 for (i
= 0; i
< CHANNEL_MAX_NUMBER_5G
; ++i
) {
2260 if (channel_5g
[i
] == channel
) {
2269 static char _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path
, u8 rate
)
2271 char rate_section
= 0;
2305 case DESC_RATEMCS10
:
2306 case DESC_RATEMCS11
:
2309 case DESC_RATEMCS12
:
2310 case DESC_RATEMCS13
:
2311 case DESC_RATEMCS14
:
2312 case DESC_RATEMCS15
:
2315 case DESC_RATEVHT1SS_MCS0
:
2316 case DESC_RATEVHT1SS_MCS1
:
2317 case DESC_RATEVHT1SS_MCS2
:
2318 case DESC_RATEVHT1SS_MCS3
:
2321 case DESC_RATEVHT1SS_MCS4
:
2322 case DESC_RATEVHT1SS_MCS5
:
2323 case DESC_RATEVHT1SS_MCS6
:
2324 case DESC_RATEVHT1SS_MCS7
:
2327 case DESC_RATEVHT1SS_MCS8
:
2328 case DESC_RATEVHT1SS_MCS9
:
2329 case DESC_RATEVHT2SS_MCS0
:
2330 case DESC_RATEVHT2SS_MCS1
:
2333 case DESC_RATEVHT2SS_MCS2
:
2334 case DESC_RATEVHT2SS_MCS3
:
2335 case DESC_RATEVHT2SS_MCS4
:
2336 case DESC_RATEVHT2SS_MCS5
:
2339 case DESC_RATEVHT2SS_MCS6
:
2340 case DESC_RATEVHT2SS_MCS7
:
2341 case DESC_RATEVHT2SS_MCS8
:
2342 case DESC_RATEVHT2SS_MCS9
:
2346 RT_ASSERT(true, "Rate_Section is Illegal\n");
2350 return rate_section
;
2353 static char _rtl8812ae_phy_get_world_wide_limit(char *limit_table
)
2355 char min
= limit_table
[0];
2358 for (i
= 0; i
< MAX_REGULATION_NUM
; ++i
) {
2359 if (limit_table
[i
] < min
)
2360 min
= limit_table
[i
];
2365 static char _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw
*hw
,
2367 enum ht_channel_width bandwidth
,
2368 enum radio_path rf_path
,
2369 u8 rate
, u8 channel
)
2371 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2372 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtlpriv
);
2373 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
2374 short band_temp
= -1, regulation
= -1, bandwidth_temp
= -1,
2375 rate_section
= -1, channel_temp
= -1;
2376 u16 bd
, regu
, bdwidth
, sec
, chnl
;
2377 char power_limit
= MAX_POWER_INDEX
;
2379 if (rtlefuse
->eeprom_regulatory
== 2)
2380 return MAX_POWER_INDEX
;
2382 regulation
= TXPWR_LMT_WW
;
2384 if (band
== BAND_ON_2_4G
)
2386 else if (band
== BAND_ON_5G
)
2389 if (bandwidth
== HT_CHANNEL_WIDTH_20
)
2391 else if (bandwidth
== HT_CHANNEL_WIDTH_20_40
)
2393 else if (bandwidth
== HT_CHANNEL_WIDTH_80
)
2425 case DESC_RATEMCS10
:
2426 case DESC_RATEMCS11
:
2427 case DESC_RATEMCS12
:
2428 case DESC_RATEMCS13
:
2429 case DESC_RATEMCS14
:
2430 case DESC_RATEMCS15
:
2433 case DESC_RATEVHT1SS_MCS0
:
2434 case DESC_RATEVHT1SS_MCS1
:
2435 case DESC_RATEVHT1SS_MCS2
:
2436 case DESC_RATEVHT1SS_MCS3
:
2437 case DESC_RATEVHT1SS_MCS4
:
2438 case DESC_RATEVHT1SS_MCS5
:
2439 case DESC_RATEVHT1SS_MCS6
:
2440 case DESC_RATEVHT1SS_MCS7
:
2441 case DESC_RATEVHT1SS_MCS8
:
2442 case DESC_RATEVHT1SS_MCS9
:
2445 case DESC_RATEVHT2SS_MCS0
:
2446 case DESC_RATEVHT2SS_MCS1
:
2447 case DESC_RATEVHT2SS_MCS2
:
2448 case DESC_RATEVHT2SS_MCS3
:
2449 case DESC_RATEVHT2SS_MCS4
:
2450 case DESC_RATEVHT2SS_MCS5
:
2451 case DESC_RATEVHT2SS_MCS6
:
2452 case DESC_RATEVHT2SS_MCS7
:
2453 case DESC_RATEVHT2SS_MCS8
:
2454 case DESC_RATEVHT2SS_MCS9
:
2458 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
2459 "Wrong rate 0x%x\n", rate
);
2463 if (band_temp
== BAND_ON_5G
&& rate_section
== 0)
2464 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
2465 "Wrong rate 0x%x: No CCK in 5G Band\n", rate
);
2467 /*workaround for wrong index combination to obtain tx power limit,
2468 OFDM only exists in BW 20M*/
2469 if (rate_section
== 1)
2472 /*workaround for wrong index combination to obtain tx power limit,
2473 *HT on 80M will reference to HT on 40M
2475 if ((rate_section
== 2 || rate_section
== 3) && band
== BAND_ON_5G
&&
2476 bandwidth_temp
== 2)
2479 if (band
== BAND_ON_2_4G
)
2480 channel_temp
= _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw
,
2481 BAND_ON_2_4G
, channel
);
2482 else if (band
== BAND_ON_5G
)
2483 channel_temp
= _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw
,
2484 BAND_ON_5G
, channel
);
2485 else if (band
== BAND_ON_BOTH
)
2486 ;/* BAND_ON_BOTH don't care temporarily */
2488 if (band_temp
== -1 || regulation
== -1 || bandwidth_temp
== -1 ||
2489 rate_section
== -1 || channel_temp
== -1) {
2490 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
2491 "Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n",
2492 band_temp
, regulation
, bandwidth_temp
, rf_path
,
2493 rate_section
, channel_temp
);
2494 return MAX_POWER_INDEX
;
2499 bdwidth
= bandwidth_temp
;
2501 chnl
= channel_temp
;
2503 if (band
== BAND_ON_2_4G
) {
2504 char limits
[10] = {0};
2507 for (i
= 0; i
< 4; ++i
)
2508 limits
[i
] = rtlphy
->txpwr_limit_2_4g
[i
][bdwidth
]
2509 [sec
][chnl
][rf_path
];
2511 power_limit
= (regulation
== TXPWR_LMT_WW
) ?
2512 _rtl8812ae_phy_get_world_wide_limit(limits
) :
2513 rtlphy
->txpwr_limit_2_4g
[regu
][bdwidth
]
2514 [sec
][chnl
][rf_path
];
2515 } else if (band
== BAND_ON_5G
) {
2516 char limits
[10] = {0};
2519 for (i
= 0; i
< MAX_REGULATION_NUM
; ++i
)
2520 limits
[i
] = rtlphy
->txpwr_limit_5g
[i
][bdwidth
]
2521 [sec
][chnl
][rf_path
];
2523 power_limit
= (regulation
== TXPWR_LMT_WW
) ?
2524 _rtl8812ae_phy_get_world_wide_limit(limits
) :
2525 rtlphy
->txpwr_limit_5g
[regu
][chnl
]
2526 [sec
][chnl
][rf_path
];
2528 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
2529 "No power limit table of the specified band\n");
2534 static char _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw
*hw
,
2535 u8 band
, u8 path
, u8 rate
)
2537 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2538 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
2539 u8 shift
= 0, rate_section
, tx_num
;
2540 char tx_pwr_diff
= 0;
2543 rate_section
= _rtl8821ae_phy_get_ratesection_intxpower_byrate(path
, rate
);
2544 tx_num
= RF_TX_NUM_NONIMPLEMENT
;
2546 if (tx_num
== RF_TX_NUM_NONIMPLEMENT
) {
2547 if ((rate
>= DESC_RATEMCS8
&& rate
<= DESC_RATEMCS15
) ||
2548 (rate
>= DESC_RATEVHT2SS_MCS2
&& rate
<= DESC_RATEVHT2SS_MCS9
))
2561 case DESC_RATEMCS12
:
2562 case DESC_RATEVHT1SS_MCS0
:
2563 case DESC_RATEVHT1SS_MCS4
:
2564 case DESC_RATEVHT1SS_MCS8
:
2565 case DESC_RATEVHT2SS_MCS2
:
2566 case DESC_RATEVHT2SS_MCS6
:
2575 case DESC_RATEMCS13
:
2576 case DESC_RATEVHT1SS_MCS1
:
2577 case DESC_RATEVHT1SS_MCS5
:
2578 case DESC_RATEVHT1SS_MCS9
:
2579 case DESC_RATEVHT2SS_MCS3
:
2580 case DESC_RATEVHT2SS_MCS7
:
2588 case DESC_RATEMCS10
:
2589 case DESC_RATEMCS14
:
2590 case DESC_RATEVHT1SS_MCS2
:
2591 case DESC_RATEVHT1SS_MCS6
:
2592 case DESC_RATEVHT2SS_MCS0
:
2593 case DESC_RATEVHT2SS_MCS4
:
2594 case DESC_RATEVHT2SS_MCS8
:
2602 case DESC_RATEMCS11
:
2603 case DESC_RATEMCS15
:
2604 case DESC_RATEVHT1SS_MCS3
:
2605 case DESC_RATEVHT1SS_MCS7
:
2606 case DESC_RATEVHT2SS_MCS1
:
2607 case DESC_RATEVHT2SS_MCS5
:
2608 case DESC_RATEVHT2SS_MCS9
:
2612 RT_ASSERT(true, "Rate_Section is Illegal\n");
2616 tx_pwr_diff
= (u8
)(rtlphy
->tx_power_by_rate_offset
[band
][path
]
2617 [tx_num
][rate_section
] >> shift
) & 0xff;
2619 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
2620 if (rtlpriv
->efuse
.eeprom_regulatory
!= 2) {
2621 limit
= _rtl8812ae_phy_get_txpower_limit(hw
, band
,
2622 rtlphy
->current_chan_bw
, path
, rate
,
2623 rtlphy
->current_channel
);
2625 if (rate
== DESC_RATEVHT1SS_MCS8
|| rate
== DESC_RATEVHT1SS_MCS9
||
2626 rate
== DESC_RATEVHT2SS_MCS8
|| rate
== DESC_RATEVHT2SS_MCS9
) {
2628 if (tx_pwr_diff
< (-limit
))
2629 tx_pwr_diff
= -limit
;
2633 tx_pwr_diff
= limit
;
2635 tx_pwr_diff
= tx_pwr_diff
> limit
? limit
: tx_pwr_diff
;
2637 RT_TRACE(rtlpriv
, COMP_POWER_TRACKING
, DBG_LOUD
,
2638 "Maximum power by rate %d, final power by rate %d\n",
2639 limit
, tx_pwr_diff
);
2645 static u8
_rtl8821ae_get_txpower_index(struct ieee80211_hw
*hw
, u8 path
,
2646 u8 rate
, u8 bandwidth
, u8 channel
)
2648 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2649 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
2650 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
2651 u8 index
= (channel
- 1);
2653 bool in_24g
= false;
2654 char powerdiff_byrate
= 0;
2656 if (((rtlhal
->current_bandtype
== BAND_ON_2_4G
) &&
2657 (channel
> 14 || channel
< 1)) ||
2658 ((rtlhal
->current_bandtype
== BAND_ON_5G
) && (channel
<= 14))) {
2660 RT_TRACE(rtlpriv
, COMP_POWER_TRACKING
, DBG_LOUD
,
2661 "Illegal channel!!\n");
2664 in_24g
= _rtl8821ae_phy_get_chnl_index(channel
, &index
);
2666 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate
))
2667 txpower
= rtlefuse
->txpwrlevel_cck
[path
][index
];
2668 else if (DESC_RATE6M
<= rate
)
2669 txpower
= rtlefuse
->txpwrlevel_ht40_1s
[path
][index
];
2671 RT_TRACE(rtlpriv
, COMP_POWER_TRACKING
, DBG_LOUD
, "invalid rate\n");
2673 if (DESC_RATE6M
<= rate
&& rate
<= DESC_RATE54M
&&
2674 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate
))
2675 txpower
+= rtlefuse
->txpwr_legacyhtdiff
[path
][TX_1S
];
2677 if (bandwidth
== HT_CHANNEL_WIDTH_20
) {
2678 if ((DESC_RATEMCS0
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2679 (DESC_RATEVHT1SS_MCS0
<= rate
&& rate
<= DESC_RATEVHT2SS_MCS9
))
2680 txpower
+= rtlefuse
->txpwr_ht20diff
[path
][TX_1S
];
2681 if ((DESC_RATEMCS8
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2682 (DESC_RATEVHT2SS_MCS0
<= rate
&& rate
<= DESC_RATEVHT2SS_MCS9
))
2683 txpower
+= rtlefuse
->txpwr_ht20diff
[path
][TX_2S
];
2684 } else if (bandwidth
== HT_CHANNEL_WIDTH_20_40
) {
2685 if ((DESC_RATEMCS0
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2686 (DESC_RATEVHT1SS_MCS0
<= rate
&& rate
<= DESC_RATEVHT2SS_MCS9
))
2687 txpower
+= rtlefuse
->txpwr_ht40diff
[path
][TX_1S
];
2688 if ((DESC_RATEMCS8
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2689 (DESC_RATEVHT2SS_MCS0
<= rate
&& rate
<= DESC_RATEVHT2SS_MCS9
))
2690 txpower
+= rtlefuse
->txpwr_ht40diff
[path
][TX_2S
];
2691 } else if (bandwidth
== HT_CHANNEL_WIDTH_80
) {
2692 if ((DESC_RATEMCS0
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2693 (DESC_RATEVHT1SS_MCS0
<= rate
&&
2694 rate
<= DESC_RATEVHT2SS_MCS9
))
2695 txpower
+= rtlefuse
->txpwr_ht40diff
[path
][TX_1S
];
2696 if ((DESC_RATEMCS8
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2697 (DESC_RATEVHT2SS_MCS0
<= rate
&&
2698 rate
<= DESC_RATEVHT2SS_MCS9
))
2699 txpower
+= rtlefuse
->txpwr_ht40diff
[path
][TX_2S
];
2702 if (DESC_RATE6M
<= rate
)
2703 txpower
= rtlefuse
->txpwr_5g_bw40base
[path
][index
];
2705 RT_TRACE(rtlpriv
, COMP_POWER_TRACKING
, DBG_WARNING
,
2708 if (DESC_RATE6M
<= rate
&& rate
<= DESC_RATE54M
&&
2709 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate
))
2710 txpower
+= rtlefuse
->txpwr_5g_ofdmdiff
[path
][TX_1S
];
2712 if (bandwidth
== HT_CHANNEL_WIDTH_20
) {
2713 if ((DESC_RATEMCS0
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2714 (DESC_RATEVHT1SS_MCS0
<= rate
&&
2715 rate
<= DESC_RATEVHT2SS_MCS9
))
2716 txpower
+= rtlefuse
->txpwr_5g_bw20diff
[path
][TX_1S
];
2717 if ((DESC_RATEMCS8
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2718 (DESC_RATEVHT2SS_MCS0
<= rate
&&
2719 rate
<= DESC_RATEVHT2SS_MCS9
))
2720 txpower
+= rtlefuse
->txpwr_5g_bw20diff
[path
][TX_2S
];
2721 } else if (bandwidth
== HT_CHANNEL_WIDTH_20_40
) {
2722 if ((DESC_RATEMCS0
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2723 (DESC_RATEVHT1SS_MCS0
<= rate
&&
2724 rate
<= DESC_RATEVHT2SS_MCS9
))
2725 txpower
+= rtlefuse
->txpwr_5g_bw40diff
[path
][TX_1S
];
2726 if ((DESC_RATEMCS8
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2727 (DESC_RATEVHT2SS_MCS0
<= rate
&&
2728 rate
<= DESC_RATEVHT2SS_MCS9
))
2729 txpower
+= rtlefuse
->txpwr_5g_bw40diff
[path
][TX_2S
];
2730 } else if (bandwidth
== HT_CHANNEL_WIDTH_80
) {
2731 u8 channel_5g_80m
[CHANNEL_MAX_NUMBER_5G_80M
] = {
2732 42, 58, 106, 122, 138, 155, 171
2736 for (i
= 0; i
< sizeof(channel_5g_80m
) / sizeof(u8
); ++i
)
2737 if (channel_5g_80m
[i
] == channel
)
2740 if ((DESC_RATEMCS0
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2741 (DESC_RATEVHT1SS_MCS0
<= rate
&&
2742 rate
<= DESC_RATEVHT2SS_MCS9
))
2743 txpower
= rtlefuse
->txpwr_5g_bw80base
[path
][index
]
2744 + rtlefuse
->txpwr_5g_bw80diff
[path
][TX_1S
];
2745 if ((DESC_RATEMCS8
<= rate
&& rate
<= DESC_RATEMCS15
) ||
2746 (DESC_RATEVHT2SS_MCS0
<= rate
&&
2747 rate
<= DESC_RATEVHT2SS_MCS9
))
2748 txpower
= rtlefuse
->txpwr_5g_bw80base
[path
][index
]
2749 + rtlefuse
->txpwr_5g_bw80diff
[path
][TX_1S
]
2750 + rtlefuse
->txpwr_5g_bw80diff
[path
][TX_2S
];
2753 if (rtlefuse
->eeprom_regulatory
!= 2)
2755 _rtl8821ae_phy_get_txpower_by_rate(hw
, (u8
)(!in_24g
),
2758 if (rate
== DESC_RATEVHT1SS_MCS8
|| rate
== DESC_RATEVHT1SS_MCS9
||
2759 rate
== DESC_RATEVHT2SS_MCS8
|| rate
== DESC_RATEVHT2SS_MCS9
)
2760 txpower
-= powerdiff_byrate
;
2762 txpower
+= powerdiff_byrate
;
2764 if (rate
> DESC_RATE11M
)
2765 txpower
+= rtlpriv
->dm
.remnant_ofdm_swing_idx
[path
];
2767 txpower
+= rtlpriv
->dm
.remnant_cck_idx
;
2769 if (txpower
> MAX_POWER_INDEX
)
2770 txpower
= MAX_POWER_INDEX
;
2775 static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw
*hw
,
2776 u8 power_index
, u8 path
, u8 rate
)
2778 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2780 if (path
== RF90_PATH_A
) {
2783 rtl_set_bbreg(hw
, RTXAGC_A_CCK11_CCK1
,
2784 MASKBYTE0
, power_index
);
2787 rtl_set_bbreg(hw
, RTXAGC_A_CCK11_CCK1
,
2788 MASKBYTE1
, power_index
);
2791 rtl_set_bbreg(hw
, RTXAGC_A_CCK11_CCK1
,
2792 MASKBYTE2
, power_index
);
2795 rtl_set_bbreg(hw
, RTXAGC_A_CCK11_CCK1
,
2796 MASKBYTE3
, power_index
);
2799 rtl_set_bbreg(hw
, RTXAGC_A_OFDM18_OFDM6
,
2800 MASKBYTE0
, power_index
);
2803 rtl_set_bbreg(hw
, RTXAGC_A_OFDM18_OFDM6
,
2804 MASKBYTE1
, power_index
);
2807 rtl_set_bbreg(hw
, RTXAGC_A_OFDM18_OFDM6
,
2808 MASKBYTE2
, power_index
);
2811 rtl_set_bbreg(hw
, RTXAGC_A_OFDM18_OFDM6
,
2812 MASKBYTE3
, power_index
);
2815 rtl_set_bbreg(hw
, RTXAGC_A_OFDM54_OFDM24
,
2816 MASKBYTE0
, power_index
);
2819 rtl_set_bbreg(hw
, RTXAGC_A_OFDM54_OFDM24
,
2820 MASKBYTE1
, power_index
);
2823 rtl_set_bbreg(hw
, RTXAGC_A_OFDM54_OFDM24
,
2824 MASKBYTE2
, power_index
);
2827 rtl_set_bbreg(hw
, RTXAGC_A_OFDM54_OFDM24
,
2828 MASKBYTE3
, power_index
);
2831 rtl_set_bbreg(hw
, RTXAGC_A_MCS03_MCS00
,
2832 MASKBYTE0
, power_index
);
2835 rtl_set_bbreg(hw
, RTXAGC_A_MCS03_MCS00
,
2836 MASKBYTE1
, power_index
);
2839 rtl_set_bbreg(hw
, RTXAGC_A_MCS03_MCS00
,
2840 MASKBYTE2
, power_index
);
2843 rtl_set_bbreg(hw
, RTXAGC_A_MCS03_MCS00
,
2844 MASKBYTE3
, power_index
);
2847 rtl_set_bbreg(hw
, RTXAGC_A_MCS07_MCS04
,
2848 MASKBYTE0
, power_index
);
2851 rtl_set_bbreg(hw
, RTXAGC_A_MCS07_MCS04
,
2852 MASKBYTE1
, power_index
);
2855 rtl_set_bbreg(hw
, RTXAGC_A_MCS07_MCS04
,
2856 MASKBYTE2
, power_index
);
2859 rtl_set_bbreg(hw
, RTXAGC_A_MCS07_MCS04
,
2860 MASKBYTE3
, power_index
);
2863 rtl_set_bbreg(hw
, RTXAGC_A_MCS11_MCS08
,
2864 MASKBYTE0
, power_index
);
2867 rtl_set_bbreg(hw
, RTXAGC_A_MCS11_MCS08
,
2868 MASKBYTE1
, power_index
);
2870 case DESC_RATEMCS10
:
2871 rtl_set_bbreg(hw
, RTXAGC_A_MCS11_MCS08
,
2872 MASKBYTE2
, power_index
);
2874 case DESC_RATEMCS11
:
2875 rtl_set_bbreg(hw
, RTXAGC_A_MCS11_MCS08
,
2876 MASKBYTE3
, power_index
);
2878 case DESC_RATEMCS12
:
2879 rtl_set_bbreg(hw
, RTXAGC_A_MCS15_MCS12
,
2880 MASKBYTE0
, power_index
);
2882 case DESC_RATEMCS13
:
2883 rtl_set_bbreg(hw
, RTXAGC_A_MCS15_MCS12
,
2884 MASKBYTE1
, power_index
);
2886 case DESC_RATEMCS14
:
2887 rtl_set_bbreg(hw
, RTXAGC_A_MCS15_MCS12
,
2888 MASKBYTE2
, power_index
);
2890 case DESC_RATEMCS15
:
2891 rtl_set_bbreg(hw
, RTXAGC_A_MCS15_MCS12
,
2892 MASKBYTE3
, power_index
);
2894 case DESC_RATEVHT1SS_MCS0
:
2895 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX3_NSS1INDEX0
,
2896 MASKBYTE0
, power_index
);
2898 case DESC_RATEVHT1SS_MCS1
:
2899 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX3_NSS1INDEX0
,
2900 MASKBYTE1
, power_index
);
2902 case DESC_RATEVHT1SS_MCS2
:
2903 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX3_NSS1INDEX0
,
2904 MASKBYTE2
, power_index
);
2906 case DESC_RATEVHT1SS_MCS3
:
2907 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX3_NSS1INDEX0
,
2908 MASKBYTE3
, power_index
);
2910 case DESC_RATEVHT1SS_MCS4
:
2911 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX7_NSS1INDEX4
,
2912 MASKBYTE0
, power_index
);
2914 case DESC_RATEVHT1SS_MCS5
:
2915 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX7_NSS1INDEX4
,
2916 MASKBYTE1
, power_index
);
2918 case DESC_RATEVHT1SS_MCS6
:
2919 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX7_NSS1INDEX4
,
2920 MASKBYTE2
, power_index
);
2922 case DESC_RATEVHT1SS_MCS7
:
2923 rtl_set_bbreg(hw
, RTXAGC_A_NSS1INDEX7_NSS1INDEX4
,
2924 MASKBYTE3
, power_index
);
2926 case DESC_RATEVHT1SS_MCS8
:
2927 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX1_NSS1INDEX8
,
2928 MASKBYTE0
, power_index
);
2930 case DESC_RATEVHT1SS_MCS9
:
2931 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX1_NSS1INDEX8
,
2932 MASKBYTE1
, power_index
);
2934 case DESC_RATEVHT2SS_MCS0
:
2935 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX1_NSS1INDEX8
,
2936 MASKBYTE2
, power_index
);
2938 case DESC_RATEVHT2SS_MCS1
:
2939 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX1_NSS1INDEX8
,
2940 MASKBYTE3
, power_index
);
2942 case DESC_RATEVHT2SS_MCS2
:
2943 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX5_NSS2INDEX2
,
2944 MASKBYTE0
, power_index
);
2946 case DESC_RATEVHT2SS_MCS3
:
2947 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX5_NSS2INDEX2
,
2948 MASKBYTE1
, power_index
);
2950 case DESC_RATEVHT2SS_MCS4
:
2951 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX5_NSS2INDEX2
,
2952 MASKBYTE2
, power_index
);
2954 case DESC_RATEVHT2SS_MCS5
:
2955 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX5_NSS2INDEX2
,
2956 MASKBYTE3
, power_index
);
2958 case DESC_RATEVHT2SS_MCS6
:
2959 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX9_NSS2INDEX6
,
2960 MASKBYTE0
, power_index
);
2962 case DESC_RATEVHT2SS_MCS7
:
2963 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX9_NSS2INDEX6
,
2964 MASKBYTE1
, power_index
);
2966 case DESC_RATEVHT2SS_MCS8
:
2967 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX9_NSS2INDEX6
,
2968 MASKBYTE2
, power_index
);
2970 case DESC_RATEVHT2SS_MCS9
:
2971 rtl_set_bbreg(hw
, RTXAGC_A_NSS2INDEX9_NSS2INDEX6
,
2972 MASKBYTE3
, power_index
);
2975 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
2976 "Invalid Rate!!\n");
2979 } else if (path
== RF90_PATH_B
) {
2982 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_CCK1
,
2983 MASKBYTE0
, power_index
);
2986 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_CCK1
,
2987 MASKBYTE1
, power_index
);
2990 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_CCK1
,
2991 MASKBYTE2
, power_index
);
2994 rtl_set_bbreg(hw
, RTXAGC_B_CCK11_CCK1
,
2995 MASKBYTE3
, power_index
);
2998 rtl_set_bbreg(hw
, RTXAGC_B_OFDM18_OFDM6
,
2999 MASKBYTE0
, power_index
);
3002 rtl_set_bbreg(hw
, RTXAGC_B_OFDM18_OFDM6
,
3003 MASKBYTE1
, power_index
);
3006 rtl_set_bbreg(hw
, RTXAGC_B_OFDM18_OFDM6
,
3007 MASKBYTE2
, power_index
);
3010 rtl_set_bbreg(hw
, RTXAGC_B_OFDM18_OFDM6
,
3011 MASKBYTE3
, power_index
);
3014 rtl_set_bbreg(hw
, RTXAGC_B_OFDM54_OFDM24
,
3015 MASKBYTE0
, power_index
);
3018 rtl_set_bbreg(hw
, RTXAGC_B_OFDM54_OFDM24
,
3019 MASKBYTE1
, power_index
);
3022 rtl_set_bbreg(hw
, RTXAGC_B_OFDM54_OFDM24
,
3023 MASKBYTE2
, power_index
);
3026 rtl_set_bbreg(hw
, RTXAGC_B_OFDM54_OFDM24
,
3027 MASKBYTE3
, power_index
);
3030 rtl_set_bbreg(hw
, RTXAGC_B_MCS03_MCS00
,
3031 MASKBYTE0
, power_index
);
3034 rtl_set_bbreg(hw
, RTXAGC_B_MCS03_MCS00
,
3035 MASKBYTE1
, power_index
);
3038 rtl_set_bbreg(hw
, RTXAGC_B_MCS03_MCS00
,
3039 MASKBYTE2
, power_index
);
3042 rtl_set_bbreg(hw
, RTXAGC_B_MCS03_MCS00
,
3043 MASKBYTE3
, power_index
);
3046 rtl_set_bbreg(hw
, RTXAGC_B_MCS07_MCS04
,
3047 MASKBYTE0
, power_index
);
3050 rtl_set_bbreg(hw
, RTXAGC_B_MCS07_MCS04
,
3051 MASKBYTE1
, power_index
);
3054 rtl_set_bbreg(hw
, RTXAGC_B_MCS07_MCS04
,
3055 MASKBYTE2
, power_index
);
3058 rtl_set_bbreg(hw
, RTXAGC_B_MCS07_MCS04
,
3059 MASKBYTE3
, power_index
);
3062 rtl_set_bbreg(hw
, RTXAGC_B_MCS11_MCS08
,
3063 MASKBYTE0
, power_index
);
3066 rtl_set_bbreg(hw
, RTXAGC_B_MCS11_MCS08
,
3067 MASKBYTE1
, power_index
);
3069 case DESC_RATEMCS10
:
3070 rtl_set_bbreg(hw
, RTXAGC_B_MCS11_MCS08
,
3071 MASKBYTE2
, power_index
);
3073 case DESC_RATEMCS11
:
3074 rtl_set_bbreg(hw
, RTXAGC_B_MCS11_MCS08
,
3075 MASKBYTE3
, power_index
);
3077 case DESC_RATEMCS12
:
3078 rtl_set_bbreg(hw
, RTXAGC_B_MCS15_MCS12
,
3079 MASKBYTE0
, power_index
);
3081 case DESC_RATEMCS13
:
3082 rtl_set_bbreg(hw
, RTXAGC_B_MCS15_MCS12
,
3083 MASKBYTE1
, power_index
);
3085 case DESC_RATEMCS14
:
3086 rtl_set_bbreg(hw
, RTXAGC_B_MCS15_MCS12
,
3087 MASKBYTE2
, power_index
);
3089 case DESC_RATEMCS15
:
3090 rtl_set_bbreg(hw
, RTXAGC_B_MCS15_MCS12
,
3091 MASKBYTE3
, power_index
);
3093 case DESC_RATEVHT1SS_MCS0
:
3094 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX3_NSS1INDEX0
,
3095 MASKBYTE0
, power_index
);
3097 case DESC_RATEVHT1SS_MCS1
:
3098 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX3_NSS1INDEX0
,
3099 MASKBYTE1
, power_index
);
3101 case DESC_RATEVHT1SS_MCS2
:
3102 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX3_NSS1INDEX0
,
3103 MASKBYTE2
, power_index
);
3105 case DESC_RATEVHT1SS_MCS3
:
3106 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX3_NSS1INDEX0
,
3107 MASKBYTE3
, power_index
);
3109 case DESC_RATEVHT1SS_MCS4
:
3110 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX7_NSS1INDEX4
,
3111 MASKBYTE0
, power_index
);
3113 case DESC_RATEVHT1SS_MCS5
:
3114 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX7_NSS1INDEX4
,
3115 MASKBYTE1
, power_index
);
3117 case DESC_RATEVHT1SS_MCS6
:
3118 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX7_NSS1INDEX4
,
3119 MASKBYTE2
, power_index
);
3121 case DESC_RATEVHT1SS_MCS7
:
3122 rtl_set_bbreg(hw
, RTXAGC_B_NSS1INDEX7_NSS1INDEX4
,
3123 MASKBYTE3
, power_index
);
3125 case DESC_RATEVHT1SS_MCS8
:
3126 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX1_NSS1INDEX8
,
3127 MASKBYTE0
, power_index
);
3129 case DESC_RATEVHT1SS_MCS9
:
3130 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX1_NSS1INDEX8
,
3131 MASKBYTE1
, power_index
);
3133 case DESC_RATEVHT2SS_MCS0
:
3134 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX1_NSS1INDEX8
,
3135 MASKBYTE2
, power_index
);
3137 case DESC_RATEVHT2SS_MCS1
:
3138 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX1_NSS1INDEX8
,
3139 MASKBYTE3
, power_index
);
3141 case DESC_RATEVHT2SS_MCS2
:
3142 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX5_NSS2INDEX2
,
3143 MASKBYTE0
, power_index
);
3145 case DESC_RATEVHT2SS_MCS3
:
3146 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX5_NSS2INDEX2
,
3147 MASKBYTE1
, power_index
);
3149 case DESC_RATEVHT2SS_MCS4
:
3150 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX5_NSS2INDEX2
,
3151 MASKBYTE2
, power_index
);
3153 case DESC_RATEVHT2SS_MCS5
:
3154 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX5_NSS2INDEX2
,
3155 MASKBYTE3
, power_index
);
3157 case DESC_RATEVHT2SS_MCS6
:
3158 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX9_NSS2INDEX6
,
3159 MASKBYTE0
, power_index
);
3161 case DESC_RATEVHT2SS_MCS7
:
3162 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX9_NSS2INDEX6
,
3163 MASKBYTE1
, power_index
);
3165 case DESC_RATEVHT2SS_MCS8
:
3166 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX9_NSS2INDEX6
,
3167 MASKBYTE2
, power_index
);
3169 case DESC_RATEVHT2SS_MCS9
:
3170 rtl_set_bbreg(hw
, RTXAGC_B_NSS2INDEX9_NSS2INDEX6
,
3171 MASKBYTE3
, power_index
);
3174 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
3175 "Invalid Rate!!\n");
3179 RT_TRACE(rtlpriv
, COMP_POWER
, DBG_LOUD
,
3180 "Invalid RFPath!!\n");
3184 static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw
*hw
,
3186 u8 channel
, u8 size
)
3188 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3189 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3193 for (i
= 0; i
< size
; i
++) {
3195 _rtl8821ae_get_txpower_index(hw
, path
, array
[i
],
3196 rtlphy
->current_chan_bw
,
3198 _rtl8821ae_phy_set_txpower_index(hw
, power_index
, path
,
3203 static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw
*hw
,
3204 u8 bw
, u8 channel
, u8 path
)
3206 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3207 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3210 u32 power_level
, data
, offset
;
3212 if (path
>= rtlphy
->num_total_rfpath
)
3216 if (path
== RF90_PATH_A
) {
3218 _rtl8821ae_get_txpower_index(hw
, RF90_PATH_A
,
3219 DESC_RATEMCS7
, bw
, channel
);
3220 offset
= RA_TXPWRTRAING
;
3223 _rtl8821ae_get_txpower_index(hw
, RF90_PATH_B
,
3224 DESC_RATEMCS7
, bw
, channel
);
3225 offset
= RB_TXPWRTRAING
;
3228 for (i
= 0; i
< 3; i
++) {
3230 power_level
= power_level
- 10;
3232 power_level
= power_level
- 8;
3234 power_level
= power_level
- 6;
3236 data
|= (((power_level
> 2) ? (power_level
) : 2) << (i
* 8));
3238 rtl_set_bbreg(hw
, offset
, 0xffffff, data
);
3241 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw
*hw
,
3242 u8 channel
, u8 path
)
3244 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
3245 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
3246 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3247 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3248 u8 cck_rates
[] = {DESC_RATE1M
, DESC_RATE2M
, DESC_RATE5_5M
,
3250 u8 sizes_of_cck_retes
= 4;
3251 u8 ofdm_rates
[] = {DESC_RATE6M
, DESC_RATE9M
, DESC_RATE12M
,
3252 DESC_RATE18M
, DESC_RATE24M
, DESC_RATE36M
,
3253 DESC_RATE48M
, DESC_RATE54M
};
3254 u8 sizes_of_ofdm_retes
= 8;
3255 u8 ht_rates_1t
[] = {DESC_RATEMCS0
, DESC_RATEMCS1
, DESC_RATEMCS2
,
3256 DESC_RATEMCS3
, DESC_RATEMCS4
, DESC_RATEMCS5
,
3257 DESC_RATEMCS6
, DESC_RATEMCS7
};
3258 u8 sizes_of_ht_retes_1t
= 8;
3259 u8 ht_rates_2t
[] = {DESC_RATEMCS8
, DESC_RATEMCS9
,
3260 DESC_RATEMCS10
, DESC_RATEMCS11
,
3261 DESC_RATEMCS12
, DESC_RATEMCS13
,
3262 DESC_RATEMCS14
, DESC_RATEMCS15
};
3263 u8 sizes_of_ht_retes_2t
= 8;
3264 u8 vht_rates_1t
[] = {DESC_RATEVHT1SS_MCS0
, DESC_RATEVHT1SS_MCS1
,
3265 DESC_RATEVHT1SS_MCS2
, DESC_RATEVHT1SS_MCS3
,
3266 DESC_RATEVHT1SS_MCS4
, DESC_RATEVHT1SS_MCS5
,
3267 DESC_RATEVHT1SS_MCS6
, DESC_RATEVHT1SS_MCS7
,
3268 DESC_RATEVHT1SS_MCS8
, DESC_RATEVHT1SS_MCS9
};
3269 u8 vht_rates_2t
[] = {DESC_RATEVHT2SS_MCS0
, DESC_RATEVHT2SS_MCS1
,
3270 DESC_RATEVHT2SS_MCS2
, DESC_RATEVHT2SS_MCS3
,
3271 DESC_RATEVHT2SS_MCS4
, DESC_RATEVHT2SS_MCS5
,
3272 DESC_RATEVHT2SS_MCS6
, DESC_RATEVHT2SS_MCS7
,
3273 DESC_RATEVHT2SS_MCS8
, DESC_RATEVHT2SS_MCS9
};
3274 u8 sizes_of_vht_retes
= 10;
3276 if (rtlhal
->current_bandtype
== BAND_ON_2_4G
)
3277 _rtl8821ae_phy_set_txpower_level_by_path(hw
, cck_rates
, path
, channel
,
3278 sizes_of_cck_retes
);
3280 _rtl8821ae_phy_set_txpower_level_by_path(hw
, ofdm_rates
, path
, channel
,
3281 sizes_of_ofdm_retes
);
3282 _rtl8821ae_phy_set_txpower_level_by_path(hw
, ht_rates_1t
, path
, channel
,
3283 sizes_of_ht_retes_1t
);
3284 _rtl8821ae_phy_set_txpower_level_by_path(hw
, vht_rates_1t
, path
, channel
,
3285 sizes_of_vht_retes
);
3287 if (rtlphy
->num_total_rfpath
>= 2) {
3288 _rtl8821ae_phy_set_txpower_level_by_path(hw
, ht_rates_2t
, path
,
3290 sizes_of_ht_retes_2t
);
3291 _rtl8821ae_phy_set_txpower_level_by_path(hw
, vht_rates_2t
, path
,
3293 sizes_of_vht_retes
);
3296 _rtl8821ae_phy_txpower_training_by_path(hw
, rtlphy
->current_chan_bw
,
3300 /*just in case, write txpower in DW, to reduce time*/
3301 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw
*hw
, u8 channel
)
3303 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3304 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3307 for (path
= RF90_PATH_A
; path
< rtlphy
->num_total_rfpath
; ++path
)
3308 rtl8821ae_phy_set_txpower_level_by_path(hw
, channel
, path
);
3311 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw
*hw
,
3312 enum wireless_mode wirelessmode
,
3318 switch (wirelessmode
) {
3319 case WIRELESS_MODE_B
:
3322 case WIRELESS_MODE_G
:
3323 case WIRELESS_MODE_N_24G
:
3330 pwrout_dbm
= txpwridx
/ 2 + offset
;
3334 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw
*hw
, u8 operation
)
3336 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3337 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
3338 enum io_type iotype
= IO_CMD_PAUSE_BAND0_DM_BY_SCAN
;
3340 if (!is_hal_stop(rtlhal
)) {
3341 switch (operation
) {
3342 case SCAN_OPT_BACKUP_BAND0
:
3343 iotype
= IO_CMD_PAUSE_BAND0_DM_BY_SCAN
;
3344 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
3349 case SCAN_OPT_BACKUP_BAND1
:
3350 iotype
= IO_CMD_PAUSE_BAND1_DM_BY_SCAN
;
3351 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
3356 case SCAN_OPT_RESTORE
:
3357 iotype
= IO_CMD_RESUME_DM_BY_SCAN
;
3358 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
3363 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
3364 "Unknown Scan Backup operation.\n");
3370 static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv
*rtlpriv
, u8 bw
)
3372 u16 reg_rf_mode_bw
, tmp
= 0;
3374 reg_rf_mode_bw
= rtl_read_word(rtlpriv
, REG_TRXPTCL_CTL
);
3376 case HT_CHANNEL_WIDTH_20
:
3377 rtl_write_word(rtlpriv
, REG_TRXPTCL_CTL
, reg_rf_mode_bw
& 0xFE7F);
3379 case HT_CHANNEL_WIDTH_20_40
:
3380 tmp
= reg_rf_mode_bw
| BIT(7);
3381 rtl_write_word(rtlpriv
, REG_TRXPTCL_CTL
, tmp
& 0xFEFF);
3383 case HT_CHANNEL_WIDTH_80
:
3384 tmp
= reg_rf_mode_bw
| BIT(8);
3385 rtl_write_word(rtlpriv
, REG_TRXPTCL_CTL
, tmp
& 0xFF7F);
3388 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
, "unknown Bandwidth: 0x%x\n", bw
);
3393 static u8
_rtl8821ae_phy_get_secondary_chnl(struct rtl_priv
*rtlpriv
)
3395 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3396 struct rtl_mac
*mac
= rtl_mac(rtlpriv
);
3397 u8 sc_set_40
= 0, sc_set_20
= 0;
3399 if (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_80
) {
3400 if (mac
->cur_80_prime_sc
== PRIME_CHNL_OFFSET_LOWER
)
3401 sc_set_40
= VHT_DATA_SC_40_LOWER_OF_80MHZ
;
3402 else if (mac
->cur_80_prime_sc
== PRIME_CHNL_OFFSET_UPPER
)
3403 sc_set_40
= VHT_DATA_SC_40_UPPER_OF_80MHZ
;
3405 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
3406 "SCMapping: Not Correct Primary40MHz Setting\n");
3408 if ((mac
->cur_40_prime_sc
== PRIME_CHNL_OFFSET_LOWER
) &&
3409 (mac
->cur_80_prime_sc
== HAL_PRIME_CHNL_OFFSET_LOWER
))
3410 sc_set_20
= VHT_DATA_SC_20_LOWEST_OF_80MHZ
;
3411 else if ((mac
->cur_40_prime_sc
== PRIME_CHNL_OFFSET_UPPER
) &&
3412 (mac
->cur_80_prime_sc
== HAL_PRIME_CHNL_OFFSET_LOWER
))
3413 sc_set_20
= VHT_DATA_SC_20_LOWER_OF_80MHZ
;
3414 else if ((mac
->cur_40_prime_sc
== PRIME_CHNL_OFFSET_LOWER
) &&
3415 (mac
->cur_80_prime_sc
== HAL_PRIME_CHNL_OFFSET_UPPER
))
3416 sc_set_20
= VHT_DATA_SC_20_UPPER_OF_80MHZ
;
3417 else if ((mac
->cur_40_prime_sc
== PRIME_CHNL_OFFSET_UPPER
) &&
3418 (mac
->cur_80_prime_sc
== HAL_PRIME_CHNL_OFFSET_UPPER
))
3419 sc_set_20
= VHT_DATA_SC_20_UPPERST_OF_80MHZ
;
3421 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
3422 "SCMapping: Not Correct Primary40MHz Setting\n");
3423 } else if (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20_40
) {
3424 if (mac
->cur_40_prime_sc
== PRIME_CHNL_OFFSET_UPPER
)
3425 sc_set_20
= VHT_DATA_SC_20_UPPER_OF_80MHZ
;
3426 else if (mac
->cur_40_prime_sc
== PRIME_CHNL_OFFSET_LOWER
)
3427 sc_set_20
= VHT_DATA_SC_20_LOWER_OF_80MHZ
;
3429 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
3430 "SCMapping: Not Correct Primary40MHz Setting\n");
3432 return (sc_set_40
<< 4) | sc_set_20
;
3435 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw
*hw
)
3437 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3438 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3442 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
,
3443 "Switch to %s bandwidth\n",
3444 (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20
?
3446 (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_20_40
?
3447 "40MHz" : "80MHz")));
3449 _rtl8821ae_phy_set_reg_bw(rtlpriv
, rtlphy
->current_chan_bw
);
3450 sub_chnl
= _rtl8821ae_phy_get_secondary_chnl(rtlpriv
);
3451 rtl_write_byte(rtlpriv
, 0x0483, sub_chnl
);
3453 switch (rtlphy
->current_chan_bw
) {
3454 case HT_CHANNEL_WIDTH_20
:
3455 rtl_set_bbreg(hw
, RRFMOD
, 0x003003C3, 0x00300200);
3456 rtl_set_bbreg(hw
, RADC_BUF_CLK
, BIT(30), 0);
3458 if (rtlphy
->rf_type
== RF_2T2R
)
3459 rtl_set_bbreg(hw
, RL1PEAKTH
, 0x03C00000, 7);
3461 rtl_set_bbreg(hw
, RL1PEAKTH
, 0x03C00000, 8);
3463 case HT_CHANNEL_WIDTH_20_40
:
3464 rtl_set_bbreg(hw
, RRFMOD
, 0x003003C3, 0x00300201);
3465 rtl_set_bbreg(hw
, RADC_BUF_CLK
, BIT(30), 0);
3466 rtl_set_bbreg(hw
, RRFMOD
, 0x3C, sub_chnl
);
3467 rtl_set_bbreg(hw
, RCCAONSEC
, 0xf0000000, sub_chnl
);
3469 if (rtlphy
->reg_837
& BIT(2))
3472 if (rtlphy
->rf_type
== RF_2T2R
)
3477 /* 0x848[25:22] = 0x6 */
3478 rtl_set_bbreg(hw
, RL1PEAKTH
, 0x03C00000, l1pk_val
);
3480 if (sub_chnl
== VHT_DATA_SC_20_UPPER_OF_80MHZ
)
3481 rtl_set_bbreg(hw
, RCCK_SYSTEM
, BCCK_SYSTEM
, 1);
3483 rtl_set_bbreg(hw
, RCCK_SYSTEM
, BCCK_SYSTEM
, 0);
3486 case HT_CHANNEL_WIDTH_80
:
3487 /* 0x8ac[21,20,9:6,1,0]=8'b11100010 */
3488 rtl_set_bbreg(hw
, RRFMOD
, 0x003003C3, 0x00300202);
3490 rtl_set_bbreg(hw
, RADC_BUF_CLK
, BIT(30), 1);
3491 rtl_set_bbreg(hw
, RRFMOD
, 0x3C, sub_chnl
);
3492 rtl_set_bbreg(hw
, RCCAONSEC
, 0xf0000000, sub_chnl
);
3494 if (rtlphy
->reg_837
& BIT(2))
3497 if (rtlphy
->rf_type
== RF_2T2R
)
3502 rtl_set_bbreg(hw
, RL1PEAKTH
, 0x03C00000, l1pk_val
);
3506 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
3507 "unknown bandwidth: %#X\n", rtlphy
->current_chan_bw
);
3511 rtl8812ae_fixspur(hw
, rtlphy
->current_chan_bw
, rtlphy
->current_channel
);
3513 rtl8821ae_phy_rf6052_set_bandwidth(hw
, rtlphy
->current_chan_bw
);
3514 rtlphy
->set_bwmode_inprogress
= false;
3516 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_LOUD
, "\n");
3519 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw
*hw
,
3520 enum nl80211_channel_type ch_type
)
3522 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3523 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3524 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
3525 u8 tmp_bw
= rtlphy
->current_chan_bw
;
3527 if (rtlphy
->set_bwmode_inprogress
)
3529 rtlphy
->set_bwmode_inprogress
= true;
3530 if ((!is_hal_stop(rtlhal
)) && !(RT_CANNOT_IO(hw
)))
3531 rtl8821ae_phy_set_bw_mode_callback(hw
);
3533 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
3534 "FALSE driver sleep or unload\n");
3535 rtlphy
->set_bwmode_inprogress
= false;
3536 rtlphy
->current_chan_bw
= tmp_bw
;
3540 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw
*hw
)
3542 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3543 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
3544 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3545 u8 channel
= rtlphy
->current_channel
;
3549 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
,
3550 "switch to channel%d\n", rtlphy
->current_channel
);
3551 if (is_hal_stop(rtlhal
))
3554 if (36 <= channel
&& channel
<= 48)
3556 else if (50 <= channel
&& channel
<= 64)
3558 else if (100 <= channel
&& channel
<= 116)
3560 else if (118 <= channel
)
3564 rtl_set_bbreg(hw
, RFC_AREA
, 0x1ffe0000, data
);
3566 for (path
= RF90_PATH_A
; path
< rtlphy
->num_total_rfpath
; path
++) {
3567 if (36 <= channel
&& channel
<= 64)
3569 else if (100 <= channel
&& channel
<= 140)
3571 else if (140 < channel
)
3575 rtl8821ae_phy_set_rf_reg(hw
, path
, RF_CHNLBW
,
3576 BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data
);
3578 rtl8821ae_phy_set_rf_reg(hw
, path
, RF_CHNLBW
,
3579 BMASKBYTE0
, channel
);
3582 if (rtlhal
->hw_type
== HARDWARE_TYPE_RTL8821AE
) {
3583 if (36 <= channel
&& channel
<= 64)
3585 else if (100 <= channel
&& channel
<= 140)
3589 rtl8821ae_phy_set_rf_reg(hw
, path
, RF_APK
,
3590 BRFREGOFFSETMASK
, data
);
3594 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
, "\n");
3597 u8
rtl8821ae_phy_sw_chnl(struct ieee80211_hw
*hw
)
3599 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3600 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3601 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
3602 u32 timeout
= 1000, timecount
= 0;
3603 u8 channel
= rtlphy
->current_channel
;
3605 if (rtlphy
->sw_chnl_inprogress
)
3607 if (rtlphy
->set_bwmode_inprogress
)
3610 if ((is_hal_stop(rtlhal
)) || (RT_CANNOT_IO(hw
))) {
3611 RT_TRACE(rtlpriv
, COMP_CHAN
, DBG_LOUD
,
3612 "sw_chnl_inprogress false driver sleep or unload\n");
3615 while (rtlphy
->lck_inprogress
&& timecount
< timeout
) {
3620 if (rtlphy
->current_channel
> 14 && rtlhal
->current_bandtype
!= BAND_ON_5G
)
3621 rtl8821ae_phy_switch_wirelessband(hw
, BAND_ON_5G
);
3622 else if (rtlphy
->current_channel
<= 14 && rtlhal
->current_bandtype
!= BAND_ON_2_4G
)
3623 rtl8821ae_phy_switch_wirelessband(hw
, BAND_ON_2_4G
);
3625 rtlphy
->sw_chnl_inprogress
= true;
3629 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
,
3630 "switch to channel%d, band type is %d\n",
3631 rtlphy
->current_channel
, rtlhal
->current_bandtype
);
3633 rtl8821ae_phy_sw_chnl_callback(hw
);
3635 rtl8821ae_dm_clear_txpower_tracking_state(hw
);
3636 rtl8821ae_phy_set_txpower_level(hw
, rtlphy
->current_channel
);
3638 RT_TRACE(rtlpriv
, COMP_SCAN
, DBG_TRACE
, "\n");
3639 rtlphy
->sw_chnl_inprogress
= false;
3643 u8
_rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl
)
3645 u8 channel_all
[TARGET_CHNL_NUM_2G_5G_8812
] = {
3646 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3647 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
3648 56, 58, 60, 62, 64, 100, 102, 104, 106, 108,
3649 110, 112, 114, 116, 118, 120, 122, 124, 126,
3650 128, 130, 132, 134, 136, 138, 140, 149, 151,
3651 153, 155, 157, 159, 161, 163, 165};
3655 for (place
= 14; place
< sizeof(channel_all
); place
++)
3656 if (channel_all
[place
] == chnl
)
3663 #define MACBB_REG_NUM 10
3664 #define AFE_REG_NUM 14
3665 #define RF_REG_NUM 3
3667 static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw
*hw
,
3669 u32
*backup_macbb_reg
, u32 mac_bb_num
)
3671 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3674 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3675 /*save MACBB default value*/
3676 for (i
= 0; i
< mac_bb_num
; i
++)
3677 macbb_backup
[i
] = rtl_read_dword(rtlpriv
, backup_macbb_reg
[i
]);
3679 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "BackupMacBB Success!!!!\n");
3682 static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw
*hw
, u32
*afe_backup
,
3683 u32
*backup_afe_REG
, u32 afe_num
)
3685 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3688 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3689 /*Save AFE Parameters */
3690 for (i
= 0; i
< afe_num
; i
++)
3691 afe_backup
[i
] = rtl_read_dword(rtlpriv
, backup_afe_REG
[i
]);
3692 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "BackupAFE Success!!!!\n");
3695 static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw
*hw
, u32
*rfa_backup
,
3696 u32
*rfb_backup
, u32
*backup_rf_reg
,
3699 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3702 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3703 /*Save RF Parameters*/
3704 for (i
= 0; i
< rf_num
; i
++) {
3705 rfa_backup
[i
] = rtl_get_rfreg(hw
, RF90_PATH_A
, backup_rf_reg
[i
],
3707 rfb_backup
[i
] = rtl_get_rfreg(hw
, RF90_PATH_B
, backup_rf_reg
[i
],
3710 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "BackupRF Success!!!!\n");
3713 static void _rtl8821ae_iqk_configure_mac(
3714 struct ieee80211_hw
*hw
3717 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3718 /* ========MAC register setting========*/
3719 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3720 rtl_write_byte(rtlpriv
, 0x522, 0x3f);
3721 rtl_set_bbreg(hw
, 0x550, BIT(11) | BIT(3), 0x0);
3722 rtl_write_byte(rtlpriv
, 0x808, 0x00); /*RX ante off*/
3723 rtl_set_bbreg(hw
, 0x838, 0xf, 0xc); /*CCA off*/
3726 static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw
*hw
,
3727 enum radio_path path
, u32 tx_x
, u32 tx_y
)
3729 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3732 /* [31] = 1 --> Page C1 */
3733 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1);
3734 rtl_write_dword(rtlpriv
, 0xc90, 0x00000080);
3735 rtl_write_dword(rtlpriv
, 0xcc4, 0x20040000);
3736 rtl_write_dword(rtlpriv
, 0xcc8, 0x20000000);
3737 rtl_set_bbreg(hw
, 0xccc, 0x000007ff, tx_y
);
3738 rtl_set_bbreg(hw
, 0xcd4, 0x000007ff, tx_x
);
3739 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
3740 "TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3742 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
3743 "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
3744 rtl_get_bbreg(hw
, 0xcd4, 0x000007ff),
3745 rtl_get_bbreg(hw
, 0xccc, 0x000007ff));
3752 static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw
*hw
,
3753 enum radio_path path
, u32 rx_x
, u32 rx_y
)
3755 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3758 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3759 rtl_set_bbreg(hw
, 0xc10, 0x000003ff, rx_x
>>1);
3760 rtl_set_bbreg(hw
, 0xc10, 0x03ff0000, rx_y
>>1);
3761 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
3762 "rx_x = %x;;rx_y = %x ====>fill to IQC\n",
3764 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
3765 "0xc10 = %x ====>fill to IQC\n",
3766 rtl_read_dword(rtlpriv
, 0xc10));
3775 static void _rtl8821ae_iqk_tx(struct ieee80211_hw
*hw
, enum radio_path path
)
3777 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
3778 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
3779 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
3781 u32 tx_fail
, rx_fail
, delay_count
, iqk_ready
, cal_retry
, cal
= 0, temp_reg65
;
3782 int tx_x
= 0, tx_y
= 0, rx_x
= 0, rx_y
= 0, tx_average
= 0, rx_average
= 0;
3783 int tx_x0
[cal_num
], tx_y0
[cal_num
], tx_x0_rxk
[cal_num
],
3784 tx_y0_rxk
[cal_num
], rx_x0
[cal_num
], rx_y0
[cal_num
];
3785 bool tx0iqkok
= false, rx0iqkok
= false;
3786 bool vdf_enable
= false;
3787 int i
, k
, vdf_y
[3], vdf_x
[3], tx_dt
[3], rx_dt
[3],
3788 ii
, dx
= 0, dy
= 0, tx_finish
= 0, rx_finish
= 0;
3790 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
3791 "BandWidth = %d.\n",
3792 rtlphy
->current_chan_bw
);
3793 if (rtlphy
->current_chan_bw
== HT_CHANNEL_WIDTH_80
)
3796 while (cal
< cal_num
) {
3799 temp_reg65
= rtl_get_rfreg(hw
, path
, 0x65, 0xffffffff);
3801 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3802 /*========Path-A AFE all on========*/
3803 /*Port 0 DAC/ADC on*/
3804 rtl_write_dword(rtlpriv
, 0xc60, 0x77777777);
3805 rtl_write_dword(rtlpriv
, 0xc64, 0x77777777);
3806 rtl_write_dword(rtlpriv
, 0xc68, 0x19791979);
3807 rtl_write_dword(rtlpriv
, 0xc6c, 0x19791979);
3808 rtl_write_dword(rtlpriv
, 0xc70, 0x19791979);
3809 rtl_write_dword(rtlpriv
, 0xc74, 0x19791979);
3810 rtl_write_dword(rtlpriv
, 0xc78, 0x19791979);
3811 rtl_write_dword(rtlpriv
, 0xc7c, 0x19791979);
3812 rtl_write_dword(rtlpriv
, 0xc80, 0x19791979);
3813 rtl_write_dword(rtlpriv
, 0xc84, 0x19791979);
3815 rtl_set_bbreg(hw
, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
3818 /* ====== LOK ====== */
3819 /*DAC/ADC sampling rate (160 MHz)*/
3820 rtl_set_bbreg(hw
, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3822 /* 2. LoK RF Setting (at BW = 20M) */
3823 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x80002);
3824 rtl_set_rfreg(hw
, path
, 0x18, 0x00c00, 0x3); /* BW 20M */
3825 rtl_set_rfreg(hw
, path
, 0x30, RFREG_OFFSET_MASK
, 0x20000);
3826 rtl_set_rfreg(hw
, path
, 0x31, RFREG_OFFSET_MASK
, 0x0003f);
3827 rtl_set_rfreg(hw
, path
, 0x32, RFREG_OFFSET_MASK
, 0xf3fc3);
3828 rtl_set_rfreg(hw
, path
, 0x65, RFREG_OFFSET_MASK
, 0x931d5);
3829 rtl_set_rfreg(hw
, path
, 0x8f, RFREG_OFFSET_MASK
, 0x8a001);
3830 rtl_set_bbreg(hw
, 0xcb8, 0xf, 0xd);
3831 rtl_write_dword(rtlpriv
, 0x90c, 0x00008000);
3832 rtl_write_dword(rtlpriv
, 0xb00, 0x03000100);
3833 rtl_set_bbreg(hw
, 0xc94, BIT(0), 0x1);
3834 rtl_write_dword(rtlpriv
, 0x978, 0x29002000);/* TX (X,Y) */
3835 rtl_write_dword(rtlpriv
, 0x97c, 0xa9002000);/* RX (X,Y) */
3836 rtl_write_dword(rtlpriv
, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
3838 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3839 rtl_write_dword(rtlpriv
, 0xc88, 0x821403f4);
3841 if (rtlhal
->current_bandtype
)
3842 rtl_write_dword(rtlpriv
, 0xc8c, 0x68163e96);
3844 rtl_write_dword(rtlpriv
, 0xc8c, 0x28163e96);
3846 rtl_write_dword(rtlpriv
, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3847 rtl_write_dword(rtlpriv
, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3848 rtl_write_dword(rtlpriv
, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3849 rtl_write_dword(rtlpriv
, 0x980, 0xfa000000);
3850 rtl_write_dword(rtlpriv
, 0x980, 0xf8000000);
3852 mdelay(10); /* Delay 10ms */
3853 rtl_write_dword(rtlpriv
, 0xcb8, 0x00000000);
3855 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3856 rtl_set_rfreg(hw
, path
, 0x58, 0x7fe00, rtl_get_rfreg(hw
, path
, 0x8, 0xffc00)); /* Load LOK */
3858 switch (rtlphy
->current_chan_bw
) {
3860 rtl_set_rfreg(hw
, path
, 0x18, 0x00c00, 0x1);
3863 rtl_set_rfreg(hw
, path
, 0x18, 0x00c00, 0x0);
3869 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3871 /* 3. TX RF Setting */
3872 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3873 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x80000);
3874 rtl_set_rfreg(hw
, path
, 0x30, RFREG_OFFSET_MASK
, 0x20000);
3875 rtl_set_rfreg(hw
, path
, 0x31, RFREG_OFFSET_MASK
, 0x0003f);
3876 rtl_set_rfreg(hw
, path
, 0x32, RFREG_OFFSET_MASK
, 0xf3fc3);
3877 rtl_set_rfreg(hw
, path
, 0x65, RFREG_OFFSET_MASK
, 0x931d5);
3878 rtl_set_rfreg(hw
, path
, 0x8f, RFREG_OFFSET_MASK
, 0x8a001);
3879 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x00000);
3880 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd); */
3881 rtl_write_dword(rtlpriv
, 0x90c, 0x00008000);
3882 rtl_write_dword(rtlpriv
, 0xb00, 0x03000100);
3883 rtl_set_bbreg(hw
, 0xc94, BIT(0), 0x1);
3884 rtl_write_dword(rtlpriv
, 0x978, 0x29002000);/* TX (X,Y) */
3885 rtl_write_dword(rtlpriv
, 0x97c, 0xa9002000);/* RX (X,Y) */
3886 rtl_write_dword(rtlpriv
, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
3888 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3889 rtl_write_dword(rtlpriv
, 0xc88, 0x821403f1);
3890 if (rtlhal
->current_bandtype
)
3891 rtl_write_dword(rtlpriv
, 0xc8c, 0x40163e96);
3893 rtl_write_dword(rtlpriv
, 0xc8c, 0x00163e96);
3895 if (vdf_enable
== 1) {
3896 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "VDF_enable\n");
3897 for (k
= 0; k
<= 2; k
++) {
3900 rtl_write_dword(rtlpriv
, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3901 rtl_write_dword(rtlpriv
, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3902 rtl_set_bbreg(hw
, 0xce8, BIT(31), 0x0);
3905 rtl_set_bbreg(hw
, 0xc80, BIT(28), 0x0);
3906 rtl_set_bbreg(hw
, 0xc84, BIT(28), 0x0);
3907 rtl_set_bbreg(hw
, 0xce8, BIT(31), 0x0);
3910 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
3911 "vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y
[1]>>21 & 0x00007ff, vdf_y
[0]>>21 & 0x00007ff);
3912 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
3913 "vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x
[1]>>21 & 0x00007ff, vdf_x
[0]>>21 & 0x00007ff);
3914 tx_dt
[cal
] = (vdf_y
[1]>>20)-(vdf_y
[0]>>20);
3915 tx_dt
[cal
] = ((16*tx_dt
[cal
])*10000/15708);
3916 tx_dt
[cal
] = (tx_dt
[cal
] >> 1)+(tx_dt
[cal
] & BIT(0));
3917 rtl_write_dword(rtlpriv
, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3918 rtl_write_dword(rtlpriv
, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3919 rtl_set_bbreg(hw
, 0xce8, BIT(31), 0x1);
3920 rtl_set_bbreg(hw
, 0xce8, 0x3fff0000, tx_dt
[cal
] & 0x00003fff);
3925 rtl_write_dword(rtlpriv
, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3929 rtl_write_dword(rtlpriv
, 0x980, 0xfa000000);
3930 rtl_write_dword(rtlpriv
, 0x980, 0xf8000000);
3932 mdelay(10); /* Delay 10ms */
3933 rtl_write_dword(rtlpriv
, 0xcb8, 0x00000000);
3936 iqk_ready
= rtl_get_bbreg(hw
, 0xd00, BIT(10));
3937 if ((~iqk_ready
) || (delay_count
> 20))
3945 if (delay_count
< 20) { /* If 20ms No Result, then cal_retry++ */
3946 /* ============TXIQK Check============== */
3947 tx_fail
= rtl_get_bbreg(hw
, 0xd00, BIT(12));
3950 rtl_write_dword(rtlpriv
, 0xcb8, 0x02000000);
3951 vdf_x
[k
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
3952 rtl_write_dword(rtlpriv
, 0xcb8, 0x04000000);
3953 vdf_y
[k
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
3957 rtl_set_bbreg(hw
, 0xccc, 0x000007ff, 0x0);
3958 rtl_set_bbreg(hw
, 0xcd4, 0x000007ff, 0x200);
3961 if (cal_retry
== 10)
3967 if (cal_retry
== 10)
3973 tx_x0
[cal
] = vdf_x
[k
-1];
3974 tx_y0
[cal
] = vdf_y
[k
-1];
3977 rtl_write_dword(rtlpriv
, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3978 rtl_write_dword(rtlpriv
, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3979 rtl_write_dword(rtlpriv
, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3983 rtl_write_dword(rtlpriv
, 0x980, 0xfa000000);
3984 rtl_write_dword(rtlpriv
, 0x980, 0xf8000000);
3986 mdelay(10); /* Delay 10ms */
3987 rtl_write_dword(rtlpriv
, 0xcb8, 0x00000000);
3990 iqk_ready
= rtl_get_bbreg(hw
, 0xd00, BIT(10));
3991 if ((~iqk_ready
) || (delay_count
> 20))
3999 if (delay_count
< 20) { /* If 20ms No Result, then cal_retry++ */
4000 /* ============TXIQK Check============== */
4001 tx_fail
= rtl_get_bbreg(hw
, 0xd00, BIT(12));
4004 rtl_write_dword(rtlpriv
, 0xcb8, 0x02000000);
4005 tx_x0
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4006 rtl_write_dword(rtlpriv
, 0xcb8, 0x04000000);
4007 tx_y0
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4011 rtl_set_bbreg(hw
, 0xccc, 0x000007ff, 0x0);
4012 rtl_set_bbreg(hw
, 0xcd4, 0x000007ff, 0x200);
4015 if (cal_retry
== 10)
4021 if (cal_retry
== 10)
4027 if (tx0iqkok
== false)
4028 break; /* TXK fail, Don't do RXK */
4030 if (vdf_enable
== 1) {
4031 rtl_set_bbreg(hw
, 0xce8, BIT(31), 0x0); /* TX VDF Disable */
4032 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "RXVDF Start\n");
4033 for (k
= 0; k
<= 2; k
++) {
4034 /* ====== RX mode TXK (RXK Step 1) ====== */
4035 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4036 /* 1. TX RF Setting */
4037 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x80000);
4038 rtl_set_rfreg(hw
, path
, 0x30, RFREG_OFFSET_MASK
, 0x30000);
4039 rtl_set_rfreg(hw
, path
, 0x31, RFREG_OFFSET_MASK
, 0x00029);
4040 rtl_set_rfreg(hw
, path
, 0x32, RFREG_OFFSET_MASK
, 0xd7ffb);
4041 rtl_set_rfreg(hw
, path
, 0x65, RFREG_OFFSET_MASK
, temp_reg65
);
4042 rtl_set_rfreg(hw
, path
, 0x8f, RFREG_OFFSET_MASK
, 0x8a001);
4043 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x00000);
4045 rtl_set_bbreg(hw
, 0xcb8, 0xf, 0xd);
4046 rtl_write_dword(rtlpriv
, 0x978, 0x29002000);/* TX (X,Y) */
4047 rtl_write_dword(rtlpriv
, 0x97c, 0xa9002000);/* RX (X,Y) */
4048 rtl_write_dword(rtlpriv
, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4049 rtl_write_dword(rtlpriv
, 0x90c, 0x00008000);
4050 rtl_write_dword(rtlpriv
, 0xb00, 0x03000100);
4051 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4055 rtl_write_dword(rtlpriv
, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4056 rtl_write_dword(rtlpriv
, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4057 rtl_set_bbreg(hw
, 0xce8, BIT(30), 0x0);
4062 rtl_write_dword(rtlpriv
, 0xc80, 0x08008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4063 rtl_write_dword(rtlpriv
, 0xc84, 0x28008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4064 rtl_set_bbreg(hw
, 0xce8, BIT(30), 0x0);
4069 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4070 "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n",
4071 vdf_y
[1]>>21 & 0x00007ff, vdf_y
[0]>>21 & 0x00007ff);
4072 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4073 "VDF_X[1] = %x;;;VDF_X[0] = %x\n",
4074 vdf_x
[1]>>21 & 0x00007ff, vdf_x
[0]>>21 & 0x00007ff);
4075 rx_dt
[cal
] = (vdf_y
[1]>>20)-(vdf_y
[0]>>20);
4076 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "Rx_dt = %d\n", rx_dt
[cal
]);
4077 rx_dt
[cal
] = ((16*rx_dt
[cal
])*10000/13823);
4078 rx_dt
[cal
] = (rx_dt
[cal
] >> 1)+(rx_dt
[cal
] & BIT(0));
4079 rtl_write_dword(rtlpriv
, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4080 rtl_write_dword(rtlpriv
, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4081 rtl_set_bbreg(hw
, 0xce8, 0x00003fff, rx_dt
[cal
] & 0x00003fff);
4087 rtl_write_dword(rtlpriv
, 0xc88, 0x821603e0);
4088 rtl_write_dword(rtlpriv
, 0xc8c, 0x68163e96);
4089 rtl_write_dword(rtlpriv
, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4093 rtl_write_dword(rtlpriv
, 0x980, 0xfa000000);
4094 rtl_write_dword(rtlpriv
, 0x980, 0xf8000000);
4096 mdelay(10); /* Delay 10ms */
4097 rtl_write_dword(rtlpriv
, 0xcb8, 0x00000000);
4100 iqk_ready
= rtl_get_bbreg(hw
, 0xd00, BIT(10));
4101 if ((~iqk_ready
) || (delay_count
> 20))
4109 if (delay_count
< 20) { /* If 20ms No Result, then cal_retry++ */
4110 /* ============TXIQK Check============== */
4111 tx_fail
= rtl_get_bbreg(hw
, 0xd00, BIT(12));
4114 rtl_write_dword(rtlpriv
, 0xcb8, 0x02000000);
4115 tx_x0_rxk
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4116 rtl_write_dword(rtlpriv
, 0xcb8, 0x04000000);
4117 tx_y0_rxk
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4123 if (cal_retry
== 10)
4129 if (cal_retry
== 10)
4134 if (tx0iqkok
== false) { /* If RX mode TXK fail, then take TXK Result */
4135 tx_x0_rxk
[cal
] = tx_x0
[cal
];
4136 tx_y0_rxk
[cal
] = tx_y0
[cal
];
4141 "RXK Step 1 fail\n");
4144 /* ====== RX IQK ====== */
4145 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4146 /* 1. RX RF Setting */
4147 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x80000);
4148 rtl_set_rfreg(hw
, path
, 0x30, RFREG_OFFSET_MASK
, 0x30000);
4149 rtl_set_rfreg(hw
, path
, 0x31, RFREG_OFFSET_MASK
, 0x0002f);
4150 rtl_set_rfreg(hw
, path
, 0x32, RFREG_OFFSET_MASK
, 0xfffbb);
4151 rtl_set_rfreg(hw
, path
, 0x8f, RFREG_OFFSET_MASK
, 0x88001);
4152 rtl_set_rfreg(hw
, path
, 0x65, RFREG_OFFSET_MASK
, 0x931d8);
4153 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x00000);
4155 rtl_set_bbreg(hw
, 0x978, 0x03FF8000, (tx_x0_rxk
[cal
])>>21&0x000007ff);
4156 rtl_set_bbreg(hw
, 0x978, 0x000007FF, (tx_y0_rxk
[cal
])>>21&0x000007ff);
4157 rtl_set_bbreg(hw
, 0x978, BIT(31), 0x1);
4158 rtl_set_bbreg(hw
, 0x97c, BIT(31), 0x0);
4159 rtl_set_bbreg(hw
, 0xcb8, 0xF, 0xe);
4160 rtl_write_dword(rtlpriv
, 0x90c, 0x00008000);
4161 rtl_write_dword(rtlpriv
, 0x984, 0x0046a911);
4163 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4164 rtl_set_bbreg(hw
, 0xc80, BIT(29), 0x1);
4165 rtl_set_bbreg(hw
, 0xc84, BIT(29), 0x0);
4166 rtl_write_dword(rtlpriv
, 0xc88, 0x02140119);
4168 rtl_write_dword(rtlpriv
, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */
4171 rtl_set_bbreg(hw
, 0xce8, BIT(30), 0x1); /* RX VDF Enable */
4172 rtl_write_dword(rtlpriv
, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4177 rtl_write_dword(rtlpriv
, 0x980, 0xfa000000);
4178 rtl_write_dword(rtlpriv
, 0x980, 0xf8000000);
4180 mdelay(10); /* Delay 10ms */
4181 rtl_write_dword(rtlpriv
, 0xcb8, 0x00000000);
4184 iqk_ready
= rtl_get_bbreg(hw
, 0xd00, BIT(10));
4185 if ((~iqk_ready
) || (delay_count
> 20))
4193 if (delay_count
< 20) { /* If 20ms No Result, then cal_retry++ */
4194 /* ============RXIQK Check============== */
4195 rx_fail
= rtl_get_bbreg(hw
, 0xd00, BIT(11));
4197 rtl_write_dword(rtlpriv
, 0xcb8, 0x06000000);
4198 vdf_x
[k
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4199 rtl_write_dword(rtlpriv
, 0xcb8, 0x08000000);
4200 vdf_y
[k
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4204 rtl_set_bbreg(hw
, 0xc10, 0x000003ff, 0x200>>1);
4205 rtl_set_bbreg(hw
, 0xc10, 0x03ff0000, 0x0>>1);
4208 if (cal_retry
== 10)
4215 if (cal_retry
== 10)
4222 rx_x0
[cal
] = vdf_x
[k
-1];
4223 rx_y0
[cal
] = vdf_y
[k
-1];
4225 rtl_set_bbreg(hw
, 0xce8, BIT(31), 0x1); /* TX VDF Enable */
4229 /* ====== RX mode TXK (RXK Step 1) ====== */
4230 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4231 /* 1. TX RF Setting */
4232 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x80000);
4233 rtl_set_rfreg(hw
, path
, 0x30, RFREG_OFFSET_MASK
, 0x30000);
4234 rtl_set_rfreg(hw
, path
, 0x31, RFREG_OFFSET_MASK
, 0x00029);
4235 rtl_set_rfreg(hw
, path
, 0x32, RFREG_OFFSET_MASK
, 0xd7ffb);
4236 rtl_set_rfreg(hw
, path
, 0x65, RFREG_OFFSET_MASK
, temp_reg65
);
4237 rtl_set_rfreg(hw
, path
, 0x8f, RFREG_OFFSET_MASK
, 0x8a001);
4238 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x00000);
4239 rtl_write_dword(rtlpriv
, 0x90c, 0x00008000);
4240 rtl_write_dword(rtlpriv
, 0xb00, 0x03000100);
4241 rtl_write_dword(rtlpriv
, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4243 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4244 rtl_write_dword(rtlpriv
, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4245 rtl_write_dword(rtlpriv
, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4246 rtl_write_dword(rtlpriv
, 0xc88, 0x821603e0);
4247 /* ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); */
4248 rtl_write_dword(rtlpriv
, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4252 rtl_write_dword(rtlpriv
, 0x980, 0xfa000000);
4253 rtl_write_dword(rtlpriv
, 0x980, 0xf8000000);
4255 mdelay(10); /* Delay 10ms */
4256 rtl_write_dword(rtlpriv
, 0xcb8, 0x00000000);
4259 iqk_ready
= rtl_get_bbreg(hw
, 0xd00, BIT(10));
4260 if ((~iqk_ready
) || (delay_count
> 20))
4268 if (delay_count
< 20) { /* If 20ms No Result, then cal_retry++ */
4269 /* ============TXIQK Check============== */
4270 tx_fail
= rtl_get_bbreg(hw
, 0xd00, BIT(12));
4273 rtl_write_dword(rtlpriv
, 0xcb8, 0x02000000);
4274 tx_x0_rxk
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4275 rtl_write_dword(rtlpriv
, 0xcb8, 0x04000000);
4276 tx_y0_rxk
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4282 if (cal_retry
== 10)
4288 if (cal_retry
== 10)
4293 if (tx0iqkok
== false) { /* If RX mode TXK fail, then take TXK Result */
4294 tx_x0_rxk
[cal
] = tx_x0
[cal
];
4295 tx_y0_rxk
[cal
] = tx_y0
[cal
];
4297 RT_TRACE(rtlpriv
, COMP_IQK
,
4301 /* ====== RX IQK ====== */
4302 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4303 /* 1. RX RF Setting */
4304 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x80000);
4305 rtl_set_rfreg(hw
, path
, 0x30, RFREG_OFFSET_MASK
, 0x30000);
4306 rtl_set_rfreg(hw
, path
, 0x31, RFREG_OFFSET_MASK
, 0x0002f);
4307 rtl_set_rfreg(hw
, path
, 0x32, RFREG_OFFSET_MASK
, 0xfffbb);
4308 rtl_set_rfreg(hw
, path
, 0x8f, RFREG_OFFSET_MASK
, 0x88001);
4309 rtl_set_rfreg(hw
, path
, 0x65, RFREG_OFFSET_MASK
, 0x931d8);
4310 rtl_set_rfreg(hw
, path
, 0xef, RFREG_OFFSET_MASK
, 0x00000);
4312 rtl_set_bbreg(hw
, 0x978, 0x03FF8000, (tx_x0_rxk
[cal
])>>21&0x000007ff);
4313 rtl_set_bbreg(hw
, 0x978, 0x000007FF, (tx_y0_rxk
[cal
])>>21&0x000007ff);
4314 rtl_set_bbreg(hw
, 0x978, BIT(31), 0x1);
4315 rtl_set_bbreg(hw
, 0x97c, BIT(31), 0x0);
4316 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe); */
4317 rtl_write_dword(rtlpriv
, 0x90c, 0x00008000);
4318 rtl_write_dword(rtlpriv
, 0x984, 0x0046a911);
4320 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4321 rtl_write_dword(rtlpriv
, 0xc80, 0x38008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4322 rtl_write_dword(rtlpriv
, 0xc84, 0x18008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4323 rtl_write_dword(rtlpriv
, 0xc88, 0x02140119);
4325 rtl_write_dword(rtlpriv
, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/
4327 rtl_write_dword(rtlpriv
, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8Ï¥\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4332 rtl_write_dword(rtlpriv
, 0x980, 0xfa000000);
4333 rtl_write_dword(rtlpriv
, 0x980, 0xf8000000);
4335 mdelay(10); /* Delay 10ms */
4336 rtl_write_dword(rtlpriv
, 0xcb8, 0x00000000);
4339 iqk_ready
= rtl_get_bbreg(hw
, 0xd00, BIT(10));
4340 if ((~iqk_ready
) || (delay_count
> 20))
4348 if (delay_count
< 20) { /* If 20ms No Result, then cal_retry++ */
4349 /* ============RXIQK Check============== */
4350 rx_fail
= rtl_get_bbreg(hw
, 0xd00, BIT(11));
4352 rtl_write_dword(rtlpriv
, 0xcb8, 0x06000000);
4353 rx_x0
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4354 rtl_write_dword(rtlpriv
, 0xcb8, 0x08000000);
4355 rx_y0
[cal
] = rtl_get_bbreg(hw
, 0xd00, 0x07ff0000)<<21;
4359 rtl_set_bbreg(hw
, 0xc10, 0x000003ff, 0x200>>1);
4360 rtl_set_bbreg(hw
, 0xc10, 0x03ff0000, 0x0>>1);
4363 if (cal_retry
== 10)
4370 if (cal_retry
== 10)
4380 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4381 rtl_set_rfreg(hw
, path
, 0x65, RFREG_OFFSET_MASK
, temp_reg65
);
4389 /* FillIQK Result */
4392 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4393 "========Path_A =======\n");
4394 if (tx_average
== 0)
4397 for (i
= 0; i
< tx_average
; i
++) {
4398 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4399 "TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i
,
4400 (tx_x0_rxk
[i
])>>21&0x000007ff, i
,
4401 (tx_y0_rxk
[i
])>>21&0x000007ff);
4402 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4403 "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i
,
4404 (tx_x0
[i
])>>21&0x000007ff, i
,
4405 (tx_y0
[i
])>>21&0x000007ff);
4407 for (i
= 0; i
< tx_average
; i
++) {
4408 for (ii
= i
+1; ii
< tx_average
; ii
++) {
4409 dx
= (tx_x0
[i
]>>21) - (tx_x0
[ii
]>>21);
4410 if (dx
< 3 && dx
> -3) {
4411 dy
= (tx_y0
[i
]>>21) - (tx_y0
[ii
]>>21);
4412 if (dy
< 3 && dy
> -3) {
4413 tx_x
= ((tx_x0
[i
]>>21) + (tx_x0
[ii
]>>21))/2;
4414 tx_y
= ((tx_y0
[i
]>>21) + (tx_y0
[ii
]>>21))/2;
4425 _rtl8821ae_iqk_tx_fill_iqc(hw
, path
, tx_x
, tx_y
); /* ? */
4427 _rtl8821ae_iqk_tx_fill_iqc(hw
, path
, 0x200, 0x0);
4429 if (rx_average
== 0)
4432 for (i
= 0; i
< rx_average
; i
++)
4433 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4434 "RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i
,
4435 (rx_x0
[i
])>>21&0x000007ff, i
,
4436 (rx_y0
[i
])>>21&0x000007ff);
4437 for (i
= 0; i
< rx_average
; i
++) {
4438 for (ii
= i
+1; ii
< rx_average
; ii
++) {
4439 dx
= (rx_x0
[i
]>>21) - (rx_x0
[ii
]>>21);
4440 if (dx
< 4 && dx
> -4) {
4441 dy
= (rx_y0
[i
]>>21) - (rx_y0
[ii
]>>21);
4442 if (dy
< 4 && dy
> -4) {
4443 rx_x
= ((rx_x0
[i
]>>21) + (rx_x0
[ii
]>>21))/2;
4444 rx_y
= ((rx_y0
[i
]>>21) + (rx_y0
[ii
]>>21))/2;
4455 _rtl8821ae_iqk_rx_fill_iqc(hw
, path
, rx_x
, rx_y
);
4457 _rtl8821ae_iqk_rx_fill_iqc(hw
, path
, 0x200, 0x0);
4464 static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw
*hw
,
4465 enum radio_path path
,
4467 u32
*rf_backup
, u32 rf_reg_num
)
4469 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4472 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4473 for (i
= 0; i
< RF_REG_NUM
; i
++)
4474 rtl_set_rfreg(hw
, path
, backup_rf_reg
[i
], RFREG_OFFSET_MASK
,
4479 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4480 "RestoreRF Path A Success!!!!\n");
4487 static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw
*hw
,
4488 u32
*afe_backup
, u32
*backup_afe_reg
,
4492 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4494 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4495 /* Reload AFE Parameters */
4496 for (i
= 0; i
< afe_num
; i
++)
4497 rtl_write_dword(rtlpriv
, backup_afe_reg
[i
], afe_backup
[i
]);
4498 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4499 rtl_write_dword(rtlpriv
, 0xc80, 0x0);
4500 rtl_write_dword(rtlpriv
, 0xc84, 0x0);
4501 rtl_write_dword(rtlpriv
, 0xc88, 0x0);
4502 rtl_write_dword(rtlpriv
, 0xc8c, 0x3c000000);
4503 rtl_write_dword(rtlpriv
, 0xc90, 0x00000080);
4504 rtl_write_dword(rtlpriv
, 0xc94, 0x00000000);
4505 rtl_write_dword(rtlpriv
, 0xcc4, 0x20040000);
4506 rtl_write_dword(rtlpriv
, 0xcc8, 0x20000000);
4507 rtl_write_dword(rtlpriv
, 0xcb8, 0x0);
4508 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "RestoreAFE Success!!!!\n");
4511 static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw
*hw
,
4513 u32
*backup_macbb_reg
,
4517 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4519 rtl_set_bbreg(hw
, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4520 /* Reload MacBB Parameters */
4521 for (i
= 0; i
< macbb_num
; i
++)
4522 rtl_write_dword(rtlpriv
, backup_macbb_reg
[i
], macbb_backup
[i
]);
4523 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
, "RestoreMacBB Success!!!!\n");
4526 #undef MACBB_REG_NUM
4530 #define MACBB_REG_NUM 11
4531 #define AFE_REG_NUM 12
4532 #define RF_REG_NUM 3
4534 static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw
*hw
)
4536 u32 macbb_backup
[MACBB_REG_NUM
];
4537 u32 afe_backup
[AFE_REG_NUM
];
4538 u32 rfa_backup
[RF_REG_NUM
];
4539 u32 rfb_backup
[RF_REG_NUM
];
4540 u32 backup_macbb_reg
[MACBB_REG_NUM
] = {
4541 0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50,
4542 0xe00, 0xe50, 0x838, 0x82c
4544 u32 backup_afe_reg
[AFE_REG_NUM
] = {
4545 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
4546 0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8
4548 u32 backup_rf_reg
[RF_REG_NUM
] = {0x65, 0x8f, 0x0};
4550 _rtl8821ae_iqk_backup_macbb(hw
, macbb_backup
, backup_macbb_reg
,
4552 _rtl8821ae_iqk_backup_afe(hw
, afe_backup
, backup_afe_reg
, AFE_REG_NUM
);
4553 _rtl8821ae_iqk_backup_rf(hw
, rfa_backup
, rfb_backup
, backup_rf_reg
,
4556 _rtl8821ae_iqk_configure_mac(hw
);
4557 _rtl8821ae_iqk_tx(hw
, RF90_PATH_A
);
4558 _rtl8821ae_iqk_restore_rf(hw
, RF90_PATH_A
, backup_rf_reg
, rfa_backup
,
4561 _rtl8821ae_iqk_restore_afe(hw
, afe_backup
, backup_afe_reg
, AFE_REG_NUM
);
4562 _rtl8821ae_iqk_restore_macbb(hw
, macbb_backup
, backup_macbb_reg
,
4566 static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw
*hw
, bool main
)
4568 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4569 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */
4570 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
4571 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "\n");
4574 rtl_set_bbreg(hw
, RA_RFE_PINMUX
+ 4, BIT(29) | BIT(28), 0x1);
4576 rtl_set_bbreg(hw
, RA_RFE_PINMUX
+ 4, BIT(29) | BIT(28), 0x2);
4579 #undef IQK_ADDA_REG_NUM
4580 #undef IQK_DELAY_TIME
4582 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw
*hw
, bool b_recovery
)
4586 void rtl8812ae_do_iqk(struct ieee80211_hw
*hw
, u8 delta_thermal_index
,
4587 u8 thermal_value
, u8 threshold
)
4589 struct rtl_dm
*rtldm
= rtl_dm(rtl_priv(hw
));
4591 rtldm
->thermalvalue_iqk
= thermal_value
;
4592 rtl8812ae_phy_iq_calibrate(hw
, false);
4595 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw
*hw
, bool b_recovery
)
4597 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4598 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
4600 if (!rtlphy
->lck_inprogress
) {
4601 spin_lock(&rtlpriv
->locks
.iqk_lock
);
4602 rtlphy
->lck_inprogress
= true;
4603 spin_unlock(&rtlpriv
->locks
.iqk_lock
);
4605 _rtl8821ae_phy_iq_calibrate(hw
);
4607 spin_lock(&rtlpriv
->locks
.iqk_lock
);
4608 rtlphy
->lck_inprogress
= false;
4609 spin_unlock(&rtlpriv
->locks
.iqk_lock
);
4613 void rtl8821ae_reset_iqk_result(struct ieee80211_hw
*hw
)
4615 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4616 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
4619 RT_TRACE(rtlpriv
, COMP_IQK
, DBG_LOUD
,
4620 "rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
4621 (int)(sizeof(rtlphy
->iqk_matrix
) /
4622 sizeof(struct iqk_matrix_regs
)),
4623 IQK_MATRIX_SETTINGS_NUM
);
4625 for (i
= 0; i
< IQK_MATRIX_SETTINGS_NUM
; i
++) {
4626 rtlphy
->iqk_matrix
[i
].value
[0][0] = 0x100;
4627 rtlphy
->iqk_matrix
[i
].value
[0][2] = 0x100;
4628 rtlphy
->iqk_matrix
[i
].value
[0][4] = 0x100;
4629 rtlphy
->iqk_matrix
[i
].value
[0][6] = 0x100;
4631 rtlphy
->iqk_matrix
[i
].value
[0][1] = 0x0;
4632 rtlphy
->iqk_matrix
[i
].value
[0][3] = 0x0;
4633 rtlphy
->iqk_matrix
[i
].value
[0][5] = 0x0;
4634 rtlphy
->iqk_matrix
[i
].value
[0][7] = 0x0;
4636 rtlphy
->iqk_matrix
[i
].iqk_done
= false;
4640 void rtl8821ae_do_iqk(struct ieee80211_hw
*hw
, u8 delta_thermal_index
,
4641 u8 thermal_value
, u8 threshold
)
4643 struct rtl_dm
*rtldm
= rtl_dm(rtl_priv(hw
));
4645 rtl8821ae_reset_iqk_result(hw
);
4647 rtldm
->thermalvalue_iqk
= thermal_value
;
4648 rtl8821ae_phy_iq_calibrate(hw
, false);
4651 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw
*hw
)
4655 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw
*hw
, char delta
)
4659 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw
*hw
, bool bmain
)
4661 _rtl8821ae_phy_set_rfpath_switch(hw
, bmain
);
4664 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw
*hw
, enum io_type iotype
)
4666 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4667 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
4668 bool postprocessing
= false;
4670 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_TRACE
,
4671 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
4672 iotype
, rtlphy
->set_io_inprogress
);
4675 case IO_CMD_RESUME_DM_BY_SCAN
:
4676 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_TRACE
,
4677 "[IO CMD] Resume DM after scan.\n");
4678 postprocessing
= true;
4680 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN
:
4681 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN
:
4682 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_TRACE
,
4683 "[IO CMD] Pause DM before scan.\n");
4684 postprocessing
= true;
4687 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
4688 "switch case not process\n");
4692 if (postprocessing
&& !rtlphy
->set_io_inprogress
) {
4693 rtlphy
->set_io_inprogress
= true;
4694 rtlphy
->current_io_type
= iotype
;
4698 rtl8821ae_phy_set_io(hw
);
4699 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_TRACE
, "IO Type(%#x)\n", iotype
);
4703 static void rtl8821ae_phy_set_io(struct ieee80211_hw
*hw
)
4705 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4706 struct dig_t
*dm_digtable
= &rtlpriv
->dm_digtable
;
4707 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
4709 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_TRACE
,
4710 "--->Cmd(%#x), set_io_inprogress(%d)\n",
4711 rtlphy
->current_io_type
, rtlphy
->set_io_inprogress
);
4712 switch (rtlphy
->current_io_type
) {
4713 case IO_CMD_RESUME_DM_BY_SCAN
:
4714 if (rtlpriv
->mac80211
.opmode
== NL80211_IFTYPE_ADHOC
)
4715 _rtl8821ae_resume_tx_beacon(hw
);
4716 rtl8821ae_dm_write_dig(hw
, rtlphy
->initgain_backup
.xaagccore1
);
4717 rtl8821ae_dm_write_cck_cca_thres(hw
,
4718 rtlphy
->initgain_backup
.cca
);
4720 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN
:
4721 if (rtlpriv
->mac80211
.opmode
== NL80211_IFTYPE_ADHOC
)
4722 _rtl8821ae_stop_tx_beacon(hw
);
4723 rtlphy
->initgain_backup
.xaagccore1
= dm_digtable
->cur_igvalue
;
4724 rtl8821ae_dm_write_dig(hw
, 0x17);
4725 rtlphy
->initgain_backup
.cca
= dm_digtable
->cur_cck_cca_thres
;
4726 rtl8821ae_dm_write_cck_cca_thres(hw
, 0x40);
4728 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN
:
4731 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
4732 "switch case not process\n");
4735 rtlphy
->set_io_inprogress
= false;
4736 RT_TRACE(rtlpriv
, COMP_CMD
, DBG_TRACE
,
4737 "(%#x)\n", rtlphy
->current_io_type
);
4740 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw
*hw
)
4742 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4744 rtl_write_byte(rtlpriv
, REG_SPS0_CTRL
, 0x2b);
4745 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE3);
4746 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE2);
4747 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE3);
4748 rtl_write_byte(rtlpriv
, REG_TXPAUSE
, 0x00);
4751 static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw
*hw
,
4752 enum rf_pwrstate rfpwr_state
)
4754 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
4755 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
4756 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
4757 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
4758 bool bresult
= true;
4760 struct rtl8192_tx_ring
*ring
= NULL
;
4762 switch (rfpwr_state
) {
4764 if ((ppsc
->rfpwr_state
== ERFOFF
) &&
4765 RT_IN_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
)) {
4766 bool rtstatus
= false;
4767 u32 initializecount
= 0;
4771 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
4772 "IPS Set eRf nic enable\n");
4773 rtstatus
= rtl_ps_enable_nic(hw
);
4774 } while (!rtstatus
&& (initializecount
< 10));
4775 RT_CLEAR_PS_LEVEL(ppsc
,
4776 RT_RF_OFF_LEVL_HALT_NIC
);
4778 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
4779 "Set ERFON sleeped:%d ms\n",
4780 jiffies_to_msecs(jiffies
-
4782 last_sleep_jiffies
));
4783 ppsc
->last_awake_jiffies
= jiffies
;
4784 rtl8821ae_phy_set_rf_on(hw
);
4786 if (mac
->link_state
== MAC80211_LINKED
) {
4787 rtlpriv
->cfg
->ops
->led_control(hw
,
4790 rtlpriv
->cfg
->ops
->led_control(hw
,
4795 for (queue_id
= 0, i
= 0;
4796 queue_id
< RTL_PCI_MAX_TX_QUEUE_COUNT
;) {
4797 ring
= &pcipriv
->dev
.tx_ring
[queue_id
];
4798 if (queue_id
== BEACON_QUEUE
||
4799 skb_queue_len(&ring
->queue
) == 0) {
4803 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
4804 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
4806 skb_queue_len(&ring
->queue
));
4811 if (i
>= MAX_DOZE_WAITING_TIMES_9x
) {
4812 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
4813 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
4814 MAX_DOZE_WAITING_TIMES_9x
,
4816 skb_queue_len(&ring
->queue
));
4821 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
) {
4822 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
4823 "IPS Set eRf nic disable\n");
4824 rtl_ps_disable_nic(hw
);
4825 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
4827 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
) {
4828 rtlpriv
->cfg
->ops
->led_control(hw
,
4831 rtlpriv
->cfg
->ops
->led_control(hw
,
4837 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
4838 "switch case not process\n");
4843 ppsc
->rfpwr_state
= rfpwr_state
;
4847 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw
*hw
,
4848 enum rf_pwrstate rfpwr_state
)
4850 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
4852 bool bresult
= false;
4854 if (rfpwr_state
== ppsc
->rfpwr_state
)
4856 bresult
= _rtl8821ae_phy_set_rf_power_state(hw
, rfpwr_state
);