1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #include <linux/sched.h>
34 #include <linux/firmware.h>
35 #include <linux/etherdevice.h>
36 #include <linux/vmalloc.h>
37 #include <linux/usb.h>
38 #include <net/mac80211.h>
41 #define RF_CHANGE_BY_INIT 0
42 #define RF_CHANGE_BY_IPS BIT(28)
43 #define RF_CHANGE_BY_PS BIT(29)
44 #define RF_CHANGE_BY_HW BIT(30)
45 #define RF_CHANGE_BY_SW BIT(31)
47 #define IQK_ADDA_REG_NUM 16
48 #define IQK_MAC_REG_NUM 4
50 #define MAX_KEY_LEN 61
51 #define KEY_BUF_SIZE 5
54 /*aci: 0x00 Best Effort*/
55 /*aci: 0x01 Background*/
58 /*Max: define total number.*/
64 #define QOS_QUEUE_NUM 4
65 #define RTL_MAC80211_NUM_QUEUE 5
66 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
68 #define QBSS_LOAD_SIZE 5
69 #define MAX_WMMELE_LENGTH 64
71 #define TOTAL_CAM_ENTRY 32
73 /*slot time for 11g. */
74 #define RTL_SLOT_TIME_9 9
75 #define RTL_SLOT_TIME_20 20
77 /*related with tcp/ip. */
79 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
80 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
81 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
83 #define PROTOC_TYPE_SIZE 2
85 /*related with 802.11 frame*/
86 #define MAC80211_3ADDR_LEN 24
87 #define MAC80211_4ADDR_LEN 30
89 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
90 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
91 #define MAX_PG_GROUP 13
92 #define CHANNEL_GROUP_MAX_2G 3
93 #define CHANNEL_GROUP_IDX_5GL 3
94 #define CHANNEL_GROUP_IDX_5GM 6
95 #define CHANNEL_GROUP_IDX_5GH 9
96 #define CHANNEL_GROUP_MAX_5G 9
97 #define CHANNEL_MAX_NUMBER_2G 14
98 #define AVG_THERMAL_NUM 8
99 #define MAX_TID_COUNT 9
116 enum rt_eeprom_type
{
123 RTL_STATUS_INTERFACE_START
= 0,
127 HARDWARE_TYPE_RTL8192E
,
128 HARDWARE_TYPE_RTL8192U
,
129 HARDWARE_TYPE_RTL8192SE
,
130 HARDWARE_TYPE_RTL8192SU
,
131 HARDWARE_TYPE_RTL8192CE
,
132 HARDWARE_TYPE_RTL8192CU
,
133 HARDWARE_TYPE_RTL8192DE
,
134 HARDWARE_TYPE_RTL8192DU
,
135 HARDWARE_TYPE_RTL8723E
,
136 HARDWARE_TYPE_RTL8723U
,
142 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
143 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
144 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
145 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
146 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
147 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
148 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
149 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
150 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
151 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
152 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
153 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
154 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
155 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
156 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
157 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
158 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
159 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
160 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
161 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
162 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
163 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
164 #define IS_HARDWARE_TYPE_8723(rtlhal) \
165 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
166 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
167 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
169 #define RX_HAL_IS_CCK_RATE(_pdesc)\
170 (_pdesc->rxmcs == DESC92_RATE1M || \
171 _pdesc->rxmcs == DESC92_RATE2M || \
172 _pdesc->rxmcs == DESC92_RATE5_5M || \
173 _pdesc->rxmcs == DESC92_RATE11M)
175 enum scan_operation_backup_opt
{
198 u32 rfswitch_control
;
201 u32 rfrxiq_imbalance
;
203 u32 rftxiq_imbalance
;
206 u32 rflssi_readbackpi
;
210 IO_CMD_PAUSE_DM_BY_SCAN
= 0,
211 IO_CMD_RESUME_DM_BY_SCAN
= 1,
216 HW_VAR_MULTICAST_REG
,
220 HW_VAR_SECURITY_CONF
,
221 HW_VAR_BEACON_INTERVAL
,
223 HW_VAR_LISTEN_INTERVAL
,
236 HW_VAR_RATE_FALLBACK_CONTROL
,
237 HW_VAR_CONTENTION_WINDOW
,
242 HW_VAR_AMPDU_MIN_SPACE
,
243 HW_VAR_SHORTGI_DENSITY
,
245 HW_VAR_MCS_RATE_AVAILABLE
,
248 HW_VAR_DIS_Req_Qsize
,
249 HW_VAR_CCX_CHNL_LOAD
,
250 HW_VAR_CCX_NOISE_HISTOGRAM
,
257 HW_VAR_SET_DEV_POWER
,
267 HW_VAR_USER_CONTROL_TURBO_MODE
,
273 HW_VAR_AUTOLOAD_STATUS
,
274 HW_VAR_RF_2R_DISABLE
,
276 HW_VAR_H2C_FW_PWRMODE
,
277 HW_VAR_H2C_FW_JOINBSSRPT
,
278 HW_VAR_FW_PSMODE_STATUS
,
279 HW_VAR_1X1_RECV_COMBINE
,
280 HW_VAR_STOP_SEND_BEACON
,
285 HW_VAR_H2C_FW_UPDATE_GTK
,
288 HW_VAR_WF_IS_MAC_ADDR
,
289 HW_VAR_H2C_FW_OFFLOAD
,
292 HW_VAR_HANDLE_FW_C2H
,
293 HW_VAR_DL_FW_RSVD_PAGE
,
295 HW_VAR_HW_SEQ_ENABLE
,
300 HW_VAR_SWITCH_EPHY_WoWLAN
,
301 HW_VAR_INT_MIGRATION
,
312 enum _RT_MEDIA_STATUS
{
313 RT_MEDIA_DISCONNECT
= 0,
319 RT_CID_8187_ALPHA0
= 1,
320 RT_CID_8187_SERCOMM_PS
= 2,
321 RT_CID_8187_HW_LED
= 3,
322 RT_CID_8187_NETGEAR
= 4,
324 RT_CID_819x_CAMEO
= 6,
325 RT_CID_819x_RUNTOP
= 7,
326 RT_CID_819x_Senao
= 8,
328 RT_CID_819x_Netcore
= 10,
329 RT_CID_Nettronix
= 11,
333 RT_CID_819x_ALPHA
= 15,
334 RT_CID_819x_Sitecom
= 16,
336 RT_CID_819x_Lenovo
= 18,
337 RT_CID_819x_QMI
= 19,
338 RT_CID_819x_Edimax_Belkin
= 20,
339 RT_CID_819x_Sercomm_Belkin
= 21,
340 RT_CID_819x_CAMEO1
= 22,
341 RT_CID_819x_MSI
= 23,
342 RT_CID_819x_Acer
= 24,
344 RT_CID_819x_CLEVO
= 28,
345 RT_CID_819x_Arcadyan_Belkin
= 29,
346 RT_CID_819x_SAMSUNG
= 30,
347 RT_CID_819x_WNC_COREGA
= 31,
348 RT_CID_819x_Foxcoon
= 32,
349 RT_CID_819x_DELL
= 33,
355 HW_DESC_TX_NEXTDESC_ADDR
,
363 PRIME_CHNL_OFFSET_DONT_CARE
= 0,
364 PRIME_CHNL_OFFSET_LOWER
= 1,
365 PRIME_CHNL_OFFSET_UPPER
= 2,
375 enum ht_channel_width
{
376 HT_CHANNEL_WIDTH_20
= 0,
377 HT_CHANNEL_WIDTH_20_40
= 1,
380 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
381 Cipher Suites Encryption Algorithms */
384 WEP40_ENCRYPTION
= 1,
386 RSERVED_ENCRYPTION
= 3,
387 AESCCMP_ENCRYPTION
= 4,
388 WEP104_ENCRYPTION
= 5,
393 _HAL_STATE_START
= 1,
396 enum rtl_desc92_rate
{
397 DESC92_RATE1M
= 0x00,
398 DESC92_RATE2M
= 0x01,
399 DESC92_RATE5_5M
= 0x02,
400 DESC92_RATE11M
= 0x03,
402 DESC92_RATE6M
= 0x04,
403 DESC92_RATE9M
= 0x05,
404 DESC92_RATE12M
= 0x06,
405 DESC92_RATE18M
= 0x07,
406 DESC92_RATE24M
= 0x08,
407 DESC92_RATE36M
= 0x09,
408 DESC92_RATE48M
= 0x0a,
409 DESC92_RATE54M
= 0x0b,
411 DESC92_RATEMCS0
= 0x0c,
412 DESC92_RATEMCS1
= 0x0d,
413 DESC92_RATEMCS2
= 0x0e,
414 DESC92_RATEMCS3
= 0x0f,
415 DESC92_RATEMCS4
= 0x10,
416 DESC92_RATEMCS5
= 0x11,
417 DESC92_RATEMCS6
= 0x12,
418 DESC92_RATEMCS7
= 0x13,
419 DESC92_RATEMCS8
= 0x14,
420 DESC92_RATEMCS9
= 0x15,
421 DESC92_RATEMCS10
= 0x16,
422 DESC92_RATEMCS11
= 0x17,
423 DESC92_RATEMCS12
= 0x18,
424 DESC92_RATEMCS13
= 0x19,
425 DESC92_RATEMCS14
= 0x1a,
426 DESC92_RATEMCS15
= 0x1b,
427 DESC92_RATEMCS15_SG
= 0x1c,
428 DESC92_RATEMCS32
= 0x20,
451 EFUSE_HWSET_MAX_SIZE
,
452 EFUSE_MAX_SECTION_MAP
,
453 EFUSE_REAL_CONTENT_SIZE
,
454 EFUSE_OOB_PROTECT_BYTES_LEN
,
469 RTL_IMR_BCNDMAINT6
, /*Beacon DMA Interrupt 6 */
470 RTL_IMR_BCNDMAINT5
, /*Beacon DMA Interrupt 5 */
471 RTL_IMR_BCNDMAINT4
, /*Beacon DMA Interrupt 4 */
472 RTL_IMR_BCNDMAINT3
, /*Beacon DMA Interrupt 3 */
473 RTL_IMR_BCNDMAINT2
, /*Beacon DMA Interrupt 2 */
474 RTL_IMR_BCNDMAINT1
, /*Beacon DMA Interrupt 1 */
475 RTL_IMR_BCNDOK8
, /*Beacon Queue DMA OK Interrup 8 */
476 RTL_IMR_BCNDOK7
, /*Beacon Queue DMA OK Interrup 7 */
477 RTL_IMR_BCNDOK6
, /*Beacon Queue DMA OK Interrup 6 */
478 RTL_IMR_BCNDOK5
, /*Beacon Queue DMA OK Interrup 5 */
479 RTL_IMR_BCNDOK4
, /*Beacon Queue DMA OK Interrup 4 */
480 RTL_IMR_BCNDOK3
, /*Beacon Queue DMA OK Interrup 3 */
481 RTL_IMR_BCNDOK2
, /*Beacon Queue DMA OK Interrup 2 */
482 RTL_IMR_BCNDOK1
, /*Beacon Queue DMA OK Interrup 1 */
483 RTL_IMR_TIMEOUT2
, /*Timeout interrupt 2 */
484 RTL_IMR_TIMEOUT1
, /*Timeout interrupt 1 */
485 RTL_IMR_TXFOVW
, /*Transmit FIFO Overflow */
486 RTL_IMR_PSTIMEOUT
, /*Power save time out interrupt */
487 RTL_IMR_BcnInt
, /*Beacon DMA Interrupt 0 */
488 RTL_IMR_RXFOVW
, /*Receive FIFO Overflow */
489 RTL_IMR_RDU
, /*Receive Descriptor Unavailable */
490 RTL_IMR_ATIMEND
, /*For 92C,ATIM Window End Interrupt */
491 RTL_IMR_BDOK
, /*Beacon Queue DMA OK Interrup */
492 RTL_IMR_HIGHDOK
, /*High Queue DMA OK Interrupt */
493 RTL_IMR_COMDOK
, /*Command Queue DMA OK Interrupt*/
494 RTL_IMR_TBDOK
, /*Transmit Beacon OK interrup */
495 RTL_IMR_MGNTDOK
, /*Management Queue DMA OK Interrupt */
496 RTL_IMR_TBDER
, /*For 92C,Transmit Beacon Error Interrupt */
497 RTL_IMR_BKDOK
, /*AC_BK DMA OK Interrupt */
498 RTL_IMR_BEDOK
, /*AC_BE DMA OK Interrupt */
499 RTL_IMR_VIDOK
, /*AC_VI DMA OK Interrupt */
500 RTL_IMR_VODOK
, /*AC_VO DMA Interrupt */
501 RTL_IMR_ROK
, /*Receive DMA OK Interrupt */
502 RTL_IBSS_INT_MASKS
, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
505 /*CCK Rates, TxHT = 0 */
511 /*OFDM Rates, TxHT = 0 */
528 /*Firmware PS mode for control LPS.*/
530 FW_PS_ACTIVE_MODE
= 0,
535 FW_PS_UAPSD_WMM_MODE
= 5,
536 FW_PS_UAPSD_MODE
= 6,
538 FW_PS_WWLAN_MODE
= 8,
539 FW_PS_PM_Radio_Off
= 9,
540 FW_PS_PM_Card_Disable
= 10,
544 EACTIVE
, /*Active/Continuous access. */
545 EMAXPS
, /*Max power save mode. */
546 EFASTPS
, /*Fast power save mode. */
547 EAUTOPS
, /*Auto power save mode. */
552 LED_CTL_POWER_ON
= 1,
557 LED_CTL_SITE_SURVEY
= 6,
558 LED_CTL_POWER_OFF
= 7,
559 LED_CTL_START_TO_LINK
= 8,
560 LED_CTL_START_WPS
= 9,
561 LED_CTL_STOP_WPS
= 10,
572 /*acm implementation method.*/
574 eAcmWay0_SwAndHw
= 0,
580 SINGLEMAC_SINGLEPHY
= 0,
593 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
607 WIRELESS_MODE_UNKNOWN
= 0x00,
608 WIRELESS_MODE_A
= 0x01,
609 WIRELESS_MODE_B
= 0x02,
610 WIRELESS_MODE_G
= 0x04,
611 WIRELESS_MODE_AUTO
= 0x08,
612 WIRELESS_MODE_N_24G
= 0x10,
613 WIRELESS_MODE_N_5G
= 0x20
616 #define IS_WIRELESS_MODE_A(wirelessmode) \
617 (wirelessmode == WIRELESS_MODE_A)
618 #define IS_WIRELESS_MODE_B(wirelessmode) \
619 (wirelessmode == WIRELESS_MODE_B)
620 #define IS_WIRELESS_MODE_G(wirelessmode) \
621 (wirelessmode == WIRELESS_MODE_G)
622 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
623 (wirelessmode == WIRELESS_MODE_N_24G)
624 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
625 (wirelessmode == WIRELESS_MODE_N_5G)
627 enum ratr_table_mode
{
628 RATR_INX_WIRELESS_NGB
= 0,
629 RATR_INX_WIRELESS_NG
= 1,
630 RATR_INX_WIRELESS_NB
= 2,
631 RATR_INX_WIRELESS_N
= 3,
632 RATR_INX_WIRELESS_GB
= 4,
633 RATR_INX_WIRELESS_G
= 5,
634 RATR_INX_WIRELESS_B
= 6,
635 RATR_INX_WIRELESS_MC
= 7,
636 RATR_INX_WIRELESS_A
= 8,
639 enum rtl_link_state
{
641 MAC80211_LINKING
= 1,
643 MAC80211_LINKED_SCANNING
= 3,
660 struct octet_string
{
665 struct rtl_hdr_3addr
{
675 struct rtl_info_element
{
681 struct rtl_probe_rsp
{
682 struct rtl_hdr_3addr header
;
684 __le16 beacon_interval
;
686 /*SSID, supported rates, FH params, DS params,
687 CF params, IBSS params, TIM (if beacon), RSN */
688 struct rtl_info_element info_element
[0];
692 /*ledpin Identify how to implement this SW led.*/
695 enum rtl_led_pin ledpin
;
701 struct rtl_led sw_led0
;
702 struct rtl_led sw_led1
;
705 struct rtl_qos_parameters
{
713 struct rt_smooth_data
{
714 u32 elements
[100]; /*array to store values */
715 u32 index
; /*index to current array to store */
716 u32 total_num
; /*num of valid elements */
717 u32 total_val
; /*sum of valid elements */
720 struct false_alarm_statistics
{
722 u32 cnt_rate_illegal
;
725 u32 cnt_fast_fsync_fail
;
726 u32 cnt_sb_search_fail
;
741 struct wireless_stats
{
742 unsigned long txbytesunicast
;
743 unsigned long txbytesmulticast
;
744 unsigned long txbytesbroadcast
;
745 unsigned long rxbytesunicast
;
748 /*Correct smoothed ss in Dbm, only used
749 in driver to report real power now. */
750 long recv_signal_power
;
752 long last_sigstrength_inpercent
;
754 u32 rssi_calculate_cnt
;
756 /*Transformed, in dbm. Beautified signal
757 strength for UI, not correct. */
758 long signal_strength
;
760 u8 rx_rssi_percentage
[4];
761 u8 rx_evm_percentage
[2];
763 struct rt_smooth_data ui_rssi
;
764 struct rt_smooth_data ui_link_quality
;
767 struct rate_adaptive
{
768 u8 rate_adaptive_disabled
;
772 u32 high_rssi_thresh_for_ra
;
773 u32 high2low_rssi_thresh_for_ra
;
774 u8 low2high_rssi_thresh_for_ra40m
;
775 u32 low_rssi_thresh_for_ra40M
;
776 u8 low2high_rssi_thresh_for_ra20m
;
777 u32 low_rssi_thresh_for_ra20M
;
778 u32 upper_rssi_threshold_ratr
;
779 u32 middleupper_rssi_threshold_ratr
;
780 u32 middle_rssi_threshold_ratr
;
781 u32 middlelow_rssi_threshold_ratr
;
782 u32 low_rssi_threshold_ratr
;
783 u32 ultralow_rssi_threshold_ratr
;
784 u32 low_rssi_threshold_ratr_40m
;
785 u32 low_rssi_threshold_ratr_20m
;
788 u32 ping_rssi_thresh_for_ra
;
793 struct regd_pair_mapping
{
799 struct rtl_regulatory
{
807 struct regd_pair_mapping
*regpair
;
811 bool rfkill_state
; /*0 is off, 1 is on */
814 #define IQK_MATRIX_REG_NUM 8
815 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
816 struct iqk_matrix_regs
{
818 long value
[1][IQK_MATRIX_REG_NUM
];
821 struct phy_parameters
{
826 enum hw_param_tab_index
{
841 struct bb_reg_def phyreg_def
[4]; /*Radio A/B/C/D */
842 struct init_gain initgain_backup
;
843 enum io_type current_io_type
;
848 u8 set_bwmode_inprogress
;
849 u8 sw_chnl_inprogress
;
854 u8 set_io_inprogress
;
857 /* record for power tracking */
869 u32 reg_c04
, reg_c08
, reg_874
;
871 u32 iqk_mac_backup
[IQK_MAC_REG_NUM
];
872 u32 iqk_bb_backup
[10];
876 struct iqk_matrix_regs iqk_matrix_regsetting
[IQK_MATRIX_SETTINGS_NUM
];
882 /* MAX_PG_GROUP groups of pwr diff by rates */
883 u32 mcs_txpwrlevel_origoffset
[MAX_PG_GROUP
][16];
884 u8 default_initialgain
[4];
886 /* the current Tx power level */
888 u8 cur_ofdm24g_txpwridx
;
890 u32 rfreg_chnlval
[2];
892 u32 reg_rf3c
[2]; /* pathA / pathB */
899 struct phy_parameters hwparam_tables
[MAX_TAB
];
903 #define MAX_TID_COUNT 9
904 #define RTL_AGG_STOP 0
905 #define RTL_AGG_PROGRESS 1
906 #define RTL_AGG_START 2
907 #define RTL_AGG_OPERATIONAL 3
908 #define RTL_AGG_OFF 0
910 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
911 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
922 struct rtl_tid_data
{
924 struct rtl_ht_agg agg
;
927 struct rtl_sta_info
{
931 struct rtl_tid_data tids
[MAX_TID_COUNT
];
937 struct mutex bb_mutex
;
940 unsigned long pci_mem_end
; /*shared mem end */
941 unsigned long pci_mem_start
; /*shared mem start */
944 unsigned long pci_base_addr
; /*device I/O address */
946 void (*write8_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u8 val
);
947 void (*write16_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u16 val
);
948 void (*write32_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u32 val
);
949 void (*writeN_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
, void *buf
,
952 u8(*read8_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
953 u16(*read16_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
954 u32(*read32_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
959 u8 mac_addr
[ETH_ALEN
];
960 u8 mac80211_registered
;
966 struct ieee80211_supported_band bands
[IEEE80211_NUM_BANDS
];
967 struct ieee80211_hw
*hw
;
968 struct ieee80211_vif
*vif
;
969 enum nl80211_iftype opmode
;
971 /*Probe Beacon management */
972 struct rtl_tid_data tids
[MAX_TID_COUNT
];
973 enum rtl_link_state link_state
;
991 struct sk_buff_head skb_waitq
[MAX_TID_COUNT
];
992 u8 earlymode_threshold
;
1000 u8 mcs
[16]; /* 16 bytes mcs for HT rates. */
1001 u32 basic_rates
; /* b/g rates */
1006 u8 mode
; /* wireless mode */
1011 u8 cur_40_prime_sc_bk
;
1018 int beacon_interval
;
1021 u8 min_space_cfg
; /*For Min spacing configurations */
1023 u8 current_ampdu_factor
;
1024 u8 current_ampdu_density
;
1027 struct ieee80211_tx_queue_params edca_param
[RTL_MAC80211_NUM_QUEUE
];
1028 struct rtl_qos_parameters ac
[AC_MAX
];
1032 struct ieee80211_hw
*hw
;
1034 enum intf_type interface
;
1035 u16 hw_type
; /*92c or 92d or 92s and so on */
1038 u32 version
; /*version of chip */
1039 u8 state
; /*stop 0, start 1 */
1046 bool h2c_setinprogress
;
1049 /*Reserve page start offset except beacon in TxQ. */
1050 u8 fw_rsvdpage_startoffset
;
1053 /* FW Cmd IO related */
1056 bool set_fwcmd_inprogress
;
1057 u8 current_fwcmd_io
;
1060 bool driver_going2unload
;
1062 /*AMPDU init min space*/
1063 u8 minspace_cfg
; /*For Min spacing configurations */
1066 enum macphy_mode macphymode
;
1067 enum band_type current_bandtype
; /* 0:2.4G, 1:5G */
1068 enum band_type current_bandtypebackup
;
1069 enum band_type bandset
;
1070 /* dual MAC 0--Mac0 1--Mac1 */
1072 /* just for DualMac S3S4 */
1074 bool earlymode_enable
;
1076 bool during_mac0init_radiob
;
1077 bool during_mac1init_radioa
;
1078 bool reloadtxpowerindex
;
1079 /* True if IMR or IQK have done
1080 for 2.4G in scan progress */
1081 bool load_imrandiqk_setting_for2g
;
1083 bool disable_amsdu_8k
;
1086 struct rtl_security
{
1091 bool use_defaultkey
;
1092 /*Encryption Algorithm for Unicast Packet */
1093 enum rt_enc_alg pairwise_enc_algorithm
;
1094 /*Encryption Algorithm for Brocast/Multicast */
1095 enum rt_enc_alg group_enc_algorithm
;
1096 /*Cam Entry Bitmap */
1097 u32 hwsec_cam_bitmap
;
1098 u8 hwsec_cam_sta_addr
[TOTAL_CAM_ENTRY
][ETH_ALEN
];
1099 /*local Key buffer, indx 0 is for
1100 pairwise key 1-4 is for agoup key. */
1101 u8 key_buf
[KEY_BUF_SIZE
][MAX_KEY_LEN
];
1102 u8 key_len
[KEY_BUF_SIZE
];
1104 /*The pointer of Pairwise Key,
1105 it always points to KeyBuf[4] */
1110 /*PHY status for Dynamic Management */
1111 long entry_min_undecoratedsmoothed_pwdb
;
1112 long undecorated_smoothed_pwdb
; /*out dm */
1113 long entry_max_undecoratedsmoothed_pwdb
;
1114 bool dm_initialgain_enable
;
1115 bool dynamic_txpower_enable
;
1116 bool current_turbo_edca
;
1117 bool is_any_nonbepkts
; /*out dm */
1118 bool is_cur_rdlstate
;
1119 bool txpower_trackinginit
;
1120 bool disable_framebursting
;
1122 bool txpower_tracking
;
1124 bool rfpath_rxenable
[4];
1125 bool inform_fw_driverctrldm
;
1126 bool current_mrc_switch
;
1129 u8 thermalvalue_rxgain
;
1130 u8 thermalvalue_iqk
;
1131 u8 thermalvalue_lck
;
1134 u8 thermalvalue_avg
[AVG_THERMAL_NUM
];
1135 u8 thermalvalue_avg_index
;
1137 u8 dynamic_txhighpower_lvl
; /*Tx high power level */
1138 u8 dm_flag
; /*Indicate each dynamic mechanism's status. */
1140 u8 txpower_track_control
;
1141 bool interrupt_migration
;
1142 bool disable_tx_int
;
1147 #define EFUSE_MAX_LOGICAL_SIZE 256
1152 u16 max_physical_size
;
1154 u8 efuse_map
[2][EFUSE_MAX_LOGICAL_SIZE
];
1155 u16 efuse_usedbytes
;
1156 u8 efuse_usedpercentage
;
1157 #ifdef EFUSE_REPG_WORKAROUND
1158 bool efuse_re_pg_sec1flag
;
1159 u8 efuse_re_pg_data
[8];
1162 u8 autoload_failflag
;
1171 u16 eeprom_channelplan
;
1178 bool txpwr_fromeprom
;
1179 u8 eeprom_crystalcap
;
1181 u8 eeprom_tssi_5g
[3][2]; /* for 5GL/5GM/5GH band. */
1182 u8 eeprom_pwrlimit_ht20
[CHANNEL_GROUP_MAX
];
1183 u8 eeprom_pwrlimit_ht40
[CHANNEL_GROUP_MAX
];
1184 u8 eeprom_chnlarea_txpwr_cck
[2][CHANNEL_GROUP_MAX_2G
];
1185 u8 eeprom_chnlarea_txpwr_ht40_1s
[2][CHANNEL_GROUP_MAX
];
1186 u8 eeprom_chnlarea_txpwr_ht40_2sdiif
[2][CHANNEL_GROUP_MAX
];
1187 u8 txpwrlevel_cck
[2][CHANNEL_MAX_NUMBER_2G
];
1188 u8 txpwrlevel_ht40_1s
[2][CHANNEL_MAX_NUMBER
]; /*For HT 40MHZ pwr */
1189 u8 txpwrlevel_ht40_2s
[2][CHANNEL_MAX_NUMBER
]; /*For HT 40MHZ pwr */
1191 u8 internal_pa_5g
[2]; /* pathA / pathB */
1195 /*For power group */
1196 u8 eeprom_pwrgroup
[2][3];
1197 u8 pwrgroup_ht20
[2][CHANNEL_MAX_NUMBER
];
1198 u8 pwrgroup_ht40
[2][CHANNEL_MAX_NUMBER
];
1200 char txpwr_ht20diff
[2][CHANNEL_MAX_NUMBER
]; /*HT 20<->40 Pwr diff */
1201 /*For HT<->legacy pwr diff*/
1202 u8 txpwr_legacyhtdiff
[2][CHANNEL_MAX_NUMBER
];
1203 u8 txpwr_safetyflag
; /* Band edge enable flag */
1204 u16 eeprom_txpowerdiff
;
1205 u8 legacy_httxpowerdiff
; /* Legacy to HT rate power diff */
1206 u8 antenna_txpwdiff
[3];
1208 u8 eeprom_regulatory
;
1209 u8 eeprom_thermalmeter
;
1210 u8 thermalmeter
[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1212 u8 crystalcap
; /* CrystalCap. */
1216 u8 legacy_ht_txpowerdiff
; /*Legacy to HT rate power diff */
1217 bool apk_thermalmeterignore
;
1219 bool b1x1_recvcombine
;
1227 bool pwrdomain_protect
;
1228 bool in_powersavemode
;
1229 bool rfchange_inprogress
;
1230 bool swrf_processing
;
1234 * just for PCIE ASPM
1235 * If it supports ASPM, Offset[560h] = 0x40,
1236 * otherwise Offset[560h] = 0x00.
1240 bool support_backdoor
;
1243 enum rt_psmode dot11_psmode
; /*Power save mode configured. */
1248 /*For Fw control LPS mode */
1250 /*Record Fw PS mode status. */
1251 bool fw_current_inpsmode
;
1252 u8 reg_max_lps_awakeintvl
;
1264 /*just for PCIE ASPM */
1265 u8 const_amdpci_aspm
;
1268 enum rf_pwrstate inactive_pwrstate
;
1269 enum rf_pwrstate rfpwr_state
; /*cur power state */
1275 bool multi_buffered
;
1277 unsigned int dtim_counter
;
1278 unsigned int sleep_ms
;
1279 unsigned long last_sleep_jiffies
;
1280 unsigned long last_awake_jiffies
;
1281 unsigned long last_delaylps_stamp_jiffies
;
1282 unsigned long last_dtim
;
1283 unsigned long last_beacon
;
1284 unsigned long last_action
;
1285 unsigned long last_slept
;
1293 u16 rate
; /*in 100 kbps */
1294 u8 received_channel
;
1303 u8 signalquality
; /*in 0-100 index. */
1305 * Real power in dBm for this packet,
1306 * no beautification and aggregation.
1308 s32 recvsignalpower
;
1309 s8 rxpower
; /*in dBm Translate from PWdB */
1310 u8 signalstrength
; /*in 0-100 index. */
1314 u16 shortpreamble
:1;
1325 bool rx_is40Mhzpacket
;
1327 u8 rx_mimo_signalstrength
[4]; /*in 0~100 index */
1328 s8 rx_mimo_signalquality
[2];
1329 bool packet_matchbssid
;
1333 bool packet_beacon
; /*for rssi */
1334 char cck_adc_pwdb
[4]; /*for rx path selection */
1337 struct rt_link_detect
{
1338 u32 num_tx_in4period
[4];
1339 u32 num_rx_in4period
[4];
1341 u32 num_tx_inperiod
;
1342 u32 num_rx_inperiod
;
1345 bool higher_busytraffic
;
1346 bool higher_busyrxtraffic
;
1348 u32 tidtx_in4period
[MAX_TID_COUNT
][4];
1349 u32 tidtx_inperiod
[MAX_TID_COUNT
];
1350 bool higher_busytxtraffic
[MAX_TID_COUNT
];
1353 struct rtl_tcb_desc
{
1361 u8 rts_use_shortpreamble
:1;
1362 u8 rts_use_shortgi
:1;
1368 u8 use_shortpreamble
:1;
1369 u8 use_driver_rate
:1;
1370 u8 disable_ratefallback
:1;
1382 /* The max value by HW */
1386 struct rtl_hal_ops
{
1387 int (*init_sw_vars
) (struct ieee80211_hw
*hw
);
1388 void (*deinit_sw_vars
) (struct ieee80211_hw
*hw
);
1389 void (*read_chip_version
)(struct ieee80211_hw
*hw
);
1390 void (*read_eeprom_info
) (struct ieee80211_hw
*hw
);
1391 void (*interrupt_recognized
) (struct ieee80211_hw
*hw
,
1392 u32
*p_inta
, u32
*p_intb
);
1393 int (*hw_init
) (struct ieee80211_hw
*hw
);
1394 void (*hw_disable
) (struct ieee80211_hw
*hw
);
1395 void (*hw_suspend
) (struct ieee80211_hw
*hw
);
1396 void (*hw_resume
) (struct ieee80211_hw
*hw
);
1397 void (*enable_interrupt
) (struct ieee80211_hw
*hw
);
1398 void (*disable_interrupt
) (struct ieee80211_hw
*hw
);
1399 int (*set_network_type
) (struct ieee80211_hw
*hw
,
1400 enum nl80211_iftype type
);
1401 void (*set_chk_bssid
)(struct ieee80211_hw
*hw
,
1403 void (*set_bw_mode
) (struct ieee80211_hw
*hw
,
1404 enum nl80211_channel_type ch_type
);
1405 u8(*switch_channel
) (struct ieee80211_hw
*hw
);
1406 void (*set_qos
) (struct ieee80211_hw
*hw
, int aci
);
1407 void (*set_bcn_reg
) (struct ieee80211_hw
*hw
);
1408 void (*set_bcn_intv
) (struct ieee80211_hw
*hw
);
1409 void (*update_interrupt_mask
) (struct ieee80211_hw
*hw
,
1410 u32 add_msr
, u32 rm_msr
);
1411 void (*get_hw_reg
) (struct ieee80211_hw
*hw
, u8 variable
, u8
*val
);
1412 void (*set_hw_reg
) (struct ieee80211_hw
*hw
, u8 variable
, u8
*val
);
1413 void (*update_rate_tbl
) (struct ieee80211_hw
*hw
,
1414 struct ieee80211_sta
*sta
, u8 rssi_level
);
1415 void (*update_rate_mask
) (struct ieee80211_hw
*hw
, u8 rssi_level
);
1416 void (*fill_tx_desc
) (struct ieee80211_hw
*hw
,
1417 struct ieee80211_hdr
*hdr
, u8
*pdesc_tx
,
1418 struct ieee80211_tx_info
*info
,
1419 struct sk_buff
*skb
, u8 hw_queue
,
1420 struct rtl_tcb_desc
*ptcb_desc
);
1421 void (*fill_fake_txdesc
) (struct ieee80211_hw
*hw
, u8
*pDesc
,
1422 u32 buffer_len
, bool bIsPsPoll
);
1423 void (*fill_tx_cmddesc
) (struct ieee80211_hw
*hw
, u8
*pdesc
,
1424 bool firstseg
, bool lastseg
,
1425 struct sk_buff
*skb
);
1426 bool (*cmd_send_packet
)(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
1427 bool (*query_rx_desc
) (struct ieee80211_hw
*hw
,
1428 struct rtl_stats
*stats
,
1429 struct ieee80211_rx_status
*rx_status
,
1430 u8
*pdesc
, struct sk_buff
*skb
);
1431 void (*set_channel_access
) (struct ieee80211_hw
*hw
);
1432 bool (*radio_onoff_checking
) (struct ieee80211_hw
*hw
, u8
*valid
);
1433 void (*dm_watchdog
) (struct ieee80211_hw
*hw
);
1434 void (*scan_operation_backup
) (struct ieee80211_hw
*hw
, u8 operation
);
1435 bool (*set_rf_power_state
) (struct ieee80211_hw
*hw
,
1436 enum rf_pwrstate rfpwr_state
);
1437 void (*led_control
) (struct ieee80211_hw
*hw
,
1438 enum led_ctl_mode ledaction
);
1439 void (*set_desc
) (u8
*pdesc
, bool istx
, u8 desc_name
, u8
*val
);
1440 u32 (*get_desc
) (u8
*pdesc
, bool istx
, u8 desc_name
);
1441 void (*tx_polling
) (struct ieee80211_hw
*hw
, u8 hw_queue
);
1442 void (*enable_hw_sec
) (struct ieee80211_hw
*hw
);
1443 void (*set_key
) (struct ieee80211_hw
*hw
, u32 key_index
,
1444 u8
*macaddr
, bool is_group
, u8 enc_algo
,
1445 bool is_wepkey
, bool clear_all
);
1446 void (*init_sw_leds
) (struct ieee80211_hw
*hw
);
1447 void (*deinit_sw_leds
) (struct ieee80211_hw
*hw
);
1448 u32 (*get_bbreg
) (struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
);
1449 void (*set_bbreg
) (struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
,
1451 u32 (*get_rfreg
) (struct ieee80211_hw
*hw
, enum radio_path rfpath
,
1452 u32 regaddr
, u32 bitmask
);
1453 void (*set_rfreg
) (struct ieee80211_hw
*hw
, enum radio_path rfpath
,
1454 u32 regaddr
, u32 bitmask
, u32 data
);
1455 void (*linked_set_reg
) (struct ieee80211_hw
*hw
);
1456 bool (*phy_rf6052_config
) (struct ieee80211_hw
*hw
);
1457 void (*phy_rf6052_set_cck_txpower
) (struct ieee80211_hw
*hw
,
1459 void (*phy_rf6052_set_ofdm_txpower
) (struct ieee80211_hw
*hw
,
1460 u8
*ppowerlevel
, u8 channel
);
1461 bool (*config_bb_with_headerfile
) (struct ieee80211_hw
*hw
,
1463 bool (*config_bb_with_pgheaderfile
) (struct ieee80211_hw
*hw
,
1465 void (*phy_lc_calibrate
) (struct ieee80211_hw
*hw
, bool is2t
);
1466 void (*phy_set_bw_mode_callback
) (struct ieee80211_hw
*hw
);
1467 void (*dm_dynamic_txpower
) (struct ieee80211_hw
*hw
);
1470 struct rtl_intf_ops
{
1472 void (*read_efuse_byte
)(struct ieee80211_hw
*hw
, u16 _offset
, u8
*pbuf
);
1473 int (*adapter_start
) (struct ieee80211_hw
*hw
);
1474 void (*adapter_stop
) (struct ieee80211_hw
*hw
);
1476 int (*adapter_tx
) (struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1477 struct rtl_tcb_desc
*ptcb_desc
);
1478 void (*flush
)(struct ieee80211_hw
*hw
, bool drop
);
1479 int (*reset_trx_ring
) (struct ieee80211_hw
*hw
);
1480 bool (*waitq_insert
) (struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
1483 void (*disable_aspm
) (struct ieee80211_hw
*hw
);
1484 void (*enable_aspm
) (struct ieee80211_hw
*hw
);
1489 struct rtl_mod_params
{
1490 /* default: 0 = using hardware encryption */
1493 /* default: 0 = DBG_EMERG (0)*/
1496 /* default: 1 = using no linked power save */
1499 /* default: 1 = using linked sw power save */
1502 /* default: 1 = using linked fw power save */
1506 struct rtl_hal_usbint_cfg
{
1513 void (*usb_rx_hdl
)(struct ieee80211_hw
*, struct sk_buff
*);
1514 void (*usb_rx_segregate_hdl
)(struct ieee80211_hw
*, struct sk_buff
*,
1515 struct sk_buff_head
*);
1518 void (*usb_tx_cleanup
)(struct ieee80211_hw
*, struct sk_buff
*);
1519 int (*usb_tx_post_hdl
)(struct ieee80211_hw
*, struct urb
*,
1521 struct sk_buff
*(*usb_tx_aggregate_hdl
)(struct ieee80211_hw
*,
1522 struct sk_buff_head
*);
1524 /* endpoint mapping */
1525 int (*usb_endpoint_mapping
)(struct ieee80211_hw
*hw
);
1526 u16 (*usb_mq_to_hwq
)(__le16 fc
, u16 mac80211_queue_index
);
1529 struct rtl_hal_cfg
{
1531 bool write_readback
;
1534 struct rtl_hal_ops
*ops
;
1535 struct rtl_mod_params
*mod_params
;
1536 struct rtl_hal_usbint_cfg
*usb_interface_cfg
;
1538 /*this map used for some registers or vars
1539 defined int HAL but used in MAIN */
1540 u32 maps
[RTL_VAR_MAP_MAX
];
1546 struct mutex conf_mutex
;
1547 struct mutex ps_mutex
;
1550 spinlock_t irq_th_lock
;
1551 spinlock_t h2c_lock
;
1552 spinlock_t rf_ps_lock
;
1554 spinlock_t waitq_lock
;
1557 spinlock_t cck_and_rw_pagea_lock
;
1561 struct ieee80211_hw
*hw
;
1564 struct timer_list watchdog_timer
;
1567 struct tasklet_struct irq_tasklet
;
1568 struct tasklet_struct irq_prepare_bcn_tasklet
;
1571 struct workqueue_struct
*rtl_wq
;
1572 struct delayed_work watchdog_wq
;
1573 struct delayed_work ips_nic_off_wq
;
1576 struct delayed_work ps_work
;
1577 struct delayed_work ps_rfon_wq
;
1579 struct work_struct lps_leave_work
;
1583 u32 dbgp_type
[DBGP_TYPE_MAX
];
1584 u32 global_debuglevel
;
1585 u64 global_debugcomponents
;
1587 /* add for proc debug */
1588 struct proc_dir_entry
*proc_dir
;
1593 struct rtl_locks locks
;
1594 struct rtl_works works
;
1595 struct rtl_mac mac80211
;
1596 struct rtl_hal rtlhal
;
1597 struct rtl_regulatory regd
;
1598 struct rtl_rfkill rfkill
;
1602 struct rtl_security sec
;
1603 struct rtl_efuse efuse
;
1605 struct rtl_ps_ctl psc
;
1606 struct rate_adaptive ra
;
1607 struct wireless_stats stats
;
1608 struct rt_link_detect link_info
;
1609 struct false_alarm_statistics falsealm_cnt
;
1611 struct rtl_rate_priv
*rate_priv
;
1613 struct rtl_debug dbg
;
1616 *hal_cfg : for diff cards
1617 *intf_ops : for diff interrface usb/pcie
1619 struct rtl_hal_cfg
*cfg
;
1620 struct rtl_intf_ops
*intf_ops
;
1622 /*this var will be set by set_bit,
1623 and was used to indicate status of
1624 interface or hardware */
1625 unsigned long status
;
1627 /*This must be the last item so
1628 that it points to the data allocated
1629 beyond this structure like:
1630 rtl_pci_priv or rtl_usb_priv */
1634 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1635 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1636 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1637 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1638 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1641 /***************************************
1642 Bluetooth Co-existence Related
1643 ****************************************/
1664 enum bt_service_type
{
1671 BT_OTHER_ACTION
= 6,
1677 enum bt_radio_shared
{
1678 BT_RADIO_SHARED
= 0,
1679 BT_RADIO_INDIVIDUAL
= 1,
1682 struct bt_coexist_info
{
1684 /* EEPROM BT info. */
1685 u8 eeprom_bt_coexist
;
1687 u8 eeprom_bt_ant_num
;
1688 u8 eeprom_bt_ant_isolation
;
1689 u8 eeprom_bt_radio_shared
;
1695 u8 bt_cur_state
; /* 0:on, 1:off */
1696 u8 bt_ant_isolation
; /* 0:good, 1:bad */
1697 u8 bt_pape_ctrl
; /* 0:SW, 1:SW/HW dynamic */
1699 u8 bt_radio_shared_type
;
1700 u8 bt_rfreg_origin_1e
;
1701 u8 bt_rfreg_origin_1f
;
1709 bool bt_busy_traffic
;
1710 bool bt_traffic_mode_set
;
1711 bool bt_non_traffic_mode_set
;
1713 bool fw_coexist_all_off
;
1714 bool sw_coexist_all_off
;
1717 u8 bt_pre_rssi_state
;
1725 /****************************************
1726 mem access macro define start
1727 Call endian free function when
1728 1. Read/write packet content.
1729 2. Before write integer to IO.
1730 3. After read integer from IO.
1731 ****************************************/
1732 /* Convert little data endian to host ordering */
1733 #define EF1BYTE(_val) \
1735 #define EF2BYTE(_val) \
1737 #define EF4BYTE(_val) \
1740 /* Read data from memory */
1741 #define READEF1BYTE(_ptr) \
1742 EF1BYTE(*((u8 *)(_ptr)))
1743 /* Read le16 data from memory and convert to host ordering */
1744 #define READEF2BYTE(_ptr) \
1745 EF2BYTE(*((u16 *)(_ptr)))
1746 #define READEF4BYTE(_ptr) \
1747 EF4BYTE(*((u32 *)(_ptr)))
1749 /* Write data to memory */
1750 #define WRITEEF1BYTE(_ptr, _val) \
1751 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1752 /* Write le16 data to memory in host ordering */
1753 #define WRITEEF2BYTE(_ptr, _val) \
1754 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1755 #define WRITEEF4BYTE(_ptr, _val) \
1756 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1758 /* Create a bit mask
1760 * BIT_LEN_MASK_32(0) => 0x00000000
1761 * BIT_LEN_MASK_32(1) => 0x00000001
1762 * BIT_LEN_MASK_32(2) => 0x00000003
1763 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1765 #define BIT_LEN_MASK_32(__bitlen) \
1766 (0xFFFFFFFF >> (32 - (__bitlen)))
1767 #define BIT_LEN_MASK_16(__bitlen) \
1768 (0xFFFF >> (16 - (__bitlen)))
1769 #define BIT_LEN_MASK_8(__bitlen) \
1770 (0xFF >> (8 - (__bitlen)))
1772 /* Create an offset bit mask
1774 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1775 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1777 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1778 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1779 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1780 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1781 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1782 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1785 * Return 4-byte value in host byte ordering from
1786 * 4-byte pointer in little-endian system.
1788 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1789 (EF4BYTE(*((u32 *)(__pstart))))
1790 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1791 (EF2BYTE(*((u16 *)(__pstart))))
1792 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1793 (EF1BYTE(*((u8 *)(__pstart))))
1796 Translate subfield (continuous bits in little-endian) of 4-byte
1797 value to host byte ordering.*/
1798 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1800 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1801 BIT_LEN_MASK_32(__bitlen) \
1803 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1805 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1806 BIT_LEN_MASK_16(__bitlen) \
1808 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1810 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1811 BIT_LEN_MASK_8(__bitlen) \
1815 * Mask subfield (continuous bits in little-endian) of 4-byte value
1816 * and return the result in 4-byte value in host byte ordering.
1818 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1820 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1821 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1823 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1825 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1826 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1828 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1830 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1831 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1835 * Set subfield of little-endian 4-byte value to specified value.
1837 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1838 *((u32 *)(__pstart)) = EF4BYTE \
1840 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1841 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1843 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1844 *((u16 *)(__pstart)) = EF2BYTE \
1846 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1847 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1849 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1850 *((u8 *)(__pstart)) = EF1BYTE \
1852 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1853 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1856 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1857 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1859 /****************************************
1860 mem access macro define end
1861 ****************************************/
1863 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1865 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1866 #define RTL_WATCH_DOG_TIME 2000
1867 #define MSECS(t) msecs_to_jiffies(t)
1868 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1869 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1870 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1871 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1872 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1873 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1874 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1876 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1877 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1878 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1879 /*NIC halt, re-initialize hw parameters*/
1880 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1881 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1882 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1883 /*Always enable ASPM and Clock Req in initialization.*/
1884 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1885 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1886 #define RT_PS_LEVEL_ASPM BIT(7)
1887 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1888 #define RT_RF_LPS_DISALBE_2R BIT(30)
1889 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1890 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1891 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1892 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1893 (ppsc->cur_ps_level &= (~(_ps_flg)))
1894 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1895 (ppsc->cur_ps_level |= _ps_flg)
1897 #define container_of_dwork_rtl(x, y, z) \
1898 container_of(container_of(x, struct delayed_work, work), y, z)
1900 #define FILL_OCTET_STRING(_os, _octet, _len) \
1901 (_os).octet = (u8 *)(_octet); \
1902 (_os).length = (_len);
1904 #define CP_MACADDR(des, src) \
1905 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1906 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1907 (des)[4] = (src)[4], (des)[5] = (src)[5])
1909 static inline u8
rtl_read_byte(struct rtl_priv
*rtlpriv
, u32 addr
)
1911 return rtlpriv
->io
.read8_sync(rtlpriv
, addr
);
1914 static inline u16
rtl_read_word(struct rtl_priv
*rtlpriv
, u32 addr
)
1916 return rtlpriv
->io
.read16_sync(rtlpriv
, addr
);
1919 static inline u32
rtl_read_dword(struct rtl_priv
*rtlpriv
, u32 addr
)
1921 return rtlpriv
->io
.read32_sync(rtlpriv
, addr
);
1924 static inline void rtl_write_byte(struct rtl_priv
*rtlpriv
, u32 addr
, u8 val8
)
1926 rtlpriv
->io
.write8_async(rtlpriv
, addr
, val8
);
1928 if (rtlpriv
->cfg
->write_readback
)
1929 rtlpriv
->io
.read8_sync(rtlpriv
, addr
);
1932 static inline void rtl_write_word(struct rtl_priv
*rtlpriv
, u32 addr
, u16 val16
)
1934 rtlpriv
->io
.write16_async(rtlpriv
, addr
, val16
);
1936 if (rtlpriv
->cfg
->write_readback
)
1937 rtlpriv
->io
.read16_sync(rtlpriv
, addr
);
1940 static inline void rtl_write_dword(struct rtl_priv
*rtlpriv
,
1941 u32 addr
, u32 val32
)
1943 rtlpriv
->io
.write32_async(rtlpriv
, addr
, val32
);
1945 if (rtlpriv
->cfg
->write_readback
)
1946 rtlpriv
->io
.read32_sync(rtlpriv
, addr
);
1949 static inline u32
rtl_get_bbreg(struct ieee80211_hw
*hw
,
1950 u32 regaddr
, u32 bitmask
)
1952 return ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->get_bbreg(hw
,
1957 static inline void rtl_set_bbreg(struct ieee80211_hw
*hw
, u32 regaddr
,
1958 u32 bitmask
, u32 data
)
1960 ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->set_bbreg(hw
,
1966 static inline u32
rtl_get_rfreg(struct ieee80211_hw
*hw
,
1967 enum radio_path rfpath
, u32 regaddr
,
1970 return ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->get_rfreg(hw
,
1976 static inline void rtl_set_rfreg(struct ieee80211_hw
*hw
,
1977 enum radio_path rfpath
, u32 regaddr
,
1978 u32 bitmask
, u32 data
)
1980 ((struct rtl_priv
*)(hw
)->priv
)->cfg
->ops
->set_rfreg(hw
,
1985 static inline bool is_hal_stop(struct rtl_hal
*rtlhal
)
1987 return (_HAL_STATE_STOP
== rtlhal
->state
);
1990 static inline void set_hal_start(struct rtl_hal
*rtlhal
)
1992 rtlhal
->state
= _HAL_STATE_START
;
1995 static inline void set_hal_stop(struct rtl_hal
*rtlhal
)
1997 rtlhal
->state
= _HAL_STATE_STOP
;
2000 static inline u8
get_rf_type(struct rtl_phy
*rtlphy
)
2002 return rtlphy
->rf_type
;
2005 static inline struct ieee80211_hdr
*rtl_get_hdr(struct sk_buff
*skb
)
2007 return (struct ieee80211_hdr
*)(skb
->data
);
2010 static inline __le16
rtl_get_fc(struct sk_buff
*skb
)
2012 return rtl_get_hdr(skb
)->frame_control
;
2015 static inline u16
rtl_get_tid_h(struct ieee80211_hdr
*hdr
)
2017 return (ieee80211_get_qos_ctl(hdr
))[0] & IEEE80211_QOS_CTL_TID_MASK
;
2020 static inline u16
rtl_get_tid(struct sk_buff
*skb
)
2022 return rtl_get_tid_h(rtl_get_hdr(skb
));
2025 static inline struct ieee80211_sta
*get_sta(struct ieee80211_hw
*hw
,
2026 struct ieee80211_vif
*vif
,
2029 return ieee80211_find_sta(vif
, bssid
);