drivers/net/wireless/rtlwifi/wifi.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_WIFI_H__
  31 #define __RTL_WIFI_H__
  32
  33 #include <linux/sched.h>
  34 #include <linux/firmware.h>
  35 #include <linux/version.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/usb.h>
  39 #include <net/mac80211.h>
  40 #include "debug.h"
  41
  42 #define RF_CHANGE_BY_INIT                       0
  43 #define RF_CHANGE_BY_IPS                        BIT(28)
  44 #define RF_CHANGE_BY_PS                         BIT(29)
  45 #define RF_CHANGE_BY_HW                         BIT(30)
  46 #define RF_CHANGE_BY_SW                         BIT(31)
  47
  48 #define IQK_ADDA_REG_NUM                        16
  49 #define IQK_MAC_REG_NUM                         4
  50
  51 #define MAX_KEY_LEN                             61
  52 #define KEY_BUF_SIZE                            5
  53
  54 /* QoS related. */
  55 /*aci: 0x00     Best Effort*/
  56 /*aci: 0x01     Background*/
  57 /*aci: 0x10     Video*/
  58 /*aci: 0x11     Voice*/
  59 /*Max: define total number.*/
  60 #define AC0_BE                                  0
  61 #define AC1_BK                                  1
  62 #define AC2_VI                                  2
  63 #define AC3_VO                                  3
  64 #define AC_MAX                                  4
  65 #define QOS_QUEUE_NUM                           4
  66 #define RTL_MAC80211_NUM_QUEUE                  5
  67
  68 #define QBSS_LOAD_SIZE                          5
  69 #define MAX_WMMELE_LENGTH                       64
  70
  71 #define TOTAL_CAM_ENTRY                         32
  72
  73 /*slot time for 11g. */
  74 #define RTL_SLOT_TIME_9                         9
  75 #define RTL_SLOT_TIME_20                        20
  76
  77 /*related with tcp/ip. */
  78 /*if_ehther.h*/
  79 #define ETH_P_PAE               0x888E  /*Port Access Entity (IEEE 802.1X) */
  80 #define ETH_P_IP                0x0800  /*Internet Protocol packet */
  81 #define ETH_P_ARP               0x0806  /*Address Resolution packet */
  82 #define SNAP_SIZE               6
  83 #define PROTOC_TYPE_SIZE        2
  84
  85 /*related with 802.11 frame*/
  86 #define MAC80211_3ADDR_LEN                      24
  87 #define MAC80211_4ADDR_LEN                      30
  88
  89 #define CHANNEL_MAX_NUMBER      (14 + 24 + 21)  /* 14 is the max channel no */
  90 #define CHANNEL_GROUP_MAX       (3 + 9) /*  ch1~3, 4~9, 10~14 = three groups */
  91 #define MAX_PG_GROUP                    13
  92 #define CHANNEL_GROUP_MAX_2G            3
  93 #define CHANNEL_GROUP_IDX_5GL           3
  94 #define CHANNEL_GROUP_IDX_5GM           6
  95 #define CHANNEL_GROUP_IDX_5GH           9
  96 #define CHANNEL_GROUP_MAX_5G            9
  97 #define CHANNEL_MAX_NUMBER_2G           14
  98 #define AVG_THERMAL_NUM                 8
  99 #define MAX_TID_COUNT                   9
 100
 101 /* for early mode */
 102 #define FCS_LEN                         4
 103 #define EM_HDR_LEN                      8
 104 enum intf_type {
 105         INTF_PCI = 0,
 106         INTF_USB = 1,
 107 };
 108
 109 enum radio_path {
 110         RF90_PATH_A = 0,
 111         RF90_PATH_B = 1,
 112         RF90_PATH_C = 2,
 113         RF90_PATH_D = 3,
 114 };
 115
 116 enum rt_eeprom_type {
 117         EEPROM_93C46,
 118         EEPROM_93C56,
 119         EEPROM_BOOT_EFUSE,
 120 };
 121
 122 enum rtl_status {
 123         RTL_STATUS_INTERFACE_START = 0,
 124 };
 125
 126 enum hardware_type {
 127         HARDWARE_TYPE_RTL8192E,
 128         HARDWARE_TYPE_RTL8192U,
 129         HARDWARE_TYPE_RTL8192SE,
 130         HARDWARE_TYPE_RTL8192SU,
 131         HARDWARE_TYPE_RTL8192CE,
 132         HARDWARE_TYPE_RTL8192CU,
 133         HARDWARE_TYPE_RTL8192DE,
 134         HARDWARE_TYPE_RTL8192DU,
 135         HARDWARE_TYPE_RTL8723E,
 136         HARDWARE_TYPE_RTL8723U,
 137
 138         /* keep it last */
 139         HARDWARE_TYPE_NUM
 140 };
 141
 142 #define IS_HARDWARE_TYPE_8192SU(rtlhal)                 \
 143         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
 144 #define IS_HARDWARE_TYPE_8192SE(rtlhal)                 \
 145         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 146 #define IS_HARDWARE_TYPE_8192CE(rtlhal)                 \
 147         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
 148 #define IS_HARDWARE_TYPE_8192CU(rtlhal)                 \
 149         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
 150 #define IS_HARDWARE_TYPE_8192DE(rtlhal)                 \
 151         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
 152 #define IS_HARDWARE_TYPE_8192DU(rtlhal)                 \
 153         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
 154 #define IS_HARDWARE_TYPE_8723E(rtlhal)                  \
 155         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
 156 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 157         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 158 #define IS_HARDWARE_TYPE_8192S(rtlhal)                  \
 159 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
 160 #define IS_HARDWARE_TYPE_8192C(rtlhal)                  \
 161 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
 162 #define IS_HARDWARE_TYPE_8192D(rtlhal)                  \
 163 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
 164 #define IS_HARDWARE_TYPE_8723(rtlhal)                   \
 165 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
 166 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 167         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 168
 169 enum scan_operation_backup_opt {
 170         SCAN_OPT_BACKUP = 0,
 171         SCAN_OPT_RESTORE,
 172         SCAN_OPT_MAX
 173 };
 174
 175 /*RF state.*/
 176 enum rf_pwrstate {
 177         ERFON,
 178         ERFSLEEP,
 179         ERFOFF
 180 };
 181
 182 struct bb_reg_def {
 183         u32 rfintfs;
 184         u32 rfintfi;
 185         u32 rfintfo;
 186         u32 rfintfe;
 187         u32 rf3wire_offset;
 188         u32 rflssi_select;
 189         u32 rftxgain_stage;
 190         u32 rfhssi_para1;
 191         u32 rfhssi_para2;
 192         u32 rfswitch_control;
 193         u32 rfagc_control1;
 194         u32 rfagc_control2;
 195         u32 rfrxiq_imbalance;
 196         u32 rfrx_afe;
 197         u32 rftxiq_imbalance;
 198         u32 rftx_afe;
 199         u32 rflssi_readback;
 200         u32 rflssi_readbackpi;
 201 };
 202
 203 enum io_type {
 204         IO_CMD_PAUSE_DM_BY_SCAN = 0,
 205         IO_CMD_RESUME_DM_BY_SCAN = 1,
 206 };
 207
 208 enum hw_variables {
 209         HW_VAR_ETHER_ADDR,
 210         HW_VAR_MULTICAST_REG,
 211         HW_VAR_BASIC_RATE,
 212         HW_VAR_BSSID,
 213         HW_VAR_MEDIA_STATUS,
 214         HW_VAR_SECURITY_CONF,
 215         HW_VAR_BEACON_INTERVAL,
 216         HW_VAR_ATIM_WINDOW,
 217         HW_VAR_LISTEN_INTERVAL,
 218         HW_VAR_CS_COUNTER,
 219         HW_VAR_DEFAULTKEY0,
 220         HW_VAR_DEFAULTKEY1,
 221         HW_VAR_DEFAULTKEY2,
 222         HW_VAR_DEFAULTKEY3,
 223         HW_VAR_SIFS,
 224         HW_VAR_DIFS,
 225         HW_VAR_EIFS,
 226         HW_VAR_SLOT_TIME,
 227         HW_VAR_ACK_PREAMBLE,
 228         HW_VAR_CW_CONFIG,
 229         HW_VAR_CW_VALUES,
 230         HW_VAR_RATE_FALLBACK_CONTROL,
 231         HW_VAR_CONTENTION_WINDOW,
 232         HW_VAR_RETRY_COUNT,
 233         HW_VAR_TR_SWITCH,
 234         HW_VAR_COMMAND,
 235         HW_VAR_WPA_CONFIG,
 236         HW_VAR_AMPDU_MIN_SPACE,
 237         HW_VAR_SHORTGI_DENSITY,
 238         HW_VAR_AMPDU_FACTOR,
 239         HW_VAR_MCS_RATE_AVAILABLE,
 240         HW_VAR_AC_PARAM,
 241         HW_VAR_ACM_CTRL,
 242         HW_VAR_DIS_Req_Qsize,
 243         HW_VAR_CCX_CHNL_LOAD,
 244         HW_VAR_CCX_NOISE_HISTOGRAM,
 245         HW_VAR_CCX_CLM_NHM,
 246         HW_VAR_TxOPLimit,
 247         HW_VAR_TURBO_MODE,
 248         HW_VAR_RF_STATE,
 249         HW_VAR_RF_OFF_BY_HW,
 250         HW_VAR_BUS_SPEED,
 251         HW_VAR_SET_DEV_POWER,
 252
 253         HW_VAR_RCR,
 254         HW_VAR_RATR_0,
 255         HW_VAR_RRSR,
 256         HW_VAR_CPU_RST,
 257         HW_VAR_CECHK_BSSID,
 258         HW_VAR_LBK_MODE,
 259         HW_VAR_AES_11N_FIX,
 260         HW_VAR_USB_RX_AGGR,
 261         HW_VAR_USER_CONTROL_TURBO_MODE,
 262         HW_VAR_RETRY_LIMIT,
 263         HW_VAR_INIT_TX_RATE,
 264         HW_VAR_TX_RATE_REG,
 265         HW_VAR_EFUSE_USAGE,
 266         HW_VAR_EFUSE_BYTES,
 267         HW_VAR_AUTOLOAD_STATUS,
 268         HW_VAR_RF_2R_DISABLE,
 269         HW_VAR_SET_RPWM,
 270         HW_VAR_H2C_FW_PWRMODE,
 271         HW_VAR_H2C_FW_JOINBSSRPT,
 272         HW_VAR_FW_PSMODE_STATUS,
 273         HW_VAR_1X1_RECV_COMBINE,
 274         HW_VAR_STOP_SEND_BEACON,
 275         HW_VAR_TSF_TIMER,
 276         HW_VAR_IO_CMD,
 277
 278         HW_VAR_RF_RECOVERY,
 279         HW_VAR_H2C_FW_UPDATE_GTK,
 280         HW_VAR_WF_MASK,
 281         HW_VAR_WF_CRC,
 282         HW_VAR_WF_IS_MAC_ADDR,
 283         HW_VAR_H2C_FW_OFFLOAD,
 284         HW_VAR_RESET_WFCRC,
 285
 286         HW_VAR_HANDLE_FW_C2H,
 287         HW_VAR_DL_FW_RSVD_PAGE,
 288         HW_VAR_AID,
 289         HW_VAR_HW_SEQ_ENABLE,
 290         HW_VAR_CORRECT_TSF,
 291         HW_VAR_BCN_VALID,
 292         HW_VAR_FWLPS_RF_ON,
 293         HW_VAR_DUAL_TSF_RST,
 294         HW_VAR_SWITCH_EPHY_WoWLAN,
 295         HW_VAR_INT_MIGRATION,
 296         HW_VAR_INT_AC,
 297         HW_VAR_RF_TIMING,
 298
 299         HW_VAR_MRC,
 300
 301         HW_VAR_MGT_FILTER,
 302         HW_VAR_CTRL_FILTER,
 303         HW_VAR_DATA_FILTER,
 304 };
 305
 306 #define HWSET_MAX_SIZE                          128
 307 #define EFUSE_MAX_SECTION                       16
 308
 309 enum _RT_MEDIA_STATUS {
 310         RT_MEDIA_DISCONNECT = 0,
 311         RT_MEDIA_CONNECT = 1
 312 };
 313
 314 enum rt_oem_id {
 315         RT_CID_DEFAULT = 0,
 316         RT_CID_8187_ALPHA0 = 1,
 317         RT_CID_8187_SERCOMM_PS = 2,
 318         RT_CID_8187_HW_LED = 3,
 319         RT_CID_8187_NETGEAR = 4,
 320         RT_CID_WHQL = 5,
 321         RT_CID_819x_CAMEO = 6,
 322         RT_CID_819x_RUNTOP = 7,
 323         RT_CID_819x_Senao = 8,
 324         RT_CID_TOSHIBA = 9,
 325         RT_CID_819x_Netcore = 10,
 326         RT_CID_Nettronix = 11,
 327         RT_CID_DLINK = 12,
 328         RT_CID_PRONET = 13,
 329         RT_CID_COREGA = 14,
 330         RT_CID_819x_ALPHA = 15,
 331         RT_CID_819x_Sitecom = 16,
 332         RT_CID_CCX = 17,
 333         RT_CID_819x_Lenovo = 18,
 334         RT_CID_819x_QMI = 19,
 335         RT_CID_819x_Edimax_Belkin = 20,
 336         RT_CID_819x_Sercomm_Belkin = 21,
 337         RT_CID_819x_CAMEO1 = 22,
 338         RT_CID_819x_MSI = 23,
 339         RT_CID_819x_Acer = 24,
 340         RT_CID_819x_HP = 27,
 341         RT_CID_819x_CLEVO = 28,
 342         RT_CID_819x_Arcadyan_Belkin = 29,
 343         RT_CID_819x_SAMSUNG = 30,
 344         RT_CID_819x_WNC_COREGA = 31,
 345         RT_CID_819x_Foxcoon = 32,
 346         RT_CID_819x_DELL = 33,
 347 };
 348
 349 enum hw_descs {
 350         HW_DESC_OWN,
 351         HW_DESC_RXOWN,
 352         HW_DESC_TX_NEXTDESC_ADDR,
 353         HW_DESC_TXBUFF_ADDR,
 354         HW_DESC_RXBUFF_ADDR,
 355         HW_DESC_RXPKT_LEN,
 356         HW_DESC_RXERO,
 357 };
 358
 359 enum prime_sc {
 360         PRIME_CHNL_OFFSET_DONT_CARE = 0,
 361         PRIME_CHNL_OFFSET_LOWER = 1,
 362         PRIME_CHNL_OFFSET_UPPER = 2,
 363 };
 364
 365 enum rf_type {
 366         RF_1T1R = 0,
 367         RF_1T2R = 1,
 368         RF_2T2R = 2,
 369         RF_2T2R_GREEN = 3,
 370 };
 371
 372 enum ht_channel_width {
 373         HT_CHANNEL_WIDTH_20 = 0,
 374         HT_CHANNEL_WIDTH_20_40 = 1,
 375 };
 376
 377 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
 378 Cipher Suites Encryption Algorithms */
 379 enum rt_enc_alg {
 380         NO_ENCRYPTION = 0,
 381         WEP40_ENCRYPTION = 1,
 382         TKIP_ENCRYPTION = 2,
 383         RSERVED_ENCRYPTION = 3,
 384         AESCCMP_ENCRYPTION = 4,
 385         WEP104_ENCRYPTION = 5,
 386 };
 387
 388 enum rtl_hal_state {
 389         _HAL_STATE_STOP = 0,
 390         _HAL_STATE_START = 1,
 391 };
 392
 393 enum rtl_var_map {
 394         /*reg map */
 395         SYS_ISO_CTRL = 0,
 396         SYS_FUNC_EN,
 397         SYS_CLK,
 398         MAC_RCR_AM,
 399         MAC_RCR_AB,
 400         MAC_RCR_ACRC32,
 401         MAC_RCR_ACF,
 402         MAC_RCR_AAP,
 403
 404         /*efuse map */
 405         EFUSE_TEST,
 406         EFUSE_CTRL,
 407         EFUSE_CLK,
 408         EFUSE_CLK_CTRL,
 409         EFUSE_PWC_EV12V,
 410         EFUSE_FEN_ELDR,
 411         EFUSE_LOADER_CLK_EN,
 412         EFUSE_ANA8M,
 413         EFUSE_HWSET_MAX_SIZE,
 414         EFUSE_MAX_SECTION_MAP,
 415         EFUSE_REAL_CONTENT_SIZE,
 416
 417         /*CAM map */
 418         RWCAM,
 419         WCAMI,
 420         RCAMO,
 421         CAMDBG,
 422         SECR,
 423         SEC_CAM_NONE,
 424         SEC_CAM_WEP40,
 425         SEC_CAM_TKIP,
 426         SEC_CAM_AES,
 427         SEC_CAM_WEP104,
 428
 429         /*IMR map */
 430         RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
 431         RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
 432         RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
 433         RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
 434         RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
 435         RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
 436         RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrup 8 */
 437         RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrup 7 */
 438         RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrup 6 */
 439         RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrup 5 */
 440         RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrup 4 */
 441         RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrup 3 */
 442         RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrup 2 */
 443         RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrup 1 */
 444         RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
 445         RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
 446         RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
 447         RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
 448         RTL_IMR_BcnInt,         /*Beacon DMA Interrupt 0 */
 449         RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
 450         RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
 451         RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
 452         RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrup */
 453         RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
 454         RTL_IMR_COMDOK,         /*Command Queue DMA OK Interrupt*/
 455         RTL_IMR_TBDOK,          /*Transmit Beacon OK interrup */
 456         RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
 457         RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
 458         RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
 459         RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
 460         RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
 461         RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
 462         RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
 463         RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
 464                                  * RTL_IMR_TBDER) */
 465
 466         /*CCK Rates, TxHT = 0 */
 467         RTL_RC_CCK_RATE1M,
 468         RTL_RC_CCK_RATE2M,
 469         RTL_RC_CCK_RATE5_5M,
 470         RTL_RC_CCK_RATE11M,
 471
 472         /*OFDM Rates, TxHT = 0 */
 473         RTL_RC_OFDM_RATE6M,
 474         RTL_RC_OFDM_RATE9M,
 475         RTL_RC_OFDM_RATE12M,
 476         RTL_RC_OFDM_RATE18M,
 477         RTL_RC_OFDM_RATE24M,
 478         RTL_RC_OFDM_RATE36M,
 479         RTL_RC_OFDM_RATE48M,
 480         RTL_RC_OFDM_RATE54M,
 481
 482         RTL_RC_HT_RATEMCS7,
 483         RTL_RC_HT_RATEMCS15,
 484
 485         /*keep it last */
 486         RTL_VAR_MAP_MAX,
 487 };
 488
 489 /*Firmware PS mode for control LPS.*/
 490 enum _fw_ps_mode {
 491         FW_PS_ACTIVE_MODE = 0,
 492         FW_PS_MIN_MODE = 1,
 493         FW_PS_MAX_MODE = 2,
 494         FW_PS_DTIM_MODE = 3,
 495         FW_PS_VOIP_MODE = 4,
 496         FW_PS_UAPSD_WMM_MODE = 5,
 497         FW_PS_UAPSD_MODE = 6,
 498         FW_PS_IBSS_MODE = 7,
 499         FW_PS_WWLAN_MODE = 8,
 500         FW_PS_PM_Radio_Off = 9,
 501         FW_PS_PM_Card_Disable = 10,
 502 };
 503
 504 enum rt_psmode {
 505         EACTIVE,                /*Active/Continuous access. */
 506         EMAXPS,                 /*Max power save mode. */
 507         EFASTPS,                /*Fast power save mode. */
 508         EAUTOPS,                /*Auto power save mode. */
 509 };
 510
 511 /*LED related.*/
 512 enum led_ctl_mode {
 513         LED_CTL_POWER_ON = 1,
 514         LED_CTL_LINK = 2,
 515         LED_CTL_NO_LINK = 3,
 516         LED_CTL_TX = 4,
 517         LED_CTL_RX = 5,
 518         LED_CTL_SITE_SURVEY = 6,
 519         LED_CTL_POWER_OFF = 7,
 520         LED_CTL_START_TO_LINK = 8,
 521         LED_CTL_START_WPS = 9,
 522         LED_CTL_STOP_WPS = 10,
 523 };
 524
 525 enum rtl_led_pin {
 526         LED_PIN_GPIO0,
 527         LED_PIN_LED0,
 528         LED_PIN_LED1,
 529         LED_PIN_LED2
 530 };
 531
 532 /*QoS related.*/
 533 /*acm implementation method.*/
 534 enum acm_method {
 535         eAcmWay0_SwAndHw = 0,
 536         eAcmWay1_HW = 1,
 537         eAcmWay2_SW = 2,
 538 };
 539
 540 enum macphy_mode {
 541         SINGLEMAC_SINGLEPHY = 0,
 542         DUALMAC_DUALPHY,
 543         DUALMAC_SINGLEPHY,
 544 };
 545
 546 enum band_type {
 547         BAND_ON_2_4G = 0,
 548         BAND_ON_5G,
 549         BAND_ON_BOTH,
 550         BANDMAX
 551 };
 552
 553 /*aci/aifsn Field.
 554 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
 555 union aci_aifsn {
 556         u8 char_data;
 557
 558         struct {
 559                 u8 aifsn:4;
 560                 u8 acm:1;
 561                 u8 aci:2;
 562                 u8 reserved:1;
 563         } f;                    /* Field */
 564 };
 565
 566 /*mlme related.*/
 567 enum wireless_mode {
 568         WIRELESS_MODE_UNKNOWN = 0x00,
 569         WIRELESS_MODE_A = 0x01,
 570         WIRELESS_MODE_B = 0x02,
 571         WIRELESS_MODE_G = 0x04,
 572         WIRELESS_MODE_AUTO = 0x08,
 573         WIRELESS_MODE_N_24G = 0x10,
 574         WIRELESS_MODE_N_5G = 0x20
 575 };
 576
 577 #define IS_WIRELESS_MODE_A(wirelessmode)        \
 578         (wirelessmode == WIRELESS_MODE_A)
 579 #define IS_WIRELESS_MODE_B(wirelessmode)        \
 580         (wirelessmode == WIRELESS_MODE_B)
 581 #define IS_WIRELESS_MODE_G(wirelessmode)        \
 582         (wirelessmode == WIRELESS_MODE_G)
 583 #define IS_WIRELESS_MODE_N_24G(wirelessmode)    \
 584         (wirelessmode == WIRELESS_MODE_N_24G)
 585 #define IS_WIRELESS_MODE_N_5G(wirelessmode)     \
 586         (wirelessmode == WIRELESS_MODE_N_5G)
 587
 588 enum ratr_table_mode {
 589         RATR_INX_WIRELESS_NGB = 0,
 590         RATR_INX_WIRELESS_NG = 1,
 591         RATR_INX_WIRELESS_NB = 2,
 592         RATR_INX_WIRELESS_N = 3,
 593         RATR_INX_WIRELESS_GB = 4,
 594         RATR_INX_WIRELESS_G = 5,
 595         RATR_INX_WIRELESS_B = 6,
 596         RATR_INX_WIRELESS_MC = 7,
 597         RATR_INX_WIRELESS_A = 8,
 598 };
 599
 600 enum rtl_link_state {
 601         MAC80211_NOLINK = 0,
 602         MAC80211_LINKING = 1,
 603         MAC80211_LINKED = 2,
 604         MAC80211_LINKED_SCANNING = 3,
 605 };
 606
 607 enum act_category {
 608         ACT_CAT_QOS = 1,
 609         ACT_CAT_DLS = 2,
 610         ACT_CAT_BA = 3,
 611         ACT_CAT_HT = 7,
 612         ACT_CAT_WMM = 17,
 613 };
 614
 615 enum ba_action {
 616         ACT_ADDBAREQ = 0,
 617         ACT_ADDBARSP = 1,
 618         ACT_DELBA = 2,
 619 };
 620
 621 struct octet_string {
 622         u8 *octet;
 623         u16 length;
 624 };
 625
 626 struct rtl_hdr_3addr {
 627         __le16 frame_ctl;
 628         __le16 duration_id;
 629         u8 addr1[ETH_ALEN];
 630         u8 addr2[ETH_ALEN];
 631         u8 addr3[ETH_ALEN];
 632         __le16 seq_ctl;
 633         u8 payload[0];
 634 } __packed;
 635
 636 struct rtl_info_element {
 637         u8 id;
 638         u8 len;
 639         u8 data[0];
 640 } __packed;
 641
 642 struct rtl_probe_rsp {
 643         struct rtl_hdr_3addr header;
 644         u32 time_stamp[2];
 645         __le16 beacon_interval;
 646         __le16 capability;
 647         /*SSID, supported rates, FH params, DS params,
 648            CF params, IBSS params, TIM (if beacon), RSN */
 649         struct rtl_info_element info_element[0];
 650 } __packed;
 651
 652 /*LED related.*/
 653 /*ledpin Identify how to implement this SW led.*/
 654 struct rtl_led {
 655         void *hw;
 656         enum rtl_led_pin ledpin;
 657         bool ledon;
 658 };
 659
 660 struct rtl_led_ctl {
 661         bool led_opendrain;
 662         struct rtl_led sw_led0;
 663         struct rtl_led sw_led1;
 664 };
 665
 666 struct rtl_qos_parameters {
 667         __le16 cw_min;
 668         __le16 cw_max;
 669         u8 aifs;
 670         u8 flag;
 671         __le16 tx_op;
 672 } __packed;
 673
 674 struct rt_smooth_data {
 675         u32 elements[100];      /*array to store values */
 676         u32 index;              /*index to current array to store */
 677         u32 total_num;          /*num of valid elements */
 678         u32 total_val;          /*sum of valid elements */
 679 };
 680
 681 struct false_alarm_statistics {
 682         u32 cnt_parity_fail;
 683         u32 cnt_rate_illegal;
 684         u32 cnt_crc8_fail;
 685         u32 cnt_mcs_fail;
 686         u32 cnt_fast_fsync_fail;
 687         u32 cnt_sb_search_fail;
 688         u32 cnt_ofdm_fail;
 689         u32 cnt_cck_fail;
 690         u32 cnt_all;
 691 };
 692
 693 struct init_gain {
 694         u8 xaagccore1;
 695         u8 xbagccore1;
 696         u8 xcagccore1;
 697         u8 xdagccore1;
 698         u8 cca;
 699
 700 };
 701
 702 struct wireless_stats {
 703         unsigned long txbytesunicast;
 704         unsigned long txbytesmulticast;
 705         unsigned long txbytesbroadcast;
 706         unsigned long rxbytesunicast;
 707
 708         long rx_snr_db[4];
 709         /*Correct smoothed ss in Dbm, only used
 710            in driver to report real power now. */
 711         long recv_signal_power;
 712         long signal_quality;
 713         long last_sigstrength_inpercent;
 714
 715         u32 rssi_calculate_cnt;
 716
 717         /*Transformed, in dbm. Beautified signal
 718            strength for UI, not correct. */
 719         long signal_strength;
 720
 721         u8 rx_rssi_percentage[4];
 722         u8 rx_evm_percentage[2];
 723
 724         struct rt_smooth_data ui_rssi;
 725         struct rt_smooth_data ui_link_quality;
 726 };
 727
 728 struct rate_adaptive {
 729         u8 rate_adaptive_disabled;
 730         u8 ratr_state;
 731         u16 reserve;
 732
 733         u32 high_rssi_thresh_for_ra;
 734         u32 high2low_rssi_thresh_for_ra;
 735         u8 low2high_rssi_thresh_for_ra40m;
 736         u32 low_rssi_thresh_for_ra40M;
 737         u8 low2high_rssi_thresh_for_ra20m;
 738         u32 low_rssi_thresh_for_ra20M;
 739         u32 upper_rssi_threshold_ratr;
 740         u32 middleupper_rssi_threshold_ratr;
 741         u32 middle_rssi_threshold_ratr;
 742         u32 middlelow_rssi_threshold_ratr;
 743         u32 low_rssi_threshold_ratr;
 744         u32 ultralow_rssi_threshold_ratr;
 745         u32 low_rssi_threshold_ratr_40m;
 746         u32 low_rssi_threshold_ratr_20m;
 747         u8 ping_rssi_enable;
 748         u32 ping_rssi_ratr;
 749         u32 ping_rssi_thresh_for_ra;
 750         u32 last_ratr;
 751         u8 pre_ratr_state;
 752 };
 753
 754 struct regd_pair_mapping {
 755         u16 reg_dmnenum;
 756         u16 reg_5ghz_ctl;
 757         u16 reg_2ghz_ctl;
 758 };
 759
 760 struct rtl_regulatory {
 761         char alpha2[2];
 762         u16 country_code;
 763         u16 max_power_level;
 764         u32 tp_scale;
 765         u16 current_rd;
 766         u16 current_rd_ext;
 767         int16_t power_limit;
 768         struct regd_pair_mapping *regpair;
 769 };
 770
 771 struct rtl_rfkill {
 772         bool rfkill_state;      /*0 is off, 1 is on */
 773 };
 774
 775 #define IQK_MATRIX_REG_NUM      8
 776 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
 777 struct iqk_matrix_regs {
 778         bool iqk_done;
 779         long value[1][IQK_MATRIX_REG_NUM];
 780 };
 781
 782 struct phy_parameters {
 783         u16 length;
 784         u32 *pdata;
 785 };
 786
 787 enum hw_param_tab_index {
 788         PHY_REG_2T,
 789         PHY_REG_1T,
 790         PHY_REG_PG,
 791         RADIOA_2T,
 792         RADIOB_2T,
 793         RADIOA_1T,
 794         RADIOB_1T,
 795         MAC_REG,
 796         AGCTAB_2T,
 797         AGCTAB_1T,
 798         MAX_TAB
 799 };
 800
 801 struct rtl_phy {
 802         struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
 803         struct init_gain initgain_backup;
 804         enum io_type current_io_type;
 805
 806         u8 rf_mode;
 807         u8 rf_type;
 808         u8 current_chan_bw;
 809         u8 set_bwmode_inprogress;
 810         u8 sw_chnl_inprogress;
 811         u8 sw_chnl_stage;
 812         u8 sw_chnl_step;
 813         u8 current_channel;
 814         u8 h2c_box_num;
 815         u8 set_io_inprogress;
 816         u8 lck_inprogress;
 817
 818         /* record for power tracking */
 819         s32 reg_e94;
 820         s32 reg_e9c;
 821         s32 reg_ea4;
 822         s32 reg_eac;
 823         s32 reg_eb4;
 824         s32 reg_ebc;
 825         s32 reg_ec4;
 826         s32 reg_ecc;
 827         u8 rfpienable;
 828         u8 reserve_0;
 829         u16 reserve_1;
 830         u32 reg_c04, reg_c08, reg_874;
 831         u32 adda_backup[16];
 832         u32 iqk_mac_backup[IQK_MAC_REG_NUM];
 833         u32 iqk_bb_backup[10];
 834
 835         /* Dual mac */
 836         bool need_iqk;
 837         struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
 838
 839         bool rfpi_enable;
 840
 841         u8 pwrgroup_cnt;
 842         u8 cck_high_power;
 843         /* MAX_PG_GROUP groups of pwr diff by rates */
 844         u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
 845         u8 default_initialgain[4];
 846
 847         /* the current Tx power level */
 848         u8 cur_cck_txpwridx;
 849         u8 cur_ofdm24g_txpwridx;
 850
 851         u32 rfreg_chnlval[2];
 852         bool apk_done;
 853         u32 reg_rf3c[2];        /* pathA / pathB  */
 854
 855         /* bfsync */
 856         u8 framesync;
 857         u32 framesync_c34;
 858
 859         u8 num_total_rfpath;
 860         struct phy_parameters hwparam_tables[MAX_TAB];
 861         u16 rf_pathmap;
 862 };
 863
 864 #define MAX_TID_COUNT                           9
 865 #define RTL_AGG_STOP                            0
 866 #define RTL_AGG_PROGRESS                        1
 867 #define RTL_AGG_START                           2
 868 #define RTL_AGG_OPERATIONAL                     3
 869 #define RTL_AGG_OFF                             0
 870 #define RTL_AGG_ON                              1
 871 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
 872 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
 873
 874 struct rtl_ht_agg {
 875         u16 txq_id;
 876         u16 wait_for_ba;
 877         u16 start_idx;
 878         u64 bitmap;
 879         u32 rate_n_flags;
 880         u8 agg_state;
 881 };
 882
 883 struct rtl_tid_data {
 884         u16 seq_number;
 885         struct rtl_ht_agg agg;
 886 };
 887
 888 struct rtl_sta_info {
 889         u8 ratr_index;
 890         u8 wireless_mode;
 891         u8 mimo_ps;
 892         struct rtl_tid_data tids[MAX_TID_COUNT];
 893 } __packed;
 894
 895 struct rtl_priv;
 896 struct rtl_io {
 897         struct device *dev;
 898         struct mutex bb_mutex;
 899
 900         /*PCI MEM map */
 901         unsigned long pci_mem_end;      /*shared mem end        */
 902         unsigned long pci_mem_start;    /*shared mem start */
 903
 904         /*PCI IO map */
 905         unsigned long pci_base_addr;    /*device I/O address */
 906
 907         void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
 908         void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
 909         void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
 910         int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
 911                              u8 *pdata);
 912
 913         u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
 914         u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
 915         u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
 916         int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
 917                             u8 *pdata);
 918
 919 };
 920
 921 struct rtl_mac {
 922         u8 mac_addr[ETH_ALEN];
 923         u8 mac80211_registered;
 924         u8 beacon_enabled;
 925
 926         u32 tx_ss_num;
 927         u32 rx_ss_num;
 928
 929         struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
 930         struct ieee80211_hw *hw;
 931         struct ieee80211_vif *vif;
 932         enum nl80211_iftype opmode;
 933
 934         /*Probe Beacon management */
 935         struct rtl_tid_data tids[MAX_TID_COUNT];
 936         enum rtl_link_state link_state;
 937
 938         int n_channels;
 939         int n_bitrates;
 940
 941         bool offchan_deley;
 942
 943         /*filters */
 944         u32 rx_conf;
 945         u16 rx_mgt_filter;
 946         u16 rx_ctrl_filter;
 947         u16 rx_data_filter;
 948
 949         bool act_scanning;
 950         u8 cnt_after_linked;
 951
 952         /* early mode */
 953         /* skb wait queue */
 954         struct sk_buff_head skb_waitq[MAX_TID_COUNT];
 955         u8 earlymode_threshold;
 956
 957         /*RDG*/
 958         bool rdg_en;
 959
 960         /*AP*/
 961         u8 bssid[6];
 962         u32 vendor;
 963         u8 mcs[16];     /* 16 bytes mcs for HT rates. */
 964         u32 basic_rates; /* b/g rates */
 965         u8 ht_enable;
 966         u8 sgi_40;
 967         u8 sgi_20;
 968         u8 bw_40;
 969         u8 mode;                /* wireless mode */
 970         u8 slot_time;
 971         u8 short_preamble;
 972         u8 use_cts_protect;
 973         u8 cur_40_prime_sc;
 974         u8 cur_40_prime_sc_bk;
 975         u64 tsf;
 976         u8 retry_short;
 977         u8 retry_long;
 978         u16 assoc_id;
 979
 980         /*IBSS*/
 981         int beacon_interval;
 982
 983         /*AMPDU*/
 984         u8 min_space_cfg;       /*For Min spacing configurations */
 985         u8 max_mss_density;
 986         u8 current_ampdu_factor;
 987         u8 current_ampdu_density;
 988
 989         /*QOS & EDCA */
 990         struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
 991         struct rtl_qos_parameters ac[AC_MAX];
 992 };
 993
 994 struct rtl_hal {
 995         struct ieee80211_hw *hw;
 996
 997         enum intf_type interface;
 998         u16 hw_type;            /*92c or 92d or 92s and so on */
 999         u8 ic_class;
1000         u8 oem_id;
1001         u32 version;            /*version of chip */
1002         u8 state;               /*stop 0, start 1 */
1003
1004         /*firmware */
1005         u32 fwsize;
1006         u8 *pfirmware;
1007         u16 fw_version;
1008         u16 fw_subversion;
1009         bool h2c_setinprogress;
1010         u8 last_hmeboxnum;
1011         bool fw_ready;
1012         /*Reserve page start offset except beacon in TxQ. */
1013         u8 fw_rsvdpage_startoffset;
1014         u8 h2c_txcmd_seq;
1015
1016         /* FW Cmd IO related */
1017         u16 fwcmd_iomap;
1018         u32 fwcmd_ioparam;
1019         bool set_fwcmd_inprogress;
1020         u8 current_fwcmd_io;
1021
1022         /**/
1023         bool driver_going2unload;
1024
1025         /*AMPDU init min space*/
1026         u8 minspace_cfg;        /*For Min spacing configurations */
1027
1028         /* Dual mac */
1029         enum macphy_mode macphymode;
1030         enum band_type current_bandtype;        /* 0:2.4G, 1:5G */
1031         enum band_type current_bandtypebackup;
1032         enum band_type bandset;
1033         /* dual MAC 0--Mac0 1--Mac1 */
1034         u32 interfaceindex;
1035         /* just for DualMac S3S4 */
1036         u8 macphyctl_reg;
1037         bool earlymode_enable;
1038         /* Dual mac*/
1039         bool during_mac0init_radiob;
1040         bool during_mac1init_radioa;
1041         bool reloadtxpowerindex;
1042         /* True if IMR or IQK  have done
1043         for 2.4G in scan progress */
1044         bool load_imrandiqk_setting_for2g;
1045
1046         bool disable_amsdu_8k;
1047 };
1048
1049 struct rtl_security {
1050         /*default 0 */
1051         bool use_sw_sec;
1052
1053         bool being_setkey;
1054         bool use_defaultkey;
1055         /*Encryption Algorithm for Unicast Packet */
1056         enum rt_enc_alg pairwise_enc_algorithm;
1057         /*Encryption Algorithm for Brocast/Multicast */
1058         enum rt_enc_alg group_enc_algorithm;
1059         /*Cam Entry Bitmap */
1060         u32 hwsec_cam_bitmap;
1061         u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1062         /*local Key buffer, indx 0 is for
1063            pairwise key 1-4 is for agoup key. */
1064         u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1065         u8 key_len[KEY_BUF_SIZE];
1066
1067         /*The pointer of Pairwise Key,
1068            it always points to KeyBuf[4] */
1069         u8 *pairwise_key;
1070 };
1071
1072 struct rtl_dm {
1073         /*PHY status for Dynamic Management */
1074         long entry_min_undecoratedsmoothed_pwdb;
1075         long undecorated_smoothed_pwdb; /*out dm */
1076         long entry_max_undecoratedsmoothed_pwdb;
1077         bool dm_initialgain_enable;
1078         bool dynamic_txpower_enable;
1079         bool current_turbo_edca;
1080         bool is_any_nonbepkts;  /*out dm */
1081         bool is_cur_rdlstate;
1082         bool txpower_trackinginit;
1083         bool disable_framebursting;
1084         bool cck_inch14;
1085         bool txpower_tracking;
1086         bool useramask;
1087         bool rfpath_rxenable[4];
1088         bool inform_fw_driverctrldm;
1089         bool current_mrc_switch;
1090         u8 txpowercount;
1091
1092         u8 thermalvalue_rxgain;
1093         u8 thermalvalue_iqk;
1094         u8 thermalvalue_lck;
1095         u8 thermalvalue;
1096         u8 last_dtp_lvl;
1097         u8 thermalvalue_avg[AVG_THERMAL_NUM];
1098         u8 thermalvalue_avg_index;
1099         bool done_txpower;
1100         u8 dynamic_txhighpower_lvl;     /*Tx high power level */
1101         u8 dm_flag;             /*Indicate each dynamic mechanism's status. */
1102         u8 dm_type;
1103         u8 txpower_track_control;
1104         bool interrupt_migration;
1105         bool disable_tx_int;
1106         char ofdm_index[2];
1107         char cck_index;
1108 };
1109
1110 #define EFUSE_MAX_LOGICAL_SIZE                  256
1111
1112 struct rtl_efuse {
1113         bool autoLoad_ok;
1114         bool bootfromefuse;
1115         u16 max_physical_size;
1116
1117         u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1118         u16 efuse_usedbytes;
1119         u8 efuse_usedpercentage;
1120 #ifdef EFUSE_REPG_WORKAROUND
1121         bool efuse_re_pg_sec1flag;
1122         u8 efuse_re_pg_data[8];
1123 #endif
1124
1125         u8 autoload_failflag;
1126         u8 autoload_status;
1127
1128         short epromtype;
1129         u16 eeprom_vid;
1130         u16 eeprom_did;
1131         u16 eeprom_svid;
1132         u16 eeprom_smid;
1133         u8 eeprom_oemid;
1134         u16 eeprom_channelplan;
1135         u8 eeprom_version;
1136         u8 board_type;
1137         u8 external_pa;
1138
1139         u8 dev_addr[6];
1140
1141         bool txpwr_fromeprom;
1142         u8 eeprom_crystalcap;
1143         u8 eeprom_tssi[2];
1144         u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1145         u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1146         u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1147         u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1148         u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1149         u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1150         u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1151         u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1152         u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1153
1154         u8 internal_pa_5g[2];   /* pathA / pathB */
1155         u8 eeprom_c9;
1156         u8 eeprom_cc;
1157
1158         /*For power group */
1159         u8 eeprom_pwrgroup[2][3];
1160         u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1161         u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1162
1163         char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1164         /*For HT<->legacy pwr diff*/
1165         u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1166         u8 txpwr_safetyflag;                    /* Band edge enable flag */
1167         u16 eeprom_txpowerdiff;
1168         u8 legacy_httxpowerdiff;        /* Legacy to HT rate power diff */
1169         u8 antenna_txpwdiff[3];
1170
1171         u8 eeprom_regulatory;
1172         u8 eeprom_thermalmeter;
1173         u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1174         u16 tssi_13dbm;
1175         u8 crystalcap;          /* CrystalCap. */
1176         u8 delta_iqk;
1177         u8 delta_lck;
1178
1179         u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
1180         bool apk_thermalmeterignore;
1181
1182         bool b1x1_recvcombine;
1183         bool b1ss_support;
1184
1185         /*channel plan */
1186         u8 channel_plan;
1187 };
1188
1189 struct rtl_ps_ctl {
1190         bool pwrdomain_protect;
1191         bool set_rfpowerstate_inprogress;
1192         bool in_powersavemode;
1193         bool rfchange_inprogress;
1194         bool swrf_processing;
1195         bool hwradiooff;
1196
1197         /*
1198          * just for PCIE ASPM
1199          * If it supports ASPM, Offset[560h] = 0x40,
1200          * otherwise Offset[560h] = 0x00.
1201          * */
1202         bool support_aspm;
1203
1204         bool support_backdoor;
1205
1206         /*for LPS */
1207         enum rt_psmode dot11_psmode;    /*Power save mode configured. */
1208         bool swctrl_lps;
1209         bool leisure_ps;
1210         bool fwctrl_lps;
1211         u8 fwctrl_psmode;
1212         /*For Fw control LPS mode */
1213         u8 reg_fwctrl_lps;
1214         /*Record Fw PS mode status. */
1215         bool fw_current_inpsmode;
1216         u8 reg_max_lps_awakeintvl;
1217         bool report_linked;
1218
1219         /*for IPS */
1220         bool inactiveps;
1221
1222         u32 rfoff_reason;
1223
1224         /*RF OFF Level */
1225         u32 cur_ps_level;
1226         u32 reg_rfps_level;
1227
1228         /*just for PCIE ASPM */
1229         u8 const_amdpci_aspm;
1230         bool pwrdown_mode;
1231
1232         enum rf_pwrstate inactive_pwrstate;
1233         enum rf_pwrstate rfpwr_state;   /*cur power state */
1234
1235         /* for SW LPS*/
1236         bool sw_ps_enabled;
1237         bool state;
1238         bool state_inap;
1239         bool multi_buffered;
1240         u16 nullfunc_seq;
1241         unsigned int dtim_counter;
1242         unsigned int sleep_ms;
1243         unsigned long last_sleep_jiffies;
1244         unsigned long last_awake_jiffies;
1245         unsigned long last_delaylps_stamp_jiffies;
1246         unsigned long last_dtim;
1247         unsigned long last_beacon;
1248         unsigned long last_action;
1249         unsigned long last_slept;
1250 };
1251
1252 struct rtl_stats {
1253         u32 mac_time[2];
1254         s8 rssi;
1255         u8 signal;
1256         u8 noise;
1257         u16 rate;               /*in 100 kbps */
1258         u8 received_channel;
1259         u8 control;
1260         u8 mask;
1261         u8 freq;
1262         u16 len;
1263         u64 tsf;
1264         u32 beacon_time;
1265         u8 nic_type;
1266         u16 length;
1267         u8 signalquality;       /*in 0-100 index. */
1268         /*
1269          * Real power in dBm for this packet,
1270          * no beautification and aggregation.
1271          * */
1272         s32 recvsignalpower;
1273         s8 rxpower;             /*in dBm Translate from PWdB */
1274         u8 signalstrength;      /*in 0-100 index. */
1275         u16 hwerror:1;
1276         u16 crc:1;
1277         u16 icv:1;
1278         u16 shortpreamble:1;
1279         u16 antenna:1;
1280         u16 decrypted:1;
1281         u16 wakeup:1;
1282         u32 timestamp_low;
1283         u32 timestamp_high;
1284
1285         u8 rx_drvinfo_size;
1286         u8 rx_bufshift;
1287         bool isampdu;
1288         bool isfirst_ampdu;
1289         bool rx_is40Mhzpacket;
1290         u32 rx_pwdb_all;
1291         u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
1292         s8 rx_mimo_signalquality[2];
1293         bool packet_matchbssid;
1294         bool is_cck;
1295         bool packet_toself;
1296         bool packet_beacon;     /*for rssi */
1297         char cck_adc_pwdb[4];   /*for rx path selection */
1298 };
1299
1300 struct rt_link_detect {
1301         u32 num_tx_in4period[4];
1302         u32 num_rx_in4period[4];
1303
1304         u32 num_tx_inperiod;
1305         u32 num_rx_inperiod;
1306
1307         bool busytraffic;
1308         bool higher_busytraffic;
1309         bool higher_busyrxtraffic;
1310
1311         u32 tidtx_in4period[MAX_TID_COUNT][4];
1312         u32 tidtx_inperiod[MAX_TID_COUNT];
1313         bool higher_busytxtraffic[MAX_TID_COUNT];
1314 };
1315
1316 struct rtl_tcb_desc {
1317         u8 packet_bw:1;
1318         u8 multicast:1;
1319         u8 broadcast:1;
1320
1321         u8 rts_stbc:1;
1322         u8 rts_enable:1;
1323         u8 cts_enable:1;
1324         u8 rts_use_shortpreamble:1;
1325         u8 rts_use_shortgi:1;
1326         u8 rts_sc:1;
1327         u8 rts_bw:1;
1328         u8 rts_rate;
1329
1330         u8 use_shortgi:1;
1331         u8 use_shortpreamble:1;
1332         u8 use_driver_rate:1;
1333         u8 disable_ratefallback:1;
1334
1335         u8 ratr_index;
1336         u8 mac_id;
1337         u8 hw_rate;
1338
1339         u8 last_inipkt:1;
1340         u8 cmd_or_init:1;
1341         u8 queue_index;
1342
1343         /* early mode */
1344         u8 empkt_num;
1345         /* The max value by HW */
1346         u32 empkt_len[5];
1347 };
1348
1349 struct rtl_hal_ops {
1350         int (*init_sw_vars) (struct ieee80211_hw *hw);
1351         void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1352         void (*read_chip_version)(struct ieee80211_hw *hw);
1353         void (*read_eeprom_info) (struct ieee80211_hw *hw);
1354         void (*interrupt_recognized) (struct ieee80211_hw *hw,
1355                                       u32 *p_inta, u32 *p_intb);
1356         int (*hw_init) (struct ieee80211_hw *hw);
1357         void (*hw_disable) (struct ieee80211_hw *hw);
1358         void (*hw_suspend) (struct ieee80211_hw *hw);
1359         void (*hw_resume) (struct ieee80211_hw *hw);
1360         void (*enable_interrupt) (struct ieee80211_hw *hw);
1361         void (*disable_interrupt) (struct ieee80211_hw *hw);
1362         int (*set_network_type) (struct ieee80211_hw *hw,
1363                                  enum nl80211_iftype type);
1364         void (*set_chk_bssid)(struct ieee80211_hw *hw,
1365                                 bool check_bssid);
1366         void (*set_bw_mode) (struct ieee80211_hw *hw,
1367                              enum nl80211_channel_type ch_type);
1368          u8(*switch_channel) (struct ieee80211_hw *hw);
1369         void (*set_qos) (struct ieee80211_hw *hw, int aci);
1370         void (*set_bcn_reg) (struct ieee80211_hw *hw);
1371         void (*set_bcn_intv) (struct ieee80211_hw *hw);
1372         void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1373                                        u32 add_msr, u32 rm_msr);
1374         void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1375         void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1376         void (*update_rate_tbl) (struct ieee80211_hw *hw,
1377                               struct ieee80211_sta *sta, u8 rssi_level);
1378         void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1379         void (*fill_tx_desc) (struct ieee80211_hw *hw,
1380                               struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1381                               struct ieee80211_tx_info *info,
1382                               struct sk_buff *skb, u8 hw_queue,
1383                               struct rtl_tcb_desc *ptcb_desc);
1384         void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1385                                   u32 buffer_len, bool bIsPsPoll);
1386         void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1387                                  bool firstseg, bool lastseg,
1388                                  struct sk_buff *skb);
1389         bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1390         bool (*query_rx_desc) (struct ieee80211_hw *hw,
1391                                struct rtl_stats *stats,
1392                                struct ieee80211_rx_status *rx_status,
1393                                u8 *pdesc, struct sk_buff *skb);
1394         void (*set_channel_access) (struct ieee80211_hw *hw);
1395         bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1396         void (*dm_watchdog) (struct ieee80211_hw *hw);
1397         void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1398         bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1399                                     enum rf_pwrstate rfpwr_state);
1400         void (*led_control) (struct ieee80211_hw *hw,
1401                              enum led_ctl_mode ledaction);
1402         void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1403         u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1404         void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1405         void (*enable_hw_sec) (struct ieee80211_hw *hw);
1406         void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1407                          u8 *macaddr, bool is_group, u8 enc_algo,
1408                          bool is_wepkey, bool clear_all);
1409         void (*init_sw_leds) (struct ieee80211_hw *hw);
1410         void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1411         u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1412         void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1413                            u32 data);
1414         u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1415                           u32 regaddr, u32 bitmask);
1416         void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1417                            u32 regaddr, u32 bitmask, u32 data);
1418         void (*linked_set_reg) (struct ieee80211_hw *hw);
1419         bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1420         void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1421                                             u8 *powerlevel);
1422         void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1423                                              u8 *ppowerlevel, u8 channel);
1424         bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1425                                            u8 configtype);
1426         bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1427                                              u8 configtype);
1428         void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1429         void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1430         void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1431 };
1432
1433 struct rtl_intf_ops {
1434         /*com */
1435         void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1436         int (*adapter_start) (struct ieee80211_hw *hw);
1437         void (*adapter_stop) (struct ieee80211_hw *hw);
1438
1439         int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1440                         struct rtl_tcb_desc *ptcb_desc);
1441         void (*flush)(struct ieee80211_hw *hw, bool drop);
1442         int (*reset_trx_ring) (struct ieee80211_hw *hw);
1443         bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1444
1445         /*pci */
1446         void (*disable_aspm) (struct ieee80211_hw *hw);
1447         void (*enable_aspm) (struct ieee80211_hw *hw);
1448
1449         /*usb */
1450 };
1451
1452 struct rtl_mod_params {
1453         /* default: 0 = using hardware encryption */
1454         int sw_crypto;
1455
1456         /* default: 1 = using no linked power save */
1457         bool inactiveps;
1458
1459         /* default: 1 = using linked sw power save */
1460         bool swctrl_lps;
1461
1462         /* default: 1 = using linked fw power save */
1463         bool fwctrl_lps;
1464 };
1465
1466 struct rtl_hal_usbint_cfg {
1467         /* data - rx */
1468         u32 in_ep_num;
1469         u32 rx_urb_num;
1470         u32 rx_max_size;
1471
1472         /* op - rx */
1473         void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1474         void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1475                                      struct sk_buff_head *);
1476
1477         /* tx */
1478         void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1479         int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1480                                struct sk_buff *);
1481         struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1482                                                 struct sk_buff_head *);
1483
1484         /* endpoint mapping */
1485         int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1486         u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1487 };
1488
1489 struct rtl_hal_cfg {
1490         u8 bar_id;
1491         bool write_readback;
1492         char *name;
1493         char *fw_name;
1494         struct rtl_hal_ops *ops;
1495         struct rtl_mod_params *mod_params;
1496         struct rtl_hal_usbint_cfg *usb_interface_cfg;
1497
1498         /*this map used for some registers or vars
1499            defined int HAL but used in MAIN */
1500         u32 maps[RTL_VAR_MAP_MAX];
1501
1502 };
1503
1504 struct rtl_locks {
1505         /* mutex */
1506         struct mutex conf_mutex;
1507
1508         /*spin lock */
1509         spinlock_t ips_lock;
1510         spinlock_t irq_th_lock;
1511         spinlock_t h2c_lock;
1512         spinlock_t rf_ps_lock;
1513         spinlock_t rf_lock;
1514         spinlock_t lps_lock;
1515         spinlock_t waitq_lock;
1516
1517         /*Dual mac*/
1518         spinlock_t cck_and_rw_pagea_lock;
1519 };
1520
1521 struct rtl_works {
1522         struct ieee80211_hw *hw;
1523
1524         /*timer */
1525         struct timer_list watchdog_timer;
1526
1527         /*task */
1528         struct tasklet_struct irq_tasklet;
1529         struct tasklet_struct irq_prepare_bcn_tasklet;
1530
1531         /*work queue */
1532         struct workqueue_struct *rtl_wq;
1533         struct delayed_work watchdog_wq;
1534         struct delayed_work ips_nic_off_wq;
1535
1536         /* For SW LPS */
1537         struct delayed_work ps_work;
1538         struct delayed_work ps_rfon_wq;
1539 };
1540
1541 struct rtl_debug {
1542         u32 dbgp_type[DBGP_TYPE_MAX];
1543         u32 global_debuglevel;
1544         u64 global_debugcomponents;
1545
1546         /* add for proc debug */
1547         struct proc_dir_entry *proc_dir;
1548         char proc_name[20];
1549 };
1550
1551 struct rtl_priv {
1552         struct rtl_locks locks;
1553         struct rtl_works works;
1554         struct rtl_mac mac80211;
1555         struct rtl_hal rtlhal;
1556         struct rtl_regulatory regd;
1557         struct rtl_rfkill rfkill;
1558         struct rtl_io io;
1559         struct rtl_phy phy;
1560         struct rtl_dm dm;
1561         struct rtl_security sec;
1562         struct rtl_efuse efuse;
1563
1564         struct rtl_ps_ctl psc;
1565         struct rate_adaptive ra;
1566         struct wireless_stats stats;
1567         struct rt_link_detect link_info;
1568         struct false_alarm_statistics falsealm_cnt;
1569
1570         struct rtl_rate_priv *rate_priv;
1571
1572         struct rtl_debug dbg;
1573
1574         /*
1575          *hal_cfg : for diff cards
1576          *intf_ops : for diff interrface usb/pcie
1577          */
1578         struct rtl_hal_cfg *cfg;
1579         struct rtl_intf_ops *intf_ops;
1580
1581         /*this var will be set by set_bit,
1582            and was used to indicate status of
1583            interface or hardware */
1584         unsigned long status;
1585
1586         /*This must be the last item so
1587            that it points to the data allocated
1588            beyond  this structure like:
1589            rtl_pci_priv or rtl_usb_priv */
1590         u8 priv[0];
1591 };
1592
1593 #define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
1594 #define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
1595 #define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
1596 #define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
1597 #define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
1598
1599
1600 /***************************************
1601     Bluetooth Co-existence Related
1602 ****************************************/
1603
1604 enum bt_ant_num {
1605         ANT_X2 = 0,
1606         ANT_X1 = 1,
1607 };
1608
1609 enum bt_co_type {
1610         BT_2WIRE = 0,
1611         BT_ISSC_3WIRE = 1,
1612         BT_ACCEL = 2,
1613         BT_CSR_BC4 = 3,
1614         BT_CSR_BC8 = 4,
1615         BT_RTL8756 = 5,
1616 };
1617
1618 enum bt_cur_state {
1619         BT_OFF = 0,
1620         BT_ON = 1,
1621 };
1622
1623 enum bt_service_type {
1624         BT_SCO = 0,
1625         BT_A2DP = 1,
1626         BT_HID = 2,
1627         BT_HID_IDLE = 3,
1628         BT_SCAN = 4,
1629         BT_IDLE = 5,
1630         BT_OTHER_ACTION = 6,
1631         BT_BUSY = 7,
1632         BT_OTHERBUSY = 8,
1633         BT_PAN = 9,
1634 };
1635
1636 enum bt_radio_shared {
1637         BT_RADIO_SHARED = 0,
1638         BT_RADIO_INDIVIDUAL = 1,
1639 };
1640
1641 struct bt_coexist_info {
1642
1643         /* EEPROM BT info. */
1644         u8 eeprom_bt_coexist;
1645         u8 eeprom_bt_type;
1646         u8 eeprom_bt_ant_num;
1647         u8 eeprom_bt_ant_isolation;
1648         u8 eeprom_bt_radio_shared;
1649
1650         u8 bt_coexistence;
1651         u8 bt_ant_num;
1652         u8 bt_coexist_type;
1653         u8 bt_state;
1654         u8 bt_cur_state;        /* 0:on, 1:off */
1655         u8 bt_ant_isolation;    /* 0:good, 1:bad */
1656         u8 bt_pape_ctrl;        /* 0:SW, 1:SW/HW dynamic */
1657         u8 bt_service;
1658         u8 bt_radio_shared_type;
1659         u8 bt_rfreg_origin_1e;
1660         u8 bt_rfreg_origin_1f;
1661         u8 bt_rssi_state;
1662         u32 ratio_tx;
1663         u32 ratio_pri;
1664         u32 bt_edca_ul;
1665         u32 bt_edca_dl;
1666
1667         bool init_set;
1668         bool bt_busy_traffic;
1669         bool bt_traffic_mode_set;
1670         bool bt_non_traffic_mode_set;
1671
1672         bool fw_coexist_all_off;
1673         bool sw_coexist_all_off;
1674         u32 current_state;
1675         u32 previous_state;
1676         u8 bt_pre_rssi_state;
1677
1678         u8 reg_bt_iso;
1679         u8 reg_bt_sco;
1680
1681 };
1682
1683
1684 /****************************************
1685         mem access macro define start
1686         Call endian free function when
1687         1. Read/write packet content.
1688         2. Before write integer to IO.
1689         3. After read integer from IO.
1690 ****************************************/
1691 /* Convert little data endian to host ordering */
1692 #define EF1BYTE(_val)           \
1693         ((u8)(_val))
1694 #define EF2BYTE(_val)           \
1695         (le16_to_cpu(_val))
1696 #define EF4BYTE(_val)           \
1697         (le32_to_cpu(_val))
1698
1699 /* Read data from memory */
1700 #define READEF1BYTE(_ptr)       \
1701         EF1BYTE(*((u8 *)(_ptr)))
1702 /* Read le16 data from memory and convert to host ordering */
1703 #define READEF2BYTE(_ptr)       \
1704         EF2BYTE(*((u16 *)(_ptr)))
1705 #define READEF4BYTE(_ptr)       \
1706         EF4BYTE(*((u32 *)(_ptr)))
1707
1708 /* Write data to memory */
1709 #define WRITEEF1BYTE(_ptr, _val)        \
1710         (*((u8 *)(_ptr))) = EF1BYTE(_val)
1711 /* Write le16 data to memory in host ordering */
1712 #define WRITEEF2BYTE(_ptr, _val)        \
1713         (*((u16 *)(_ptr))) = EF2BYTE(_val)
1714 #define WRITEEF4BYTE(_ptr, _val)        \
1715         (*((u16 *)(_ptr))) = EF2BYTE(_val)
1716
1717 /* Create a bit mask
1718  * Examples:
1719  * BIT_LEN_MASK_32(0) => 0x00000000
1720  * BIT_LEN_MASK_32(1) => 0x00000001
1721  * BIT_LEN_MASK_32(2) => 0x00000003
1722  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1723  */
1724 #define BIT_LEN_MASK_32(__bitlen)        \
1725         (0xFFFFFFFF >> (32 - (__bitlen)))
1726 #define BIT_LEN_MASK_16(__bitlen)        \
1727         (0xFFFF >> (16 - (__bitlen)))
1728 #define BIT_LEN_MASK_8(__bitlen) \
1729         (0xFF >> (8 - (__bitlen)))
1730
1731 /* Create an offset bit mask
1732  * Examples:
1733  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1734  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1735  */
1736 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1737         (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1738 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1739         (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1740 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1741         (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1742
1743 /*Description:
1744  * Return 4-byte value in host byte ordering from
1745  * 4-byte pointer in little-endian system.
1746  */
1747 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1748         (EF4BYTE(*((u32 *)(__pstart))))
1749 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1750         (EF2BYTE(*((u16 *)(__pstart))))
1751 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1752         (EF1BYTE(*((u8 *)(__pstart))))
1753
1754 /*Description:
1755 Translate subfield (continuous bits in little-endian) of 4-byte
1756 value to host byte ordering.*/
1757 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1758         ( \
1759                 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
1760                 BIT_LEN_MASK_32(__bitlen) \
1761         )
1762 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1763         ( \
1764                 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1765                 BIT_LEN_MASK_16(__bitlen) \
1766         )
1767 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1768         ( \
1769                 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1770                 BIT_LEN_MASK_8(__bitlen) \
1771         )
1772
1773 /* Description:
1774  * Mask subfield (continuous bits in little-endian) of 4-byte value
1775  * and return the result in 4-byte value in host byte ordering.
1776  */
1777 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1778         ( \
1779                 LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
1780                 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1781         )
1782 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1783         ( \
1784                 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1785                 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1786         )
1787 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1788         ( \
1789                 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1790                 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1791         )
1792
1793 /* Description:
1794  * Set subfield of little-endian 4-byte value to specified value.
1795  */
1796 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1797         *((u32 *)(__pstart)) = EF4BYTE \
1798         ( \
1799                 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1800                 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1801         );
1802 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1803         *((u16 *)(__pstart)) = EF2BYTE \
1804         ( \
1805                 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1806                 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1807         );
1808 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1809         *((u8 *)(__pstart)) = EF1BYTE \
1810         ( \
1811                 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1812                 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1813         );
1814
1815 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1816         (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1817
1818 /****************************************
1819         mem access macro define end
1820 ****************************************/
1821
1822 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1823
1824 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1825 #define RTL_WATCH_DOG_TIME      2000
1826 #define MSECS(t)                msecs_to_jiffies(t)
1827 #define WLAN_FC_GET_VERS(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1828 #define WLAN_FC_GET_TYPE(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1829 #define WLAN_FC_GET_STYPE(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1830 #define WLAN_FC_MORE_DATA(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1831 #define SEQ_TO_SN(seq)          (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1832 #define SN_TO_SEQ(ssn)          (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1833 #define MAX_SN                  ((IEEE80211_SCTL_SEQ) >> 4)
1834
1835 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
1836 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
1837 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
1838 /*NIC halt, re-initialize hw parameters*/
1839 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
1840 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
1841 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
1842 /*Always enable ASPM and Clock Req in initialization.*/
1843 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
1844 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1845 #define RT_PS_LEVEL_ASPM                BIT(7)
1846 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1847 #define RT_RF_LPS_DISALBE_2R            BIT(30)
1848 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
1849 #define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
1850         ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1851 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
1852         (ppsc->cur_ps_level &= (~(_ps_flg)))
1853 #define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
1854         (ppsc->cur_ps_level |= _ps_flg)
1855
1856 #define container_of_dwork_rtl(x, y, z) \
1857         container_of(container_of(x, struct delayed_work, work), y, z)
1858
1859 #define FILL_OCTET_STRING(_os, _octet, _len)    \
1860                 (_os).octet = (u8 *)(_octet);           \
1861                 (_os).length = (_len);
1862
1863 #define CP_MACADDR(des, src)    \
1864         ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1865         (des)[2] = (src)[2], (des)[3] = (src)[3],\
1866         (des)[4] = (src)[4], (des)[5] = (src)[5])
1867
1868 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1869 {
1870         return rtlpriv->io.read8_sync(rtlpriv, addr);
1871 }
1872
1873 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1874 {
1875         return rtlpriv->io.read16_sync(rtlpriv, addr);
1876 }
1877
1878 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1879 {
1880         return rtlpriv->io.read32_sync(rtlpriv, addr);
1881 }
1882
1883 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1884 {
1885         rtlpriv->io.write8_async(rtlpriv, addr, val8);
1886
1887         if (rtlpriv->cfg->write_readback)
1888                 rtlpriv->io.read8_sync(rtlpriv, addr);
1889 }
1890
1891 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1892 {
1893         rtlpriv->io.write16_async(rtlpriv, addr, val16);
1894
1895         if (rtlpriv->cfg->write_readback)
1896                 rtlpriv->io.read16_sync(rtlpriv, addr);
1897 }
1898
1899 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1900                                    u32 addr, u32 val32)
1901 {
1902         rtlpriv->io.write32_async(rtlpriv, addr, val32);
1903
1904         if (rtlpriv->cfg->write_readback)
1905                 rtlpriv->io.read32_sync(rtlpriv, addr);
1906 }
1907
1908 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1909                                 u32 regaddr, u32 bitmask)
1910 {
1911         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1912                                                                     regaddr,
1913                                                                     bitmask);
1914 }
1915
1916 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1917                                  u32 bitmask, u32 data)
1918 {
1919         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1920                                                              regaddr, bitmask,
1921                                                              data);
1922
1923 }
1924
1925 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1926                                 enum radio_path rfpath, u32 regaddr,
1927                                 u32 bitmask)
1928 {
1929         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1930                                                                     rfpath,
1931                                                                     regaddr,
1932                                                                     bitmask);
1933 }
1934
1935 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1936                                  enum radio_path rfpath, u32 regaddr,
1937                                  u32 bitmask, u32 data)
1938 {
1939         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1940                                                              rfpath, regaddr,
1941                                                              bitmask, data);
1942 }
1943
1944 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1945 {
1946         return (_HAL_STATE_STOP == rtlhal->state);
1947 }
1948
1949 static inline void set_hal_start(struct rtl_hal *rtlhal)
1950 {
1951         rtlhal->state = _HAL_STATE_START;
1952 }
1953
1954 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1955 {
1956         rtlhal->state = _HAL_STATE_STOP;
1957 }
1958
1959 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1960 {
1961         return rtlphy->rf_type;
1962 }
1963
1964 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
1965 {
1966         return (struct ieee80211_hdr *)(skb->data);
1967 }
1968
1969 static inline __le16 rtl_get_fc(struct sk_buff *skb)
1970 {
1971         return rtl_get_hdr(skb)->frame_control;
1972 }
1973
1974 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
1975 {
1976         return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
1977 }
1978
1979 static inline u16 rtl_get_tid(struct sk_buff *skb)
1980 {
1981         return rtl_get_tid_h(rtl_get_hdr(skb));
1982 }
1983
1984 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
1985                                             struct ieee80211_vif *vif,
1986                                             u8 *bssid)
1987 {
1988         return ieee80211_find_sta(vif, bssid);
1989 }
1990
1991 #endif