drivers/net/wireless/rtlwifi/wifi.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_WIFI_H__
  31 #define __RTL_WIFI_H__
  32
  33 #include <linux/sched.h>
  34 #include <linux/firmware.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/usb.h>
  38 #include <net/mac80211.h>
  39 #include "debug.h"
  40
  41 #define RF_CHANGE_BY_INIT                       0
  42 #define RF_CHANGE_BY_IPS                        BIT(28)
  43 #define RF_CHANGE_BY_PS                         BIT(29)
  44 #define RF_CHANGE_BY_HW                         BIT(30)
  45 #define RF_CHANGE_BY_SW                         BIT(31)
  46
  47 #define IQK_ADDA_REG_NUM                        16
  48 #define IQK_MAC_REG_NUM                         4
  49
  50 #define MAX_KEY_LEN                             61
  51 #define KEY_BUF_SIZE                            5
  52
  53 /* QoS related. */
  54 /*aci: 0x00     Best Effort*/
  55 /*aci: 0x01     Background*/
  56 /*aci: 0x10     Video*/
  57 /*aci: 0x11     Voice*/
  58 /*Max: define total number.*/
  59 #define AC0_BE                                  0
  60 #define AC1_BK                                  1
  61 #define AC2_VI                                  2
  62 #define AC3_VO                                  3
  63 #define AC_MAX                                  4
  64 #define QOS_QUEUE_NUM                           4
  65 #define RTL_MAC80211_NUM_QUEUE                  5
  66
  67 #define QBSS_LOAD_SIZE                          5
  68 #define MAX_WMMELE_LENGTH                       64
  69
  70 #define TOTAL_CAM_ENTRY                         32
  71
  72 /*slot time for 11g. */
  73 #define RTL_SLOT_TIME_9                         9
  74 #define RTL_SLOT_TIME_20                        20
  75
  76 /*related with tcp/ip. */
  77 /*if_ehther.h*/
  78 #define ETH_P_PAE               0x888E  /*Port Access Entity (IEEE 802.1X) */
  79 #define ETH_P_IP                0x0800  /*Internet Protocol packet */
  80 #define ETH_P_ARP               0x0806  /*Address Resolution packet */
  81 #define SNAP_SIZE               6
  82 #define PROTOC_TYPE_SIZE        2
  83
  84 /*related with 802.11 frame*/
  85 #define MAC80211_3ADDR_LEN                      24
  86 #define MAC80211_4ADDR_LEN                      30
  87
  88 #define CHANNEL_MAX_NUMBER      (14 + 24 + 21)  /* 14 is the max channel no */
  89 #define CHANNEL_GROUP_MAX       (3 + 9) /*  ch1~3, 4~9, 10~14 = three groups */
  90 #define MAX_PG_GROUP                    13
  91 #define CHANNEL_GROUP_MAX_2G            3
  92 #define CHANNEL_GROUP_IDX_5GL           3
  93 #define CHANNEL_GROUP_IDX_5GM           6
  94 #define CHANNEL_GROUP_IDX_5GH           9
  95 #define CHANNEL_GROUP_MAX_5G            9
  96 #define CHANNEL_MAX_NUMBER_2G           14
  97 #define AVG_THERMAL_NUM                 8
  98 #define MAX_TID_COUNT                   9
  99
 100 /* for early mode */
 101 #define FCS_LEN                         4
 102 #define EM_HDR_LEN                      8
 103 enum intf_type {
 104         INTF_PCI = 0,
 105         INTF_USB = 1,
 106 };
 107
 108 enum radio_path {
 109         RF90_PATH_A = 0,
 110         RF90_PATH_B = 1,
 111         RF90_PATH_C = 2,
 112         RF90_PATH_D = 3,
 113 };
 114
 115 enum rt_eeprom_type {
 116         EEPROM_93C46,
 117         EEPROM_93C56,
 118         EEPROM_BOOT_EFUSE,
 119 };
 120
 121 enum rtl_status {
 122         RTL_STATUS_INTERFACE_START = 0,
 123 };
 124
 125 enum hardware_type {
 126         HARDWARE_TYPE_RTL8192E,
 127         HARDWARE_TYPE_RTL8192U,
 128         HARDWARE_TYPE_RTL8192SE,
 129         HARDWARE_TYPE_RTL8192SU,
 130         HARDWARE_TYPE_RTL8192CE,
 131         HARDWARE_TYPE_RTL8192CU,
 132         HARDWARE_TYPE_RTL8192DE,
 133         HARDWARE_TYPE_RTL8192DU,
 134         HARDWARE_TYPE_RTL8723E,
 135         HARDWARE_TYPE_RTL8723U,
 136
 137         /* keep it last */
 138         HARDWARE_TYPE_NUM
 139 };
 140
 141 #define IS_HARDWARE_TYPE_8192SU(rtlhal)                 \
 142         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
 143 #define IS_HARDWARE_TYPE_8192SE(rtlhal)                 \
 144         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 145 #define IS_HARDWARE_TYPE_8192CE(rtlhal)                 \
 146         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
 147 #define IS_HARDWARE_TYPE_8192CU(rtlhal)                 \
 148         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
 149 #define IS_HARDWARE_TYPE_8192DE(rtlhal)                 \
 150         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
 151 #define IS_HARDWARE_TYPE_8192DU(rtlhal)                 \
 152         (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
 153 #define IS_HARDWARE_TYPE_8723E(rtlhal)                  \
 154         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
 155 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 156         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 157 #define IS_HARDWARE_TYPE_8192S(rtlhal)                  \
 158 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
 159 #define IS_HARDWARE_TYPE_8192C(rtlhal)                  \
 160 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
 161 #define IS_HARDWARE_TYPE_8192D(rtlhal)                  \
 162 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
 163 #define IS_HARDWARE_TYPE_8723(rtlhal)                   \
 164 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
 165 #define IS_HARDWARE_TYPE_8723U(rtlhal)                  \
 166         (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 167
 168 enum scan_operation_backup_opt {
 169         SCAN_OPT_BACKUP = 0,
 170         SCAN_OPT_RESTORE,
 171         SCAN_OPT_MAX
 172 };
 173
 174 /*RF state.*/
 175 enum rf_pwrstate {
 176         ERFON,
 177         ERFSLEEP,
 178         ERFOFF
 179 };
 180
 181 struct bb_reg_def {
 182         u32 rfintfs;
 183         u32 rfintfi;
 184         u32 rfintfo;
 185         u32 rfintfe;
 186         u32 rf3wire_offset;
 187         u32 rflssi_select;
 188         u32 rftxgain_stage;
 189         u32 rfhssi_para1;
 190         u32 rfhssi_para2;
 191         u32 rfswitch_control;
 192         u32 rfagc_control1;
 193         u32 rfagc_control2;
 194         u32 rfrxiq_imbalance;
 195         u32 rfrx_afe;
 196         u32 rftxiq_imbalance;
 197         u32 rftx_afe;
 198         u32 rflssi_readback;
 199         u32 rflssi_readbackpi;
 200 };
 201
 202 enum io_type {
 203         IO_CMD_PAUSE_DM_BY_SCAN = 0,
 204         IO_CMD_RESUME_DM_BY_SCAN = 1,
 205 };
 206
 207 enum hw_variables {
 208         HW_VAR_ETHER_ADDR,
 209         HW_VAR_MULTICAST_REG,
 210         HW_VAR_BASIC_RATE,
 211         HW_VAR_BSSID,
 212         HW_VAR_MEDIA_STATUS,
 213         HW_VAR_SECURITY_CONF,
 214         HW_VAR_BEACON_INTERVAL,
 215         HW_VAR_ATIM_WINDOW,
 216         HW_VAR_LISTEN_INTERVAL,
 217         HW_VAR_CS_COUNTER,
 218         HW_VAR_DEFAULTKEY0,
 219         HW_VAR_DEFAULTKEY1,
 220         HW_VAR_DEFAULTKEY2,
 221         HW_VAR_DEFAULTKEY3,
 222         HW_VAR_SIFS,
 223         HW_VAR_DIFS,
 224         HW_VAR_EIFS,
 225         HW_VAR_SLOT_TIME,
 226         HW_VAR_ACK_PREAMBLE,
 227         HW_VAR_CW_CONFIG,
 228         HW_VAR_CW_VALUES,
 229         HW_VAR_RATE_FALLBACK_CONTROL,
 230         HW_VAR_CONTENTION_WINDOW,
 231         HW_VAR_RETRY_COUNT,
 232         HW_VAR_TR_SWITCH,
 233         HW_VAR_COMMAND,
 234         HW_VAR_WPA_CONFIG,
 235         HW_VAR_AMPDU_MIN_SPACE,
 236         HW_VAR_SHORTGI_DENSITY,
 237         HW_VAR_AMPDU_FACTOR,
 238         HW_VAR_MCS_RATE_AVAILABLE,
 239         HW_VAR_AC_PARAM,
 240         HW_VAR_ACM_CTRL,
 241         HW_VAR_DIS_Req_Qsize,
 242         HW_VAR_CCX_CHNL_LOAD,
 243         HW_VAR_CCX_NOISE_HISTOGRAM,
 244         HW_VAR_CCX_CLM_NHM,
 245         HW_VAR_TxOPLimit,
 246         HW_VAR_TURBO_MODE,
 247         HW_VAR_RF_STATE,
 248         HW_VAR_RF_OFF_BY_HW,
 249         HW_VAR_BUS_SPEED,
 250         HW_VAR_SET_DEV_POWER,
 251
 252         HW_VAR_RCR,
 253         HW_VAR_RATR_0,
 254         HW_VAR_RRSR,
 255         HW_VAR_CPU_RST,
 256         HW_VAR_CECHK_BSSID,
 257         HW_VAR_LBK_MODE,
 258         HW_VAR_AES_11N_FIX,
 259         HW_VAR_USB_RX_AGGR,
 260         HW_VAR_USER_CONTROL_TURBO_MODE,
 261         HW_VAR_RETRY_LIMIT,
 262         HW_VAR_INIT_TX_RATE,
 263         HW_VAR_TX_RATE_REG,
 264         HW_VAR_EFUSE_USAGE,
 265         HW_VAR_EFUSE_BYTES,
 266         HW_VAR_AUTOLOAD_STATUS,
 267         HW_VAR_RF_2R_DISABLE,
 268         HW_VAR_SET_RPWM,
 269         HW_VAR_H2C_FW_PWRMODE,
 270         HW_VAR_H2C_FW_JOINBSSRPT,
 271         HW_VAR_FW_PSMODE_STATUS,
 272         HW_VAR_1X1_RECV_COMBINE,
 273         HW_VAR_STOP_SEND_BEACON,
 274         HW_VAR_TSF_TIMER,
 275         HW_VAR_IO_CMD,
 276
 277         HW_VAR_RF_RECOVERY,
 278         HW_VAR_H2C_FW_UPDATE_GTK,
 279         HW_VAR_WF_MASK,
 280         HW_VAR_WF_CRC,
 281         HW_VAR_WF_IS_MAC_ADDR,
 282         HW_VAR_H2C_FW_OFFLOAD,
 283         HW_VAR_RESET_WFCRC,
 284
 285         HW_VAR_HANDLE_FW_C2H,
 286         HW_VAR_DL_FW_RSVD_PAGE,
 287         HW_VAR_AID,
 288         HW_VAR_HW_SEQ_ENABLE,
 289         HW_VAR_CORRECT_TSF,
 290         HW_VAR_BCN_VALID,
 291         HW_VAR_FWLPS_RF_ON,
 292         HW_VAR_DUAL_TSF_RST,
 293         HW_VAR_SWITCH_EPHY_WoWLAN,
 294         HW_VAR_INT_MIGRATION,
 295         HW_VAR_INT_AC,
 296         HW_VAR_RF_TIMING,
 297
 298         HW_VAR_MRC,
 299
 300         HW_VAR_MGT_FILTER,
 301         HW_VAR_CTRL_FILTER,
 302         HW_VAR_DATA_FILTER,
 303 };
 304
 305 #define HWSET_MAX_SIZE                          128
 306 #define EFUSE_MAX_SECTION                       16
 307
 308 enum _RT_MEDIA_STATUS {
 309         RT_MEDIA_DISCONNECT = 0,
 310         RT_MEDIA_CONNECT = 1
 311 };
 312
 313 enum rt_oem_id {
 314         RT_CID_DEFAULT = 0,
 315         RT_CID_8187_ALPHA0 = 1,
 316         RT_CID_8187_SERCOMM_PS = 2,
 317         RT_CID_8187_HW_LED = 3,
 318         RT_CID_8187_NETGEAR = 4,
 319         RT_CID_WHQL = 5,
 320         RT_CID_819x_CAMEO = 6,
 321         RT_CID_819x_RUNTOP = 7,
 322         RT_CID_819x_Senao = 8,
 323         RT_CID_TOSHIBA = 9,
 324         RT_CID_819x_Netcore = 10,
 325         RT_CID_Nettronix = 11,
 326         RT_CID_DLINK = 12,
 327         RT_CID_PRONET = 13,
 328         RT_CID_COREGA = 14,
 329         RT_CID_819x_ALPHA = 15,
 330         RT_CID_819x_Sitecom = 16,
 331         RT_CID_CCX = 17,
 332         RT_CID_819x_Lenovo = 18,
 333         RT_CID_819x_QMI = 19,
 334         RT_CID_819x_Edimax_Belkin = 20,
 335         RT_CID_819x_Sercomm_Belkin = 21,
 336         RT_CID_819x_CAMEO1 = 22,
 337         RT_CID_819x_MSI = 23,
 338         RT_CID_819x_Acer = 24,
 339         RT_CID_819x_HP = 27,
 340         RT_CID_819x_CLEVO = 28,
 341         RT_CID_819x_Arcadyan_Belkin = 29,
 342         RT_CID_819x_SAMSUNG = 30,
 343         RT_CID_819x_WNC_COREGA = 31,
 344         RT_CID_819x_Foxcoon = 32,
 345         RT_CID_819x_DELL = 33,
 346 };
 347
 348 enum hw_descs {
 349         HW_DESC_OWN,
 350         HW_DESC_RXOWN,
 351         HW_DESC_TX_NEXTDESC_ADDR,
 352         HW_DESC_TXBUFF_ADDR,
 353         HW_DESC_RXBUFF_ADDR,
 354         HW_DESC_RXPKT_LEN,
 355         HW_DESC_RXERO,
 356 };
 357
 358 enum prime_sc {
 359         PRIME_CHNL_OFFSET_DONT_CARE = 0,
 360         PRIME_CHNL_OFFSET_LOWER = 1,
 361         PRIME_CHNL_OFFSET_UPPER = 2,
 362 };
 363
 364 enum rf_type {
 365         RF_1T1R = 0,
 366         RF_1T2R = 1,
 367         RF_2T2R = 2,
 368         RF_2T2R_GREEN = 3,
 369 };
 370
 371 enum ht_channel_width {
 372         HT_CHANNEL_WIDTH_20 = 0,
 373         HT_CHANNEL_WIDTH_20_40 = 1,
 374 };
 375
 376 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
 377 Cipher Suites Encryption Algorithms */
 378 enum rt_enc_alg {
 379         NO_ENCRYPTION = 0,
 380         WEP40_ENCRYPTION = 1,
 381         TKIP_ENCRYPTION = 2,
 382         RSERVED_ENCRYPTION = 3,
 383         AESCCMP_ENCRYPTION = 4,
 384         WEP104_ENCRYPTION = 5,
 385 };
 386
 387 enum rtl_hal_state {
 388         _HAL_STATE_STOP = 0,
 389         _HAL_STATE_START = 1,
 390 };
 391
 392 enum rtl_var_map {
 393         /*reg map */
 394         SYS_ISO_CTRL = 0,
 395         SYS_FUNC_EN,
 396         SYS_CLK,
 397         MAC_RCR_AM,
 398         MAC_RCR_AB,
 399         MAC_RCR_ACRC32,
 400         MAC_RCR_ACF,
 401         MAC_RCR_AAP,
 402
 403         /*efuse map */
 404         EFUSE_TEST,
 405         EFUSE_CTRL,
 406         EFUSE_CLK,
 407         EFUSE_CLK_CTRL,
 408         EFUSE_PWC_EV12V,
 409         EFUSE_FEN_ELDR,
 410         EFUSE_LOADER_CLK_EN,
 411         EFUSE_ANA8M,
 412         EFUSE_HWSET_MAX_SIZE,
 413         EFUSE_MAX_SECTION_MAP,
 414         EFUSE_REAL_CONTENT_SIZE,
 415
 416         /*CAM map */
 417         RWCAM,
 418         WCAMI,
 419         RCAMO,
 420         CAMDBG,
 421         SECR,
 422         SEC_CAM_NONE,
 423         SEC_CAM_WEP40,
 424         SEC_CAM_TKIP,
 425         SEC_CAM_AES,
 426         SEC_CAM_WEP104,
 427
 428         /*IMR map */
 429         RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
 430         RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
 431         RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
 432         RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
 433         RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
 434         RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
 435         RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrup 8 */
 436         RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrup 7 */
 437         RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrup 6 */
 438         RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrup 5 */
 439         RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrup 4 */
 440         RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrup 3 */
 441         RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrup 2 */
 442         RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrup 1 */
 443         RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
 444         RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
 445         RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
 446         RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
 447         RTL_IMR_BcnInt,         /*Beacon DMA Interrupt 0 */
 448         RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
 449         RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
 450         RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
 451         RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrup */
 452         RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
 453         RTL_IMR_COMDOK,         /*Command Queue DMA OK Interrupt*/
 454         RTL_IMR_TBDOK,          /*Transmit Beacon OK interrup */
 455         RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
 456         RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
 457         RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
 458         RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
 459         RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
 460         RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
 461         RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
 462         RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
 463                                  * RTL_IMR_TBDER) */
 464
 465         /*CCK Rates, TxHT = 0 */
 466         RTL_RC_CCK_RATE1M,
 467         RTL_RC_CCK_RATE2M,
 468         RTL_RC_CCK_RATE5_5M,
 469         RTL_RC_CCK_RATE11M,
 470
 471         /*OFDM Rates, TxHT = 0 */
 472         RTL_RC_OFDM_RATE6M,
 473         RTL_RC_OFDM_RATE9M,
 474         RTL_RC_OFDM_RATE12M,
 475         RTL_RC_OFDM_RATE18M,
 476         RTL_RC_OFDM_RATE24M,
 477         RTL_RC_OFDM_RATE36M,
 478         RTL_RC_OFDM_RATE48M,
 479         RTL_RC_OFDM_RATE54M,
 480
 481         RTL_RC_HT_RATEMCS7,
 482         RTL_RC_HT_RATEMCS15,
 483
 484         /*keep it last */
 485         RTL_VAR_MAP_MAX,
 486 };
 487
 488 /*Firmware PS mode for control LPS.*/
 489 enum _fw_ps_mode {
 490         FW_PS_ACTIVE_MODE = 0,
 491         FW_PS_MIN_MODE = 1,
 492         FW_PS_MAX_MODE = 2,
 493         FW_PS_DTIM_MODE = 3,
 494         FW_PS_VOIP_MODE = 4,
 495         FW_PS_UAPSD_WMM_MODE = 5,
 496         FW_PS_UAPSD_MODE = 6,
 497         FW_PS_IBSS_MODE = 7,
 498         FW_PS_WWLAN_MODE = 8,
 499         FW_PS_PM_Radio_Off = 9,
 500         FW_PS_PM_Card_Disable = 10,
 501 };
 502
 503 enum rt_psmode {
 504         EACTIVE,                /*Active/Continuous access. */
 505         EMAXPS,                 /*Max power save mode. */
 506         EFASTPS,                /*Fast power save mode. */
 507         EAUTOPS,                /*Auto power save mode. */
 508 };
 509
 510 /*LED related.*/
 511 enum led_ctl_mode {
 512         LED_CTL_POWER_ON = 1,
 513         LED_CTL_LINK = 2,
 514         LED_CTL_NO_LINK = 3,
 515         LED_CTL_TX = 4,
 516         LED_CTL_RX = 5,
 517         LED_CTL_SITE_SURVEY = 6,
 518         LED_CTL_POWER_OFF = 7,
 519         LED_CTL_START_TO_LINK = 8,
 520         LED_CTL_START_WPS = 9,
 521         LED_CTL_STOP_WPS = 10,
 522 };
 523
 524 enum rtl_led_pin {
 525         LED_PIN_GPIO0,
 526         LED_PIN_LED0,
 527         LED_PIN_LED1,
 528         LED_PIN_LED2
 529 };
 530
 531 /*QoS related.*/
 532 /*acm implementation method.*/
 533 enum acm_method {
 534         eAcmWay0_SwAndHw = 0,
 535         eAcmWay1_HW = 1,
 536         eAcmWay2_SW = 2,
 537 };
 538
 539 enum macphy_mode {
 540         SINGLEMAC_SINGLEPHY = 0,
 541         DUALMAC_DUALPHY,
 542         DUALMAC_SINGLEPHY,
 543 };
 544
 545 enum band_type {
 546         BAND_ON_2_4G = 0,
 547         BAND_ON_5G,
 548         BAND_ON_BOTH,
 549         BANDMAX
 550 };
 551
 552 /*aci/aifsn Field.
 553 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
 554 union aci_aifsn {
 555         u8 char_data;
 556
 557         struct {
 558                 u8 aifsn:4;
 559                 u8 acm:1;
 560                 u8 aci:2;
 561                 u8 reserved:1;
 562         } f;                    /* Field */
 563 };
 564
 565 /*mlme related.*/
 566 enum wireless_mode {
 567         WIRELESS_MODE_UNKNOWN = 0x00,
 568         WIRELESS_MODE_A = 0x01,
 569         WIRELESS_MODE_B = 0x02,
 570         WIRELESS_MODE_G = 0x04,
 571         WIRELESS_MODE_AUTO = 0x08,
 572         WIRELESS_MODE_N_24G = 0x10,
 573         WIRELESS_MODE_N_5G = 0x20
 574 };
 575
 576 #define IS_WIRELESS_MODE_A(wirelessmode)        \
 577         (wirelessmode == WIRELESS_MODE_A)
 578 #define IS_WIRELESS_MODE_B(wirelessmode)        \
 579         (wirelessmode == WIRELESS_MODE_B)
 580 #define IS_WIRELESS_MODE_G(wirelessmode)        \
 581         (wirelessmode == WIRELESS_MODE_G)
 582 #define IS_WIRELESS_MODE_N_24G(wirelessmode)    \
 583         (wirelessmode == WIRELESS_MODE_N_24G)
 584 #define IS_WIRELESS_MODE_N_5G(wirelessmode)     \
 585         (wirelessmode == WIRELESS_MODE_N_5G)
 586
 587 enum ratr_table_mode {
 588         RATR_INX_WIRELESS_NGB = 0,
 589         RATR_INX_WIRELESS_NG = 1,
 590         RATR_INX_WIRELESS_NB = 2,
 591         RATR_INX_WIRELESS_N = 3,
 592         RATR_INX_WIRELESS_GB = 4,
 593         RATR_INX_WIRELESS_G = 5,
 594         RATR_INX_WIRELESS_B = 6,
 595         RATR_INX_WIRELESS_MC = 7,
 596         RATR_INX_WIRELESS_A = 8,
 597 };
 598
 599 enum rtl_link_state {
 600         MAC80211_NOLINK = 0,
 601         MAC80211_LINKING = 1,
 602         MAC80211_LINKED = 2,
 603         MAC80211_LINKED_SCANNING = 3,
 604 };
 605
 606 enum act_category {
 607         ACT_CAT_QOS = 1,
 608         ACT_CAT_DLS = 2,
 609         ACT_CAT_BA = 3,
 610         ACT_CAT_HT = 7,
 611         ACT_CAT_WMM = 17,
 612 };
 613
 614 enum ba_action {
 615         ACT_ADDBAREQ = 0,
 616         ACT_ADDBARSP = 1,
 617         ACT_DELBA = 2,
 618 };
 619
 620 struct octet_string {
 621         u8 *octet;
 622         u16 length;
 623 };
 624
 625 struct rtl_hdr_3addr {
 626         __le16 frame_ctl;
 627         __le16 duration_id;
 628         u8 addr1[ETH_ALEN];
 629         u8 addr2[ETH_ALEN];
 630         u8 addr3[ETH_ALEN];
 631         __le16 seq_ctl;
 632         u8 payload[0];
 633 } __packed;
 634
 635 struct rtl_info_element {
 636         u8 id;
 637         u8 len;
 638         u8 data[0];
 639 } __packed;
 640
 641 struct rtl_probe_rsp {
 642         struct rtl_hdr_3addr header;
 643         u32 time_stamp[2];
 644         __le16 beacon_interval;
 645         __le16 capability;
 646         /*SSID, supported rates, FH params, DS params,
 647            CF params, IBSS params, TIM (if beacon), RSN */
 648         struct rtl_info_element info_element[0];
 649 } __packed;
 650
 651 /*LED related.*/
 652 /*ledpin Identify how to implement this SW led.*/
 653 struct rtl_led {
 654         void *hw;
 655         enum rtl_led_pin ledpin;
 656         bool ledon;
 657 };
 658
 659 struct rtl_led_ctl {
 660         bool led_opendrain;
 661         struct rtl_led sw_led0;
 662         struct rtl_led sw_led1;
 663 };
 664
 665 struct rtl_qos_parameters {
 666         __le16 cw_min;
 667         __le16 cw_max;
 668         u8 aifs;
 669         u8 flag;
 670         __le16 tx_op;
 671 } __packed;
 672
 673 struct rt_smooth_data {
 674         u32 elements[100];      /*array to store values */
 675         u32 index;              /*index to current array to store */
 676         u32 total_num;          /*num of valid elements */
 677         u32 total_val;          /*sum of valid elements */
 678 };
 679
 680 struct false_alarm_statistics {
 681         u32 cnt_parity_fail;
 682         u32 cnt_rate_illegal;
 683         u32 cnt_crc8_fail;
 684         u32 cnt_mcs_fail;
 685         u32 cnt_fast_fsync_fail;
 686         u32 cnt_sb_search_fail;
 687         u32 cnt_ofdm_fail;
 688         u32 cnt_cck_fail;
 689         u32 cnt_all;
 690 };
 691
 692 struct init_gain {
 693         u8 xaagccore1;
 694         u8 xbagccore1;
 695         u8 xcagccore1;
 696         u8 xdagccore1;
 697         u8 cca;
 698
 699 };
 700
 701 struct wireless_stats {
 702         unsigned long txbytesunicast;
 703         unsigned long txbytesmulticast;
 704         unsigned long txbytesbroadcast;
 705         unsigned long rxbytesunicast;
 706
 707         long rx_snr_db[4];
 708         /*Correct smoothed ss in Dbm, only used
 709            in driver to report real power now. */
 710         long recv_signal_power;
 711         long signal_quality;
 712         long last_sigstrength_inpercent;
 713
 714         u32 rssi_calculate_cnt;
 715
 716         /*Transformed, in dbm. Beautified signal
 717            strength for UI, not correct. */
 718         long signal_strength;
 719
 720         u8 rx_rssi_percentage[4];
 721         u8 rx_evm_percentage[2];
 722
 723         struct rt_smooth_data ui_rssi;
 724         struct rt_smooth_data ui_link_quality;
 725 };
 726
 727 struct rate_adaptive {
 728         u8 rate_adaptive_disabled;
 729         u8 ratr_state;
 730         u16 reserve;
 731
 732         u32 high_rssi_thresh_for_ra;
 733         u32 high2low_rssi_thresh_for_ra;
 734         u8 low2high_rssi_thresh_for_ra40m;
 735         u32 low_rssi_thresh_for_ra40M;
 736         u8 low2high_rssi_thresh_for_ra20m;
 737         u32 low_rssi_thresh_for_ra20M;
 738         u32 upper_rssi_threshold_ratr;
 739         u32 middleupper_rssi_threshold_ratr;
 740         u32 middle_rssi_threshold_ratr;
 741         u32 middlelow_rssi_threshold_ratr;
 742         u32 low_rssi_threshold_ratr;
 743         u32 ultralow_rssi_threshold_ratr;
 744         u32 low_rssi_threshold_ratr_40m;
 745         u32 low_rssi_threshold_ratr_20m;
 746         u8 ping_rssi_enable;
 747         u32 ping_rssi_ratr;
 748         u32 ping_rssi_thresh_for_ra;
 749         u32 last_ratr;
 750         u8 pre_ratr_state;
 751 };
 752
 753 struct regd_pair_mapping {
 754         u16 reg_dmnenum;
 755         u16 reg_5ghz_ctl;
 756         u16 reg_2ghz_ctl;
 757 };
 758
 759 struct rtl_regulatory {
 760         char alpha2[2];
 761         u16 country_code;
 762         u16 max_power_level;
 763         u32 tp_scale;
 764         u16 current_rd;
 765         u16 current_rd_ext;
 766         int16_t power_limit;
 767         struct regd_pair_mapping *regpair;
 768 };
 769
 770 struct rtl_rfkill {
 771         bool rfkill_state;      /*0 is off, 1 is on */
 772 };
 773
 774 #define IQK_MATRIX_REG_NUM      8
 775 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
 776 struct iqk_matrix_regs {
 777         bool iqk_done;
 778         long value[1][IQK_MATRIX_REG_NUM];
 779 };
 780
 781 struct phy_parameters {
 782         u16 length;
 783         u32 *pdata;
 784 };
 785
 786 enum hw_param_tab_index {
 787         PHY_REG_2T,
 788         PHY_REG_1T,
 789         PHY_REG_PG,
 790         RADIOA_2T,
 791         RADIOB_2T,
 792         RADIOA_1T,
 793         RADIOB_1T,
 794         MAC_REG,
 795         AGCTAB_2T,
 796         AGCTAB_1T,
 797         MAX_TAB
 798 };
 799
 800 struct rtl_phy {
 801         struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
 802         struct init_gain initgain_backup;
 803         enum io_type current_io_type;
 804
 805         u8 rf_mode;
 806         u8 rf_type;
 807         u8 current_chan_bw;
 808         u8 set_bwmode_inprogress;
 809         u8 sw_chnl_inprogress;
 810         u8 sw_chnl_stage;
 811         u8 sw_chnl_step;
 812         u8 current_channel;
 813         u8 h2c_box_num;
 814         u8 set_io_inprogress;
 815         u8 lck_inprogress;
 816
 817         /* record for power tracking */
 818         s32 reg_e94;
 819         s32 reg_e9c;
 820         s32 reg_ea4;
 821         s32 reg_eac;
 822         s32 reg_eb4;
 823         s32 reg_ebc;
 824         s32 reg_ec4;
 825         s32 reg_ecc;
 826         u8 rfpienable;
 827         u8 reserve_0;
 828         u16 reserve_1;
 829         u32 reg_c04, reg_c08, reg_874;
 830         u32 adda_backup[16];
 831         u32 iqk_mac_backup[IQK_MAC_REG_NUM];
 832         u32 iqk_bb_backup[10];
 833
 834         /* Dual mac */
 835         bool need_iqk;
 836         struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
 837
 838         bool rfpi_enable;
 839
 840         u8 pwrgroup_cnt;
 841         u8 cck_high_power;
 842         /* MAX_PG_GROUP groups of pwr diff by rates */
 843         u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
 844         u8 default_initialgain[4];
 845
 846         /* the current Tx power level */
 847         u8 cur_cck_txpwridx;
 848         u8 cur_ofdm24g_txpwridx;
 849
 850         u32 rfreg_chnlval[2];
 851         bool apk_done;
 852         u32 reg_rf3c[2];        /* pathA / pathB  */
 853
 854         /* bfsync */
 855         u8 framesync;
 856         u32 framesync_c34;
 857
 858         u8 num_total_rfpath;
 859         struct phy_parameters hwparam_tables[MAX_TAB];
 860         u16 rf_pathmap;
 861 };
 862
 863 #define MAX_TID_COUNT                           9
 864 #define RTL_AGG_STOP                            0
 865 #define RTL_AGG_PROGRESS                        1
 866 #define RTL_AGG_START                           2
 867 #define RTL_AGG_OPERATIONAL                     3
 868 #define RTL_AGG_OFF                             0
 869 #define RTL_AGG_ON                              1
 870 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
 871 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
 872
 873 struct rtl_ht_agg {
 874         u16 txq_id;
 875         u16 wait_for_ba;
 876         u16 start_idx;
 877         u64 bitmap;
 878         u32 rate_n_flags;
 879         u8 agg_state;
 880 };
 881
 882 struct rtl_tid_data {
 883         u16 seq_number;
 884         struct rtl_ht_agg agg;
 885 };
 886
 887 struct rtl_sta_info {
 888         u8 ratr_index;
 889         u8 wireless_mode;
 890         u8 mimo_ps;
 891         struct rtl_tid_data tids[MAX_TID_COUNT];
 892 } __packed;
 893
 894 struct rtl_priv;
 895 struct rtl_io {
 896         struct device *dev;
 897         struct mutex bb_mutex;
 898
 899         /*PCI MEM map */
 900         unsigned long pci_mem_end;      /*shared mem end        */
 901         unsigned long pci_mem_start;    /*shared mem start */
 902
 903         /*PCI IO map */
 904         unsigned long pci_base_addr;    /*device I/O address */
 905
 906         void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
 907         void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
 908         void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
 909         int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
 910                              u8 *pdata);
 911
 912         u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
 913         u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
 914         u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
 915         int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
 916                             u8 *pdata);
 917
 918 };
 919
 920 struct rtl_mac {
 921         u8 mac_addr[ETH_ALEN];
 922         u8 mac80211_registered;
 923         u8 beacon_enabled;
 924
 925         u32 tx_ss_num;
 926         u32 rx_ss_num;
 927
 928         struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
 929         struct ieee80211_hw *hw;
 930         struct ieee80211_vif *vif;
 931         enum nl80211_iftype opmode;
 932
 933         /*Probe Beacon management */
 934         struct rtl_tid_data tids[MAX_TID_COUNT];
 935         enum rtl_link_state link_state;
 936
 937         int n_channels;
 938         int n_bitrates;
 939
 940         bool offchan_deley;
 941
 942         /*filters */
 943         u32 rx_conf;
 944         u16 rx_mgt_filter;
 945         u16 rx_ctrl_filter;
 946         u16 rx_data_filter;
 947
 948         bool act_scanning;
 949         u8 cnt_after_linked;
 950
 951         /* early mode */
 952         /* skb wait queue */
 953         struct sk_buff_head skb_waitq[MAX_TID_COUNT];
 954         u8 earlymode_threshold;
 955
 956         /*RDG*/
 957         bool rdg_en;
 958
 959         /*AP*/
 960         u8 bssid[6];
 961         u32 vendor;
 962         u8 mcs[16];     /* 16 bytes mcs for HT rates. */
 963         u32 basic_rates; /* b/g rates */
 964         u8 ht_enable;
 965         u8 sgi_40;
 966         u8 sgi_20;
 967         u8 bw_40;
 968         u8 mode;                /* wireless mode */
 969         u8 slot_time;
 970         u8 short_preamble;
 971         u8 use_cts_protect;
 972         u8 cur_40_prime_sc;
 973         u8 cur_40_prime_sc_bk;
 974         u64 tsf;
 975         u8 retry_short;
 976         u8 retry_long;
 977         u16 assoc_id;
 978
 979         /*IBSS*/
 980         int beacon_interval;
 981
 982         /*AMPDU*/
 983         u8 min_space_cfg;       /*For Min spacing configurations */
 984         u8 max_mss_density;
 985         u8 current_ampdu_factor;
 986         u8 current_ampdu_density;
 987
 988         /*QOS & EDCA */
 989         struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
 990         struct rtl_qos_parameters ac[AC_MAX];
 991 };
 992
 993 struct rtl_hal {
 994         struct ieee80211_hw *hw;
 995
 996         enum intf_type interface;
 997         u16 hw_type;            /*92c or 92d or 92s and so on */
 998         u8 ic_class;
 999         u8 oem_id;
1000         u32 version;            /*version of chip */
1001         u8 state;               /*stop 0, start 1 */
1002
1003         /*firmware */
1004         u32 fwsize;
1005         u8 *pfirmware;
1006         u16 fw_version;
1007         u16 fw_subversion;
1008         bool h2c_setinprogress;
1009         u8 last_hmeboxnum;
1010         bool fw_ready;
1011         /*Reserve page start offset except beacon in TxQ. */
1012         u8 fw_rsvdpage_startoffset;
1013         u8 h2c_txcmd_seq;
1014
1015         /* FW Cmd IO related */
1016         u16 fwcmd_iomap;
1017         u32 fwcmd_ioparam;
1018         bool set_fwcmd_inprogress;
1019         u8 current_fwcmd_io;
1020
1021         /**/
1022         bool driver_going2unload;
1023
1024         /*AMPDU init min space*/
1025         u8 minspace_cfg;        /*For Min spacing configurations */
1026
1027         /* Dual mac */
1028         enum macphy_mode macphymode;
1029         enum band_type current_bandtype;        /* 0:2.4G, 1:5G */
1030         enum band_type current_bandtypebackup;
1031         enum band_type bandset;
1032         /* dual MAC 0--Mac0 1--Mac1 */
1033         u32 interfaceindex;
1034         /* just for DualMac S3S4 */
1035         u8 macphyctl_reg;
1036         bool earlymode_enable;
1037         /* Dual mac*/
1038         bool during_mac0init_radiob;
1039         bool during_mac1init_radioa;
1040         bool reloadtxpowerindex;
1041         /* True if IMR or IQK  have done
1042         for 2.4G in scan progress */
1043         bool load_imrandiqk_setting_for2g;
1044
1045         bool disable_amsdu_8k;
1046 };
1047
1048 struct rtl_security {
1049         /*default 0 */
1050         bool use_sw_sec;
1051
1052         bool being_setkey;
1053         bool use_defaultkey;
1054         /*Encryption Algorithm for Unicast Packet */
1055         enum rt_enc_alg pairwise_enc_algorithm;
1056         /*Encryption Algorithm for Brocast/Multicast */
1057         enum rt_enc_alg group_enc_algorithm;
1058         /*Cam Entry Bitmap */
1059         u32 hwsec_cam_bitmap;
1060         u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1061         /*local Key buffer, indx 0 is for
1062            pairwise key 1-4 is for agoup key. */
1063         u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1064         u8 key_len[KEY_BUF_SIZE];
1065
1066         /*The pointer of Pairwise Key,
1067            it always points to KeyBuf[4] */
1068         u8 *pairwise_key;
1069 };
1070
1071 struct rtl_dm {
1072         /*PHY status for Dynamic Management */
1073         long entry_min_undecoratedsmoothed_pwdb;
1074         long undecorated_smoothed_pwdb; /*out dm */
1075         long entry_max_undecoratedsmoothed_pwdb;
1076         bool dm_initialgain_enable;
1077         bool dynamic_txpower_enable;
1078         bool current_turbo_edca;
1079         bool is_any_nonbepkts;  /*out dm */
1080         bool is_cur_rdlstate;
1081         bool txpower_trackinginit;
1082         bool disable_framebursting;
1083         bool cck_inch14;
1084         bool txpower_tracking;
1085         bool useramask;
1086         bool rfpath_rxenable[4];
1087         bool inform_fw_driverctrldm;
1088         bool current_mrc_switch;
1089         u8 txpowercount;
1090
1091         u8 thermalvalue_rxgain;
1092         u8 thermalvalue_iqk;
1093         u8 thermalvalue_lck;
1094         u8 thermalvalue;
1095         u8 last_dtp_lvl;
1096         u8 thermalvalue_avg[AVG_THERMAL_NUM];
1097         u8 thermalvalue_avg_index;
1098         bool done_txpower;
1099         u8 dynamic_txhighpower_lvl;     /*Tx high power level */
1100         u8 dm_flag;             /*Indicate each dynamic mechanism's status. */
1101         u8 dm_type;
1102         u8 txpower_track_control;
1103         bool interrupt_migration;
1104         bool disable_tx_int;
1105         char ofdm_index[2];
1106         char cck_index;
1107 };
1108
1109 #define EFUSE_MAX_LOGICAL_SIZE                  256
1110
1111 struct rtl_efuse {
1112         bool autoLoad_ok;
1113         bool bootfromefuse;
1114         u16 max_physical_size;
1115
1116         u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1117         u16 efuse_usedbytes;
1118         u8 efuse_usedpercentage;
1119 #ifdef EFUSE_REPG_WORKAROUND
1120         bool efuse_re_pg_sec1flag;
1121         u8 efuse_re_pg_data[8];
1122 #endif
1123
1124         u8 autoload_failflag;
1125         u8 autoload_status;
1126
1127         short epromtype;
1128         u16 eeprom_vid;
1129         u16 eeprom_did;
1130         u16 eeprom_svid;
1131         u16 eeprom_smid;
1132         u8 eeprom_oemid;
1133         u16 eeprom_channelplan;
1134         u8 eeprom_version;
1135         u8 board_type;
1136         u8 external_pa;
1137
1138         u8 dev_addr[6];
1139
1140         bool txpwr_fromeprom;
1141         u8 eeprom_crystalcap;
1142         u8 eeprom_tssi[2];
1143         u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1144         u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1145         u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1146         u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1147         u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1148         u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1149         u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1150         u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1151         u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER];   /*For HT 40MHZ pwr */
1152
1153         u8 internal_pa_5g[2];   /* pathA / pathB */
1154         u8 eeprom_c9;
1155         u8 eeprom_cc;
1156
1157         /*For power group */
1158         u8 eeprom_pwrgroup[2][3];
1159         u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1160         u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1161
1162         char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1163         /*For HT<->legacy pwr diff*/
1164         u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1165         u8 txpwr_safetyflag;                    /* Band edge enable flag */
1166         u16 eeprom_txpowerdiff;
1167         u8 legacy_httxpowerdiff;        /* Legacy to HT rate power diff */
1168         u8 antenna_txpwdiff[3];
1169
1170         u8 eeprom_regulatory;
1171         u8 eeprom_thermalmeter;
1172         u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1173         u16 tssi_13dbm;
1174         u8 crystalcap;          /* CrystalCap. */
1175         u8 delta_iqk;
1176         u8 delta_lck;
1177
1178         u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
1179         bool apk_thermalmeterignore;
1180
1181         bool b1x1_recvcombine;
1182         bool b1ss_support;
1183
1184         /*channel plan */
1185         u8 channel_plan;
1186 };
1187
1188 struct rtl_ps_ctl {
1189         bool pwrdomain_protect;
1190         bool in_powersavemode;
1191         bool rfchange_inprogress;
1192         bool swrf_processing;
1193         bool hwradiooff;
1194
1195         /*
1196          * just for PCIE ASPM
1197          * If it supports ASPM, Offset[560h] = 0x40,
1198          * otherwise Offset[560h] = 0x00.
1199          * */
1200         bool support_aspm;
1201
1202         bool support_backdoor;
1203
1204         /*for LPS */
1205         enum rt_psmode dot11_psmode;    /*Power save mode configured. */
1206         bool swctrl_lps;
1207         bool leisure_ps;
1208         bool fwctrl_lps;
1209         u8 fwctrl_psmode;
1210         /*For Fw control LPS mode */
1211         u8 reg_fwctrl_lps;
1212         /*Record Fw PS mode status. */
1213         bool fw_current_inpsmode;
1214         u8 reg_max_lps_awakeintvl;
1215         bool report_linked;
1216
1217         /*for IPS */
1218         bool inactiveps;
1219
1220         u32 rfoff_reason;
1221
1222         /*RF OFF Level */
1223         u32 cur_ps_level;
1224         u32 reg_rfps_level;
1225
1226         /*just for PCIE ASPM */
1227         u8 const_amdpci_aspm;
1228         bool pwrdown_mode;
1229
1230         enum rf_pwrstate inactive_pwrstate;
1231         enum rf_pwrstate rfpwr_state;   /*cur power state */
1232
1233         /* for SW LPS*/
1234         bool sw_ps_enabled;
1235         bool state;
1236         bool state_inap;
1237         bool multi_buffered;
1238         u16 nullfunc_seq;
1239         unsigned int dtim_counter;
1240         unsigned int sleep_ms;
1241         unsigned long last_sleep_jiffies;
1242         unsigned long last_awake_jiffies;
1243         unsigned long last_delaylps_stamp_jiffies;
1244         unsigned long last_dtim;
1245         unsigned long last_beacon;
1246         unsigned long last_action;
1247         unsigned long last_slept;
1248 };
1249
1250 struct rtl_stats {
1251         u32 mac_time[2];
1252         s8 rssi;
1253         u8 signal;
1254         u8 noise;
1255         u16 rate;               /*in 100 kbps */
1256         u8 received_channel;
1257         u8 control;
1258         u8 mask;
1259         u8 freq;
1260         u16 len;
1261         u64 tsf;
1262         u32 beacon_time;
1263         u8 nic_type;
1264         u16 length;
1265         u8 signalquality;       /*in 0-100 index. */
1266         /*
1267          * Real power in dBm for this packet,
1268          * no beautification and aggregation.
1269          * */
1270         s32 recvsignalpower;
1271         s8 rxpower;             /*in dBm Translate from PWdB */
1272         u8 signalstrength;      /*in 0-100 index. */
1273         u16 hwerror:1;
1274         u16 crc:1;
1275         u16 icv:1;
1276         u16 shortpreamble:1;
1277         u16 antenna:1;
1278         u16 decrypted:1;
1279         u16 wakeup:1;
1280         u32 timestamp_low;
1281         u32 timestamp_high;
1282
1283         u8 rx_drvinfo_size;
1284         u8 rx_bufshift;
1285         bool isampdu;
1286         bool isfirst_ampdu;
1287         bool rx_is40Mhzpacket;
1288         u32 rx_pwdb_all;
1289         u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
1290         s8 rx_mimo_signalquality[2];
1291         bool packet_matchbssid;
1292         bool is_cck;
1293         bool packet_toself;
1294         bool packet_beacon;     /*for rssi */
1295         char cck_adc_pwdb[4];   /*for rx path selection */
1296 };
1297
1298 struct rt_link_detect {
1299         u32 num_tx_in4period[4];
1300         u32 num_rx_in4period[4];
1301
1302         u32 num_tx_inperiod;
1303         u32 num_rx_inperiod;
1304
1305         bool busytraffic;
1306         bool higher_busytraffic;
1307         bool higher_busyrxtraffic;
1308
1309         u32 tidtx_in4period[MAX_TID_COUNT][4];
1310         u32 tidtx_inperiod[MAX_TID_COUNT];
1311         bool higher_busytxtraffic[MAX_TID_COUNT];
1312 };
1313
1314 struct rtl_tcb_desc {
1315         u8 packet_bw:1;
1316         u8 multicast:1;
1317         u8 broadcast:1;
1318
1319         u8 rts_stbc:1;
1320         u8 rts_enable:1;
1321         u8 cts_enable:1;
1322         u8 rts_use_shortpreamble:1;
1323         u8 rts_use_shortgi:1;
1324         u8 rts_sc:1;
1325         u8 rts_bw:1;
1326         u8 rts_rate;
1327
1328         u8 use_shortgi:1;
1329         u8 use_shortpreamble:1;
1330         u8 use_driver_rate:1;
1331         u8 disable_ratefallback:1;
1332
1333         u8 ratr_index;
1334         u8 mac_id;
1335         u8 hw_rate;
1336
1337         u8 last_inipkt:1;
1338         u8 cmd_or_init:1;
1339         u8 queue_index;
1340
1341         /* early mode */
1342         u8 empkt_num;
1343         /* The max value by HW */
1344         u32 empkt_len[5];
1345 };
1346
1347 struct rtl_hal_ops {
1348         int (*init_sw_vars) (struct ieee80211_hw *hw);
1349         void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1350         void (*read_chip_version)(struct ieee80211_hw *hw);
1351         void (*read_eeprom_info) (struct ieee80211_hw *hw);
1352         void (*interrupt_recognized) (struct ieee80211_hw *hw,
1353                                       u32 *p_inta, u32 *p_intb);
1354         int (*hw_init) (struct ieee80211_hw *hw);
1355         void (*hw_disable) (struct ieee80211_hw *hw);
1356         void (*hw_suspend) (struct ieee80211_hw *hw);
1357         void (*hw_resume) (struct ieee80211_hw *hw);
1358         void (*enable_interrupt) (struct ieee80211_hw *hw);
1359         void (*disable_interrupt) (struct ieee80211_hw *hw);
1360         int (*set_network_type) (struct ieee80211_hw *hw,
1361                                  enum nl80211_iftype type);
1362         void (*set_chk_bssid)(struct ieee80211_hw *hw,
1363                                 bool check_bssid);
1364         void (*set_bw_mode) (struct ieee80211_hw *hw,
1365                              enum nl80211_channel_type ch_type);
1366          u8(*switch_channel) (struct ieee80211_hw *hw);
1367         void (*set_qos) (struct ieee80211_hw *hw, int aci);
1368         void (*set_bcn_reg) (struct ieee80211_hw *hw);
1369         void (*set_bcn_intv) (struct ieee80211_hw *hw);
1370         void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1371                                        u32 add_msr, u32 rm_msr);
1372         void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1373         void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1374         void (*update_rate_tbl) (struct ieee80211_hw *hw,
1375                               struct ieee80211_sta *sta, u8 rssi_level);
1376         void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1377         void (*fill_tx_desc) (struct ieee80211_hw *hw,
1378                               struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1379                               struct ieee80211_tx_info *info,
1380                               struct sk_buff *skb, u8 hw_queue,
1381                               struct rtl_tcb_desc *ptcb_desc);
1382         void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1383                                   u32 buffer_len, bool bIsPsPoll);
1384         void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1385                                  bool firstseg, bool lastseg,
1386                                  struct sk_buff *skb);
1387         bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1388         bool (*query_rx_desc) (struct ieee80211_hw *hw,
1389                                struct rtl_stats *stats,
1390                                struct ieee80211_rx_status *rx_status,
1391                                u8 *pdesc, struct sk_buff *skb);
1392         void (*set_channel_access) (struct ieee80211_hw *hw);
1393         bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1394         void (*dm_watchdog) (struct ieee80211_hw *hw);
1395         void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1396         bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1397                                     enum rf_pwrstate rfpwr_state);
1398         void (*led_control) (struct ieee80211_hw *hw,
1399                              enum led_ctl_mode ledaction);
1400         void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1401         u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1402         void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1403         void (*enable_hw_sec) (struct ieee80211_hw *hw);
1404         void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1405                          u8 *macaddr, bool is_group, u8 enc_algo,
1406                          bool is_wepkey, bool clear_all);
1407         void (*init_sw_leds) (struct ieee80211_hw *hw);
1408         void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1409         u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1410         void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1411                            u32 data);
1412         u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1413                           u32 regaddr, u32 bitmask);
1414         void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1415                            u32 regaddr, u32 bitmask, u32 data);
1416         void (*linked_set_reg) (struct ieee80211_hw *hw);
1417         bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1418         void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1419                                             u8 *powerlevel);
1420         void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1421                                              u8 *ppowerlevel, u8 channel);
1422         bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1423                                            u8 configtype);
1424         bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1425                                              u8 configtype);
1426         void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1427         void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1428         void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1429 };
1430
1431 struct rtl_intf_ops {
1432         /*com */
1433         void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1434         int (*adapter_start) (struct ieee80211_hw *hw);
1435         void (*adapter_stop) (struct ieee80211_hw *hw);
1436
1437         int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1438                         struct rtl_tcb_desc *ptcb_desc);
1439         void (*flush)(struct ieee80211_hw *hw, bool drop);
1440         int (*reset_trx_ring) (struct ieee80211_hw *hw);
1441         bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1442
1443         /*pci */
1444         void (*disable_aspm) (struct ieee80211_hw *hw);
1445         void (*enable_aspm) (struct ieee80211_hw *hw);
1446
1447         /*usb */
1448 };
1449
1450 struct rtl_mod_params {
1451         /* default: 0 = using hardware encryption */
1452         int sw_crypto;
1453
1454         /* default: 1 = using no linked power save */
1455         bool inactiveps;
1456
1457         /* default: 1 = using linked sw power save */
1458         bool swctrl_lps;
1459
1460         /* default: 1 = using linked fw power save */
1461         bool fwctrl_lps;
1462 };
1463
1464 struct rtl_hal_usbint_cfg {
1465         /* data - rx */
1466         u32 in_ep_num;
1467         u32 rx_urb_num;
1468         u32 rx_max_size;
1469
1470         /* op - rx */
1471         void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1472         void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1473                                      struct sk_buff_head *);
1474
1475         /* tx */
1476         void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1477         int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1478                                struct sk_buff *);
1479         struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1480                                                 struct sk_buff_head *);
1481
1482         /* endpoint mapping */
1483         int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1484         u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1485 };
1486
1487 struct rtl_hal_cfg {
1488         u8 bar_id;
1489         bool write_readback;
1490         char *name;
1491         char *fw_name;
1492         struct rtl_hal_ops *ops;
1493         struct rtl_mod_params *mod_params;
1494         struct rtl_hal_usbint_cfg *usb_interface_cfg;
1495
1496         /*this map used for some registers or vars
1497            defined int HAL but used in MAIN */
1498         u32 maps[RTL_VAR_MAP_MAX];
1499
1500 };
1501
1502 struct rtl_locks {
1503         /* mutex */
1504         struct mutex conf_mutex;
1505
1506         /*spin lock */
1507         spinlock_t ips_lock;
1508         spinlock_t irq_th_lock;
1509         spinlock_t h2c_lock;
1510         spinlock_t rf_ps_lock;
1511         spinlock_t rf_lock;
1512         spinlock_t lps_lock;
1513         spinlock_t waitq_lock;
1514
1515         /*Dual mac*/
1516         spinlock_t cck_and_rw_pagea_lock;
1517 };
1518
1519 struct rtl_works {
1520         struct ieee80211_hw *hw;
1521
1522         /*timer */
1523         struct timer_list watchdog_timer;
1524
1525         /*task */
1526         struct tasklet_struct irq_tasklet;
1527         struct tasklet_struct irq_prepare_bcn_tasklet;
1528
1529         /*work queue */
1530         struct workqueue_struct *rtl_wq;
1531         struct delayed_work watchdog_wq;
1532         struct delayed_work ips_nic_off_wq;
1533
1534         /* For SW LPS */
1535         struct delayed_work ps_work;
1536         struct delayed_work ps_rfon_wq;
1537         struct tasklet_struct ips_leave_tasklet;
1538 };
1539
1540 struct rtl_debug {
1541         u32 dbgp_type[DBGP_TYPE_MAX];
1542         u32 global_debuglevel;
1543         u64 global_debugcomponents;
1544
1545         /* add for proc debug */
1546         struct proc_dir_entry *proc_dir;
1547         char proc_name[20];
1548 };
1549
1550 struct rtl_priv {
1551         struct rtl_locks locks;
1552         struct rtl_works works;
1553         struct rtl_mac mac80211;
1554         struct rtl_hal rtlhal;
1555         struct rtl_regulatory regd;
1556         struct rtl_rfkill rfkill;
1557         struct rtl_io io;
1558         struct rtl_phy phy;
1559         struct rtl_dm dm;
1560         struct rtl_security sec;
1561         struct rtl_efuse efuse;
1562
1563         struct rtl_ps_ctl psc;
1564         struct rate_adaptive ra;
1565         struct wireless_stats stats;
1566         struct rt_link_detect link_info;
1567         struct false_alarm_statistics falsealm_cnt;
1568
1569         struct rtl_rate_priv *rate_priv;
1570
1571         struct rtl_debug dbg;
1572
1573         /*
1574          *hal_cfg : for diff cards
1575          *intf_ops : for diff interrface usb/pcie
1576          */
1577         struct rtl_hal_cfg *cfg;
1578         struct rtl_intf_ops *intf_ops;
1579
1580         /*this var will be set by set_bit,
1581            and was used to indicate status of
1582            interface or hardware */
1583         unsigned long status;
1584
1585         /*This must be the last item so
1586            that it points to the data allocated
1587            beyond  this structure like:
1588            rtl_pci_priv or rtl_usb_priv */
1589         u8 priv[0];
1590 };
1591
1592 #define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
1593 #define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
1594 #define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
1595 #define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
1596 #define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
1597
1598
1599 /***************************************
1600     Bluetooth Co-existence Related
1601 ****************************************/
1602
1603 enum bt_ant_num {
1604         ANT_X2 = 0,
1605         ANT_X1 = 1,
1606 };
1607
1608 enum bt_co_type {
1609         BT_2WIRE = 0,
1610         BT_ISSC_3WIRE = 1,
1611         BT_ACCEL = 2,
1612         BT_CSR_BC4 = 3,
1613         BT_CSR_BC8 = 4,
1614         BT_RTL8756 = 5,
1615 };
1616
1617 enum bt_cur_state {
1618         BT_OFF = 0,
1619         BT_ON = 1,
1620 };
1621
1622 enum bt_service_type {
1623         BT_SCO = 0,
1624         BT_A2DP = 1,
1625         BT_HID = 2,
1626         BT_HID_IDLE = 3,
1627         BT_SCAN = 4,
1628         BT_IDLE = 5,
1629         BT_OTHER_ACTION = 6,
1630         BT_BUSY = 7,
1631         BT_OTHERBUSY = 8,
1632         BT_PAN = 9,
1633 };
1634
1635 enum bt_radio_shared {
1636         BT_RADIO_SHARED = 0,
1637         BT_RADIO_INDIVIDUAL = 1,
1638 };
1639
1640 struct bt_coexist_info {
1641
1642         /* EEPROM BT info. */
1643         u8 eeprom_bt_coexist;
1644         u8 eeprom_bt_type;
1645         u8 eeprom_bt_ant_num;
1646         u8 eeprom_bt_ant_isolation;
1647         u8 eeprom_bt_radio_shared;
1648
1649         u8 bt_coexistence;
1650         u8 bt_ant_num;
1651         u8 bt_coexist_type;
1652         u8 bt_state;
1653         u8 bt_cur_state;        /* 0:on, 1:off */
1654         u8 bt_ant_isolation;    /* 0:good, 1:bad */
1655         u8 bt_pape_ctrl;        /* 0:SW, 1:SW/HW dynamic */
1656         u8 bt_service;
1657         u8 bt_radio_shared_type;
1658         u8 bt_rfreg_origin_1e;
1659         u8 bt_rfreg_origin_1f;
1660         u8 bt_rssi_state;
1661         u32 ratio_tx;
1662         u32 ratio_pri;
1663         u32 bt_edca_ul;
1664         u32 bt_edca_dl;
1665
1666         bool init_set;
1667         bool bt_busy_traffic;
1668         bool bt_traffic_mode_set;
1669         bool bt_non_traffic_mode_set;
1670
1671         bool fw_coexist_all_off;
1672         bool sw_coexist_all_off;
1673         u32 current_state;
1674         u32 previous_state;
1675         u8 bt_pre_rssi_state;
1676
1677         u8 reg_bt_iso;
1678         u8 reg_bt_sco;
1679
1680 };
1681
1682
1683 /****************************************
1684         mem access macro define start
1685         Call endian free function when
1686         1. Read/write packet content.
1687         2. Before write integer to IO.
1688         3. After read integer from IO.
1689 ****************************************/
1690 /* Convert little data endian to host ordering */
1691 #define EF1BYTE(_val)           \
1692         ((u8)(_val))
1693 #define EF2BYTE(_val)           \
1694         (le16_to_cpu(_val))
1695 #define EF4BYTE(_val)           \
1696         (le32_to_cpu(_val))
1697
1698 /* Read data from memory */
1699 #define READEF1BYTE(_ptr)       \
1700         EF1BYTE(*((u8 *)(_ptr)))
1701 /* Read le16 data from memory and convert to host ordering */
1702 #define READEF2BYTE(_ptr)       \
1703         EF2BYTE(*((u16 *)(_ptr)))
1704 #define READEF4BYTE(_ptr)       \
1705         EF4BYTE(*((u32 *)(_ptr)))
1706
1707 /* Write data to memory */
1708 #define WRITEEF1BYTE(_ptr, _val)        \
1709         (*((u8 *)(_ptr))) = EF1BYTE(_val)
1710 /* Write le16 data to memory in host ordering */
1711 #define WRITEEF2BYTE(_ptr, _val)        \
1712         (*((u16 *)(_ptr))) = EF2BYTE(_val)
1713 #define WRITEEF4BYTE(_ptr, _val)        \
1714         (*((u16 *)(_ptr))) = EF2BYTE(_val)
1715
1716 /* Create a bit mask
1717  * Examples:
1718  * BIT_LEN_MASK_32(0) => 0x00000000
1719  * BIT_LEN_MASK_32(1) => 0x00000001
1720  * BIT_LEN_MASK_32(2) => 0x00000003
1721  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1722  */
1723 #define BIT_LEN_MASK_32(__bitlen)        \
1724         (0xFFFFFFFF >> (32 - (__bitlen)))
1725 #define BIT_LEN_MASK_16(__bitlen)        \
1726         (0xFFFF >> (16 - (__bitlen)))
1727 #define BIT_LEN_MASK_8(__bitlen) \
1728         (0xFF >> (8 - (__bitlen)))
1729
1730 /* Create an offset bit mask
1731  * Examples:
1732  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1733  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1734  */
1735 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1736         (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1737 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1738         (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1739 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1740         (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1741
1742 /*Description:
1743  * Return 4-byte value in host byte ordering from
1744  * 4-byte pointer in little-endian system.
1745  */
1746 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1747         (EF4BYTE(*((u32 *)(__pstart))))
1748 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1749         (EF2BYTE(*((u16 *)(__pstart))))
1750 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1751         (EF1BYTE(*((u8 *)(__pstart))))
1752
1753 /*Description:
1754 Translate subfield (continuous bits in little-endian) of 4-byte
1755 value to host byte ordering.*/
1756 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1757         ( \
1758                 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
1759                 BIT_LEN_MASK_32(__bitlen) \
1760         )
1761 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1762         ( \
1763                 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1764                 BIT_LEN_MASK_16(__bitlen) \
1765         )
1766 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1767         ( \
1768                 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1769                 BIT_LEN_MASK_8(__bitlen) \
1770         )
1771
1772 /* Description:
1773  * Mask subfield (continuous bits in little-endian) of 4-byte value
1774  * and return the result in 4-byte value in host byte ordering.
1775  */
1776 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1777         ( \
1778                 LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
1779                 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1780         )
1781 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1782         ( \
1783                 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1784                 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1785         )
1786 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1787         ( \
1788                 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1789                 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1790         )
1791
1792 /* Description:
1793  * Set subfield of little-endian 4-byte value to specified value.
1794  */
1795 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1796         *((u32 *)(__pstart)) = EF4BYTE \
1797         ( \
1798                 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1799                 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1800         );
1801 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1802         *((u16 *)(__pstart)) = EF2BYTE \
1803         ( \
1804                 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1805                 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1806         );
1807 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1808         *((u8 *)(__pstart)) = EF1BYTE \
1809         ( \
1810                 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1811                 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1812         );
1813
1814 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1815         (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1816
1817 /****************************************
1818         mem access macro define end
1819 ****************************************/
1820
1821 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1822
1823 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1824 #define RTL_WATCH_DOG_TIME      2000
1825 #define MSECS(t)                msecs_to_jiffies(t)
1826 #define WLAN_FC_GET_VERS(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1827 #define WLAN_FC_GET_TYPE(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1828 #define WLAN_FC_GET_STYPE(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1829 #define WLAN_FC_MORE_DATA(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1830 #define SEQ_TO_SN(seq)          (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1831 #define SN_TO_SEQ(ssn)          (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1832 #define MAX_SN                  ((IEEE80211_SCTL_SEQ) >> 4)
1833
1834 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
1835 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
1836 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
1837 /*NIC halt, re-initialize hw parameters*/
1838 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
1839 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
1840 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
1841 /*Always enable ASPM and Clock Req in initialization.*/
1842 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
1843 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1844 #define RT_PS_LEVEL_ASPM                BIT(7)
1845 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1846 #define RT_RF_LPS_DISALBE_2R            BIT(30)
1847 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
1848 #define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
1849         ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1850 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
1851         (ppsc->cur_ps_level &= (~(_ps_flg)))
1852 #define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
1853         (ppsc->cur_ps_level |= _ps_flg)
1854
1855 #define container_of_dwork_rtl(x, y, z) \
1856         container_of(container_of(x, struct delayed_work, work), y, z)
1857
1858 #define FILL_OCTET_STRING(_os, _octet, _len)    \
1859                 (_os).octet = (u8 *)(_octet);           \
1860                 (_os).length = (_len);
1861
1862 #define CP_MACADDR(des, src)    \
1863         ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1864         (des)[2] = (src)[2], (des)[3] = (src)[3],\
1865         (des)[4] = (src)[4], (des)[5] = (src)[5])
1866
1867 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1868 {
1869         return rtlpriv->io.read8_sync(rtlpriv, addr);
1870 }
1871
1872 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1873 {
1874         return rtlpriv->io.read16_sync(rtlpriv, addr);
1875 }
1876
1877 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1878 {
1879         return rtlpriv->io.read32_sync(rtlpriv, addr);
1880 }
1881
1882 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1883 {
1884         rtlpriv->io.write8_async(rtlpriv, addr, val8);
1885
1886         if (rtlpriv->cfg->write_readback)
1887                 rtlpriv->io.read8_sync(rtlpriv, addr);
1888 }
1889
1890 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1891 {
1892         rtlpriv->io.write16_async(rtlpriv, addr, val16);
1893
1894         if (rtlpriv->cfg->write_readback)
1895                 rtlpriv->io.read16_sync(rtlpriv, addr);
1896 }
1897
1898 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1899                                    u32 addr, u32 val32)
1900 {
1901         rtlpriv->io.write32_async(rtlpriv, addr, val32);
1902
1903         if (rtlpriv->cfg->write_readback)
1904                 rtlpriv->io.read32_sync(rtlpriv, addr);
1905 }
1906
1907 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1908                                 u32 regaddr, u32 bitmask)
1909 {
1910         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1911                                                                     regaddr,
1912                                                                     bitmask);
1913 }
1914
1915 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1916                                  u32 bitmask, u32 data)
1917 {
1918         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1919                                                              regaddr, bitmask,
1920                                                              data);
1921
1922 }
1923
1924 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1925                                 enum radio_path rfpath, u32 regaddr,
1926                                 u32 bitmask)
1927 {
1928         return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1929                                                                     rfpath,
1930                                                                     regaddr,
1931                                                                     bitmask);
1932 }
1933
1934 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1935                                  enum radio_path rfpath, u32 regaddr,
1936                                  u32 bitmask, u32 data)
1937 {
1938         ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1939                                                              rfpath, regaddr,
1940                                                              bitmask, data);
1941 }
1942
1943 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1944 {
1945         return (_HAL_STATE_STOP == rtlhal->state);
1946 }
1947
1948 static inline void set_hal_start(struct rtl_hal *rtlhal)
1949 {
1950         rtlhal->state = _HAL_STATE_START;
1951 }
1952
1953 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1954 {
1955         rtlhal->state = _HAL_STATE_STOP;
1956 }
1957
1958 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1959 {
1960         return rtlphy->rf_type;
1961 }
1962
1963 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
1964 {
1965         return (struct ieee80211_hdr *)(skb->data);
1966 }
1967
1968 static inline __le16 rtl_get_fc(struct sk_buff *skb)
1969 {
1970         return rtl_get_hdr(skb)->frame_control;
1971 }
1972
1973 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
1974 {
1975         return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
1976 }
1977
1978 static inline u16 rtl_get_tid(struct sk_buff *skb)
1979 {
1980         return rtl_get_tid_h(rtl_get_hdr(skb));
1981 }
1982
1983 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
1984                                             struct ieee80211_vif *vif,
1985                                             u8 *bssid)
1986 {
1987         return ieee80211_find_sta(vif, bssid);
1988 }
1989
1990 #endif