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wlcore: Propagate errors from wl1271_raw_write32
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ti / wl18xx / main.c
1 /*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25 #include <linux/firmware.h>
26
27 #include "../wlcore/wlcore.h"
28 #include "../wlcore/debug.h"
29 #include "../wlcore/io.h"
30 #include "../wlcore/acx.h"
31 #include "../wlcore/tx.h"
32 #include "../wlcore/rx.h"
33 #include "../wlcore/io.h"
34 #include "../wlcore/boot.h"
35
36 #include "reg.h"
37 #include "conf.h"
38 #include "acx.h"
39 #include "tx.h"
40 #include "wl18xx.h"
41 #include "io.h"
42 #include "debugfs.h"
43
44 #define WL18XX_RX_CHECKSUM_MASK 0x40
45
46 static char *ht_mode_param = "default";
47 static char *board_type_param = "hdk";
48 static bool checksum_param = false;
49 static bool enable_11a_param = true;
50 static int num_rx_desc_param = -1;
51
52 /* phy paramters */
53 static int dc2dc_param = -1;
54 static int n_antennas_2_param = -1;
55 static int n_antennas_5_param = -1;
56 static int low_band_component_param = -1;
57 static int low_band_component_type_param = -1;
58 static int high_band_component_param = -1;
59 static int high_band_component_type_param = -1;
60 static int pwr_limit_reference_11_abg_param = -1;
61
62 static const u8 wl18xx_rate_to_idx_2ghz[] = {
63 /* MCS rates are used only with 11n */
64 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
65 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
66 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
67 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
68 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
69 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
70 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
71 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
72 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
73 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
74 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
75 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
76 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
77 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
78 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
79 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
80
81 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
82 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
83 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
84 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
85
86 /* TI-specific rate */
87 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
88
89 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
90 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
91 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
92 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
93 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
94 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
95 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
96 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
97 };
98
99 static const u8 wl18xx_rate_to_idx_5ghz[] = {
100 /* MCS rates are used only with 11n */
101 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
102 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
103 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
104 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
105 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
106 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
107 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
108 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
109 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
110 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
111 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
112 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
113 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
114 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
115 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
116 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
117
118 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
119 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
120 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
121 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
122
123 /* TI-specific rate */
124 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
125
126 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
127 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
128 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
129 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
130 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
131 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
132 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
133 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
134 };
135
136 static const u8 *wl18xx_band_rate_to_idx[] = {
137 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
138 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
139 };
140
141 enum wl18xx_hw_rates {
142 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
143 WL18XX_CONF_HW_RXTX_RATE_MCS14,
144 WL18XX_CONF_HW_RXTX_RATE_MCS13,
145 WL18XX_CONF_HW_RXTX_RATE_MCS12,
146 WL18XX_CONF_HW_RXTX_RATE_MCS11,
147 WL18XX_CONF_HW_RXTX_RATE_MCS10,
148 WL18XX_CONF_HW_RXTX_RATE_MCS9,
149 WL18XX_CONF_HW_RXTX_RATE_MCS8,
150 WL18XX_CONF_HW_RXTX_RATE_MCS7,
151 WL18XX_CONF_HW_RXTX_RATE_MCS6,
152 WL18XX_CONF_HW_RXTX_RATE_MCS5,
153 WL18XX_CONF_HW_RXTX_RATE_MCS4,
154 WL18XX_CONF_HW_RXTX_RATE_MCS3,
155 WL18XX_CONF_HW_RXTX_RATE_MCS2,
156 WL18XX_CONF_HW_RXTX_RATE_MCS1,
157 WL18XX_CONF_HW_RXTX_RATE_MCS0,
158 WL18XX_CONF_HW_RXTX_RATE_54,
159 WL18XX_CONF_HW_RXTX_RATE_48,
160 WL18XX_CONF_HW_RXTX_RATE_36,
161 WL18XX_CONF_HW_RXTX_RATE_24,
162 WL18XX_CONF_HW_RXTX_RATE_22,
163 WL18XX_CONF_HW_RXTX_RATE_18,
164 WL18XX_CONF_HW_RXTX_RATE_12,
165 WL18XX_CONF_HW_RXTX_RATE_11,
166 WL18XX_CONF_HW_RXTX_RATE_9,
167 WL18XX_CONF_HW_RXTX_RATE_6,
168 WL18XX_CONF_HW_RXTX_RATE_5_5,
169 WL18XX_CONF_HW_RXTX_RATE_2,
170 WL18XX_CONF_HW_RXTX_RATE_1,
171 WL18XX_CONF_HW_RXTX_RATE_MAX,
172 };
173
174 static struct wlcore_conf wl18xx_conf = {
175 .sg = {
176 .params = {
177 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
178 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
179 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
180 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
181 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
182 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
183 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
184 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
185 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
186 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
187 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
188 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
189 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
190 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
191 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
192 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
193 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
194 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
195 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
196 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
197 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
198 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
199 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
200 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
201 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
202 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
203 /* active scan params */
204 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
205 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
206 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
207 /* passive scan params */
208 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
209 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
210 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
211 /* passive scan in dual antenna params */
212 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
213 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
214 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
215 /* general params */
216 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
217 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
218 [CONF_SG_BEACON_MISS_PERCENT] = 60,
219 [CONF_SG_DHCP_TIME] = 5000,
220 [CONF_SG_RXT] = 1200,
221 [CONF_SG_TXT] = 1000,
222 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
223 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
224 [CONF_SG_HV3_MAX_SERVED] = 6,
225 [CONF_SG_PS_POLL_TIMEOUT] = 10,
226 [CONF_SG_UPSD_TIMEOUT] = 10,
227 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
228 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
229 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
230 /* AP params */
231 [CONF_AP_BEACON_MISS_TX] = 3,
232 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
233 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
234 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
235 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
236 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
237 /* CTS Diluting params */
238 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
239 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
240 },
241 .state = CONF_SG_PROTECTIVE,
242 },
243 .rx = {
244 .rx_msdu_life_time = 512000,
245 .packet_detection_threshold = 0,
246 .ps_poll_timeout = 15,
247 .upsd_timeout = 15,
248 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
249 .rx_cca_threshold = 0,
250 .irq_blk_threshold = 0xFFFF,
251 .irq_pkt_threshold = 0,
252 .irq_timeout = 600,
253 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
254 },
255 .tx = {
256 .tx_energy_detection = 0,
257 .sta_rc_conf = {
258 .enabled_rates = 0,
259 .short_retry_limit = 10,
260 .long_retry_limit = 10,
261 .aflags = 0,
262 },
263 .ac_conf_count = 4,
264 .ac_conf = {
265 [CONF_TX_AC_BE] = {
266 .ac = CONF_TX_AC_BE,
267 .cw_min = 15,
268 .cw_max = 63,
269 .aifsn = 3,
270 .tx_op_limit = 0,
271 },
272 [CONF_TX_AC_BK] = {
273 .ac = CONF_TX_AC_BK,
274 .cw_min = 15,
275 .cw_max = 63,
276 .aifsn = 7,
277 .tx_op_limit = 0,
278 },
279 [CONF_TX_AC_VI] = {
280 .ac = CONF_TX_AC_VI,
281 .cw_min = 15,
282 .cw_max = 63,
283 .aifsn = CONF_TX_AIFS_PIFS,
284 .tx_op_limit = 3008,
285 },
286 [CONF_TX_AC_VO] = {
287 .ac = CONF_TX_AC_VO,
288 .cw_min = 15,
289 .cw_max = 63,
290 .aifsn = CONF_TX_AIFS_PIFS,
291 .tx_op_limit = 1504,
292 },
293 },
294 .max_tx_retries = 100,
295 .ap_aging_period = 300,
296 .tid_conf_count = 4,
297 .tid_conf = {
298 [CONF_TX_AC_BE] = {
299 .queue_id = CONF_TX_AC_BE,
300 .channel_type = CONF_CHANNEL_TYPE_EDCF,
301 .tsid = CONF_TX_AC_BE,
302 .ps_scheme = CONF_PS_SCHEME_LEGACY,
303 .ack_policy = CONF_ACK_POLICY_LEGACY,
304 .apsd_conf = {0, 0},
305 },
306 [CONF_TX_AC_BK] = {
307 .queue_id = CONF_TX_AC_BK,
308 .channel_type = CONF_CHANNEL_TYPE_EDCF,
309 .tsid = CONF_TX_AC_BK,
310 .ps_scheme = CONF_PS_SCHEME_LEGACY,
311 .ack_policy = CONF_ACK_POLICY_LEGACY,
312 .apsd_conf = {0, 0},
313 },
314 [CONF_TX_AC_VI] = {
315 .queue_id = CONF_TX_AC_VI,
316 .channel_type = CONF_CHANNEL_TYPE_EDCF,
317 .tsid = CONF_TX_AC_VI,
318 .ps_scheme = CONF_PS_SCHEME_LEGACY,
319 .ack_policy = CONF_ACK_POLICY_LEGACY,
320 .apsd_conf = {0, 0},
321 },
322 [CONF_TX_AC_VO] = {
323 .queue_id = CONF_TX_AC_VO,
324 .channel_type = CONF_CHANNEL_TYPE_EDCF,
325 .tsid = CONF_TX_AC_VO,
326 .ps_scheme = CONF_PS_SCHEME_LEGACY,
327 .ack_policy = CONF_ACK_POLICY_LEGACY,
328 .apsd_conf = {0, 0},
329 },
330 },
331 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
332 .tx_compl_timeout = 350,
333 .tx_compl_threshold = 10,
334 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
335 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
336 .tmpl_short_retry_limit = 10,
337 .tmpl_long_retry_limit = 10,
338 .tx_watchdog_timeout = 5000,
339 },
340 .conn = {
341 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
342 .listen_interval = 1,
343 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
344 .suspend_listen_interval = 3,
345 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
346 .bcn_filt_ie_count = 3,
347 .bcn_filt_ie = {
348 [0] = {
349 .ie = WLAN_EID_CHANNEL_SWITCH,
350 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
351 },
352 [1] = {
353 .ie = WLAN_EID_HT_OPERATION,
354 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
355 },
356 [2] = {
357 .ie = WLAN_EID_ERP_INFO,
358 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
359 },
360 },
361 .synch_fail_thold = 12,
362 .bss_lose_timeout = 400,
363 .beacon_rx_timeout = 10000,
364 .broadcast_timeout = 20000,
365 .rx_broadcast_in_ps = 1,
366 .ps_poll_threshold = 10,
367 .bet_enable = CONF_BET_MODE_ENABLE,
368 .bet_max_consecutive = 50,
369 .psm_entry_retries = 8,
370 .psm_exit_retries = 16,
371 .psm_entry_nullfunc_retries = 3,
372 .dynamic_ps_timeout = 200,
373 .forced_ps = false,
374 .keep_alive_interval = 55000,
375 .max_listen_interval = 20,
376 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
377 },
378 .itrim = {
379 .enable = false,
380 .timeout = 50000,
381 },
382 .pm_config = {
383 .host_clk_settling_time = 5000,
384 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
385 },
386 .roam_trigger = {
387 .trigger_pacing = 1,
388 .avg_weight_rssi_beacon = 20,
389 .avg_weight_rssi_data = 10,
390 .avg_weight_snr_beacon = 20,
391 .avg_weight_snr_data = 10,
392 },
393 .scan = {
394 .min_dwell_time_active = 7500,
395 .max_dwell_time_active = 30000,
396 .min_dwell_time_passive = 100000,
397 .max_dwell_time_passive = 100000,
398 .num_probe_reqs = 2,
399 .split_scan_timeout = 50000,
400 },
401 .sched_scan = {
402 /*
403 * Values are in TU/1000 but since sched scan FW command
404 * params are in TUs rounding up may occur.
405 */
406 .base_dwell_time = 7500,
407 .max_dwell_time_delta = 22500,
408 /* based on 250bits per probe @1Mbps */
409 .dwell_time_delta_per_probe = 2000,
410 /* based on 250bits per probe @6Mbps (plus a bit more) */
411 .dwell_time_delta_per_probe_5 = 350,
412 .dwell_time_passive = 100000,
413 .dwell_time_dfs = 150000,
414 .num_probe_reqs = 2,
415 .rssi_threshold = -90,
416 .snr_threshold = 0,
417 },
418 .ht = {
419 .rx_ba_win_size = 10,
420 .tx_ba_win_size = 64,
421 .inactivity_timeout = 10000,
422 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
423 },
424 .mem = {
425 .num_stations = 1,
426 .ssid_profiles = 1,
427 .rx_block_num = 40,
428 .tx_min_block_num = 40,
429 .dynamic_memory = 1,
430 .min_req_tx_blocks = 45,
431 .min_req_rx_blocks = 22,
432 .tx_min = 27,
433 },
434 .fm_coex = {
435 .enable = true,
436 .swallow_period = 5,
437 .n_divider_fref_set_1 = 0xff, /* default */
438 .n_divider_fref_set_2 = 12,
439 .m_divider_fref_set_1 = 0xffff,
440 .m_divider_fref_set_2 = 148, /* default */
441 .coex_pll_stabilization_time = 0xffffffff, /* default */
442 .ldo_stabilization_time = 0xffff, /* default */
443 .fm_disturbed_band_margin = 0xff, /* default */
444 .swallow_clk_diff = 0xff, /* default */
445 },
446 .rx_streaming = {
447 .duration = 150,
448 .queues = 0x1,
449 .interval = 20,
450 .always = 0,
451 },
452 .fwlog = {
453 .mode = WL12XX_FWLOG_ON_DEMAND,
454 .mem_blocks = 2,
455 .severity = 0,
456 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
457 .output = WL12XX_FWLOG_OUTPUT_HOST,
458 .threshold = 0,
459 },
460 .rate = {
461 .rate_retry_score = 32000,
462 .per_add = 8192,
463 .per_th1 = 2048,
464 .per_th2 = 4096,
465 .max_per = 8100,
466 .inverse_curiosity_factor = 5,
467 .tx_fail_low_th = 4,
468 .tx_fail_high_th = 10,
469 .per_alpha_shift = 4,
470 .per_add_shift = 13,
471 .per_beta1_shift = 10,
472 .per_beta2_shift = 8,
473 .rate_check_up = 2,
474 .rate_check_down = 12,
475 .rate_retry_policy = {
476 0x00, 0x00, 0x00, 0x00, 0x00,
477 0x00, 0x00, 0x00, 0x00, 0x00,
478 0x00, 0x00, 0x00,
479 },
480 },
481 .hangover = {
482 .recover_time = 0,
483 .hangover_period = 20,
484 .dynamic_mode = 1,
485 .early_termination_mode = 1,
486 .max_period = 20,
487 .min_period = 1,
488 .increase_delta = 1,
489 .decrease_delta = 2,
490 .quiet_time = 4,
491 .increase_time = 1,
492 .window_size = 16,
493 },
494 };
495
496 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
497 .phy = {
498 .phy_standalone = 0x00,
499 .primary_clock_setting_time = 0x05,
500 .clock_valid_on_wake_up = 0x00,
501 .secondary_clock_setting_time = 0x05,
502 .rdl = 0x01,
503 .auto_detect = 0x00,
504 .dedicated_fem = FEM_NONE,
505 .low_band_component = COMPONENT_2_WAY_SWITCH,
506 .low_band_component_type = 0x05,
507 .high_band_component = COMPONENT_2_WAY_SWITCH,
508 .high_band_component_type = 0x09,
509 .tcxo_ldo_voltage = 0x00,
510 .xtal_itrim_val = 0x04,
511 .srf_state = 0x00,
512 .io_configuration = 0x01,
513 .sdio_configuration = 0x00,
514 .settings = 0x00,
515 .enable_clpc = 0x00,
516 .enable_tx_low_pwr_on_siso_rdl = 0x00,
517 .rx_profile = 0x00,
518 .pwr_limit_reference_11_abg = 0xc8,
519 .psat = 0,
520 .low_power_val = 0x00,
521 .med_power_val = 0x0a,
522 .high_power_val = 0x1e,
523 .external_pa_dc2dc = 0,
524 .number_of_assembled_ant2_4 = 1,
525 .number_of_assembled_ant5 = 1,
526 },
527 };
528
529 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
530 [PART_TOP_PRCM_ELP_SOC] = {
531 .mem = { .start = 0x00A02000, .size = 0x00010000 },
532 .reg = { .start = 0x00807000, .size = 0x00005000 },
533 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
534 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
535 },
536 [PART_DOWN] = {
537 .mem = { .start = 0x00000000, .size = 0x00014000 },
538 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
539 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
540 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
541 },
542 [PART_BOOT] = {
543 .mem = { .start = 0x00700000, .size = 0x0000030c },
544 .reg = { .start = 0x00802000, .size = 0x00014578 },
545 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
546 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
547 },
548 [PART_WORK] = {
549 .mem = { .start = 0x00800000, .size = 0x000050FC },
550 .reg = { .start = 0x00B00404, .size = 0x00001000 },
551 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
552 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
553 },
554 [PART_PHY_INIT] = {
555 .mem = { .start = 0x80926000,
556 .size = sizeof(struct wl18xx_mac_and_phy_params) },
557 .reg = { .start = 0x00000000, .size = 0x00000000 },
558 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
559 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
560 },
561 };
562
563 static const int wl18xx_rtable[REG_TABLE_LEN] = {
564 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
565 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
566 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
567 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
568 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
569 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
570 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
571 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
572 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
573 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
574
575 /* data access memory addresses, used with partition translation */
576 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
577 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
578
579 /* raw data access memory addresses */
580 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
581 };
582
583 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
584 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
585 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
586 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
587 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
588 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
589 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
590 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
591 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
592 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
593 };
594
595 /* TODO: maybe move to a new header file? */
596 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
597
598 static int wl18xx_identify_chip(struct wl1271 *wl)
599 {
600 int ret = 0;
601
602 switch (wl->chip.id) {
603 case CHIP_ID_185x_PG20:
604 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
605 wl->chip.id);
606 wl->sr_fw_name = WL18XX_FW_NAME;
607 /* wl18xx uses the same firmware for PLT */
608 wl->plt_fw_name = WL18XX_FW_NAME;
609 wl->quirks |= WLCORE_QUIRK_NO_ELP |
610 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
611 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
612 WLCORE_QUIRK_TX_PAD_LAST_FRAME;
613 break;
614 case CHIP_ID_185x_PG10:
615 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
616 wl->chip.id);
617 wl->sr_fw_name = WL18XX_FW_NAME;
618 /* wl18xx uses the same firmware for PLT */
619 wl->plt_fw_name = WL18XX_FW_NAME;
620 wl->quirks |= WLCORE_QUIRK_NO_ELP |
621 WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
622 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
623 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
624
625 /* PG 1.0 has some problems with MCS_13, so disable it */
626 wl->ht_cap[IEEE80211_BAND_2GHZ].mcs.rx_mask[1] &= ~BIT(5);
627
628 break;
629 default:
630 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
631 ret = -ENODEV;
632 goto out;
633 }
634
635 out:
636 return ret;
637 }
638
639 static int wl18xx_set_clk(struct wl1271 *wl)
640 {
641 u16 clk_freq;
642 int ret;
643
644 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
645 if (ret < 0)
646 goto out;
647
648 /* TODO: PG2: apparently we need to read the clk type */
649
650 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
651 if (ret < 0)
652 goto out;
653
654 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
655 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
656 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
657 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
658
659 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
660 wl18xx_clk_table[clk_freq].n);
661 if (ret < 0)
662 goto out;
663
664 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
665 wl18xx_clk_table[clk_freq].m);
666 if (ret < 0)
667 goto out;
668
669 if (wl18xx_clk_table[clk_freq].swallow) {
670 /* first the 16 lower bits */
671 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
672 wl18xx_clk_table[clk_freq].q &
673 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
674 if (ret < 0)
675 goto out;
676
677 /* then the 16 higher bits, masked out */
678 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
679 (wl18xx_clk_table[clk_freq].q >> 16) &
680 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
681 if (ret < 0)
682 goto out;
683
684 /* first the 16 lower bits */
685 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
686 wl18xx_clk_table[clk_freq].p &
687 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
688 if (ret < 0)
689 goto out;
690
691 /* then the 16 higher bits, masked out */
692 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
693 (wl18xx_clk_table[clk_freq].p >> 16) &
694 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
695 } else {
696 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
697 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
698 }
699
700 out:
701 return ret;
702 }
703
704 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
705 {
706 int ret;
707
708 /* disable Rx/Tx */
709 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
710 if (ret < 0)
711 goto out;
712
713 /* disable auto calibration on start*/
714 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
715
716 out:
717 return ret;
718 }
719
720 static int wl18xx_pre_boot(struct wl1271 *wl)
721 {
722 int ret;
723
724 ret = wl18xx_set_clk(wl);
725 if (ret < 0)
726 goto out;
727
728 /* Continue the ELP wake up sequence */
729 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
730 if (ret < 0)
731 goto out;
732
733 udelay(500);
734
735 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
736 if (ret < 0)
737 goto out;
738
739 /* Disable interrupts */
740 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
741 if (ret < 0)
742 goto out;
743
744 ret = wl18xx_boot_soft_reset(wl);
745
746 out:
747 return ret;
748 }
749
750 static int wl18xx_pre_upload(struct wl1271 *wl)
751 {
752 u32 tmp;
753 int ret;
754
755 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
756 if (ret < 0)
757 goto out;
758
759 /* TODO: check if this is all needed */
760 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
761 if (ret < 0)
762 goto out;
763
764 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
765 if (ret < 0)
766 goto out;
767
768 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
769
770 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
771
772 out:
773 return ret;
774 }
775
776 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
777 {
778 struct wl18xx_priv *priv = wl->priv;
779 size_t len;
780 int ret;
781
782 /* the parameters struct is smaller for PG1 */
783 if (wl->chip.id == CHIP_ID_185x_PG10)
784 len = offsetof(struct wl18xx_mac_and_phy_params, psat) + 1;
785 else
786 len = sizeof(struct wl18xx_mac_and_phy_params);
787
788 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
789 if (ret < 0)
790 goto out;
791
792 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&priv->conf.phy,
793 len, false);
794
795 out:
796 return ret;
797 }
798
799 static int wl18xx_enable_interrupts(struct wl1271 *wl)
800 {
801 u32 event_mask, intr_mask;
802 int ret;
803
804 if (wl->chip.id == CHIP_ID_185x_PG10) {
805 event_mask = WL18XX_ACX_EVENTS_VECTOR_PG1;
806 intr_mask = WL18XX_INTR_MASK_PG1;
807 } else {
808 event_mask = WL18XX_ACX_EVENTS_VECTOR_PG2;
809 intr_mask = WL18XX_INTR_MASK_PG2;
810 }
811
812 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
813 if (ret < 0)
814 goto out;
815
816 wlcore_enable_interrupts(wl);
817
818 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
819 WL1271_ACX_INTR_ALL & ~intr_mask);
820
821 out:
822 return ret;
823 }
824
825 static int wl18xx_boot(struct wl1271 *wl)
826 {
827 int ret;
828
829 ret = wl18xx_pre_boot(wl);
830 if (ret < 0)
831 goto out;
832
833 ret = wl18xx_pre_upload(wl);
834 if (ret < 0)
835 goto out;
836
837 ret = wlcore_boot_upload_firmware(wl);
838 if (ret < 0)
839 goto out;
840
841 ret = wl18xx_set_mac_and_phy(wl);
842 if (ret < 0)
843 goto out;
844
845 ret = wlcore_boot_run_firmware(wl);
846 if (ret < 0)
847 goto out;
848
849 ret = wl18xx_enable_interrupts(wl);
850
851 out:
852 return ret;
853 }
854
855 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
856 void *buf, size_t len)
857 {
858 struct wl18xx_priv *priv = wl->priv;
859
860 memcpy(priv->cmd_buf, buf, len);
861 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
862
863 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
864 WL18XX_CMD_MAX_SIZE, false);
865 }
866
867 static int wl18xx_ack_event(struct wl1271 *wl)
868 {
869 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
870 WL18XX_INTR_TRIG_EVENT_ACK);
871 }
872
873 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
874 {
875 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
876 return (len + blk_size - 1) / blk_size + spare_blks;
877 }
878
879 static void
880 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
881 u32 blks, u32 spare_blks)
882 {
883 desc->wl18xx_mem.total_mem_blocks = blks;
884 }
885
886 static void
887 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
888 struct sk_buff *skb)
889 {
890 desc->length = cpu_to_le16(skb->len);
891
892 /* if only the last frame is to be padded, we unset this bit on Tx */
893 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
894 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
895 else
896 desc->wl18xx_mem.ctrl = 0;
897
898 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
899 "len: %d life: %d mem: %d", desc->hlid,
900 le16_to_cpu(desc->length),
901 le16_to_cpu(desc->life_time),
902 desc->wl18xx_mem.total_mem_blocks);
903 }
904
905 static enum wl_rx_buf_align
906 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
907 {
908 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
909 return WLCORE_RX_BUF_PADDED;
910
911 return WLCORE_RX_BUF_ALIGNED;
912 }
913
914 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
915 u32 data_len)
916 {
917 struct wl1271_rx_descriptor *desc = rx_data;
918
919 /* invalid packet */
920 if (data_len < sizeof(*desc))
921 return 0;
922
923 return data_len - sizeof(*desc);
924 }
925
926 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
927 {
928 wl18xx_tx_immediate_complete(wl);
929 }
930
931 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
932 {
933 int ret;
934 u32 sdio_align_size = 0;
935 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
936 HOST_IF_CFG_ADD_RX_ALIGNMENT;
937
938 /* Enable Tx SDIO padding */
939 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
940 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
941 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
942 }
943
944 /* Enable Rx SDIO padding */
945 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
946 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
947 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
948 }
949
950 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
951 sdio_align_size, extra_mem_blk,
952 WL18XX_HOST_IF_LEN_SIZE_FIELD);
953 if (ret < 0)
954 return ret;
955
956 return 0;
957 }
958
959 static int wl18xx_hw_init(struct wl1271 *wl)
960 {
961 int ret;
962 struct wl18xx_priv *priv = wl->priv;
963
964 /* (re)init private structures. Relevant on recovery as well. */
965 priv->last_fw_rls_idx = 0;
966 priv->extra_spare_vif_count = 0;
967
968 /* set the default amount of spare blocks in the bitmap */
969 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
970 if (ret < 0)
971 return ret;
972
973 if (checksum_param) {
974 ret = wl18xx_acx_set_checksum_state(wl);
975 if (ret != 0)
976 return ret;
977 }
978
979 return ret;
980 }
981
982 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
983 struct wl1271_tx_hw_descr *desc,
984 struct sk_buff *skb)
985 {
986 u32 ip_hdr_offset;
987 struct iphdr *ip_hdr;
988
989 if (!checksum_param) {
990 desc->wl18xx_checksum_data = 0;
991 return;
992 }
993
994 if (skb->ip_summed != CHECKSUM_PARTIAL) {
995 desc->wl18xx_checksum_data = 0;
996 return;
997 }
998
999 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1000 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1001 desc->wl18xx_checksum_data = 0;
1002 return;
1003 }
1004
1005 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1006
1007 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
1008 ip_hdr = (void *)skb_network_header(skb);
1009 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1010 }
1011
1012 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1013 struct wl1271_rx_descriptor *desc,
1014 struct sk_buff *skb)
1015 {
1016 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1017 skb->ip_summed = CHECKSUM_UNNECESSARY;
1018 }
1019
1020 /*
1021 * TODO: instead of having these two functions to get the rate mask,
1022 * we should modify the wlvif->rate_set instead
1023 */
1024 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1025 struct wl12xx_vif *wlvif)
1026 {
1027 u32 hw_rate_set = wlvif->rate_set;
1028
1029 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1030 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1031 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1032 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1033
1034 /* we don't support MIMO in wide-channel mode */
1035 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1036 }
1037
1038 return hw_rate_set;
1039 }
1040
1041 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1042 struct wl12xx_vif *wlvif)
1043 {
1044 if ((wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1045 wlvif->channel_type == NL80211_CHAN_HT40PLUS) &&
1046 !strcmp(ht_mode_param, "wide")) {
1047 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1048 return CONF_TX_RATE_USE_WIDE_CHAN;
1049 } else if (!strcmp(ht_mode_param, "mimo")) {
1050 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1051
1052 /*
1053 * PG 1.0 has some problems with MCS_13, so disable it
1054 *
1055 * TODO: instead of hacking this in here, we should
1056 * make it more general and change a bit in the
1057 * wlvif->rate_set instead.
1058 */
1059 if (wl->chip.id == CHIP_ID_185x_PG10)
1060 return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13;
1061
1062 return CONF_TX_MIMO_RATES;
1063 } else {
1064 return 0;
1065 }
1066 }
1067
1068 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1069 {
1070 u32 fuse;
1071 int ret;
1072
1073 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1074 if (ret < 0)
1075 goto out;
1076
1077 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1078 if (ret < 0)
1079 goto out;
1080
1081 if (ver)
1082 *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1083
1084 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1085
1086 out:
1087 return ret;
1088 }
1089
1090 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1091 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1092 {
1093 struct wl18xx_priv *priv = wl->priv;
1094 struct wlcore_conf_file *conf_file;
1095 const struct firmware *fw;
1096 int ret;
1097
1098 ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1099 if (ret < 0) {
1100 wl1271_error("could not get configuration binary %s: %d",
1101 WL18XX_CONF_FILE_NAME, ret);
1102 goto out_fallback;
1103 }
1104
1105 if (fw->size != WL18XX_CONF_SIZE) {
1106 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1107 WL18XX_CONF_SIZE, fw->size);
1108 ret = -EINVAL;
1109 goto out;
1110 }
1111
1112 conf_file = (struct wlcore_conf_file *) fw->data;
1113
1114 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1115 wl1271_error("configuration binary file magic number mismatch, "
1116 "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1117 conf_file->header.magic);
1118 ret = -EINVAL;
1119 goto out;
1120 }
1121
1122 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1123 wl1271_error("configuration binary file version not supported, "
1124 "expected 0x%08x got 0x%08x",
1125 WL18XX_CONF_VERSION, conf_file->header.version);
1126 ret = -EINVAL;
1127 goto out;
1128 }
1129
1130 memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1131 memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1132
1133 goto out;
1134
1135 out_fallback:
1136 wl1271_warning("falling back to default config");
1137
1138 /* apply driver default configuration */
1139 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1140 /* apply default private configuration */
1141 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1142
1143 /* For now we just fallback */
1144 return 0;
1145
1146 out:
1147 release_firmware(fw);
1148 return ret;
1149 }
1150
1151 static int wl18xx_plt_init(struct wl1271 *wl)
1152 {
1153 int ret;
1154
1155 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1156 if (ret < 0)
1157 return ret;
1158
1159 return wl->ops->boot(wl);
1160 }
1161
1162 static int wl18xx_get_mac(struct wl1271 *wl)
1163 {
1164 u32 mac1, mac2;
1165 int ret;
1166
1167 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1168 if (ret < 0)
1169 goto out;
1170
1171 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1172 if (ret < 0)
1173 goto out;
1174
1175 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1176 if (ret < 0)
1177 goto out;
1178
1179 /* these are the two parts of the BD_ADDR */
1180 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1181 ((mac1 & 0xff000000) >> 24);
1182 wl->fuse_nic_addr = (mac1 & 0xffffff);
1183
1184 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1185
1186 out:
1187 return ret;
1188 }
1189
1190 static int wl18xx_handle_static_data(struct wl1271 *wl,
1191 struct wl1271_static_data *static_data)
1192 {
1193 struct wl18xx_static_data_priv *static_data_priv =
1194 (struct wl18xx_static_data_priv *) static_data->priv;
1195
1196 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1197
1198 return 0;
1199 }
1200
1201 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1202 {
1203 struct wl18xx_priv *priv = wl->priv;
1204
1205 /* If we have VIFs requiring extra spare, indulge them */
1206 if (priv->extra_spare_vif_count)
1207 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1208
1209 return WL18XX_TX_HW_BLOCK_SPARE;
1210 }
1211
1212 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1213 struct ieee80211_vif *vif,
1214 struct ieee80211_sta *sta,
1215 struct ieee80211_key_conf *key_conf)
1216 {
1217 struct wl18xx_priv *priv = wl->priv;
1218 bool change_spare = false;
1219 int ret;
1220
1221 /*
1222 * when adding the first or removing the last GEM/TKIP interface,
1223 * we have to adjust the number of spare blocks.
1224 */
1225 change_spare = (key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1226 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP) &&
1227 ((priv->extra_spare_vif_count == 0 && cmd == SET_KEY) ||
1228 (priv->extra_spare_vif_count == 1 && cmd == DISABLE_KEY));
1229
1230 /* no need to change spare - just regular set_key */
1231 if (!change_spare)
1232 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1233
1234 /*
1235 * stop the queues and flush to ensure the next packets are
1236 * in sync with FW spare block accounting
1237 */
1238 wlcore_stop_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK);
1239 wl1271_tx_flush(wl);
1240
1241 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1242 if (ret < 0)
1243 goto out;
1244
1245 /* key is now set, change the spare blocks */
1246 if (cmd == SET_KEY) {
1247 ret = wl18xx_set_host_cfg_bitmap(wl,
1248 WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1249 if (ret < 0)
1250 goto out;
1251
1252 priv->extra_spare_vif_count++;
1253 } else {
1254 ret = wl18xx_set_host_cfg_bitmap(wl,
1255 WL18XX_TX_HW_BLOCK_SPARE);
1256 if (ret < 0)
1257 goto out;
1258
1259 priv->extra_spare_vif_count--;
1260 }
1261
1262 out:
1263 wlcore_wake_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK);
1264 return ret;
1265 }
1266
1267 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1268 u32 buf_offset, u32 last_len)
1269 {
1270 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1271 struct wl1271_tx_hw_descr *last_desc;
1272
1273 /* get the last TX HW descriptor written to the aggr buf */
1274 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1275 buf_offset - last_len);
1276
1277 /* the last frame is padded up to an SDIO block */
1278 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1279 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1280 }
1281
1282 /* no modifications */
1283 return buf_offset;
1284 }
1285
1286 static struct wlcore_ops wl18xx_ops = {
1287 .identify_chip = wl18xx_identify_chip,
1288 .boot = wl18xx_boot,
1289 .plt_init = wl18xx_plt_init,
1290 .trigger_cmd = wl18xx_trigger_cmd,
1291 .ack_event = wl18xx_ack_event,
1292 .calc_tx_blocks = wl18xx_calc_tx_blocks,
1293 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1294 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1295 .get_rx_buf_align = wl18xx_get_rx_buf_align,
1296 .get_rx_packet_len = wl18xx_get_rx_packet_len,
1297 .tx_immediate_compl = wl18xx_tx_immediate_completion,
1298 .tx_delayed_compl = NULL,
1299 .hw_init = wl18xx_hw_init,
1300 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1301 .get_pg_ver = wl18xx_get_pg_ver,
1302 .set_rx_csum = wl18xx_set_rx_csum,
1303 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1304 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1305 .get_mac = wl18xx_get_mac,
1306 .debugfs_init = wl18xx_debugfs_add_files,
1307 .handle_static_data = wl18xx_handle_static_data,
1308 .get_spare_blocks = wl18xx_get_spare_blocks,
1309 .set_key = wl18xx_set_key,
1310 .pre_pkt_send = wl18xx_pre_pkt_send,
1311 };
1312
1313 /* HT cap appropriate for wide channels in 2Ghz */
1314 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1315 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1316 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1317 .ht_supported = true,
1318 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1319 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1320 .mcs = {
1321 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1322 .rx_highest = cpu_to_le16(150),
1323 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1324 },
1325 };
1326
1327 /* HT cap appropriate for wide channels in 5Ghz */
1328 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1329 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1330 IEEE80211_HT_CAP_SUP_WIDTH_20_40,
1331 .ht_supported = true,
1332 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1333 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1334 .mcs = {
1335 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1336 .rx_highest = cpu_to_le16(150),
1337 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1338 },
1339 };
1340
1341 /* HT cap appropriate for SISO 20 */
1342 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1343 .cap = IEEE80211_HT_CAP_SGI_20,
1344 .ht_supported = true,
1345 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1346 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1347 .mcs = {
1348 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1349 .rx_highest = cpu_to_le16(72),
1350 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1351 },
1352 };
1353
1354 /* HT cap appropriate for MIMO rates in 20mhz channel */
1355 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1356 .cap = IEEE80211_HT_CAP_SGI_20,
1357 .ht_supported = true,
1358 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1359 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1360 .mcs = {
1361 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1362 .rx_highest = cpu_to_le16(144),
1363 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1364 },
1365 };
1366
1367 static int __devinit wl18xx_probe(struct platform_device *pdev)
1368 {
1369 struct wl1271 *wl;
1370 struct ieee80211_hw *hw;
1371 struct wl18xx_priv *priv;
1372 int ret;
1373
1374 hw = wlcore_alloc_hw(sizeof(*priv));
1375 if (IS_ERR(hw)) {
1376 wl1271_error("can't allocate hw");
1377 ret = PTR_ERR(hw);
1378 goto out;
1379 }
1380
1381 wl = hw->priv;
1382 priv = wl->priv;
1383 wl->ops = &wl18xx_ops;
1384 wl->ptable = wl18xx_ptable;
1385 wl->rtable = wl18xx_rtable;
1386 wl->num_tx_desc = 32;
1387 wl->num_rx_desc = 32;
1388 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1389 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1390 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1391 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1392 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1393 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1394
1395 if (num_rx_desc_param != -1)
1396 wl->num_rx_desc = num_rx_desc_param;
1397
1398 ret = wl18xx_conf_init(wl, &pdev->dev);
1399 if (ret < 0)
1400 goto out_free;
1401
1402 if (!strcmp(board_type_param, "fpga")) {
1403 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1404 } else if (!strcmp(board_type_param, "hdk")) {
1405 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1406 /* HACK! Just for now we hardcode HDK to 0x06 */
1407 priv->conf.phy.low_band_component_type = 0x06;
1408 } else if (!strcmp(board_type_param, "dvp")) {
1409 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1410 } else if (!strcmp(board_type_param, "evb")) {
1411 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1412 } else if (!strcmp(board_type_param, "com8")) {
1413 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1414 /* HACK! Just for now we hardcode COM8 to 0x06 */
1415 priv->conf.phy.low_band_component_type = 0x06;
1416 } else {
1417 wl1271_error("invalid board type '%s'", board_type_param);
1418 ret = -EINVAL;
1419 goto out_free;
1420 }
1421
1422 /* If the module param is set, update it in conf */
1423 if (low_band_component_param != -1)
1424 priv->conf.phy.low_band_component = low_band_component_param;
1425 if (low_band_component_type_param != -1)
1426 priv->conf.phy.low_band_component_type =
1427 low_band_component_type_param;
1428 if (high_band_component_param != -1)
1429 priv->conf.phy.high_band_component = high_band_component_param;
1430 if (high_band_component_type_param != -1)
1431 priv->conf.phy.high_band_component_type =
1432 high_band_component_type_param;
1433 if (pwr_limit_reference_11_abg_param != -1)
1434 priv->conf.phy.pwr_limit_reference_11_abg =
1435 pwr_limit_reference_11_abg_param;
1436 if (n_antennas_2_param != -1)
1437 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1438 if (n_antennas_5_param != -1)
1439 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1440 if (dc2dc_param != -1)
1441 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1442
1443 if (!strcmp(ht_mode_param, "default")) {
1444 /*
1445 * Only support mimo with multiple antennas. Fall back to
1446 * siso20.
1447 */
1448 if (priv->conf.phy.number_of_assembled_ant2_4 >= 2)
1449 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1450 &wl18xx_mimo_ht_cap_2ghz);
1451 else
1452 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1453 &wl18xx_siso20_ht_cap);
1454
1455 /* 5Ghz is always wide */
1456 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1457 &wl18xx_siso40_ht_cap_5ghz);
1458 } else if (!strcmp(ht_mode_param, "wide")) {
1459 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1460 &wl18xx_siso40_ht_cap_2ghz);
1461 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1462 &wl18xx_siso40_ht_cap_5ghz);
1463 } else if (!strcmp(ht_mode_param, "siso20")) {
1464 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1465 &wl18xx_siso20_ht_cap);
1466 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1467 &wl18xx_siso20_ht_cap);
1468 } else {
1469 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1470 ret = -EINVAL;
1471 goto out_free;
1472 }
1473
1474 if (!checksum_param) {
1475 wl18xx_ops.set_rx_csum = NULL;
1476 wl18xx_ops.init_vif = NULL;
1477 }
1478
1479 wl->enable_11a = enable_11a_param;
1480
1481 return wlcore_probe(wl, pdev);
1482
1483 out_free:
1484 wlcore_free_hw(wl);
1485 out:
1486 return ret;
1487 }
1488
1489 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1490 { "wl18xx", 0 },
1491 { } /* Terminating Entry */
1492 };
1493 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1494
1495 static struct platform_driver wl18xx_driver = {
1496 .probe = wl18xx_probe,
1497 .remove = __devexit_p(wlcore_remove),
1498 .id_table = wl18xx_id_table,
1499 .driver = {
1500 .name = "wl18xx_driver",
1501 .owner = THIS_MODULE,
1502 }
1503 };
1504
1505 static int __init wl18xx_init(void)
1506 {
1507 return platform_driver_register(&wl18xx_driver);
1508 }
1509 module_init(wl18xx_init);
1510
1511 static void __exit wl18xx_exit(void)
1512 {
1513 platform_driver_unregister(&wl18xx_driver);
1514 }
1515 module_exit(wl18xx_exit);
1516
1517 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1518 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1519
1520 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1521 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1522 "dvp");
1523
1524 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1525 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1526
1527 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR);
1528 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)");
1529
1530 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1531 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1532
1533 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1534 MODULE_PARM_DESC(n_antennas_2,
1535 "Number of installed 2.4GHz antennas: 1 (default) or 2");
1536
1537 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1538 MODULE_PARM_DESC(n_antennas_5,
1539 "Number of installed 5GHz antennas: 1 (default) or 2");
1540
1541 module_param_named(low_band_component, low_band_component_param, int,
1542 S_IRUSR);
1543 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1544 "(default is 0x01)");
1545
1546 module_param_named(low_band_component_type, low_band_component_type_param,
1547 int, S_IRUSR);
1548 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1549 "(default is 0x05 or 0x06 depending on the board_type)");
1550
1551 module_param_named(high_band_component, high_band_component_param, int,
1552 S_IRUSR);
1553 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1554 "(default is 0x01)");
1555
1556 module_param_named(high_band_component_type, high_band_component_type_param,
1557 int, S_IRUSR);
1558 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1559 "(default is 0x09)");
1560
1561 module_param_named(pwr_limit_reference_11_abg,
1562 pwr_limit_reference_11_abg_param, int, S_IRUSR);
1563 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1564 "(default is 0xc8)");
1565
1566 module_param_named(num_rx_desc,
1567 num_rx_desc_param, int, S_IRUSR);
1568 MODULE_PARM_DESC(num_rx_desc_param,
1569 "Number of Rx descriptors: u8 (default is 32)");
1570
1571 MODULE_LICENSE("GPL v2");
1572 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1573 MODULE_FIRMWARE(WL18XX_FW_NAME);
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