2 * This file is part of wl1271
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2010 Nokia Corporation
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
31 /*************************************************************************
33 Host Interrupt Register (WiLink -> Host)
35 **************************************************************************/
36 /* HW Initiated interrupt Watchdog timer expiration */
37 #define WL1271_ACX_INTR_WATCHDOG BIT(0)
38 /* Init sequence is done (masked interrupt, detection through polling only ) */
39 #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
40 /* Event was entered to Event MBOX #A*/
41 #define WL1271_ACX_INTR_EVENT_A BIT(2)
42 /* Event was entered to Event MBOX #B*/
43 #define WL1271_ACX_INTR_EVENT_B BIT(3)
44 /* Command processing completion*/
45 #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
46 /* Signaling the host on HW wakeup */
47 #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
48 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
49 #define WL1271_ACX_INTR_DATA BIT(6)
50 /* Trace message on MBOX #A */
51 #define WL1271_ACX_INTR_TRACE_A BIT(7)
52 /* Trace message on MBOX #B */
53 #define WL1271_ACX_INTR_TRACE_B BIT(8)
55 #define WL1271_ACX_INTR_ALL 0xFFFFFFFF
56 #define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
57 WL1271_ACX_INTR_INIT_COMPLETE | \
58 WL1271_ACX_INTR_EVENT_A | \
59 WL1271_ACX_INTR_EVENT_B | \
60 WL1271_ACX_INTR_CMD_COMPLETE | \
61 WL1271_ACX_INTR_HW_AVAILABLE | \
64 #define WL1271_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \
65 WL1271_ACX_INTR_EVENT_A | \
66 WL1271_ACX_INTR_EVENT_B | \
67 WL1271_ACX_INTR_HW_AVAILABLE | \
70 /* Target's information element */
72 struct wl1271_cmd_header cmd
;
74 /* acx (or information element) header */
77 /* payload length (not including headers */
81 struct acx_error_counter
{
82 struct acx_header header
;
84 /* The number of PLCP errors since the last time this */
85 /* information element was interrogated. This field is */
86 /* automatically cleared when it is interrogated.*/
89 /* The number of FCS errors since the last time this */
90 /* information element was interrogated. This field is */
91 /* automatically cleared when it is interrogated.*/
94 /* The number of MPDUs without PLCP header errors received*/
95 /* since the last time this information element was interrogated. */
96 /* This field is automatically cleared when it is interrogated.*/
99 /* the number of missed sequence numbers in the squentially */
100 /* values of frames seq numbers */
112 WL12XX_INVALID_ROLE_TYPE
= 0xff
115 enum wl1271_psm_mode
{
119 /* Power save mode */
122 /* Extreme low power */
126 struct acx_sleep_auth
{
127 struct acx_header header
;
129 /* The sleep level authorization of the device. */
130 /* 0 - Always active*/
131 /* 1 - Power down mode: light / fast sleep*/
132 /* 2 - ELP mode: Deep / Max sleep*/
138 HOSTIF_PCI_MASTER_HOST_INDIRECT
,
139 HOSTIF_PCI_MASTER_HOST_DIRECT
,
142 HOSTIF_DONTCARE
= 0xFF
145 #define DEFAULT_UCAST_PRIORITY 0
146 #define DEFAULT_RX_Q_PRIORITY 0
147 #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
148 #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
149 #define TRACE_BUFFER_MAX_SIZE 256
151 #define DP_RX_PACKET_RING_CHUNK_SIZE 1600
152 #define DP_TX_PACKET_RING_CHUNK_SIZE 1600
153 #define DP_RX_PACKET_RING_CHUNK_NUM 2
154 #define DP_TX_PACKET_RING_CHUNK_NUM 2
155 #define DP_TX_COMPLETE_TIME_OUT 20
157 #define TX_MSDU_LIFETIME_MIN 0
158 #define TX_MSDU_LIFETIME_MAX 3000
159 #define TX_MSDU_LIFETIME_DEF 512
160 #define RX_MSDU_LIFETIME_MIN 0
161 #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
162 #define RX_MSDU_LIFETIME_DEF 512000
164 struct acx_rx_msdu_lifetime
{
165 struct acx_header header
;
168 * The maximum amount of time, in TU, before the
169 * firmware discards the MSDU.
174 struct acx_packet_detection
{
175 struct acx_header header
;
184 DEFAULT_SLOT_TIME
= SLOT_TIME_SHORT
,
185 MAX_SLOT_TIMES
= 0xFF
188 #define STATION_WONE_INDEX 0
191 struct acx_header header
;
194 u8 wone_index
; /* Reserved */
200 #define ACX_MC_ADDRESS_GROUP_MAX (8)
201 #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
203 struct acx_dot11_grp_addr_tbl
{
204 struct acx_header header
;
210 u8 mac_table
[ADDRESS_GROUP_MAX_LEN
];
213 struct acx_rx_timeout
{
214 struct acx_header header
;
218 __le16 ps_poll_timeout
;
223 struct acx_rts_threshold
{
224 struct acx_header header
;
231 struct acx_beacon_filter_option
{
232 struct acx_header header
;
237 * The number of beacons without the unicast TIM
238 * bit set that the firmware buffers before
239 * signaling the host about ready frames.
240 * When set to 0 and the filter is enabled, beacons
241 * without the unicast TIM bit set are dropped.
248 * ACXBeaconFilterEntry (not 221)
249 * Byte Offset Size (Bytes) Definition
250 * =========== ============ ==========
252 * 1 1 Treatment bit mask
254 * ACXBeaconFilterEntry (221)
255 * Byte Offset Size (Bytes) Definition
256 * =========== ============ ==========
258 * 1 1 Treatment bit mask
264 * Treatment bit mask - The information element handling:
265 * bit 0 - The information element is compared and transferred
267 * bit 1 - The information element is transferred to the host
268 * with each appearance or disappearance.
269 * Note that both bits can be set at the same time.
271 #define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
272 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
273 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
274 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
275 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
276 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
277 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
278 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
280 struct acx_beacon_filter_ie_table
{
281 struct acx_header header
;
286 u8 table
[BEACON_FILTER_TABLE_MAX_SIZE
];
289 struct acx_conn_monit_params
{
290 struct acx_header header
;
294 __le32 synch_fail_thold
; /* number of beacons missed */
295 __le32 bss_lose_timeout
; /* number of TU's from synch fail */
298 struct acx_bt_wlan_coex
{
299 struct acx_header header
;
305 struct acx_bt_wlan_coex_param
{
306 struct acx_header header
;
308 __le32 params
[CONF_SG_PARAMS_MAX
];
313 struct acx_dco_itrim_params
{
314 struct acx_header header
;
321 struct acx_energy_detection
{
322 struct acx_header header
;
324 /* The RX Clear Channel Assessment threshold in the PHY */
325 __le16 rx_cca_threshold
;
326 u8 tx_energy_detection
;
330 struct acx_beacon_broadcast
{
331 struct acx_header header
;
334 /* Enables receiving of broadcast packets in PS mode */
335 u8 rx_broadcast_in_ps
;
337 __le16 beacon_rx_timeout
;
338 __le16 broadcast_timeout
;
340 /* Consecutive PS Poll failures before updating the host */
341 u8 ps_poll_threshold
;
345 struct acx_event_mask
{
346 struct acx_header header
;
349 __le32 high_event_mask
; /* Unused */
352 #define SCAN_PASSIVE BIT(0)
353 #define SCAN_5GHZ_BAND BIT(1)
354 #define SCAN_TRIGGERED BIT(2)
355 #define SCAN_PRIORITY_HIGH BIT(3)
357 /* When set, disable HW encryption */
358 #define DF_ENCRYPTION_DISABLE 0x01
359 #define DF_SNIFF_MODE_ENABLE 0x80
361 struct acx_feature_config
{
362 struct acx_header header
;
367 __le32 data_flow_options
;
370 struct acx_current_tx_power
{
371 struct acx_header header
;
378 struct acx_wake_up_condition
{
379 struct acx_header header
;
382 u8 wake_up_event
; /* Only one bit can be set */
388 struct acx_header header
;
391 * To be set when associated with an AP.
398 enum acx_preamble_type
{
399 ACX_PREAMBLE_LONG
= 0,
400 ACX_PREAMBLE_SHORT
= 1
403 struct acx_preamble
{
404 struct acx_header header
;
407 * When set, the WiLink transmits the frames with a short preamble and
408 * when cleared, the WiLink transmits the frames with a long preamble.
415 enum acx_ctsprotect_type
{
416 CTSPROTECT_DISABLE
= 0,
417 CTSPROTECT_ENABLE
= 1
420 struct acx_ctsprotect
{
421 struct acx_header header
;
427 struct acx_tx_statistics
{
428 __le32 internal_desc_overflow
;
431 struct acx_rx_statistics
{
437 __le32 xfr_hint_trig
;
439 __le32 reset_counter
;
442 struct acx_dma_statistics
{
449 struct acx_isr_statistics
{
450 /* host command complete */
456 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
459 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
462 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
463 __le32 rx_mem_overflow
;
465 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
471 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
474 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
477 /* (INT_STS_ND & INT_TRIG_DMA0) */
480 /* (INT_STS_ND & INT_TRIG_DMA1) */
483 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
484 __le32 tx_exch_complete
;
486 /* (INT_STS_ND & INT_TRIG_COMMAND) */
489 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
492 /* (INT_STS_ND & INT_TRIG_PM_802) */
493 __le32 hw_pm_mode_changes
;
495 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
496 __le32 host_acknowledges
;
498 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
501 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
504 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
508 struct acx_wep_statistics
{
509 /* WEP address keys configured */
510 __le32 addr_key_count
;
512 /* default keys configured */
513 __le32 default_key_count
;
517 /* number of times that WEP key not found on lookup */
518 __le32 key_not_found
;
520 /* number of times that WEP key decryption failed */
523 /* WEP packets decrypted */
526 /* WEP decrypt interrupts */
530 #define ACX_MISSED_BEACONS_SPREAD 10
532 struct acx_pwr_statistics
{
533 /* the amount of enters into power save mode (both PD & ELP) */
536 /* the amount of enters into ELP mode */
539 /* the amount of missing beacon interrupts to the host */
542 /* the amount of wake on host-access times */
545 /* the amount of wake on timer-expire */
546 __le32 wake_on_timer_exp
;
548 /* the number of packets that were transmitted with PS bit set */
551 /* the number of packets that were transmitted with PS bit clear */
552 __le32 tx_without_ps
;
554 /* the number of received beacons */
557 /* the number of entering into PowerOn (power save off) */
558 __le32 power_save_off
;
560 /* the number of entries into power save mode */
564 * the number of exits from power save, not including failed PS
570 * the number of times the TSF counter was adjusted because
575 /* Gives statistics about the spread continuous missed beacons.
576 * The 16 LSB are dedicated for the PS mode.
577 * The 16 MSB are dedicated for the PS mode.
578 * cont_miss_bcns_spread[0] - single missed beacon.
579 * cont_miss_bcns_spread[1] - two continuous missed beacons.
580 * cont_miss_bcns_spread[2] - three continuous missed beacons.
582 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
584 __le32 cont_miss_bcns_spread
[ACX_MISSED_BEACONS_SPREAD
];
586 /* the number of beacons in awake mode */
587 __le32 rcvd_awake_beacons
;
590 struct acx_mic_statistics
{
595 struct acx_aes_statistics
{
598 __le32 encrypt_packets
;
599 __le32 decrypt_packets
;
600 __le32 encrypt_interrupt
;
601 __le32 decrypt_interrupt
;
604 struct acx_event_statistics
{
611 __le32 phy_transmit_error
;
615 struct acx_ps_statistics
{
616 __le32 pspoll_timeouts
;
617 __le32 upsd_timeouts
;
618 __le32 upsd_max_sptime
;
619 __le32 upsd_max_apturn
;
620 __le32 pspoll_max_apturn
;
621 __le32 pspoll_utilization
;
622 __le32 upsd_utilization
;
625 struct acx_rxpipe_statistics
{
626 __le32 rx_prep_beacon_drop
;
627 __le32 descr_host_int_trig_rx_data
;
628 __le32 beacon_buffer_thres_host_int_trig_rx_data
;
629 __le32 missed_beacon_host_int_trig_rx_data
;
630 __le32 tx_xfr_host_int_trig_rx_data
;
633 struct acx_statistics
{
634 struct acx_header header
;
636 struct acx_tx_statistics tx
;
637 struct acx_rx_statistics rx
;
638 struct acx_dma_statistics dma
;
639 struct acx_isr_statistics isr
;
640 struct acx_wep_statistics wep
;
641 struct acx_pwr_statistics pwr
;
642 struct acx_aes_statistics aes
;
643 struct acx_mic_statistics mic
;
644 struct acx_event_statistics event
;
645 struct acx_ps_statistics ps
;
646 struct acx_rxpipe_statistics rxpipe
;
649 struct acx_rate_class
{
650 __le32 enabled_rates
;
651 u8 short_retry_limit
;
657 struct acx_rate_policy
{
658 struct acx_header header
;
660 __le32 rate_policy_idx
;
661 struct acx_rate_class rate_policy
;
665 struct acx_header header
;
674 struct acx_tid_config
{
675 struct acx_header header
;
686 struct acx_frag_threshold
{
687 struct acx_header header
;
688 __le16 frag_threshold
;
692 struct acx_tx_config_options
{
693 struct acx_header header
;
694 __le16 tx_compl_timeout
; /* msec */
695 __le16 tx_compl_threshold
; /* number of packets */
698 struct wl12xx_acx_config_memory
{
699 struct acx_header header
;
702 u8 tx_min_mem_block_num
;
704 u8 num_ssid_profiles
;
705 __le32 total_tx_descriptors
;
714 struct wl1271_acx_mem_map
{
715 struct acx_header header
;
720 __le32 wep_defkey_start
;
721 __le32 wep_defkey_end
;
723 __le32 sta_table_start
;
724 __le32 sta_table_end
;
726 __le32 packet_template_start
;
727 __le32 packet_template_end
;
729 /* Address of the TX result interface (control block) */
731 __le32 tx_result_queue_start
;
733 __le32 queue_memory_start
;
734 __le32 queue_memory_end
;
736 __le32 packet_memory_pool_start
;
737 __le32 packet_memory_pool_end
;
739 __le32 debug_buffer1_start
;
740 __le32 debug_buffer1_end
;
742 __le32 debug_buffer2_start
;
743 __le32 debug_buffer2_end
;
745 /* Number of blocks FW allocated for TX packets */
746 __le32 num_tx_mem_blocks
;
748 /* Number of blocks FW allocated for RX packets */
749 __le32 num_rx_mem_blocks
;
751 /* the following 4 fields are valid in SLAVE mode only */
758 struct wl1271_acx_rx_config_opt
{
759 struct acx_header header
;
761 __le16 mblk_threshold
;
769 struct wl1271_acx_bet_enable
{
770 struct acx_header header
;
778 #define ACX_IPV4_VERSION 4
779 #define ACX_IPV6_VERSION 6
780 #define ACX_IPV4_ADDR_SIZE 4
782 /* bitmap of enabled arp_filter features */
783 #define ACX_ARP_FILTER_ARP_FILTERING BIT(0)
784 #define ACX_ARP_FILTER_AUTO_ARP BIT(1)
786 struct wl1271_acx_arp_filter
{
787 struct acx_header header
;
789 u8 version
; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
790 u8 enable
; /* bitmap of enabled ARP filtering features */
792 u8 address
[16]; /* The configured device IP address - all ARP
793 requests directed to this IP address will pass
794 through. For IPv4, the first four bytes are
798 struct wl1271_acx_pm_config
{
799 struct acx_header header
;
801 __le32 host_clk_settling_time
;
802 u8 host_fast_wakeup_support
;
806 struct wl1271_acx_keep_alive_mode
{
807 struct acx_header header
;
815 ACX_KEEP_ALIVE_NO_TX
= 0,
816 ACX_KEEP_ALIVE_PERIOD_ONLY
820 ACX_KEEP_ALIVE_TPL_INVALID
= 0,
821 ACX_KEEP_ALIVE_TPL_VALID
824 struct wl1271_acx_keep_alive_config
{
825 struct acx_header header
;
834 #define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0)
835 #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
836 #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)
838 struct wl1271_acx_host_config_bitmap
{
839 struct acx_header header
;
841 __le32 host_cfg_bitmap
;
845 WL1271_ACX_TRIG_TYPE_LEVEL
= 0,
846 WL1271_ACX_TRIG_TYPE_EDGE
,
850 WL1271_ACX_TRIG_DIR_LOW
= 0,
851 WL1271_ACX_TRIG_DIR_HIGH
,
852 WL1271_ACX_TRIG_DIR_BIDIR
,
856 WL1271_ACX_TRIG_ENABLE
= 1,
857 WL1271_ACX_TRIG_DISABLE
,
861 WL1271_ACX_TRIG_METRIC_RSSI_BEACON
= 0,
862 WL1271_ACX_TRIG_METRIC_RSSI_DATA
,
863 WL1271_ACX_TRIG_METRIC_SNR_BEACON
,
864 WL1271_ACX_TRIG_METRIC_SNR_DATA
,
868 WL1271_ACX_TRIG_IDX_RSSI
= 0,
869 WL1271_ACX_TRIG_COUNT
= 8,
872 struct wl1271_acx_rssi_snr_trigger
{
873 struct acx_header header
;
880 __le16 pacing
; /* 0 - 60000 ms */
887 struct wl1271_acx_rssi_snr_avg_weights
{
888 struct acx_header header
;
899 /* special capability bit (not employed by the 802.11n spec) */
900 #define WL12XX_HT_CAP_HT_OPERATION BIT(16)
904 * Configure HT capabilities - declare the capabilities of the peer
905 * we are connected to.
907 struct wl1271_acx_ht_capabilities
{
908 struct acx_header header
;
910 /* bitmask of capability bits supported by the peer */
911 __le32 ht_capabilites
;
913 /* Indicates to which link these capabilities apply. */
917 * This the maximum A-MPDU length supported by the AP. The FW may not
918 * exceed this length when sending A-MPDUs
922 /* This is the minimal spacing required when sending A-MPDUs to the AP*/
923 u8 ampdu_min_spacing
;
929 * ACX_HT_BSS_OPERATION
930 * Configure HT capabilities - AP rules for behavior in the BSS.
932 struct wl1271_acx_ht_information
{
933 struct acx_header header
;
937 /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
940 /* Values: 0 - 3 like in spec */
943 /* Values: 0 - GF protection not required, 1 - GF protection required */
946 /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
947 u8 ht_tx_burst_limit
;
950 * Values: 0 - Dual CTS protection not required,
951 * 1 - Dual CTS Protection required
952 * Note: When this value is set to 1 FW will protect all TXOP with RTS
953 * frame and will not use CTS-to-self regardless of the value of the
954 * ACX_CTS_PROTECTION information element
956 u8 dual_cts_protection
;
961 #define RX_BA_MAX_SESSIONS 2
963 struct wl1271_acx_ba_initiator_policy
{
964 struct acx_header header
;
966 /* Specifies role Id, Range 0-7, 0xFF means ANY role. */
970 * Per TID setting for allowing TX BA. Set a bit to 1 to allow
971 * TX BA sessions for the corresponding TID.
975 /* Windows size in number of packets */
980 /* As initiator inactivity timeout in time units(TU) of 1024us */
981 u16 inactivity_timeout
;
986 struct wl1271_acx_ba_receiver_setup
{
987 struct acx_header header
;
989 /* Specifies link id, range 0-31 */
996 /* Windows size in number of packets */
999 /* BA session starting sequence number. RANGE 0-FFF */
1005 struct wl1271_acx_fw_tsf_information
{
1006 struct acx_header header
;
1008 __le32 current_tsf_high
;
1009 __le32 current_tsf_low
;
1010 __le32 last_bttt_high
;
1011 __le32 last_tbtt_low
;
1016 struct wl1271_acx_ps_rx_streaming
{
1017 struct acx_header header
;
1023 /* interval between triggers (10-100 msec) */
1026 /* timeout before first trigger (0-200 msec) */
1031 struct wl1271_acx_ap_max_tx_retry
{
1032 struct acx_header header
;
1038 * the number of frames transmission failures before
1039 * issuing the aging event.
1041 __le16 max_tx_retry
;
1044 struct wl1271_acx_config_ps
{
1045 struct acx_header header
;
1050 __le32 null_data_rate
;
1053 struct wl1271_acx_inconnection_sta
{
1054 struct acx_header header
;
1062 * set the FM co-existence parameters.
1064 struct wl1271_acx_fm_coex
{
1065 struct acx_header header
;
1066 /* enable(1) / disable(0) the FM Coex feature */
1069 * Swallow period used in COEX PLL swallowing mechanism.
1070 * 0xFF = use FW default
1074 * The N divider used in COEX PLL swallowing mechanism for Fref of
1075 * 38.4/19.2 Mhz. 0xFF = use FW default
1077 u8 n_divider_fref_set_1
;
1079 * The N divider used in COEX PLL swallowing mechanism for Fref of
1080 * 26/52 Mhz. 0xFF = use FW default
1082 u8 n_divider_fref_set_2
;
1084 * The M divider used in COEX PLL swallowing mechanism for Fref of
1085 * 38.4/19.2 Mhz. 0xFFFF = use FW default
1087 __le16 m_divider_fref_set_1
;
1089 * The M divider used in COEX PLL swallowing mechanism for Fref of
1090 * 26/52 Mhz. 0xFFFF = use FW default
1092 __le16 m_divider_fref_set_2
;
1094 * The time duration in uSec required for COEX PLL to stabilize.
1095 * 0xFFFFFFFF = use FW default
1097 __le32 coex_pll_stabilization_time
;
1099 * The time duration in uSec required for LDO to stabilize.
1100 * 0xFFFFFFFF = use FW default
1102 __le16 ldo_stabilization_time
;
1104 * The disturbed frequency band margin around the disturbed frequency
1105 * center (single sided).
1106 * For example, if 2 is configured, the following channels will be
1107 * considered disturbed channel:
1108 * 80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH
1109 * 0xFF = use FW default
1111 u8 fm_disturbed_band_margin
;
1113 * The swallow clock difference of the swallowing mechanism.
1114 * 0xFF = use FW default
1116 u8 swallow_clk_diff
;
1119 #define ACX_RATE_MGMT_ALL_PARAMS 0xff
1120 struct wl12xx_acx_set_rate_mgmt_params
{
1121 struct acx_header header
;
1123 u8 index
; /* 0xff to configure all params */
1125 __le16 rate_retry_score
;
1130 u8 inverse_curiosity_factor
;
1139 u8 rate_retry_policy
[ACX_RATE_MGMT_NUM_OF_RATES
];
1143 struct wl12xx_acx_config_hangover
{
1144 struct acx_header header
;
1146 __le32 recover_time
;
1149 u8 early_termination_mode
;
1161 ACX_WAKE_UP_CONDITIONS
= 0x0002,
1162 ACX_MEM_CFG
= 0x0003,
1164 ACX_AC_CFG
= 0x0007,
1165 ACX_MEM_MAP
= 0x0008,
1167 ACX_MEDIUM_USAGE
= 0x000F,
1168 ACX_TX_QUEUE_CFG
= 0x0011, /* FIXME: only used by wl1251 */
1169 ACX_STATISTICS
= 0x0013, /* Debug API */
1170 ACX_PWR_CONSUMPTION_STATISTICS
= 0x0014,
1171 ACX_FEATURE_CFG
= 0x0015,
1172 ACX_TID_CFG
= 0x001A,
1173 ACX_PS_RX_STREAMING
= 0x001B,
1174 ACX_BEACON_FILTER_OPT
= 0x001F,
1175 ACX_NOISE_HIST
= 0x0021,
1176 ACX_HDK_VERSION
= 0x0022, /* ??? */
1177 ACX_PD_THRESHOLD
= 0x0023,
1178 ACX_TX_CONFIG_OPT
= 0x0024,
1179 ACX_CCA_THRESHOLD
= 0x0025,
1180 ACX_EVENT_MBOX_MASK
= 0x0026,
1181 ACX_CONN_MONIT_PARAMS
= 0x002D,
1182 ACX_BCN_DTIM_OPTIONS
= 0x0031,
1183 ACX_SG_ENABLE
= 0x0032,
1184 ACX_SG_CFG
= 0x0033,
1185 ACX_FM_COEX_CFG
= 0x0034,
1186 ACX_BEACON_FILTER_TABLE
= 0x0038,
1187 ACX_ARP_IP_FILTER
= 0x0039,
1188 ACX_ROAMING_STATISTICS_TBL
= 0x003B,
1189 ACX_RATE_POLICY
= 0x003D,
1190 ACX_CTS_PROTECTION
= 0x003E,
1191 ACX_SLEEP_AUTH
= 0x003F,
1192 ACX_PREAMBLE_TYPE
= 0x0040,
1193 ACX_ERROR_CNT
= 0x0041,
1194 ACX_IBSS_FILTER
= 0x0044,
1195 ACX_SERVICE_PERIOD_TIMEOUT
= 0x0045,
1196 ACX_TSF_INFO
= 0x0046,
1197 ACX_CONFIG_PS_WMM
= 0x0049,
1198 ACX_ENABLE_RX_DATA_FILTER
= 0x004A,
1199 ACX_SET_RX_DATA_FILTER
= 0x004B,
1200 ACX_GET_DATA_FILTER_STATISTICS
= 0x004C,
1201 ACX_RX_CONFIG_OPT
= 0x004E,
1202 ACX_FRAG_CFG
= 0x004F,
1203 ACX_BET_ENABLE
= 0x0050,
1204 ACX_RSSI_SNR_TRIGGER
= 0x0051,
1205 ACX_RSSI_SNR_WEIGHTS
= 0x0052,
1206 ACX_KEEP_ALIVE_MODE
= 0x0053,
1207 ACX_SET_KEEP_ALIVE_CONFIG
= 0x0054,
1208 ACX_BA_SESSION_INIT_POLICY
= 0x0055,
1209 ACX_BA_SESSION_RX_SETUP
= 0x0056,
1210 ACX_PEER_HT_CAP
= 0x0057,
1211 ACX_HT_BSS_OPERATION
= 0x0058,
1212 ACX_COEX_ACTIVITY
= 0x0059,
1213 ACX_BURST_MODE
= 0x005C,
1214 ACX_SET_RATE_MGMT_PARAMS
= 0x005D,
1215 ACX_SET_RATE_ADAPT_PARAMS
= 0x0060,
1216 ACX_SET_DCO_ITRIM_PARAMS
= 0x0061,
1217 ACX_GEN_FW_CMD
= 0x0070,
1218 ACX_HOST_IF_CFG_BITMAP
= 0x0071,
1219 ACX_MAX_TX_FAILURE
= 0x0072,
1220 ACX_UPDATE_INCONNECTION_STA_LIST
= 0x0073,
1221 DOT11_RX_MSDU_LIFE_TIME
= 0x1004,
1222 DOT11_CUR_TX_PWR
= 0x100D,
1223 DOT11_RX_DOT11_MODE
= 0x1012,
1224 DOT11_RTS_THRESHOLD
= 0x1013,
1225 DOT11_GROUP_ADDRESS_TBL
= 0x1014,
1226 ACX_PM_CONFIG
= 0x1016,
1227 ACX_CONFIG_PS
= 0x1017,
1228 ACX_CONFIG_HANGOVER
= 0x1018,
1232 int wl1271_acx_wake_up_conditions(struct wl1271
*wl
,
1233 struct wl12xx_vif
*wlvif
);
1234 int wl1271_acx_sleep_auth(struct wl1271
*wl
, u8 sleep_auth
);
1235 int wl1271_acx_tx_power(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1237 int wl1271_acx_feature_cfg(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
);
1238 int wl1271_acx_mem_map(struct wl1271
*wl
,
1239 struct acx_header
*mem_map
, size_t len
);
1240 int wl1271_acx_rx_msdu_life_time(struct wl1271
*wl
);
1241 int wl1271_acx_pd_threshold(struct wl1271
*wl
);
1242 int wl1271_acx_slot(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1243 enum acx_slot_type slot_time
);
1244 int wl1271_acx_group_address_tbl(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1245 bool enable
, void *mc_list
, u32 mc_list_len
);
1246 int wl1271_acx_service_period_timeout(struct wl1271
*wl
,
1247 struct wl12xx_vif
*wlvif
);
1248 int wl1271_acx_rts_threshold(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1250 int wl1271_acx_dco_itrim_params(struct wl1271
*wl
);
1251 int wl1271_acx_beacon_filter_opt(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1252 bool enable_filter
);
1253 int wl1271_acx_beacon_filter_table(struct wl1271
*wl
,
1254 struct wl12xx_vif
*wlvif
);
1255 int wl1271_acx_conn_monit_params(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1257 int wl1271_acx_sg_enable(struct wl1271
*wl
, bool enable
);
1258 int wl12xx_acx_sg_cfg(struct wl1271
*wl
);
1259 int wl1271_acx_cca_threshold(struct wl1271
*wl
);
1260 int wl1271_acx_bcn_dtim_options(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
);
1261 int wl1271_acx_aid(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
, u16 aid
);
1262 int wl1271_acx_event_mbox_mask(struct wl1271
*wl
, u32 event_mask
);
1263 int wl1271_acx_set_preamble(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1264 enum acx_preamble_type preamble
);
1265 int wl1271_acx_cts_protect(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1266 enum acx_ctsprotect_type ctsprotect
);
1267 int wl1271_acx_statistics(struct wl1271
*wl
, struct acx_statistics
*stats
);
1268 int wl1271_acx_sta_rate_policies(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
);
1269 int wl1271_acx_ap_rate_policy(struct wl1271
*wl
, struct conf_tx_rate_class
*c
,
1271 int wl1271_acx_ac_cfg(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1272 u8 ac
, u8 cw_min
, u16 cw_max
, u8 aifsn
, u16 txop
);
1273 int wl1271_acx_tid_cfg(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1274 u8 queue_id
, u8 channel_type
,
1275 u8 tsid
, u8 ps_scheme
, u8 ack_policy
,
1276 u32 apsd_conf0
, u32 apsd_conf1
);
1277 int wl1271_acx_frag_threshold(struct wl1271
*wl
, u32 frag_threshold
);
1278 int wl1271_acx_tx_config_options(struct wl1271
*wl
);
1279 int wl12xx_acx_mem_cfg(struct wl1271
*wl
);
1280 int wl1271_acx_init_mem_config(struct wl1271
*wl
);
1281 int wl1271_acx_host_if_cfg_bitmap(struct wl1271
*wl
, u32 host_cfg_bitmap
);
1282 int wl1271_acx_init_rx_interrupt(struct wl1271
*wl
);
1283 int wl1271_acx_smart_reflex(struct wl1271
*wl
);
1284 int wl1271_acx_bet_enable(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1286 int wl1271_acx_arp_ip_filter(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1287 u8 enable
, __be32 address
);
1288 int wl1271_acx_pm_config(struct wl1271
*wl
);
1289 int wl1271_acx_keep_alive_mode(struct wl1271
*wl
, struct wl12xx_vif
*vif
,
1291 int wl1271_acx_keep_alive_config(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1292 u8 index
, u8 tpl_valid
);
1293 int wl1271_acx_rssi_snr_trigger(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1294 bool enable
, s16 thold
, u8 hyst
);
1295 int wl1271_acx_rssi_snr_avg_weights(struct wl1271
*wl
,
1296 struct wl12xx_vif
*wlvif
);
1297 int wl1271_acx_set_ht_capabilities(struct wl1271
*wl
,
1298 struct ieee80211_sta_ht_cap
*ht_cap
,
1299 bool allow_ht_operation
, u8 hlid
);
1300 int wl1271_acx_set_ht_information(struct wl1271
*wl
,
1301 struct wl12xx_vif
*wlvif
,
1302 u16 ht_operation_mode
);
1303 int wl12xx_acx_set_ba_initiator_policy(struct wl1271
*wl
,
1304 struct wl12xx_vif
*wlvif
);
1305 int wl12xx_acx_set_ba_receiver_session(struct wl1271
*wl
, u8 tid_index
,
1306 u16 ssn
, bool enable
, u8 peer_hlid
);
1307 int wl1271_acx_tsf_info(struct wl1271
*wl
, u64
*mactime
);
1308 int wl1271_acx_ps_rx_streaming(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
,
1310 int wl1271_acx_ap_max_tx_retry(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
);
1311 int wl12xx_acx_config_ps(struct wl1271
*wl
, struct wl12xx_vif
*wlvif
);
1312 int wl1271_acx_set_inconnection_sta(struct wl1271
*wl
, u8
*addr
);
1313 int wl1271_acx_fm_coex(struct wl1271
*wl
);
1314 int wl12xx_acx_set_rate_mgmt_params(struct wl1271
*wl
);
1315 int wl12xx_acx_config_hangover(struct wl1271
*wl
);
1317 #endif /* __WL1271_ACX_H__ */