2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/slab.h>
25 #include <linux/wl12xx.h>
26 #include <linux/export.h>
36 static struct wl1271_partition_set part_table
[PART_TABLE_LEN
] = {
43 .start
= REGISTERS_BASE
,
62 .start
= REGISTERS_BASE
,
95 static void wl1271_boot_set_ecpu_ctrl(struct wl1271
*wl
, u32 flag
)
99 /* 10.5.0 run the firmware (I) */
100 cpu_ctrl
= wl1271_read32(wl
, ACX_REG_ECPU_CONTROL
);
102 /* 10.5.1 run the firmware (II) */
104 wl1271_write32(wl
, ACX_REG_ECPU_CONTROL
, cpu_ctrl
);
107 static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271
*wl
)
109 unsigned int quirks
= 0;
110 unsigned int *fw_ver
= wl
->chip
.fw_ver
;
112 /* Only new station firmwares support routing fw logs to the host */
113 if ((fw_ver
[FW_VER_IF_TYPE
] == FW_VER_IF_TYPE_STA
) &&
114 (fw_ver
[FW_VER_MINOR
] < FW_VER_MINOR_FWLOG_STA_MIN
))
115 quirks
|= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED
;
117 /* This feature is not yet supported for AP mode */
118 if (fw_ver
[FW_VER_IF_TYPE
] == FW_VER_IF_TYPE_AP
)
119 quirks
|= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED
;
124 static void wl1271_parse_fw_ver(struct wl1271
*wl
)
128 ret
= sscanf(wl
->chip
.fw_ver_str
+ 4, "%u.%u.%u.%u.%u",
129 &wl
->chip
.fw_ver
[0], &wl
->chip
.fw_ver
[1],
130 &wl
->chip
.fw_ver
[2], &wl
->chip
.fw_ver
[3],
131 &wl
->chip
.fw_ver
[4]);
134 wl1271_warning("fw version incorrect value");
135 memset(wl
->chip
.fw_ver
, 0, sizeof(wl
->chip
.fw_ver
));
139 /* Check if any quirks are needed with older fw versions */
140 wl
->quirks
|= wl12xx_get_fw_ver_quirks(wl
);
143 static void wl1271_boot_fw_version(struct wl1271
*wl
)
145 struct wl1271_static_data static_data
;
147 wl1271_read(wl
, wl
->cmd_box_addr
, &static_data
, sizeof(static_data
),
150 strncpy(wl
->chip
.fw_ver_str
, static_data
.fw_version
,
151 sizeof(wl
->chip
.fw_ver_str
));
153 /* make sure the string is NULL-terminated */
154 wl
->chip
.fw_ver_str
[sizeof(wl
->chip
.fw_ver_str
) - 1] = '\0';
156 wl1271_parse_fw_ver(wl
);
159 static int wl1271_boot_upload_firmware_chunk(struct wl1271
*wl
, void *buf
,
160 size_t fw_data_len
, u32 dest
)
162 struct wl1271_partition_set partition
;
163 int addr
, chunk_num
, partition_limit
;
166 /* whal_FwCtrl_LoadFwImageSm() */
168 wl1271_debug(DEBUG_BOOT
, "starting firmware upload");
170 wl1271_debug(DEBUG_BOOT
, "fw_data_len %zd chunk_size %d",
171 fw_data_len
, CHUNK_SIZE
);
173 if ((fw_data_len
% 4) != 0) {
174 wl1271_error("firmware length not multiple of four");
178 chunk
= kmalloc(CHUNK_SIZE
, GFP_KERNEL
);
180 wl1271_error("allocation for firmware upload chunk failed");
184 memcpy(&partition
, &part_table
[PART_DOWN
], sizeof(partition
));
185 partition
.mem
.start
= dest
;
186 wl1271_set_partition(wl
, &partition
);
188 /* 10.1 set partition limit and chunk num */
190 partition_limit
= part_table
[PART_DOWN
].mem
.size
;
192 while (chunk_num
< fw_data_len
/ CHUNK_SIZE
) {
193 /* 10.2 update partition, if needed */
194 addr
= dest
+ (chunk_num
+ 2) * CHUNK_SIZE
;
195 if (addr
> partition_limit
) {
196 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
197 partition_limit
= chunk_num
* CHUNK_SIZE
+
198 part_table
[PART_DOWN
].mem
.size
;
199 partition
.mem
.start
= addr
;
200 wl1271_set_partition(wl
, &partition
);
203 /* 10.3 upload the chunk */
204 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
205 p
= buf
+ chunk_num
* CHUNK_SIZE
;
206 memcpy(chunk
, p
, CHUNK_SIZE
);
207 wl1271_debug(DEBUG_BOOT
, "uploading fw chunk 0x%p to 0x%x",
209 wl1271_write(wl
, addr
, chunk
, CHUNK_SIZE
, false);
214 /* 10.4 upload the last chunk */
215 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
216 p
= buf
+ chunk_num
* CHUNK_SIZE
;
217 memcpy(chunk
, p
, fw_data_len
% CHUNK_SIZE
);
218 wl1271_debug(DEBUG_BOOT
, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
219 fw_data_len
% CHUNK_SIZE
, p
, addr
);
220 wl1271_write(wl
, addr
, chunk
, fw_data_len
% CHUNK_SIZE
, false);
226 static int wl1271_boot_upload_firmware(struct wl1271
*wl
)
228 u32 chunks
, addr
, len
;
233 chunks
= be32_to_cpup((__be32
*) fw
);
236 wl1271_debug(DEBUG_BOOT
, "firmware chunks to be uploaded: %u", chunks
);
239 addr
= be32_to_cpup((__be32
*) fw
);
241 len
= be32_to_cpup((__be32
*) fw
);
245 wl1271_info("firmware chunk too long: %u", len
);
248 wl1271_debug(DEBUG_BOOT
, "chunk %d addr 0x%x len %u",
250 ret
= wl1271_boot_upload_firmware_chunk(wl
, fw
, len
, addr
);
259 static int wl1271_boot_upload_nvs(struct wl1271
*wl
)
261 size_t nvs_len
, burst_len
;
264 u8
*nvs_ptr
, *nvs_aligned
;
269 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
270 struct wl128x_nvs_file
*nvs
= (struct wl128x_nvs_file
*)wl
->nvs
;
272 if (wl
->nvs_len
== sizeof(struct wl128x_nvs_file
)) {
273 if (nvs
->general_params
.dual_mode_select
)
274 wl
->enable_11a
= true;
276 wl1271_error("nvs size is not as expected: %zu != %zu",
278 sizeof(struct wl128x_nvs_file
));
285 /* only the first part of the NVS needs to be uploaded */
286 nvs_len
= sizeof(nvs
->nvs
);
287 nvs_ptr
= (u8
*)nvs
->nvs
;
290 struct wl1271_nvs_file
*nvs
=
291 (struct wl1271_nvs_file
*)wl
->nvs
;
293 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
294 * band configurations) can be removed when those NVS files stop
297 if (wl
->nvs_len
== sizeof(struct wl1271_nvs_file
) ||
298 wl
->nvs_len
== WL1271_INI_LEGACY_NVS_FILE_SIZE
) {
299 if (nvs
->general_params
.dual_mode_select
)
300 wl
->enable_11a
= true;
303 if (wl
->nvs_len
!= sizeof(struct wl1271_nvs_file
) &&
304 (wl
->nvs_len
!= WL1271_INI_LEGACY_NVS_FILE_SIZE
||
306 wl1271_error("nvs size is not as expected: %zu != %zu",
307 wl
->nvs_len
, sizeof(struct wl1271_nvs_file
));
314 /* only the first part of the NVS needs to be uploaded */
315 nvs_len
= sizeof(nvs
->nvs
);
316 nvs_ptr
= (u8
*) nvs
->nvs
;
319 /* update current MAC address to NVS */
320 nvs_ptr
[11] = wl
->mac_addr
[0];
321 nvs_ptr
[10] = wl
->mac_addr
[1];
322 nvs_ptr
[6] = wl
->mac_addr
[2];
323 nvs_ptr
[5] = wl
->mac_addr
[3];
324 nvs_ptr
[4] = wl
->mac_addr
[4];
325 nvs_ptr
[3] = wl
->mac_addr
[5];
328 * Layout before the actual NVS tables:
329 * 1 byte : burst length.
330 * 2 bytes: destination address.
331 * n bytes: data to burst copy.
333 * This is ended by a 0 length, then the NVS tables.
336 /* FIXME: Do we need to check here whether the LSB is 1? */
338 burst_len
= nvs_ptr
[0];
339 dest_addr
= (nvs_ptr
[1] & 0xfe) | ((u32
)(nvs_ptr
[2] << 8));
342 * Due to our new wl1271_translate_reg_addr function,
343 * we need to add the REGISTER_BASE to the destination
345 dest_addr
+= REGISTERS_BASE
;
347 /* We move our pointer to the data */
350 for (i
= 0; i
< burst_len
; i
++) {
351 val
= (nvs_ptr
[0] | (nvs_ptr
[1] << 8)
352 | (nvs_ptr
[2] << 16) | (nvs_ptr
[3] << 24));
354 wl1271_debug(DEBUG_BOOT
,
355 "nvs burst write 0x%x: 0x%x",
357 wl1271_write32(wl
, dest_addr
, val
);
365 * We've reached the first zero length, the first NVS table
366 * is located at an aligned offset which is at least 7 bytes further.
367 * NOTE: The wl->nvs->nvs element must be first, in order to
368 * simplify the casting, we assume it is at the beginning of
369 * the wl->nvs structure.
371 nvs_ptr
= (u8
*)wl
->nvs
+
372 ALIGN(nvs_ptr
- (u8
*)wl
->nvs
+ 7, 4);
373 nvs_len
-= nvs_ptr
- (u8
*)wl
->nvs
;
375 /* Now we must set the partition correctly */
376 wl1271_set_partition(wl
, &part_table
[PART_WORK
]);
378 /* Copy the NVS tables to a new block to ensure alignment */
379 nvs_aligned
= kmemdup(nvs_ptr
, nvs_len
, GFP_KERNEL
);
383 /* And finally we upload the NVS tables */
384 wl1271_write(wl
, CMD_MBOX_ADDRESS
, nvs_aligned
, nvs_len
, false);
390 static void wl1271_boot_enable_interrupts(struct wl1271
*wl
)
392 wl1271_enable_interrupts(wl
);
393 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
,
394 WL1271_ACX_INTR_ALL
& ~(WL1271_INTR_MASK
));
395 wl1271_write32(wl
, HI_CFG
, HI_CFG_DEF_VAL
);
398 static int wl1271_boot_soft_reset(struct wl1271
*wl
)
400 unsigned long timeout
;
403 /* perform soft reset */
404 wl1271_write32(wl
, ACX_REG_SLV_SOFT_RESET
, ACX_SLV_SOFT_RESET_BIT
);
406 /* SOFT_RESET is self clearing */
407 timeout
= jiffies
+ usecs_to_jiffies(SOFT_RESET_MAX_TIME
);
409 boot_data
= wl1271_read32(wl
, ACX_REG_SLV_SOFT_RESET
);
410 wl1271_debug(DEBUG_BOOT
, "soft reset bootdata 0x%x", boot_data
);
411 if ((boot_data
& ACX_SLV_SOFT_RESET_BIT
) == 0)
414 if (time_after(jiffies
, timeout
)) {
415 /* 1.2 check pWhalBus->uSelfClearTime if the
416 * timeout was reached */
417 wl1271_error("soft reset timeout");
421 udelay(SOFT_RESET_STALL_TIME
);
425 wl1271_write32(wl
, ENABLE
, 0x0);
427 /* disable auto calibration on start*/
428 wl1271_write32(wl
, SPARE_A2
, 0xffff);
433 static int wl1271_boot_run_firmware(struct wl1271
*wl
)
438 wl1271_boot_set_ecpu_ctrl(wl
, ECPU_CONTROL_HALT
);
440 chip_id
= wl1271_read32(wl
, CHIP_ID_B
);
442 wl1271_debug(DEBUG_BOOT
, "chip id after firmware boot: 0x%x", chip_id
);
444 if (chip_id
!= wl
->chip
.id
) {
445 wl1271_error("chip id doesn't match after firmware boot");
449 /* wait for init to complete */
451 while (loop
++ < INIT_LOOP
) {
452 udelay(INIT_LOOP_DELAY
);
453 intr
= wl1271_read32(wl
, ACX_REG_INTERRUPT_NO_CLEAR
);
455 if (intr
== 0xffffffff) {
456 wl1271_error("error reading hardware complete "
460 /* check that ACX_INTR_INIT_COMPLETE is enabled */
461 else if (intr
& WL1271_ACX_INTR_INIT_COMPLETE
) {
462 wl1271_write32(wl
, ACX_REG_INTERRUPT_ACK
,
463 WL1271_ACX_INTR_INIT_COMPLETE
);
468 if (loop
> INIT_LOOP
) {
469 wl1271_error("timeout waiting for the hardware to "
470 "complete initialization");
474 /* get hardware config command mail box */
475 wl
->cmd_box_addr
= wl1271_read32(wl
, REG_COMMAND_MAILBOX_PTR
);
477 /* get hardware config event mail box */
478 wl
->event_box_addr
= wl1271_read32(wl
, REG_EVENT_MAILBOX_PTR
);
480 /* set the working partition to its "running" mode offset */
481 wl1271_set_partition(wl
, &part_table
[PART_WORK
]);
483 wl1271_debug(DEBUG_MAILBOX
, "cmd_box_addr 0x%x event_box_addr 0x%x",
484 wl
->cmd_box_addr
, wl
->event_box_addr
);
486 wl1271_boot_fw_version(wl
);
489 * in case of full asynchronous mode the firmware event must be
490 * ready to receive event from the command mailbox
493 /* unmask required mbox events */
494 wl
->event_mask
= BSS_LOSE_EVENT_ID
|
495 SCAN_COMPLETE_EVENT_ID
|
497 DISCONNECT_EVENT_COMPLETE_ID
|
498 RSSI_SNR_TRIGGER_0_EVENT_ID
|
499 PSPOLL_DELIVERY_FAILURE_EVENT_ID
|
500 SOFT_GEMINI_SENSE_EVENT_ID
|
501 PERIODIC_SCAN_REPORT_EVENT_ID
|
502 PERIODIC_SCAN_COMPLETE_EVENT_ID
|
503 DUMMY_PACKET_EVENT_ID
|
504 PEER_REMOVE_COMPLETE_EVENT_ID
|
505 BA_SESSION_RX_CONSTRAINT_EVENT_ID
|
506 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID
|
507 INACTIVE_STA_EVENT_ID
|
508 MAX_TX_RETRY_EVENT_ID
|
509 CHANNEL_SWITCH_COMPLETE_EVENT_ID
;
511 ret
= wl1271_event_unmask(wl
);
513 wl1271_error("EVENT mask setting failed");
517 wl1271_event_mbox_config(wl
);
519 /* firmware startup completed */
523 static int wl1271_boot_write_irq_polarity(struct wl1271
*wl
)
527 polarity
= wl1271_top_reg_read(wl
, OCP_REG_POLARITY
);
529 /* We use HIGH polarity, so unset the LOW bit */
530 polarity
&= ~POLARITY_LOW
;
531 wl1271_top_reg_write(wl
, OCP_REG_POLARITY
, polarity
);
536 static void wl1271_boot_hw_version(struct wl1271
*wl
)
540 if (wl
->chip
.id
== CHIP_ID_1283_PG20
)
541 fuse
= wl1271_top_reg_read(wl
, WL128X_REG_FUSE_DATA_2_1
);
543 fuse
= wl1271_top_reg_read(wl
, WL127X_REG_FUSE_DATA_2_1
);
544 fuse
= (fuse
& PG_VER_MASK
) >> PG_VER_OFFSET
;
546 wl
->hw_pg_ver
= (s8
)fuse
;
549 static int wl128x_switch_tcxo_to_fref(struct wl1271
*wl
)
553 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
554 spare_reg
= wl1271_top_reg_read(wl
, WL_SPARE_REG
);
555 if (spare_reg
== 0xFFFF)
557 spare_reg
|= (BIT(3) | BIT(5) | BIT(6));
558 wl1271_top_reg_write(wl
, WL_SPARE_REG
, spare_reg
);
560 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
561 wl1271_top_reg_write(wl
, SYS_CLK_CFG_REG
,
562 WL_CLK_REQ_TYPE_PG2
| MCS_PLL_CLK_SEL_FREF
);
564 /* Delay execution for 15msec, to let the HW settle */
570 static bool wl128x_is_tcxo_valid(struct wl1271
*wl
)
574 tcxo_detection
= wl1271_top_reg_read(wl
, TCXO_CLK_DETECT_REG
);
575 if (tcxo_detection
& TCXO_DET_FAILED
)
581 static bool wl128x_is_fref_valid(struct wl1271
*wl
)
585 fref_detection
= wl1271_top_reg_read(wl
, FREF_CLK_DETECT_REG
);
586 if (fref_detection
& FREF_CLK_DETECT_FAIL
)
592 static int wl128x_manually_configure_mcs_pll(struct wl1271
*wl
)
594 wl1271_top_reg_write(wl
, MCS_PLL_M_REG
, MCS_PLL_M_REG_VAL
);
595 wl1271_top_reg_write(wl
, MCS_PLL_N_REG
, MCS_PLL_N_REG_VAL
);
596 wl1271_top_reg_write(wl
, MCS_PLL_CONFIG_REG
, MCS_PLL_CONFIG_REG_VAL
);
601 static int wl128x_configure_mcs_pll(struct wl1271
*wl
, int clk
)
607 /* Mask bits [3:1] in the sys_clk_cfg register */
608 spare_reg
= wl1271_top_reg_read(wl
, WL_SPARE_REG
);
609 if (spare_reg
== 0xFFFF)
612 wl1271_top_reg_write(wl
, WL_SPARE_REG
, spare_reg
);
614 /* Handle special cases of the TCXO clock */
615 if (wl
->tcxo_clock
== WL12XX_TCXOCLOCK_16_8
||
616 wl
->tcxo_clock
== WL12XX_TCXOCLOCK_33_6
)
617 return wl128x_manually_configure_mcs_pll(wl
);
619 /* Set the input frequency according to the selected clock source */
620 input_freq
= (clk
& 1) + 1;
622 pll_config
= wl1271_top_reg_read(wl
, MCS_PLL_CONFIG_REG
);
623 if (pll_config
== 0xFFFF)
625 pll_config
|= (input_freq
<< MCS_SEL_IN_FREQ_SHIFT
);
626 pll_config
|= MCS_PLL_ENABLE_HP
;
627 wl1271_top_reg_write(wl
, MCS_PLL_CONFIG_REG
, pll_config
);
633 * WL128x has two clocks input - TCXO and FREF.
634 * TCXO is the main clock of the device, while FREF is used to sync
635 * between the GPS and the cellular modem.
636 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
637 * as the WLAN/BT main clock.
639 static int wl128x_boot_clk(struct wl1271
*wl
, int *selected_clock
)
643 /* For XTAL-only modes, FREF will be used after switching from TCXO */
644 if (wl
->ref_clock
== WL12XX_REFCLOCK_26_XTAL
||
645 wl
->ref_clock
== WL12XX_REFCLOCK_38_XTAL
) {
646 if (!wl128x_switch_tcxo_to_fref(wl
))
651 /* Query the HW, to determine which clock source we should use */
652 sys_clk_cfg
= wl1271_top_reg_read(wl
, SYS_CLK_CFG_REG
);
653 if (sys_clk_cfg
== 0xFFFF)
655 if (sys_clk_cfg
& PRCM_CM_EN_MUX_WLAN_FREF
)
658 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
659 if (wl
->tcxo_clock
== WL12XX_TCXOCLOCK_16_368
||
660 wl
->tcxo_clock
== WL12XX_TCXOCLOCK_32_736
) {
661 if (!wl128x_switch_tcxo_to_fref(wl
))
666 /* TCXO clock is selected */
667 if (!wl128x_is_tcxo_valid(wl
))
669 *selected_clock
= wl
->tcxo_clock
;
673 /* FREF clock is selected */
674 if (!wl128x_is_fref_valid(wl
))
676 *selected_clock
= wl
->ref_clock
;
679 return wl128x_configure_mcs_pll(wl
, *selected_clock
);
682 static int wl127x_boot_clk(struct wl1271
*wl
)
687 if (((wl
->hw_pg_ver
& PG_MAJOR_VER_MASK
) >> PG_MAJOR_VER_OFFSET
) < 3)
688 wl
->quirks
|= WL12XX_QUIRK_END_OF_TRANSACTION
;
690 if (wl
->ref_clock
== CONF_REF_CLK_19_2_E
||
691 wl
->ref_clock
== CONF_REF_CLK_38_4_E
||
692 wl
->ref_clock
== CONF_REF_CLK_38_4_M_XTAL
)
693 /* ref clk: 19.2/38.4/38.4-XTAL */
695 else if (wl
->ref_clock
== CONF_REF_CLK_26_E
||
696 wl
->ref_clock
== CONF_REF_CLK_52_E
)
702 if (wl
->ref_clock
!= CONF_REF_CLK_19_2_E
) {
704 /* Set clock type (open drain) */
705 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_TYPE
);
706 val
&= FREF_CLK_TYPE_BITS
;
707 wl1271_top_reg_write(wl
, OCP_REG_CLK_TYPE
, val
);
709 /* Set clock pull mode (no pull) */
710 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_PULL
);
712 wl1271_top_reg_write(wl
, OCP_REG_CLK_PULL
, val
);
715 /* Set clock polarity */
716 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_POLARITY
);
717 val
&= FREF_CLK_POLARITY_BITS
;
718 val
|= CLK_REQ_OUTN_SEL
;
719 wl1271_top_reg_write(wl
, OCP_REG_CLK_POLARITY
, val
);
722 wl1271_write32(wl
, PLL_PARAMETERS
, clk
);
724 pause
= wl1271_read32(wl
, PLL_PARAMETERS
);
726 wl1271_debug(DEBUG_BOOT
, "pause1 0x%x", pause
);
728 pause
&= ~(WU_COUNTER_PAUSE_VAL
);
729 pause
|= WU_COUNTER_PAUSE_VAL
;
730 wl1271_write32(wl
, WU_COUNTER_PAUSE
, pause
);
735 /* uploads NVS and firmware */
736 int wl1271_load_firmware(struct wl1271
*wl
)
740 int selected_clock
= -1;
742 wl1271_boot_hw_version(wl
);
744 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
745 ret
= wl128x_boot_clk(wl
, &selected_clock
);
749 ret
= wl127x_boot_clk(wl
);
754 /* Continue the ELP wake up sequence */
755 wl1271_write32(wl
, WELP_ARM_COMMAND
, WELP_ARM_COMMAND_VAL
);
758 wl1271_set_partition(wl
, &part_table
[PART_DRPW
]);
760 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
761 to be used by DRPw FW. The RTRIM value will be added by the FW
762 before taking DRPw out of reset */
764 wl1271_debug(DEBUG_BOOT
, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START
);
765 clk
= wl1271_read32(wl
, DRPW_SCRATCH_START
);
767 wl1271_debug(DEBUG_BOOT
, "clk2 0x%x", clk
);
769 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
770 clk
|= ((selected_clock
& 0x3) << 1) << 4;
772 clk
|= (wl
->ref_clock
<< 1) << 4;
775 wl1271_write32(wl
, DRPW_SCRATCH_START
, clk
);
777 wl1271_set_partition(wl
, &part_table
[PART_WORK
]);
779 /* Disable interrupts */
780 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
, WL1271_ACX_INTR_ALL
);
782 ret
= wl1271_boot_soft_reset(wl
);
786 /* 2. start processing NVS file */
787 ret
= wl1271_boot_upload_nvs(wl
);
791 /* write firmware's last address (ie. it's length) to
792 * ACX_EEPROMLESS_IND_REG */
793 wl1271_debug(DEBUG_BOOT
, "ACX_EEPROMLESS_IND_REG");
795 wl1271_write32(wl
, ACX_EEPROMLESS_IND_REG
, ACX_EEPROMLESS_IND_REG
);
797 tmp
= wl1271_read32(wl
, CHIP_ID_B
);
799 wl1271_debug(DEBUG_BOOT
, "chip id 0x%x", tmp
);
801 /* 6. read the EEPROM parameters */
802 tmp
= wl1271_read32(wl
, SCR_PAD2
);
804 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
807 if (wl
->chip
.id
== CHIP_ID_1283_PG20
)
808 wl1271_top_reg_write(wl
, SDIO_IO_DS
, wl
->conf
.hci_io_ds
);
810 ret
= wl1271_boot_upload_firmware(wl
);
817 EXPORT_SYMBOL_GPL(wl1271_load_firmware
);
819 int wl1271_boot(struct wl1271
*wl
)
823 /* upload NVS and firmware */
824 ret
= wl1271_load_firmware(wl
);
828 /* 10.5 start firmware */
829 ret
= wl1271_boot_run_firmware(wl
);
833 ret
= wl1271_boot_write_irq_polarity(wl
);
837 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
,
838 WL1271_ACX_ALL_EVENTS_VECTOR
);
840 /* Enable firmware interrupts now */
841 wl1271_boot_enable_interrupts(wl
);
843 wl1271_event_mbox_config(wl
);