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[PATCH] zd1211rw: 16-bit writes for physical control registers
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / zd1211rw / zd_chip.c
1 /* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25
26 #include "zd_def.h"
27 #include "zd_chip.h"
28 #include "zd_ieee80211.h"
29 #include "zd_mac.h"
30 #include "zd_rf.h"
31 #include "zd_util.h"
32
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36 {
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41 }
42
43 void zd_chip_clear(struct zd_chip *chip)
44 {
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
50 }
51
52 static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
53 {
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
56 }
57
58 /* Prints an identifier line, which will support debugging. */
59 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
60 {
61 int i = 0;
62
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type,
71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-');
75 return i;
76 }
77
78 static void print_id(struct zd_chip *chip)
79 {
80 char buffer[80];
81
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
85 }
86
87 /* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
89 */
90 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
91 unsigned int count)
92 {
93 int r;
94 int i;
95 zd_addr_t *a16 = (zd_addr_t *)NULL;
96 u16 *v16;
97 unsigned int count16;
98
99 if (count > USB_MAX_IOREAD32_COUNT)
100 return -EINVAL;
101
102 /* Allocate a single memory block for values and addresses. */
103 count16 = 2*count;
104 a16 = (zd_addr_t *)kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
105 GFP_NOFS);
106 if (!a16) {
107 dev_dbg_f(zd_chip_dev(chip),
108 "error ENOMEM in allocation of a16\n");
109 r = -ENOMEM;
110 goto out;
111 }
112 v16 = (u16 *)(a16 + count16);
113
114 for (i = 0; i < count; i++) {
115 int j = 2*i;
116 /* We read the high word always first. */
117 a16[j] = zd_inc_word(addr[i]);
118 a16[j+1] = addr[i];
119 }
120
121 r = zd_ioread16v_locked(chip, v16, a16, count16);
122 if (r) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error: zd_ioread16v_locked. Error number %d\n", r);
125 goto out;
126 }
127
128 for (i = 0; i < count; i++) {
129 int j = 2*i;
130 values[i] = (v16[j] << 16) | v16[j+1];
131 }
132
133 out:
134 kfree((void *)a16);
135 return r;
136 }
137
138 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
139 unsigned int count)
140 {
141 int i, j, r;
142 struct zd_ioreq16 *ioreqs16;
143 unsigned int count16;
144
145 ZD_ASSERT(mutex_is_locked(&chip->mutex));
146
147 if (count == 0)
148 return 0;
149 if (count > USB_MAX_IOWRITE32_COUNT)
150 return -EINVAL;
151
152 /* Allocate a single memory block for values and addresses. */
153 count16 = 2*count;
154 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
155 if (!ioreqs16) {
156 r = -ENOMEM;
157 dev_dbg_f(zd_chip_dev(chip),
158 "error %d in ioreqs16 allocation\n", r);
159 goto out;
160 }
161
162 for (i = 0; i < count; i++) {
163 j = 2*i;
164 /* We write the high word always first. */
165 ioreqs16[j].value = ioreqs[i].value >> 16;
166 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
167 ioreqs16[j+1].value = ioreqs[i].value;
168 ioreqs16[j+1].addr = ioreqs[i].addr;
169 }
170
171 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
172 #ifdef DEBUG
173 if (r) {
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in zd_usb_write16v\n", r);
176 }
177 #endif /* DEBUG */
178 out:
179 kfree(ioreqs16);
180 return r;
181 }
182
183 int zd_iowrite16a_locked(struct zd_chip *chip,
184 const struct zd_ioreq16 *ioreqs, unsigned int count)
185 {
186 int r;
187 unsigned int i, j, t, max;
188
189 ZD_ASSERT(mutex_is_locked(&chip->mutex));
190 for (i = 0; i < count; i += j + t) {
191 t = 0;
192 max = count-i;
193 if (max > USB_MAX_IOWRITE16_COUNT)
194 max = USB_MAX_IOWRITE16_COUNT;
195 for (j = 0; j < max; j++) {
196 if (!ioreqs[i+j].addr) {
197 t = 1;
198 break;
199 }
200 }
201
202 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
203 if (r) {
204 dev_dbg_f(zd_chip_dev(chip),
205 "error zd_usb_iowrite16v. Error number %d\n",
206 r);
207 return r;
208 }
209 }
210
211 return 0;
212 }
213
214 /* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
217 */
218 int zd_iowrite32a_locked(struct zd_chip *chip,
219 const struct zd_ioreq32 *ioreqs, unsigned int count)
220 {
221 int r;
222 unsigned int i, j, t, max;
223
224 for (i = 0; i < count; i += j + t) {
225 t = 0;
226 max = count-i;
227 if (max > USB_MAX_IOWRITE32_COUNT)
228 max = USB_MAX_IOWRITE32_COUNT;
229 for (j = 0; j < max; j++) {
230 if (!ioreqs[i+j].addr) {
231 t = 1;
232 break;
233 }
234 }
235
236 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
237 if (r) {
238 dev_dbg_f(zd_chip_dev(chip),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r);
241 return r;
242 }
243 }
244
245 return 0;
246 }
247
248 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
249 {
250 int r;
251
252 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
253 mutex_lock(&chip->mutex);
254 r = zd_ioread16_locked(chip, value, addr);
255 mutex_unlock(&chip->mutex);
256 return r;
257 }
258
259 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
260 {
261 int r;
262
263 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
264 mutex_lock(&chip->mutex);
265 r = zd_ioread32_locked(chip, value, addr);
266 mutex_unlock(&chip->mutex);
267 return r;
268 }
269
270 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
271 {
272 int r;
273
274 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
275 mutex_lock(&chip->mutex);
276 r = zd_iowrite16_locked(chip, value, addr);
277 mutex_unlock(&chip->mutex);
278 return r;
279 }
280
281 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
282 {
283 int r;
284
285 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
286 mutex_lock(&chip->mutex);
287 r = zd_iowrite32_locked(chip, value, addr);
288 mutex_unlock(&chip->mutex);
289 return r;
290 }
291
292 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
293 u32 *values, unsigned int count)
294 {
295 int r;
296
297 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
298 mutex_lock(&chip->mutex);
299 r = zd_ioread32v_locked(chip, values, addresses, count);
300 mutex_unlock(&chip->mutex);
301 return r;
302 }
303
304 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
305 unsigned int count)
306 {
307 int r;
308
309 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
310 mutex_lock(&chip->mutex);
311 r = zd_iowrite32a_locked(chip, ioreqs, count);
312 mutex_unlock(&chip->mutex);
313 return r;
314 }
315
316 static int read_pod(struct zd_chip *chip, u8 *rf_type)
317 {
318 int r;
319 u32 value;
320
321 ZD_ASSERT(mutex_is_locked(&chip->mutex));
322 r = zd_ioread32_locked(chip, &value, E2P_POD);
323 if (r)
324 goto error;
325 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
326
327 /* FIXME: AL2230 handling (Bit 7 in POD) */
328 *rf_type = value & 0x0f;
329 chip->pa_type = (value >> 16) & 0x0f;
330 chip->patch_cck_gain = (value >> 8) & 0x1;
331 chip->patch_cr157 = (value >> 13) & 0x1;
332 chip->patch_6m_band_edge = (value >> 21) & 0x1;
333 chip->new_phy_layout = (value >> 31) & 0x1;
334
335 dev_dbg_f(zd_chip_dev(chip),
336 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
337 "patch 6M %d new PHY %d\n",
338 zd_rf_name(*rf_type), *rf_type,
339 chip->pa_type, chip->patch_cck_gain,
340 chip->patch_cr157, chip->patch_6m_band_edge, chip->new_phy_layout);
341 return 0;
342 error:
343 *rf_type = 0;
344 chip->pa_type = 0;
345 chip->patch_cck_gain = 0;
346 chip->patch_cr157 = 0;
347 chip->patch_6m_band_edge = 0;
348 chip->new_phy_layout = 0;
349 return r;
350 }
351
352 static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
353 const zd_addr_t *addr)
354 {
355 int r;
356 u32 parts[2];
357
358 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
359 if (r) {
360 dev_dbg_f(zd_chip_dev(chip),
361 "error: couldn't read e2p macs. Error number %d\n", r);
362 return r;
363 }
364
365 mac_addr[0] = parts[0];
366 mac_addr[1] = parts[0] >> 8;
367 mac_addr[2] = parts[0] >> 16;
368 mac_addr[3] = parts[0] >> 24;
369 mac_addr[4] = parts[1];
370 mac_addr[5] = parts[1] >> 8;
371
372 return 0;
373 }
374
375 static int read_e2p_mac_addr(struct zd_chip *chip)
376 {
377 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
378
379 ZD_ASSERT(mutex_is_locked(&chip->mutex));
380 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
381 }
382
383 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
384 * CR_MAC_ADDR_P2 must be overwritten
385 */
386 void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
387 {
388 mutex_lock(&chip->mutex);
389 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
390 mutex_unlock(&chip->mutex);
391 }
392
393 static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
394 {
395 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
396 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
397 }
398
399 int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
400 {
401 int r;
402
403 dev_dbg_f(zd_chip_dev(chip), "\n");
404 mutex_lock(&chip->mutex);
405 r = read_mac_addr(chip, mac_addr);
406 mutex_unlock(&chip->mutex);
407 return r;
408 }
409
410 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
411 {
412 int r;
413 struct zd_ioreq32 reqs[2] = {
414 [0] = { .addr = CR_MAC_ADDR_P1 },
415 [1] = { .addr = CR_MAC_ADDR_P2 },
416 };
417
418 reqs[0].value = (mac_addr[3] << 24)
419 | (mac_addr[2] << 16)
420 | (mac_addr[1] << 8)
421 | mac_addr[0];
422 reqs[1].value = (mac_addr[5] << 8)
423 | mac_addr[4];
424
425 dev_dbg_f(zd_chip_dev(chip),
426 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
427
428 mutex_lock(&chip->mutex);
429 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
430 #ifdef DEBUG
431 {
432 u8 tmp[ETH_ALEN];
433 read_mac_addr(chip, tmp);
434 }
435 #endif /* DEBUG */
436 mutex_unlock(&chip->mutex);
437 return r;
438 }
439
440 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
441 {
442 int r;
443 u32 value;
444
445 mutex_lock(&chip->mutex);
446 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
447 mutex_unlock(&chip->mutex);
448 if (r)
449 return r;
450
451 *regdomain = value >> 16;
452 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
453
454 return 0;
455 }
456
457 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
458 zd_addr_t e2p_addr, u32 guard)
459 {
460 int r;
461 int i;
462 u32 v;
463
464 ZD_ASSERT(mutex_is_locked(&chip->mutex));
465 for (i = 0;;) {
466 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
467 if (r)
468 return r;
469 v -= guard;
470 if (i+4 < count) {
471 values[i++] = v;
472 values[i++] = v >> 8;
473 values[i++] = v >> 16;
474 values[i++] = v >> 24;
475 continue;
476 }
477 for (;i < count; i++)
478 values[i] = v >> (8*(i%3));
479 return 0;
480 }
481 }
482
483 static int read_pwr_cal_values(struct zd_chip *chip)
484 {
485 return read_values(chip, chip->pwr_cal_values,
486 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
487 0);
488 }
489
490 static int read_pwr_int_values(struct zd_chip *chip)
491 {
492 return read_values(chip, chip->pwr_int_values,
493 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
494 E2P_PWR_INT_GUARD);
495 }
496
497 static int read_ofdm_cal_values(struct zd_chip *chip)
498 {
499 int r;
500 int i;
501 static const zd_addr_t addresses[] = {
502 E2P_36M_CAL_VALUE1,
503 E2P_48M_CAL_VALUE1,
504 E2P_54M_CAL_VALUE1,
505 };
506
507 for (i = 0; i < 3; i++) {
508 r = read_values(chip, chip->ofdm_cal_values[i],
509 E2P_CHANNEL_COUNT, addresses[i], 0);
510 if (r)
511 return r;
512 }
513 return 0;
514 }
515
516 static int read_cal_int_tables(struct zd_chip *chip)
517 {
518 int r;
519
520 r = read_pwr_cal_values(chip);
521 if (r)
522 return r;
523 r = read_pwr_int_values(chip);
524 if (r)
525 return r;
526 r = read_ofdm_cal_values(chip);
527 if (r)
528 return r;
529 return 0;
530 }
531
532 /* phy means physical registers */
533 int zd_chip_lock_phy_regs(struct zd_chip *chip)
534 {
535 int r;
536 u32 tmp;
537
538 ZD_ASSERT(mutex_is_locked(&chip->mutex));
539 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
540 if (r) {
541 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
542 return r;
543 }
544
545 dev_dbg_f(zd_chip_dev(chip),
546 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
547 tmp &= ~UNLOCK_PHY_REGS;
548
549 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
550 if (r)
551 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
552 return r;
553 }
554
555 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
556 {
557 int r;
558 u32 tmp;
559
560 ZD_ASSERT(mutex_is_locked(&chip->mutex));
561 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
562 if (r) {
563 dev_err(zd_chip_dev(chip),
564 "error ioread32(CR_REG1): %d\n", r);
565 return r;
566 }
567
568 dev_dbg_f(zd_chip_dev(chip),
569 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
570 tmp |= UNLOCK_PHY_REGS;
571
572 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
573 if (r)
574 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
575 return r;
576 }
577
578 /* CR157 can be optionally patched by the EEPROM */
579 static int patch_cr157(struct zd_chip *chip)
580 {
581 int r;
582 u32 value;
583
584 if (!chip->patch_cr157)
585 return 0;
586
587 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
588 if (r)
589 return r;
590
591 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
592 return zd_iowrite32_locked(chip, value >> 8, CR157);
593 }
594
595 /*
596 * 6M band edge can be optionally overwritten for certain RF's
597 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
598 * bit (for AL2230, AL2230S)
599 */
600 static int patch_6m_band_edge(struct zd_chip *chip, int channel)
601 {
602 struct zd_ioreq16 ioreqs[] = {
603 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
604 { CR47, 0x1e },
605 };
606
607 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
608 return 0;
609
610 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
611 if (channel == 1 || channel == 11)
612 ioreqs[0].value = 0x12;
613
614 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
615 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
616 }
617
618 static int zd1211_hw_reset_phy(struct zd_chip *chip)
619 {
620 static const struct zd_ioreq16 ioreqs[] = {
621 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
622 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
623 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
624 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
625 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
626 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
627 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
628 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
629 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
630 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
631 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
632 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
633 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
634 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
635 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
636 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
637 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
638 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
639 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
640 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
641 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
642 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
643 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
644 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
645 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
646 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
647 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
648 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
649 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
650 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
651 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
652 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
653 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
654 { },
655 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
656 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
657 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
658 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
659 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
660 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
661 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
662 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
663 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
664 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
665 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
666 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
667 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
668 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
669 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
670 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
671 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
672 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
673 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
674 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
675 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
676 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
677 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
678 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
679 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
680 /* Note: CR204 must lead the CR203 */
681 { CR204, 0x7d },
682 { },
683 { CR203, 0x30 },
684 };
685
686 int r, t;
687
688 dev_dbg_f(zd_chip_dev(chip), "\n");
689
690 r = zd_chip_lock_phy_regs(chip);
691 if (r)
692 goto out;
693
694 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
695 if (r)
696 goto unlock;
697
698 r = patch_cr157(chip);
699 unlock:
700 t = zd_chip_unlock_phy_regs(chip);
701 if (t && !r)
702 r = t;
703 out:
704 return r;
705 }
706
707 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
708 {
709 static const struct zd_ioreq16 ioreqs[] = {
710 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
711 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
712 { CR10, 0x81 },
713 /* power control { { CR11, 1 << 6 }, */
714 { CR11, 0x00 },
715 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
716 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
717 { CR18, 0x0a }, { CR19, 0x48 },
718 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
719 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
720 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
721 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
722 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
723 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
724 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
725 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
726 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
727 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
728 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
729 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
730 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
731 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
732 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
733 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
734 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
735 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
736 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
737 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
738 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
739 { CR94, 0x01 },
740 { CR95, 0x20 }, /* ZD1211B */
741 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
742 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
743 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
744 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
745 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
746 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
747 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
748 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
749 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
750 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
751 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
752 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
753 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
754 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
755 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
756 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
757 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
758 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
759 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
760 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
761 { CR170, 0xba }, { CR171, 0xba },
762 /* Note: CR204 must lead the CR203 */
763 { CR204, 0x7d },
764 {},
765 { CR203, 0x30 },
766 };
767
768 int r, t;
769
770 dev_dbg_f(zd_chip_dev(chip), "\n");
771
772 r = zd_chip_lock_phy_regs(chip);
773 if (r)
774 goto out;
775
776 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
777 if (r)
778 goto unlock;
779
780 r = patch_cr157(chip);
781 unlock:
782 t = zd_chip_unlock_phy_regs(chip);
783 if (t && !r)
784 r = t;
785 out:
786 return r;
787 }
788
789 static int hw_reset_phy(struct zd_chip *chip)
790 {
791 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
792 zd1211_hw_reset_phy(chip);
793 }
794
795 static int zd1211_hw_init_hmac(struct zd_chip *chip)
796 {
797 static const struct zd_ioreq32 ioreqs[] = {
798 { CR_ACK_TIMEOUT_EXT, 0x20 },
799 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
800 { CR_ZD1211_RETRY_MAX, 0x2 },
801 { CR_SNIFFER_ON, 0 },
802 { CR_RX_FILTER, STA_RX_FILTER },
803 { CR_GROUP_HASH_P1, 0x00 },
804 { CR_GROUP_HASH_P2, 0x80000000 },
805 { CR_REG1, 0xa4 },
806 { CR_ADDA_PWR_DWN, 0x7f },
807 { CR_BCN_PLCP_CFG, 0x00f00401 },
808 { CR_PHY_DELAY, 0x00 },
809 { CR_ACK_TIMEOUT_EXT, 0x80 },
810 { CR_ADDA_PWR_DWN, 0x00 },
811 { CR_ACK_TIME_80211, 0x100 },
812 { CR_RX_PE_DELAY, 0x70 },
813 { CR_PS_CTRL, 0x10000000 },
814 { CR_RTS_CTS_RATE, 0x02030203 },
815 { CR_RX_THRESHOLD, 0x000c0640 },
816 { CR_AFTER_PNP, 0x1 },
817 { CR_WEP_PROTECT, 0x114 },
818 };
819
820 int r;
821
822 dev_dbg_f(zd_chip_dev(chip), "\n");
823 ZD_ASSERT(mutex_is_locked(&chip->mutex));
824 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
825 #ifdef DEBUG
826 if (r) {
827 dev_err(zd_chip_dev(chip),
828 "error in zd_iowrite32a_locked. Error number %d\n", r);
829 }
830 #endif /* DEBUG */
831 return r;
832 }
833
834 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
835 {
836 static const struct zd_ioreq32 ioreqs[] = {
837 { CR_ACK_TIMEOUT_EXT, 0x20 },
838 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
839 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
840 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
841 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
842 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
843 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
844 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
845 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
846 { CR_ZD1211B_TXOP, 0x01800824 },
847 { CR_SNIFFER_ON, 0 },
848 { CR_RX_FILTER, STA_RX_FILTER },
849 { CR_GROUP_HASH_P1, 0x00 },
850 { CR_GROUP_HASH_P2, 0x80000000 },
851 { CR_REG1, 0xa4 },
852 { CR_ADDA_PWR_DWN, 0x7f },
853 { CR_BCN_PLCP_CFG, 0x00f00401 },
854 { CR_PHY_DELAY, 0x00 },
855 { CR_ACK_TIMEOUT_EXT, 0x80 },
856 { CR_ADDA_PWR_DWN, 0x00 },
857 { CR_ACK_TIME_80211, 0x100 },
858 { CR_RX_PE_DELAY, 0x70 },
859 { CR_PS_CTRL, 0x10000000 },
860 { CR_RTS_CTS_RATE, 0x02030203 },
861 { CR_RX_THRESHOLD, 0x000c0eff, },
862 { CR_AFTER_PNP, 0x1 },
863 { CR_WEP_PROTECT, 0x114 },
864 };
865
866 int r;
867
868 dev_dbg_f(zd_chip_dev(chip), "\n");
869 ZD_ASSERT(mutex_is_locked(&chip->mutex));
870 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
871 if (r) {
872 dev_dbg_f(zd_chip_dev(chip),
873 "error in zd_iowrite32a_locked. Error number %d\n", r);
874 }
875 return r;
876 }
877
878 static int hw_init_hmac(struct zd_chip *chip)
879 {
880 return chip->is_zd1211b ?
881 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
882 }
883
884 struct aw_pt_bi {
885 u32 atim_wnd_period;
886 u32 pre_tbtt;
887 u32 beacon_interval;
888 };
889
890 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
891 {
892 int r;
893 static const zd_addr_t aw_pt_bi_addr[] =
894 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
895 u32 values[3];
896
897 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
898 ARRAY_SIZE(aw_pt_bi_addr));
899 if (r) {
900 memset(s, 0, sizeof(*s));
901 return r;
902 }
903
904 s->atim_wnd_period = values[0];
905 s->pre_tbtt = values[1];
906 s->beacon_interval = values[2];
907 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
908 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
909 return 0;
910 }
911
912 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
913 {
914 struct zd_ioreq32 reqs[3];
915
916 if (s->beacon_interval <= 5)
917 s->beacon_interval = 5;
918 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
919 s->pre_tbtt = s->beacon_interval - 1;
920 if (s->atim_wnd_period >= s->pre_tbtt)
921 s->atim_wnd_period = s->pre_tbtt - 1;
922
923 reqs[0].addr = CR_ATIM_WND_PERIOD;
924 reqs[0].value = s->atim_wnd_period;
925 reqs[1].addr = CR_PRE_TBTT;
926 reqs[1].value = s->pre_tbtt;
927 reqs[2].addr = CR_BCN_INTERVAL;
928 reqs[2].value = s->beacon_interval;
929
930 dev_dbg_f(zd_chip_dev(chip),
931 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
932 s->beacon_interval);
933 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
934 }
935
936
937 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
938 {
939 int r;
940 struct aw_pt_bi s;
941
942 ZD_ASSERT(mutex_is_locked(&chip->mutex));
943 r = get_aw_pt_bi(chip, &s);
944 if (r)
945 return r;
946 s.beacon_interval = interval;
947 return set_aw_pt_bi(chip, &s);
948 }
949
950 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
951 {
952 int r;
953
954 mutex_lock(&chip->mutex);
955 r = set_beacon_interval(chip, interval);
956 mutex_unlock(&chip->mutex);
957 return r;
958 }
959
960 static int hw_init(struct zd_chip *chip)
961 {
962 int r;
963
964 dev_dbg_f(zd_chip_dev(chip), "\n");
965 ZD_ASSERT(mutex_is_locked(&chip->mutex));
966 r = hw_reset_phy(chip);
967 if (r)
968 return r;
969
970 r = hw_init_hmac(chip);
971 if (r)
972 return r;
973
974 /* Although the vendor driver defaults to a different value during
975 * init, it overwrites the IFS value with the following every time
976 * the channel changes. We should aim to be more intelligent... */
977 r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
978 if (r)
979 return r;
980
981 return set_beacon_interval(chip, 100);
982 }
983
984 #ifdef DEBUG
985 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
986 const char *addr_string)
987 {
988 int r;
989 u32 value;
990
991 r = zd_ioread32_locked(chip, &value, addr);
992 if (r) {
993 dev_dbg_f(zd_chip_dev(chip),
994 "error reading %s. Error number %d\n", addr_string, r);
995 return r;
996 }
997
998 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
999 addr_string, (unsigned int)value);
1000 return 0;
1001 }
1002
1003 static int test_init(struct zd_chip *chip)
1004 {
1005 int r;
1006
1007 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1008 if (r)
1009 return r;
1010 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1011 if (r)
1012 return r;
1013 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1014 }
1015
1016 static void dump_fw_registers(struct zd_chip *chip)
1017 {
1018 static const zd_addr_t addr[4] = {
1019 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
1020 FW_LINK_STATUS
1021 };
1022
1023 int r;
1024 u16 values[4];
1025
1026 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1027 ARRAY_SIZE(addr));
1028 if (r) {
1029 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1030 r);
1031 return;
1032 }
1033
1034 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1035 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1036 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1037 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1038 }
1039 #endif /* DEBUG */
1040
1041 static int print_fw_version(struct zd_chip *chip)
1042 {
1043 int r;
1044 u16 version;
1045
1046 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1047 if (r)
1048 return r;
1049
1050 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1051 return 0;
1052 }
1053
1054 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1055 {
1056 u32 rates;
1057 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1058 /* This sets the mandatory rates, which only depend from the standard
1059 * that the device is supporting. Until further notice we should try
1060 * to support 802.11g also for full speed USB.
1061 */
1062 switch (std) {
1063 case IEEE80211B:
1064 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1065 break;
1066 case IEEE80211G:
1067 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1068 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1069 break;
1070 default:
1071 return -EINVAL;
1072 }
1073 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1074 }
1075
1076 int zd_chip_enable_hwint(struct zd_chip *chip)
1077 {
1078 int r;
1079
1080 mutex_lock(&chip->mutex);
1081 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1082 mutex_unlock(&chip->mutex);
1083 return r;
1084 }
1085
1086 static int disable_hwint(struct zd_chip *chip)
1087 {
1088 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1089 }
1090
1091 int zd_chip_disable_hwint(struct zd_chip *chip)
1092 {
1093 int r;
1094
1095 mutex_lock(&chip->mutex);
1096 r = disable_hwint(chip);
1097 mutex_unlock(&chip->mutex);
1098 return r;
1099 }
1100
1101 int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1102 {
1103 int r;
1104 u8 rf_type;
1105
1106 dev_dbg_f(zd_chip_dev(chip), "\n");
1107
1108 mutex_lock(&chip->mutex);
1109 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1110
1111 #ifdef DEBUG
1112 r = test_init(chip);
1113 if (r)
1114 goto out;
1115 #endif
1116 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1117 if (r)
1118 goto out;
1119
1120 r = zd_usb_init_hw(&chip->usb);
1121 if (r)
1122 goto out;
1123
1124 /* GPI is always disabled, also in the other driver.
1125 */
1126 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1127 if (r)
1128 goto out;
1129 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1130 if (r)
1131 goto out;
1132 /* Currently we support IEEE 802.11g for full and high speed USB.
1133 * It might be discussed, whether we should suppport pure b mode for
1134 * full speed USB.
1135 */
1136 r = set_mandatory_rates(chip, IEEE80211G);
1137 if (r)
1138 goto out;
1139 /* Disabling interrupts is certainly a smart thing here.
1140 */
1141 r = disable_hwint(chip);
1142 if (r)
1143 goto out;
1144 r = read_pod(chip, &rf_type);
1145 if (r)
1146 goto out;
1147 r = hw_init(chip);
1148 if (r)
1149 goto out;
1150 r = zd_rf_init_hw(&chip->rf, rf_type);
1151 if (r)
1152 goto out;
1153
1154 r = print_fw_version(chip);
1155 if (r)
1156 goto out;
1157
1158 #ifdef DEBUG
1159 dump_fw_registers(chip);
1160 r = test_init(chip);
1161 if (r)
1162 goto out;
1163 #endif /* DEBUG */
1164
1165 r = read_e2p_mac_addr(chip);
1166 if (r)
1167 goto out;
1168
1169 r = read_cal_int_tables(chip);
1170 if (r)
1171 goto out;
1172
1173 print_id(chip);
1174 out:
1175 mutex_unlock(&chip->mutex);
1176 return r;
1177 }
1178
1179 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1180 {
1181 u8 value = chip->pwr_int_values[channel - 1];
1182 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1183 channel, value);
1184 return zd_iowrite16_locked(chip, value, CR31);
1185 }
1186
1187 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1188 {
1189 u8 value = chip->pwr_cal_values[channel-1];
1190 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1191 channel, value);
1192 return zd_iowrite16_locked(chip, value, CR68);
1193 }
1194
1195 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1196 {
1197 struct zd_ioreq16 ioreqs[3];
1198
1199 ioreqs[0].addr = CR67;
1200 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1201 ioreqs[1].addr = CR66;
1202 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1203 ioreqs[2].addr = CR65;
1204 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1205
1206 dev_dbg_f(zd_chip_dev(chip),
1207 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1208 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1209 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1210 }
1211
1212 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1213 u8 channel)
1214 {
1215 int r;
1216
1217 r = update_pwr_int(chip, channel);
1218 if (r)
1219 return r;
1220 if (chip->is_zd1211b) {
1221 static const struct zd_ioreq16 ioreqs[] = {
1222 { CR69, 0x28 },
1223 {},
1224 { CR69, 0x2a },
1225 };
1226
1227 r = update_ofdm_cal(chip, channel);
1228 if (r)
1229 return r;
1230 r = update_pwr_cal(chip, channel);
1231 if (r)
1232 return r;
1233 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1234 if (r)
1235 return r;
1236 }
1237
1238 return 0;
1239 }
1240
1241 /* The CCK baseband gain can be optionally patched by the EEPROM */
1242 static int patch_cck_gain(struct zd_chip *chip)
1243 {
1244 int r;
1245 u32 value;
1246
1247 if (!chip->patch_cck_gain)
1248 return 0;
1249
1250 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1251 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1252 if (r)
1253 return r;
1254 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1255 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1256 }
1257
1258 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1259 {
1260 int r, t;
1261
1262 mutex_lock(&chip->mutex);
1263 r = zd_chip_lock_phy_regs(chip);
1264 if (r)
1265 goto out;
1266 r = zd_rf_set_channel(&chip->rf, channel);
1267 if (r)
1268 goto unlock;
1269 r = update_channel_integration_and_calibration(chip, channel);
1270 if (r)
1271 goto unlock;
1272 r = patch_cck_gain(chip);
1273 if (r)
1274 goto unlock;
1275 r = patch_6m_band_edge(chip, channel);
1276 if (r)
1277 goto unlock;
1278 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1279 unlock:
1280 t = zd_chip_unlock_phy_regs(chip);
1281 if (t && !r)
1282 r = t;
1283 out:
1284 mutex_unlock(&chip->mutex);
1285 return r;
1286 }
1287
1288 u8 zd_chip_get_channel(struct zd_chip *chip)
1289 {
1290 u8 channel;
1291
1292 mutex_lock(&chip->mutex);
1293 channel = chip->rf.channel;
1294 mutex_unlock(&chip->mutex);
1295 return channel;
1296 }
1297
1298 static u16 led_mask(int led)
1299 {
1300 switch (led) {
1301 case 1:
1302 return LED1;
1303 case 2:
1304 return LED2;
1305 default:
1306 return 0;
1307 }
1308 }
1309
1310 static int read_led_reg(struct zd_chip *chip, u16 *status)
1311 {
1312 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1313 return zd_ioread16_locked(chip, status, CR_LED);
1314 }
1315
1316 static int write_led_reg(struct zd_chip *chip, u16 status)
1317 {
1318 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1319 return zd_iowrite16_locked(chip, status, CR_LED);
1320 }
1321
1322 int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status)
1323 {
1324 int r, ret;
1325 u16 mask = led_mask(led);
1326 u16 reg;
1327
1328 if (!mask)
1329 return -EINVAL;
1330 mutex_lock(&chip->mutex);
1331 r = read_led_reg(chip, &reg);
1332 if (r)
1333 return r;
1334 switch (status) {
1335 case LED_STATUS:
1336 return (reg & mask) ? LED_ON : LED_OFF;
1337 case LED_OFF:
1338 reg &= ~mask;
1339 ret = LED_OFF;
1340 break;
1341 case LED_FLIP:
1342 reg ^= mask;
1343 ret = (reg&mask) ? LED_ON : LED_OFF;
1344 break;
1345 case LED_ON:
1346 reg |= mask;
1347 ret = LED_ON;
1348 break;
1349 default:
1350 return -EINVAL;
1351 }
1352 r = write_led_reg(chip, reg);
1353 if (r) {
1354 ret = r;
1355 goto out;
1356 }
1357 out:
1358 mutex_unlock(&chip->mutex);
1359 return r;
1360 }
1361
1362 int zd_chip_led_flip(struct zd_chip *chip, int led,
1363 const unsigned int *phases_msecs, unsigned int count)
1364 {
1365 int i, r;
1366 enum led_status status;
1367
1368 r = zd_chip_led_status(chip, led, LED_STATUS);
1369 if (r)
1370 return r;
1371 status = r;
1372 for (i = 0; i < count; i++) {
1373 r = zd_chip_led_status(chip, led, LED_FLIP);
1374 if (r < 0)
1375 goto out;
1376 msleep(phases_msecs[i]);
1377 }
1378
1379 out:
1380 zd_chip_led_status(chip, led, status);
1381 return r;
1382 }
1383
1384 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1385 {
1386 int r;
1387
1388 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1389 return -EINVAL;
1390
1391 mutex_lock(&chip->mutex);
1392 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1393 mutex_unlock(&chip->mutex);
1394 return r;
1395 }
1396
1397 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1398 {
1399 static const u16 constants[] = {
1400 715, 655, 585, 540, 470, 410, 360, 315,
1401 270, 235, 205, 175, 150, 125, 105, 85,
1402 65, 50, 40, 25, 15
1403 };
1404
1405 int i;
1406 u32 x;
1407
1408 /* It seems that their quality parameter is somehow per signal
1409 * and is now transferred per bit.
1410 */
1411 switch (rate) {
1412 case ZD_OFDM_RATE_6M:
1413 case ZD_OFDM_RATE_12M:
1414 case ZD_OFDM_RATE_24M:
1415 size *= 2;
1416 break;
1417 case ZD_OFDM_RATE_9M:
1418 case ZD_OFDM_RATE_18M:
1419 case ZD_OFDM_RATE_36M:
1420 case ZD_OFDM_RATE_54M:
1421 size *= 4;
1422 size /= 3;
1423 break;
1424 case ZD_OFDM_RATE_48M:
1425 size *= 3;
1426 size /= 2;
1427 break;
1428 default:
1429 return -EINVAL;
1430 }
1431
1432 x = (10000 * status_quality)/size;
1433 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1434 if (x > constants[i])
1435 break;
1436 }
1437
1438 switch (rate) {
1439 case ZD_OFDM_RATE_6M:
1440 case ZD_OFDM_RATE_9M:
1441 i += 3;
1442 break;
1443 case ZD_OFDM_RATE_12M:
1444 case ZD_OFDM_RATE_18M:
1445 i += 5;
1446 break;
1447 case ZD_OFDM_RATE_24M:
1448 case ZD_OFDM_RATE_36M:
1449 i += 9;
1450 break;
1451 case ZD_OFDM_RATE_48M:
1452 case ZD_OFDM_RATE_54M:
1453 i += 15;
1454 break;
1455 default:
1456 return -EINVAL;
1457 }
1458
1459 return i;
1460 }
1461
1462 static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1463 {
1464 int r;
1465
1466 r = ofdm_qual_db(status_quality, rate, size);
1467 ZD_ASSERT(r >= 0);
1468 if (r < 0)
1469 r = 0;
1470
1471 r = (r * 100)/29;
1472 return r <= 100 ? r : 100;
1473 }
1474
1475 static unsigned int log10times100(unsigned int x)
1476 {
1477 static const u8 log10[] = {
1478 0,
1479 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1480 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1481 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1482 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1483 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1484 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1485 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1486 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1487 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1488 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1489 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1490 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1491 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1492 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1493 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1494 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1495 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1496 223, 223, 223, 224, 224, 224, 224,
1497 };
1498
1499 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1500 }
1501
1502 enum {
1503 MAX_CCK_EVM_DB = 45,
1504 };
1505
1506 static int cck_evm_db(u8 status_quality)
1507 {
1508 return (20 * log10times100(status_quality)) / 100;
1509 }
1510
1511 static int cck_snr_db(u8 status_quality)
1512 {
1513 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1514 ZD_ASSERT(r >= 0);
1515 return r;
1516 }
1517
1518 static int cck_qual_percent(u8 status_quality)
1519 {
1520 int r;
1521
1522 r = cck_snr_db(status_quality);
1523 r = (100*r)/17;
1524 return r <= 100 ? r : 100;
1525 }
1526
1527 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1528 const struct rx_status *status)
1529 {
1530 return (status->frame_status&ZD_RX_OFDM) ?
1531 ofdm_qual_percent(status->signal_quality_ofdm,
1532 zd_ofdm_plcp_header_rate(rx_frame),
1533 size) :
1534 cck_qual_percent(status->signal_quality_cck);
1535 }
1536
1537 u8 zd_rx_strength_percent(u8 rssi)
1538 {
1539 int r = (rssi*100) / 41;
1540 if (r > 100)
1541 r = 100;
1542 return (u8) r;
1543 }
1544
1545 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1546 {
1547 static const u16 ofdm_rates[] = {
1548 [ZD_OFDM_RATE_6M] = 60,
1549 [ZD_OFDM_RATE_9M] = 90,
1550 [ZD_OFDM_RATE_12M] = 120,
1551 [ZD_OFDM_RATE_18M] = 180,
1552 [ZD_OFDM_RATE_24M] = 240,
1553 [ZD_OFDM_RATE_36M] = 360,
1554 [ZD_OFDM_RATE_48M] = 480,
1555 [ZD_OFDM_RATE_54M] = 540,
1556 };
1557 u16 rate;
1558 if (status->frame_status & ZD_RX_OFDM) {
1559 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1560 rate = ofdm_rates[ofdm_rate & 0xf];
1561 } else {
1562 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1563 switch (cck_rate) {
1564 case ZD_CCK_SIGNAL_1M:
1565 rate = 10;
1566 break;
1567 case ZD_CCK_SIGNAL_2M:
1568 rate = 20;
1569 break;
1570 case ZD_CCK_SIGNAL_5M5:
1571 rate = 55;
1572 break;
1573 case ZD_CCK_SIGNAL_11M:
1574 rate = 110;
1575 break;
1576 default:
1577 rate = 0;
1578 }
1579 }
1580
1581 return rate;
1582 }
1583
1584 int zd_chip_switch_radio_on(struct zd_chip *chip)
1585 {
1586 int r;
1587
1588 mutex_lock(&chip->mutex);
1589 r = zd_switch_radio_on(&chip->rf);
1590 mutex_unlock(&chip->mutex);
1591 return r;
1592 }
1593
1594 int zd_chip_switch_radio_off(struct zd_chip *chip)
1595 {
1596 int r;
1597
1598 mutex_lock(&chip->mutex);
1599 r = zd_switch_radio_off(&chip->rf);
1600 mutex_unlock(&chip->mutex);
1601 return r;
1602 }
1603
1604 int zd_chip_enable_int(struct zd_chip *chip)
1605 {
1606 int r;
1607
1608 mutex_lock(&chip->mutex);
1609 r = zd_usb_enable_int(&chip->usb);
1610 mutex_unlock(&chip->mutex);
1611 return r;
1612 }
1613
1614 void zd_chip_disable_int(struct zd_chip *chip)
1615 {
1616 mutex_lock(&chip->mutex);
1617 zd_usb_disable_int(&chip->usb);
1618 mutex_unlock(&chip->mutex);
1619 }
1620
1621 int zd_chip_enable_rx(struct zd_chip *chip)
1622 {
1623 int r;
1624
1625 mutex_lock(&chip->mutex);
1626 r = zd_usb_enable_rx(&chip->usb);
1627 mutex_unlock(&chip->mutex);
1628 return r;
1629 }
1630
1631 void zd_chip_disable_rx(struct zd_chip *chip)
1632 {
1633 mutex_lock(&chip->mutex);
1634 zd_usb_disable_rx(&chip->usb);
1635 mutex_unlock(&chip->mutex);
1636 }
1637
1638 int zd_rfwritev_locked(struct zd_chip *chip,
1639 const u32* values, unsigned int count, u8 bits)
1640 {
1641 int r;
1642 unsigned int i;
1643
1644 for (i = 0; i < count; i++) {
1645 r = zd_rfwrite_locked(chip, values[i], bits);
1646 if (r)
1647 return r;
1648 }
1649
1650 return 0;
1651 }
1652
1653 /*
1654 * We can optionally program the RF directly through CR regs, if supported by
1655 * the hardware. This is much faster than the older method.
1656 */
1657 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1658 {
1659 struct zd_ioreq16 ioreqs[] = {
1660 { CR244, (value >> 16) & 0xff },
1661 { CR243, (value >> 8) & 0xff },
1662 { CR242, value & 0xff },
1663 };
1664 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1665 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1666 }
1667
1668 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1669 const u32 *values, unsigned int count)
1670 {
1671 int r;
1672 unsigned int i;
1673
1674 for (i = 0; i < count; i++) {
1675 r = zd_rfwrite_cr_locked(chip, values[i]);
1676 if (r)
1677 return r;
1678 }
1679
1680 return 0;
1681 }
1682
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