]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/nfc/pn544_hci.c
NFC: Remove crc generation from shdlc layer
[mirror_ubuntu-zesty-kernel.git] / drivers / nfc / pn544_hci.c
1 /*
2 * HCI based Driver for NXP PN544 NFC Chip
3 *
4 * Copyright (C) 2012 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/crc-ccitt.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/miscdevice.h>
26 #include <linux/interrupt.h>
27 #include <linux/gpio.h>
28 #include <linux/i2c.h>
29
30 #include <linux/nfc.h>
31 #include <net/nfc/hci.h>
32 #include <net/nfc/shdlc.h>
33
34 #include <linux/nfc/pn544.h>
35
36 #define DRIVER_DESC "HCI NFC driver for PN544"
37
38 #define PN544_HCI_DRIVER_NAME "pn544_hci"
39
40 /* Timing restrictions (ms) */
41 #define PN544_HCI_RESETVEN_TIME 30
42
43 static struct i2c_device_id pn544_hci_id_table[] = {
44 {"pn544", 0},
45 {}
46 };
47
48 MODULE_DEVICE_TABLE(i2c, pn544_hci_id_table);
49
50 #define HCI_MODE 0
51 #define FW_MODE 1
52
53 /* framing in HCI mode */
54 #define PN544_HCI_LLC_LEN 1
55 #define PN544_HCI_LLC_CRC 2
56 #define PN544_HCI_LLC_LEN_CRC (PN544_HCI_LLC_LEN + PN544_HCI_LLC_CRC)
57 #define PN544_HCI_LLC_MIN_SIZE (1 + PN544_HCI_LLC_LEN_CRC)
58 #define PN544_HCI_LLC_MAX_PAYLOAD 29
59 #define PN544_HCI_LLC_MAX_SIZE (PN544_HCI_LLC_LEN_CRC + 1 + \
60 PN544_HCI_LLC_MAX_PAYLOAD)
61
62 enum pn544_state {
63 PN544_ST_COLD,
64 PN544_ST_FW_READY,
65 PN544_ST_READY,
66 };
67
68 #define FULL_VERSION_LEN 11
69
70 /* Proprietary commands */
71 #define PN544_WRITE 0x3f
72
73 /* Proprietary gates, events, commands and registers */
74
75 /* NFC_HCI_RF_READER_A_GATE additional registers and commands */
76 #define PN544_RF_READER_A_AUTO_ACTIVATION 0x10
77 #define PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION 0x12
78 #define PN544_MIFARE_CMD 0x21
79
80 /* Commands that apply to all RF readers */
81 #define PN544_RF_READER_CMD_PRESENCE_CHECK 0x30
82 #define PN544_RF_READER_CMD_ACTIVATE_NEXT 0x32
83
84 /* NFC_HCI_ID_MGMT_GATE additional registers */
85 #define PN544_ID_MGMT_FULL_VERSION_SW 0x10
86
87 #define PN544_RF_READER_ISO15693_GATE 0x12
88
89 #define PN544_RF_READER_F_GATE 0x14
90 #define PN544_FELICA_ID 0x04
91 #define PN544_FELICA_RAW 0x20
92
93 #define PN544_RF_READER_JEWEL_GATE 0x15
94 #define PN544_JEWEL_RAW_CMD 0x23
95
96 #define PN544_RF_READER_NFCIP1_INITIATOR_GATE 0x30
97 #define PN544_RF_READER_NFCIP1_TARGET_GATE 0x31
98
99 #define PN544_SYS_MGMT_GATE 0x90
100 #define PN544_SYS_MGMT_INFO_NOTIFICATION 0x02
101
102 #define PN544_POLLING_LOOP_MGMT_GATE 0x94
103 #define PN544_PL_RDPHASES 0x06
104 #define PN544_PL_EMULATION 0x07
105 #define PN544_PL_NFCT_DEACTIVATED 0x09
106
107 #define PN544_SWP_MGMT_GATE 0xA0
108
109 #define PN544_NFC_WI_MGMT_GATE 0xA1
110
111 static struct nfc_hci_gate pn544_gates[] = {
112 {NFC_HCI_ADMIN_GATE, NFC_HCI_INVALID_PIPE},
113 {NFC_HCI_LOOPBACK_GATE, NFC_HCI_INVALID_PIPE},
114 {NFC_HCI_ID_MGMT_GATE, NFC_HCI_INVALID_PIPE},
115 {NFC_HCI_LINK_MGMT_GATE, NFC_HCI_INVALID_PIPE},
116 {NFC_HCI_RF_READER_B_GATE, NFC_HCI_INVALID_PIPE},
117 {NFC_HCI_RF_READER_A_GATE, NFC_HCI_INVALID_PIPE},
118 {PN544_SYS_MGMT_GATE, NFC_HCI_INVALID_PIPE},
119 {PN544_SWP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
120 {PN544_POLLING_LOOP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
121 {PN544_NFC_WI_MGMT_GATE, NFC_HCI_INVALID_PIPE},
122 {PN544_RF_READER_F_GATE, NFC_HCI_INVALID_PIPE},
123 {PN544_RF_READER_JEWEL_GATE, NFC_HCI_INVALID_PIPE},
124 {PN544_RF_READER_ISO15693_GATE, NFC_HCI_INVALID_PIPE},
125 {PN544_RF_READER_NFCIP1_INITIATOR_GATE, NFC_HCI_INVALID_PIPE},
126 {PN544_RF_READER_NFCIP1_TARGET_GATE, NFC_HCI_INVALID_PIPE}
127 };
128
129 /* Largest headroom needed for outgoing custom commands */
130 #define PN544_CMDS_HEADROOM 2
131 #define PN544_FRAME_HEADROOM 1
132 #define PN544_FRAME_TAILROOM 2
133
134 struct pn544_hci_info {
135 struct i2c_client *i2c_dev;
136 struct nfc_shdlc *shdlc;
137
138 enum pn544_state state;
139
140 struct mutex info_lock;
141
142 unsigned int gpio_en;
143 unsigned int gpio_irq;
144 unsigned int gpio_fw;
145 unsigned int en_polarity;
146
147 int hard_fault; /*
148 * < 0 if hardware error occured (e.g. i2c err)
149 * and prevents normal operation.
150 */
151 };
152
153 static void pn544_hci_platform_init(struct pn544_hci_info *info)
154 {
155 int polarity, retry, ret;
156 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
157 int count = sizeof(rset_cmd);
158
159 pr_info(DRIVER_DESC ": %s\n", __func__);
160 dev_info(&info->i2c_dev->dev, "Detecting nfc_en polarity\n");
161
162 /* Disable fw download */
163 gpio_set_value(info->gpio_fw, 0);
164
165 for (polarity = 0; polarity < 2; polarity++) {
166 info->en_polarity = polarity;
167 retry = 3;
168 while (retry--) {
169 /* power off */
170 gpio_set_value(info->gpio_en, !info->en_polarity);
171 usleep_range(10000, 15000);
172
173 /* power on */
174 gpio_set_value(info->gpio_en, info->en_polarity);
175 usleep_range(10000, 15000);
176
177 /* send reset */
178 dev_dbg(&info->i2c_dev->dev, "Sending reset cmd\n");
179 ret = i2c_master_send(info->i2c_dev, rset_cmd, count);
180 if (ret == count) {
181 dev_info(&info->i2c_dev->dev,
182 "nfc_en polarity : active %s\n",
183 (polarity == 0 ? "low" : "high"));
184 goto out;
185 }
186 }
187 }
188
189 dev_err(&info->i2c_dev->dev,
190 "Could not detect nfc_en polarity, fallback to active high\n");
191
192 out:
193 gpio_set_value(info->gpio_en, !info->en_polarity);
194 }
195
196 static int pn544_hci_enable(struct pn544_hci_info *info, int mode)
197 {
198 pr_info(DRIVER_DESC ": %s\n", __func__);
199
200 gpio_set_value(info->gpio_fw, 0);
201 gpio_set_value(info->gpio_en, info->en_polarity);
202 usleep_range(10000, 15000);
203
204 return 0;
205 }
206
207 static void pn544_hci_disable(struct pn544_hci_info *info)
208 {
209 pr_info(DRIVER_DESC ": %s\n", __func__);
210
211 gpio_set_value(info->gpio_fw, 0);
212 gpio_set_value(info->gpio_en, !info->en_polarity);
213 usleep_range(10000, 15000);
214
215 gpio_set_value(info->gpio_en, info->en_polarity);
216 usleep_range(10000, 15000);
217
218 gpio_set_value(info->gpio_en, !info->en_polarity);
219 usleep_range(10000, 15000);
220 }
221
222 static int pn544_hci_i2c_write(struct i2c_client *client, u8 *buf, int len)
223 {
224 int r;
225
226 usleep_range(3000, 6000);
227
228 r = i2c_master_send(client, buf, len);
229
230 if (r == -EREMOTEIO) { /* Retry, chip was in standby */
231 usleep_range(6000, 10000);
232 r = i2c_master_send(client, buf, len);
233 }
234
235 if (r >= 0 && r != len)
236 r = -EREMOTEIO;
237
238 return r;
239 }
240
241 static int check_crc(u8 *buf, int buflen)
242 {
243 int len;
244 u16 crc;
245
246 len = buf[0] + 1;
247 crc = crc_ccitt(0xffff, buf, len - 2);
248 crc = ~crc;
249
250 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
251 pr_err(PN544_HCI_DRIVER_NAME ": CRC error 0x%x != 0x%x 0x%x\n",
252 crc, buf[len - 1], buf[len - 2]);
253
254 pr_info(DRIVER_DESC ": %s : BAD CRC\n", __func__);
255 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
256 16, 2, buf, buflen, false);
257 return -EPERM;
258 }
259 return 0;
260 }
261
262 /*
263 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
264 * that i2c bus will be flushed and that next read will start on a new frame.
265 * returned skb contains only LLC header and payload.
266 * returns:
267 * -EREMOTEIO : i2c read error (fatal)
268 * -EBADMSG : frame was incorrect and discarded
269 * -ENOMEM : cannot allocate skb, frame dropped
270 */
271 static int pn544_hci_i2c_read(struct i2c_client *client, struct sk_buff **skb)
272 {
273 int r;
274 u8 len;
275 u8 tmp[PN544_HCI_LLC_MAX_SIZE - 1];
276
277 r = i2c_master_recv(client, &len, 1);
278 if (r != 1) {
279 dev_err(&client->dev, "cannot read len byte\n");
280 return -EREMOTEIO;
281 }
282
283 if ((len < (PN544_HCI_LLC_MIN_SIZE - 1)) ||
284 (len > (PN544_HCI_LLC_MAX_SIZE - 1))) {
285 dev_err(&client->dev, "invalid len byte\n");
286 r = -EBADMSG;
287 goto flush;
288 }
289
290 *skb = alloc_skb(1 + len, GFP_KERNEL);
291 if (*skb == NULL) {
292 r = -ENOMEM;
293 goto flush;
294 }
295
296 *skb_put(*skb, 1) = len;
297
298 r = i2c_master_recv(client, skb_put(*skb, len), len);
299 if (r != len) {
300 kfree_skb(*skb);
301 return -EREMOTEIO;
302 }
303
304 r = check_crc((*skb)->data, (*skb)->len);
305 if (r != 0) {
306 kfree_skb(*skb);
307 r = -EBADMSG;
308 goto flush;
309 }
310
311 skb_pull(*skb, 1);
312 skb_trim(*skb, (*skb)->len - 2);
313
314 usleep_range(3000, 6000);
315
316 return 0;
317
318 flush:
319 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
320 r = -EREMOTEIO;
321
322 usleep_range(3000, 6000);
323
324 return r;
325 }
326
327 /*
328 * Reads an shdlc frame from the chip. This is not as straightforward as it
329 * seems. There are cases where we could loose the frame start synchronization.
330 * The frame format is len-data-crc, and corruption can occur anywhere while
331 * transiting on i2c bus, such that we could read an invalid len.
332 * In order to recover synchronization with the next frame, we must be sure
333 * to read the real amount of data without using the len byte. We do this by
334 * assuming the following:
335 * - the chip will always present only one single complete frame on the bus
336 * before triggering the interrupt
337 * - the chip will not present a new frame until we have completely read
338 * the previous one (or until we have handled the interrupt).
339 * The tricky case is when we read a corrupted len that is less than the real
340 * len. We must detect this here in order to determine that we need to flush
341 * the bus. This is the reason why we check the crc here.
342 */
343 static irqreturn_t pn544_hci_irq_thread_fn(int irq, void *dev_id)
344 {
345 struct pn544_hci_info *info = dev_id;
346 struct i2c_client *client = info->i2c_dev;
347 struct sk_buff *skb = NULL;
348 int r;
349
350 BUG_ON(!info);
351 BUG_ON(irq != info->i2c_dev->irq);
352
353 dev_dbg(&client->dev, "IRQ\n");
354
355 if (info->hard_fault != 0)
356 return IRQ_HANDLED;
357
358 r = pn544_hci_i2c_read(client, &skb);
359 if (r == -EREMOTEIO) {
360 info->hard_fault = r;
361
362 nfc_shdlc_recv_frame(info->shdlc, NULL);
363
364 return IRQ_HANDLED;
365 } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
366 return IRQ_HANDLED;
367 }
368
369 nfc_shdlc_recv_frame(info->shdlc, skb);
370
371 return IRQ_HANDLED;
372 }
373
374 static int pn544_hci_open(struct nfc_shdlc *shdlc)
375 {
376 struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
377 int r = 0;
378
379 mutex_lock(&info->info_lock);
380
381 if (info->state != PN544_ST_COLD) {
382 r = -EBUSY;
383 goto out;
384 }
385
386 r = pn544_hci_enable(info, HCI_MODE);
387
388 if (r == 0)
389 info->state = PN544_ST_READY;
390
391 out:
392 mutex_unlock(&info->info_lock);
393 return r;
394 }
395
396 static void pn544_hci_close(struct nfc_shdlc *shdlc)
397 {
398 struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
399
400 mutex_lock(&info->info_lock);
401
402 if (info->state == PN544_ST_COLD)
403 goto out;
404
405 pn544_hci_disable(info);
406
407 info->state = PN544_ST_COLD;
408
409 out:
410 mutex_unlock(&info->info_lock);
411 }
412
413 static int pn544_hci_ready(struct nfc_shdlc *shdlc)
414 {
415 struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
416 struct sk_buff *skb;
417 static struct hw_config {
418 u8 adr[2];
419 u8 value;
420 } hw_config[] = {
421 {{0x9f, 0x9a}, 0x00},
422
423 {{0x98, 0x10}, 0xbc},
424
425 {{0x9e, 0x71}, 0x00},
426
427 {{0x98, 0x09}, 0x00},
428
429 {{0x9e, 0xb4}, 0x00},
430
431 {{0x9e, 0xd9}, 0xff},
432 {{0x9e, 0xda}, 0xff},
433 {{0x9e, 0xdb}, 0x23},
434 {{0x9e, 0xdc}, 0x21},
435 {{0x9e, 0xdd}, 0x22},
436 {{0x9e, 0xde}, 0x24},
437
438 {{0x9c, 0x01}, 0x08},
439
440 {{0x9e, 0xaa}, 0x01},
441
442 {{0x9b, 0xd1}, 0x0d},
443 {{0x9b, 0xd2}, 0x24},
444 {{0x9b, 0xd3}, 0x0a},
445 {{0x9b, 0xd4}, 0x22},
446 {{0x9b, 0xd5}, 0x08},
447 {{0x9b, 0xd6}, 0x1e},
448 {{0x9b, 0xdd}, 0x1c},
449
450 {{0x9b, 0x84}, 0x13},
451 {{0x99, 0x81}, 0x7f},
452 {{0x99, 0x31}, 0x70},
453
454 {{0x98, 0x00}, 0x3f},
455
456 {{0x9f, 0x09}, 0x00},
457
458 {{0x9f, 0x0a}, 0x05},
459
460 {{0x9e, 0xd1}, 0xa1},
461 {{0x99, 0x23}, 0x00},
462
463 {{0x9e, 0x74}, 0x80},
464
465 {{0x9f, 0x28}, 0x10},
466
467 {{0x9f, 0x35}, 0x14},
468
469 {{0x9f, 0x36}, 0x60},
470
471 {{0x9c, 0x31}, 0x00},
472
473 {{0x9c, 0x32}, 0xc8},
474
475 {{0x9c, 0x19}, 0x40},
476
477 {{0x9c, 0x1a}, 0x40},
478
479 {{0x9c, 0x0c}, 0x00},
480
481 {{0x9c, 0x0d}, 0x00},
482
483 {{0x9c, 0x12}, 0x00},
484
485 {{0x9c, 0x13}, 0x00},
486
487 {{0x98, 0xa2}, 0x0e},
488
489 {{0x98, 0x93}, 0x40},
490
491 {{0x98, 0x7d}, 0x02},
492 {{0x98, 0x7e}, 0x00},
493 {{0x9f, 0xc8}, 0x01},
494 };
495 struct hw_config *p = hw_config;
496 int count = ARRAY_SIZE(hw_config);
497 struct sk_buff *res_skb;
498 u8 param[4];
499 int r;
500
501 param[0] = 0;
502 while (count--) {
503 param[1] = p->adr[0];
504 param[2] = p->adr[1];
505 param[3] = p->value;
506
507 r = nfc_hci_send_cmd(hdev, PN544_SYS_MGMT_GATE, PN544_WRITE,
508 param, 4, &res_skb);
509 if (r < 0)
510 return r;
511
512 if (res_skb->len != 1) {
513 kfree_skb(res_skb);
514 return -EPROTO;
515 }
516
517 if (res_skb->data[0] != p->value) {
518 kfree_skb(res_skb);
519 return -EIO;
520 }
521
522 kfree_skb(res_skb);
523
524 p++;
525 }
526
527 param[0] = NFC_HCI_UICC_HOST_ID;
528 r = nfc_hci_set_param(hdev, NFC_HCI_ADMIN_GATE,
529 NFC_HCI_ADMIN_WHITELIST, param, 1);
530 if (r < 0)
531 return r;
532
533 param[0] = 0x3d;
534 r = nfc_hci_set_param(hdev, PN544_SYS_MGMT_GATE,
535 PN544_SYS_MGMT_INFO_NOTIFICATION, param, 1);
536 if (r < 0)
537 return r;
538
539 param[0] = 0x0;
540 r = nfc_hci_set_param(hdev, NFC_HCI_RF_READER_A_GATE,
541 PN544_RF_READER_A_AUTO_ACTIVATION, param, 1);
542 if (r < 0)
543 return r;
544
545 r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
546 NFC_HCI_EVT_END_OPERATION, NULL, 0);
547 if (r < 0)
548 return r;
549
550 param[0] = 0x1;
551 r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
552 PN544_PL_NFCT_DEACTIVATED, param, 1);
553 if (r < 0)
554 return r;
555
556 param[0] = 0x0;
557 r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
558 PN544_PL_RDPHASES, param, 1);
559 if (r < 0)
560 return r;
561
562 r = nfc_hci_get_param(hdev, NFC_HCI_ID_MGMT_GATE,
563 PN544_ID_MGMT_FULL_VERSION_SW, &skb);
564 if (r < 0)
565 return r;
566
567 if (skb->len != FULL_VERSION_LEN) {
568 kfree_skb(skb);
569 return -EINVAL;
570 }
571
572 print_hex_dump(KERN_DEBUG, "FULL VERSION SOFTWARE INFO: ",
573 DUMP_PREFIX_NONE, 16, 1,
574 skb->data, FULL_VERSION_LEN, false);
575
576 kfree_skb(skb);
577
578 return 0;
579 }
580
581 static void pn544_hci_add_len_crc(struct sk_buff *skb)
582 {
583 u16 crc;
584 int len;
585
586 len = skb->len + 2;
587 *skb_push(skb, 1) = len;
588
589 crc = crc_ccitt(0xffff, skb->data, skb->len);
590 crc = ~crc;
591 *skb_put(skb, 1) = crc & 0xff;
592 *skb_put(skb, 1) = crc >> 8;
593 }
594
595 static void pn544_hci_remove_len_crc(struct sk_buff *skb)
596 {
597 skb_pull(skb, PN544_FRAME_HEADROOM);
598 skb_trim(skb, PN544_FRAME_TAILROOM);
599 }
600
601 static int pn544_hci_xmit(struct nfc_shdlc *shdlc, struct sk_buff *skb)
602 {
603 struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
604 struct i2c_client *client = info->i2c_dev;
605 int r;
606
607 if (info->hard_fault != 0)
608 return info->hard_fault;
609
610 pn544_hci_add_len_crc(skb);
611 r = pn544_hci_i2c_write(client, skb->data, skb->len);
612 pn544_hci_remove_len_crc(skb);
613
614 return r;
615 }
616
617 static int pn544_hci_start_poll(struct nfc_shdlc *shdlc,
618 u32 im_protocols, u32 tm_protocols)
619 {
620 struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
621 u8 phases = 0;
622 int r;
623 u8 duration[2];
624 u8 activated;
625
626 pr_info(DRIVER_DESC ": %s protocols 0x%x 0x%x\n",
627 __func__, im_protocols, tm_protocols);
628
629 r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
630 NFC_HCI_EVT_END_OPERATION, NULL, 0);
631 if (r < 0)
632 return r;
633
634 duration[0] = 0x18;
635 duration[1] = 0x6a;
636 r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
637 PN544_PL_EMULATION, duration, 2);
638 if (r < 0)
639 return r;
640
641 activated = 0;
642 r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
643 PN544_PL_NFCT_DEACTIVATED, &activated, 1);
644 if (r < 0)
645 return r;
646
647 if (im_protocols & (NFC_PROTO_ISO14443_MASK | NFC_PROTO_MIFARE_MASK |
648 NFC_PROTO_JEWEL_MASK))
649 phases |= 1; /* Type A */
650 if (im_protocols & NFC_PROTO_FELICA_MASK) {
651 phases |= (1 << 2); /* Type F 212 */
652 phases |= (1 << 3); /* Type F 424 */
653 }
654
655 phases |= (1 << 5); /* NFC active */
656
657 r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
658 PN544_PL_RDPHASES, &phases, 1);
659 if (r < 0)
660 return r;
661
662 r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
663 NFC_HCI_EVT_READER_REQUESTED, NULL, 0);
664 if (r < 0)
665 nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
666 NFC_HCI_EVT_END_OPERATION, NULL, 0);
667
668 return r;
669 }
670
671 static int pn544_hci_target_from_gate(struct nfc_shdlc *shdlc, u8 gate,
672 struct nfc_target *target)
673 {
674 switch (gate) {
675 case PN544_RF_READER_F_GATE:
676 target->supported_protocols = NFC_PROTO_FELICA_MASK;
677 break;
678 case PN544_RF_READER_JEWEL_GATE:
679 target->supported_protocols = NFC_PROTO_JEWEL_MASK;
680 target->sens_res = 0x0c00;
681 break;
682 default:
683 return -EPROTO;
684 }
685
686 return 0;
687 }
688
689 static int pn544_hci_complete_target_discovered(struct nfc_shdlc *shdlc,
690 u8 gate,
691 struct nfc_target *target)
692 {
693 struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
694 struct sk_buff *uid_skb;
695 int r = 0;
696
697 if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
698 if (target->nfcid1_len != 4 && target->nfcid1_len != 7 &&
699 target->nfcid1_len != 10)
700 return -EPROTO;
701
702 r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
703 PN544_RF_READER_CMD_ACTIVATE_NEXT,
704 target->nfcid1, target->nfcid1_len, NULL);
705 } else if (target->supported_protocols & NFC_PROTO_FELICA_MASK) {
706 r = nfc_hci_get_param(hdev, PN544_RF_READER_F_GATE,
707 PN544_FELICA_ID, &uid_skb);
708 if (r < 0)
709 return r;
710
711 if (uid_skb->len != 8) {
712 kfree_skb(uid_skb);
713 return -EPROTO;
714 }
715
716 r = nfc_hci_send_cmd(hdev, PN544_RF_READER_F_GATE,
717 PN544_RF_READER_CMD_ACTIVATE_NEXT,
718 uid_skb->data, uid_skb->len, NULL);
719 kfree_skb(uid_skb);
720 } else if (target->supported_protocols & NFC_PROTO_ISO14443_MASK) {
721 /*
722 * TODO: maybe other ISO 14443 require some kind of continue
723 * activation, but for now we've seen only this one below.
724 */
725 if (target->sens_res == 0x4403) /* Type 4 Mifare DESFire */
726 r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
727 PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION,
728 NULL, 0, NULL);
729 }
730
731 return r;
732 }
733
734 #define MIFARE_CMD_AUTH_KEY_A 0x60
735 #define MIFARE_CMD_AUTH_KEY_B 0x61
736 #define MIFARE_CMD_HEADER 2
737 #define MIFARE_UID_LEN 4
738 #define MIFARE_KEY_LEN 6
739 #define MIFARE_CMD_LEN 12
740 /*
741 * Returns:
742 * <= 0: driver handled the data exchange
743 * 1: driver doesn't especially handle, please do standard processing
744 */
745 static int pn544_hci_data_exchange(struct nfc_shdlc *shdlc,
746 struct nfc_target *target,
747 struct sk_buff *skb,
748 struct sk_buff **res_skb)
749 {
750 struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
751 int r;
752
753 pr_info(DRIVER_DESC ": %s for gate=%d\n", __func__,
754 target->hci_reader_gate);
755
756 switch (target->hci_reader_gate) {
757 case NFC_HCI_RF_READER_A_GATE:
758 if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
759 /*
760 * It seems that pn544 is inverting key and UID for
761 * MIFARE authentication commands.
762 */
763 if (skb->len == MIFARE_CMD_LEN &&
764 (skb->data[0] == MIFARE_CMD_AUTH_KEY_A ||
765 skb->data[0] == MIFARE_CMD_AUTH_KEY_B)) {
766 u8 uid[MIFARE_UID_LEN];
767 u8 *data = skb->data + MIFARE_CMD_HEADER;
768
769 memcpy(uid, data + MIFARE_KEY_LEN,
770 MIFARE_UID_LEN);
771 memmove(data + MIFARE_UID_LEN, data,
772 MIFARE_KEY_LEN);
773 memcpy(data, uid, MIFARE_UID_LEN);
774 }
775
776 return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
777 PN544_MIFARE_CMD,
778 skb->data, skb->len, res_skb);
779 } else
780 return 1;
781 case PN544_RF_READER_F_GATE:
782 *skb_push(skb, 1) = 0;
783 *skb_push(skb, 1) = 0;
784
785 r = nfc_hci_send_cmd(hdev, target->hci_reader_gate,
786 PN544_FELICA_RAW,
787 skb->data, skb->len, res_skb);
788 if (r == 0)
789 skb_pull(*res_skb, 1);
790 return r;
791 case PN544_RF_READER_JEWEL_GATE:
792 return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
793 PN544_JEWEL_RAW_CMD,
794 skb->data, skb->len, res_skb);
795 default:
796 return 1;
797 }
798 }
799
800 static int pn544_hci_check_presence(struct nfc_shdlc *shdlc,
801 struct nfc_target *target)
802 {
803 struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
804
805 return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
806 PN544_RF_READER_CMD_PRESENCE_CHECK,
807 NULL, 0, NULL);
808 }
809
810 static struct nfc_shdlc_ops pn544_shdlc_ops = {
811 .open = pn544_hci_open,
812 .close = pn544_hci_close,
813 .hci_ready = pn544_hci_ready,
814 .xmit = pn544_hci_xmit,
815 .start_poll = pn544_hci_start_poll,
816 .target_from_gate = pn544_hci_target_from_gate,
817 .complete_target_discovered = pn544_hci_complete_target_discovered,
818 .data_exchange = pn544_hci_data_exchange,
819 .check_presence = pn544_hci_check_presence,
820 };
821
822 static int __devinit pn544_hci_probe(struct i2c_client *client,
823 const struct i2c_device_id *id)
824 {
825 struct pn544_hci_info *info;
826 struct pn544_nfc_platform_data *pdata;
827 int r = 0;
828 u32 protocols;
829 struct nfc_hci_init_data init_data;
830
831 dev_dbg(&client->dev, "%s\n", __func__);
832 dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
833
834 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
835 dev_err(&client->dev, "Need I2C_FUNC_I2C\n");
836 return -ENODEV;
837 }
838
839 info = kzalloc(sizeof(struct pn544_hci_info), GFP_KERNEL);
840 if (!info) {
841 dev_err(&client->dev,
842 "Cannot allocate memory for pn544_hci_info.\n");
843 r = -ENOMEM;
844 goto err_info_alloc;
845 }
846
847 info->i2c_dev = client;
848 info->state = PN544_ST_COLD;
849 mutex_init(&info->info_lock);
850 i2c_set_clientdata(client, info);
851
852 pdata = client->dev.platform_data;
853 if (pdata == NULL) {
854 dev_err(&client->dev, "No platform data\n");
855 r = -EINVAL;
856 goto err_pdata;
857 }
858
859 if (pdata->request_resources == NULL) {
860 dev_err(&client->dev, "request_resources() missing\n");
861 r = -EINVAL;
862 goto err_pdata;
863 }
864
865 r = pdata->request_resources(client);
866 if (r) {
867 dev_err(&client->dev, "Cannot get platform resources\n");
868 goto err_pdata;
869 }
870
871 info->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE);
872 info->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET);
873 info->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ);
874
875 pn544_hci_platform_init(info);
876
877 r = request_threaded_irq(client->irq, NULL, pn544_hci_irq_thread_fn,
878 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
879 PN544_HCI_DRIVER_NAME, info);
880 if (r < 0) {
881 dev_err(&client->dev, "Unable to register IRQ handler\n");
882 goto err_rti;
883 }
884
885 init_data.gate_count = ARRAY_SIZE(pn544_gates);
886
887 memcpy(init_data.gates, pn544_gates, sizeof(pn544_gates));
888
889 /*
890 * TODO: Session id must include the driver name + some bus addr
891 * persistent info to discriminate 2 identical chips
892 */
893 strcpy(init_data.session_id, "ID544HCI");
894
895 protocols = NFC_PROTO_JEWEL_MASK |
896 NFC_PROTO_MIFARE_MASK |
897 NFC_PROTO_FELICA_MASK |
898 NFC_PROTO_ISO14443_MASK |
899 NFC_PROTO_ISO14443_B_MASK |
900 NFC_PROTO_NFC_DEP_MASK;
901
902 info->shdlc = nfc_shdlc_allocate(&pn544_shdlc_ops,
903 &init_data, protocols,
904 PN544_FRAME_HEADROOM + PN544_CMDS_HEADROOM,
905 PN544_FRAME_TAILROOM,
906 PN544_HCI_LLC_MAX_PAYLOAD,
907 dev_name(&client->dev));
908 if (!info->shdlc) {
909 dev_err(&client->dev, "Cannot allocate nfc shdlc.\n");
910 r = -ENOMEM;
911 goto err_allocshdlc;
912 }
913
914 nfc_shdlc_set_clientdata(info->shdlc, info);
915
916 return 0;
917
918 err_allocshdlc:
919 free_irq(client->irq, info);
920
921 err_rti:
922 if (pdata->free_resources != NULL)
923 pdata->free_resources();
924
925 err_pdata:
926 kfree(info);
927
928 err_info_alloc:
929 return r;
930 }
931
932 static __devexit int pn544_hci_remove(struct i2c_client *client)
933 {
934 struct pn544_hci_info *info = i2c_get_clientdata(client);
935 struct pn544_nfc_platform_data *pdata = client->dev.platform_data;
936
937 dev_dbg(&client->dev, "%s\n", __func__);
938
939 nfc_shdlc_free(info->shdlc);
940
941 if (info->state != PN544_ST_COLD) {
942 if (pdata->disable)
943 pdata->disable();
944 }
945
946 free_irq(client->irq, info);
947 if (pdata->free_resources)
948 pdata->free_resources();
949
950 kfree(info);
951
952 return 0;
953 }
954
955 static struct i2c_driver pn544_hci_driver = {
956 .driver = {
957 .name = PN544_HCI_DRIVER_NAME,
958 },
959 .probe = pn544_hci_probe,
960 .id_table = pn544_hci_id_table,
961 .remove = __devexit_p(pn544_hci_remove),
962 };
963
964 static int __init pn544_hci_init(void)
965 {
966 int r;
967
968 pr_debug(DRIVER_DESC ": %s\n", __func__);
969
970 r = i2c_add_driver(&pn544_hci_driver);
971 if (r) {
972 pr_err(PN544_HCI_DRIVER_NAME ": driver registration failed\n");
973 return r;
974 }
975
976 return 0;
977 }
978
979 static void __exit pn544_hci_exit(void)
980 {
981 i2c_del_driver(&pn544_hci_driver);
982 }
983
984 module_init(pn544_hci_init);
985 module_exit(pn544_hci_exit);
986
987 MODULE_LICENSE("GPL");
988 MODULE_DESCRIPTION(DRIVER_DESC);