2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/pci.h>
28 #include <linux/poison.h>
29 #include <linux/t10-pi.h>
30 #include <linux/timer.h>
31 #include <linux/types.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #include <asm/unaligned.h>
34 #include <linux/sed-opal.h>
38 #define NVME_Q_DEPTH 1024
39 #define NVME_AQ_DEPTH 256
40 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
41 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
44 * We handle AEN commands ourselves and don't even let the
45 * block layer know about them.
47 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
49 static int use_threaded_interrupts
;
50 module_param(use_threaded_interrupts
, int, 0);
52 static bool use_cmb_sqes
= true;
53 module_param(use_cmb_sqes
, bool, 0644);
54 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
56 static unsigned int max_host_mem_size_mb
= 128;
57 module_param(max_host_mem_size_mb
, uint
, 0444);
58 MODULE_PARM_DESC(max_host_mem_size_mb
,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
64 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
65 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
68 * Represents an NVM Express device. Each nvme_dev is a PCI function.
71 struct nvme_queue
**queues
;
72 struct blk_mq_tag_set tagset
;
73 struct blk_mq_tag_set admin_tagset
;
76 struct dma_pool
*prp_page_pool
;
77 struct dma_pool
*prp_small_pool
;
79 unsigned online_queues
;
84 unsigned long bar_mapped_size
;
85 struct work_struct remove_work
;
86 struct mutex shutdown_lock
;
89 dma_addr_t cmb_dma_addr
;
93 struct nvme_ctrl ctrl
;
94 struct completion ioq_wait
;
96 /* shadow doorbell buffer support: */
98 dma_addr_t dbbuf_dbs_dma_addr
;
100 dma_addr_t dbbuf_eis_dma_addr
;
102 /* host memory buffer support: */
104 u32 nr_host_mem_descs
;
105 struct nvme_host_mem_buf_desc
*host_mem_descs
;
106 void **host_mem_desc_bufs
;
109 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
111 return qid
* 2 * stride
;
114 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
116 return (qid
* 2 + 1) * stride
;
119 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
121 return container_of(ctrl
, struct nvme_dev
, ctrl
);
125 * An NVM Express queue. Each device has at least two (one for admin
126 * commands and one for I/O commands).
129 struct device
*q_dmadev
;
130 struct nvme_dev
*dev
;
132 struct nvme_command
*sq_cmds
;
133 struct nvme_command __iomem
*sq_cmds_io
;
134 volatile struct nvme_completion
*cqes
;
135 struct blk_mq_tags
**tags
;
136 dma_addr_t sq_dma_addr
;
137 dma_addr_t cq_dma_addr
;
153 * The nvme_iod describes the data in an I/O, including the list of PRP
154 * entries. You can't see it in this data structure because C doesn't let
155 * me express that. Use nvme_init_iod to ensure there's enough space
156 * allocated to store the PRP list.
159 struct nvme_request req
;
160 struct nvme_queue
*nvmeq
;
162 int npages
; /* In the PRP list. 0 means small pool in use */
163 int nents
; /* Used in scatterlist */
164 int length
; /* Of data, in bytes */
165 dma_addr_t first_dma
;
166 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
167 struct scatterlist
*sg
;
168 struct scatterlist inline_sg
[0];
172 * Check we didin't inadvertently grow the command struct
174 static inline void _nvme_check_size(void)
176 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
177 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
178 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
179 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
180 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
181 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
185 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
186 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
188 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
191 static inline unsigned int nvme_dbbuf_size(u32 stride
)
193 return ((num_possible_cpus() + 1) * 8 * stride
);
196 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
198 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
203 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
204 &dev
->dbbuf_dbs_dma_addr
,
208 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
209 &dev
->dbbuf_eis_dma_addr
,
211 if (!dev
->dbbuf_eis
) {
212 dma_free_coherent(dev
->dev
, mem_size
,
213 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
214 dev
->dbbuf_dbs
= NULL
;
221 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
223 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
225 if (dev
->dbbuf_dbs
) {
226 dma_free_coherent(dev
->dev
, mem_size
,
227 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
228 dev
->dbbuf_dbs
= NULL
;
230 if (dev
->dbbuf_eis
) {
231 dma_free_coherent(dev
->dev
, mem_size
,
232 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
233 dev
->dbbuf_eis
= NULL
;
237 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
238 struct nvme_queue
*nvmeq
, int qid
)
240 if (!dev
->dbbuf_dbs
|| !qid
)
243 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
244 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
245 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
246 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
249 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
251 struct nvme_command c
;
256 memset(&c
, 0, sizeof(c
));
257 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
258 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
259 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
261 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
262 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
263 /* Free memory and continue on */
264 nvme_dbbuf_dma_free(dev
);
268 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
270 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
273 /* Update dbbuf and return true if an MMIO is required */
274 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
275 volatile u32
*dbbuf_ei
)
281 * Ensure that the queue is written before updating
282 * the doorbell in memory
286 old_value
= *dbbuf_db
;
289 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
297 * Max size of iod being embedded in the request payload
299 #define NVME_INT_PAGES 2
300 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
303 * Will slightly overestimate the number of pages needed. This is OK
304 * as it only leads to a small amount of wasted memory for the lifetime of
307 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
309 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
310 dev
->ctrl
.page_size
);
311 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
314 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
315 unsigned int size
, unsigned int nseg
)
317 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
318 sizeof(struct scatterlist
) * nseg
;
321 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
323 return sizeof(struct nvme_iod
) +
324 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
327 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
328 unsigned int hctx_idx
)
330 struct nvme_dev
*dev
= data
;
331 struct nvme_queue
*nvmeq
= dev
->queues
[0];
333 WARN_ON(hctx_idx
!= 0);
334 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
335 WARN_ON(nvmeq
->tags
);
337 hctx
->driver_data
= nvmeq
;
338 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
342 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
344 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
349 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
350 unsigned int hctx_idx
)
352 struct nvme_dev
*dev
= data
;
353 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
356 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
358 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
359 hctx
->driver_data
= nvmeq
;
363 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
364 unsigned int hctx_idx
, unsigned int numa_node
)
366 struct nvme_dev
*dev
= set
->driver_data
;
367 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
368 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
369 struct nvme_queue
*nvmeq
= dev
->queues
[queue_idx
];
376 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
378 struct nvme_dev
*dev
= set
->driver_data
;
380 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
384 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
385 * @nvmeq: The queue to use
386 * @cmd: The command to send
388 * Safe to use from interrupt context
390 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
391 struct nvme_command
*cmd
)
393 u16 tail
= nvmeq
->sq_tail
;
395 if (nvmeq
->sq_cmds_io
)
396 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
398 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
400 if (++tail
== nvmeq
->q_depth
)
402 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
404 writel(tail
, nvmeq
->q_db
);
405 nvmeq
->sq_tail
= tail
;
408 static __le64
**iod_list(struct request
*req
)
410 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
411 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
414 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
416 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
417 int nseg
= blk_rq_nr_phys_segments(rq
);
418 unsigned int size
= blk_rq_payload_bytes(rq
);
420 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
421 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
423 return BLK_STS_RESOURCE
;
425 iod
->sg
= iod
->inline_sg
;
436 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
438 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
439 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
441 __le64
**list
= iod_list(req
);
442 dma_addr_t prp_dma
= iod
->first_dma
;
444 if (iod
->npages
== 0)
445 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
446 for (i
= 0; i
< iod
->npages
; i
++) {
447 __le64
*prp_list
= list
[i
];
448 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
449 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
450 prp_dma
= next_prp_dma
;
453 if (iod
->sg
!= iod
->inline_sg
)
457 #ifdef CONFIG_BLK_DEV_INTEGRITY
458 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
460 if (be32_to_cpu(pi
->ref_tag
) == v
)
461 pi
->ref_tag
= cpu_to_be32(p
);
464 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
466 if (be32_to_cpu(pi
->ref_tag
) == p
)
467 pi
->ref_tag
= cpu_to_be32(v
);
471 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
473 * The virtual start sector is the one that was originally submitted by the
474 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
475 * start sector may be different. Remap protection information to match the
476 * physical LBA on writes, and back to the original seed on reads.
478 * Type 0 and 3 do not have a ref tag, so no remapping required.
480 static void nvme_dif_remap(struct request
*req
,
481 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
483 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
484 struct bio_integrity_payload
*bip
;
485 struct t10_pi_tuple
*pi
;
487 u32 i
, nlb
, ts
, phys
, virt
;
489 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
492 bip
= bio_integrity(req
->bio
);
496 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
499 virt
= bip_get_seed(bip
);
500 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
501 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
502 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
504 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
505 pi
= (struct t10_pi_tuple
*)p
;
506 dif_swap(phys
, virt
, pi
);
511 #else /* CONFIG_BLK_DEV_INTEGRITY */
512 static void nvme_dif_remap(struct request
*req
,
513 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
516 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
519 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
524 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
526 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
527 struct dma_pool
*pool
;
528 int length
= blk_rq_payload_bytes(req
);
529 struct scatterlist
*sg
= iod
->sg
;
530 int dma_len
= sg_dma_len(sg
);
531 u64 dma_addr
= sg_dma_address(sg
);
532 u32 page_size
= dev
->ctrl
.page_size
;
533 int offset
= dma_addr
& (page_size
- 1);
535 __le64
**list
= iod_list(req
);
539 length
-= (page_size
- offset
);
543 dma_len
-= (page_size
- offset
);
545 dma_addr
+= (page_size
- offset
);
548 dma_addr
= sg_dma_address(sg
);
549 dma_len
= sg_dma_len(sg
);
552 if (length
<= page_size
) {
553 iod
->first_dma
= dma_addr
;
557 nprps
= DIV_ROUND_UP(length
, page_size
);
558 if (nprps
<= (256 / 8)) {
559 pool
= dev
->prp_small_pool
;
562 pool
= dev
->prp_page_pool
;
566 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
568 iod
->first_dma
= dma_addr
;
573 iod
->first_dma
= prp_dma
;
576 if (i
== page_size
>> 3) {
577 __le64
*old_prp_list
= prp_list
;
578 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
581 list
[iod
->npages
++] = prp_list
;
582 prp_list
[0] = old_prp_list
[i
- 1];
583 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
586 prp_list
[i
++] = cpu_to_le64(dma_addr
);
587 dma_len
-= page_size
;
588 dma_addr
+= page_size
;
596 dma_addr
= sg_dma_address(sg
);
597 dma_len
= sg_dma_len(sg
);
603 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
604 struct nvme_command
*cmnd
)
606 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
607 struct request_queue
*q
= req
->q
;
608 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
609 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
610 blk_status_t ret
= BLK_STS_IOERR
;
612 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
613 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
617 ret
= BLK_STS_RESOURCE
;
618 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
622 if (!nvme_setup_prps(dev
, req
))
626 if (blk_integrity_rq(req
)) {
627 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
630 sg_init_table(&iod
->meta_sg
, 1);
631 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
634 if (rq_data_dir(req
))
635 nvme_dif_remap(req
, nvme_dif_prep
);
637 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
641 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
642 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
643 if (blk_integrity_rq(req
))
644 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
648 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
653 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
655 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
656 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
657 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
660 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
661 if (blk_integrity_rq(req
)) {
662 if (!rq_data_dir(req
))
663 nvme_dif_remap(req
, nvme_dif_complete
);
664 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
668 nvme_cleanup_cmd(req
);
669 nvme_free_iod(dev
, req
);
673 * NOTE: ns is NULL when called on the admin queue.
675 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
676 const struct blk_mq_queue_data
*bd
)
678 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
679 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
680 struct nvme_dev
*dev
= nvmeq
->dev
;
681 struct request
*req
= bd
->rq
;
682 struct nvme_command cmnd
;
685 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
689 ret
= nvme_init_iod(req
, dev
);
693 if (blk_rq_nr_phys_segments(req
)) {
694 ret
= nvme_map_data(dev
, req
, &cmnd
);
696 goto out_cleanup_iod
;
699 blk_mq_start_request(req
);
701 spin_lock_irq(&nvmeq
->q_lock
);
702 if (unlikely(nvmeq
->cq_vector
< 0)) {
704 spin_unlock_irq(&nvmeq
->q_lock
);
705 goto out_cleanup_iod
;
707 __nvme_submit_cmd(nvmeq
, &cmnd
);
708 nvme_process_cq(nvmeq
);
709 spin_unlock_irq(&nvmeq
->q_lock
);
712 nvme_free_iod(dev
, req
);
714 nvme_cleanup_cmd(req
);
718 static void nvme_pci_complete_rq(struct request
*req
)
720 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
722 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
723 nvme_complete_rq(req
);
726 /* We read the CQE phase first to check if the rest of the entry is valid */
727 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
730 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
733 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
735 u16 head
= nvmeq
->cq_head
;
737 if (likely(nvmeq
->cq_vector
>= 0)) {
738 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
740 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
744 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
748 head
= nvmeq
->cq_head
;
749 phase
= nvmeq
->cq_phase
;
751 while (nvme_cqe_valid(nvmeq
, head
, phase
)) {
752 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
755 if (++head
== nvmeq
->q_depth
) {
760 if (tag
&& *tag
== cqe
.command_id
)
763 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
764 dev_warn(nvmeq
->dev
->ctrl
.device
,
765 "invalid id %d completed on queue %d\n",
766 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
771 * AEN requests are special as they don't time out and can
772 * survive any kind of queue freeze and often don't respond to
773 * aborts. We don't even bother to allocate a struct request
774 * for them but rather special case them here.
776 if (unlikely(nvmeq
->qid
== 0 &&
777 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
778 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
779 cqe
.status
, &cqe
.result
);
783 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
784 nvme_end_request(req
, cqe
.status
, cqe
.result
);
787 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
790 nvmeq
->cq_head
= head
;
791 nvmeq
->cq_phase
= phase
;
793 nvme_ring_cq_doorbell(nvmeq
);
798 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
800 __nvme_process_cq(nvmeq
, NULL
);
803 static irqreturn_t
nvme_irq(int irq
, void *data
)
806 struct nvme_queue
*nvmeq
= data
;
807 spin_lock(&nvmeq
->q_lock
);
808 nvme_process_cq(nvmeq
);
809 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
811 spin_unlock(&nvmeq
->q_lock
);
815 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
817 struct nvme_queue
*nvmeq
= data
;
818 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
819 return IRQ_WAKE_THREAD
;
823 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
825 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
826 spin_lock_irq(&nvmeq
->q_lock
);
827 __nvme_process_cq(nvmeq
, &tag
);
828 spin_unlock_irq(&nvmeq
->q_lock
);
837 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
839 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
841 return __nvme_poll(nvmeq
, tag
);
844 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
846 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
847 struct nvme_queue
*nvmeq
= dev
->queues
[0];
848 struct nvme_command c
;
850 memset(&c
, 0, sizeof(c
));
851 c
.common
.opcode
= nvme_admin_async_event
;
852 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
854 spin_lock_irq(&nvmeq
->q_lock
);
855 __nvme_submit_cmd(nvmeq
, &c
);
856 spin_unlock_irq(&nvmeq
->q_lock
);
859 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
861 struct nvme_command c
;
863 memset(&c
, 0, sizeof(c
));
864 c
.delete_queue
.opcode
= opcode
;
865 c
.delete_queue
.qid
= cpu_to_le16(id
);
867 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
870 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
871 struct nvme_queue
*nvmeq
)
873 struct nvme_command c
;
874 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
877 * Note: we (ab)use the fact the the prp fields survive if no data
878 * is attached to the request.
880 memset(&c
, 0, sizeof(c
));
881 c
.create_cq
.opcode
= nvme_admin_create_cq
;
882 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
883 c
.create_cq
.cqid
= cpu_to_le16(qid
);
884 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
885 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
886 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
888 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
891 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
892 struct nvme_queue
*nvmeq
)
894 struct nvme_command c
;
895 int flags
= NVME_QUEUE_PHYS_CONTIG
;
898 * Note: we (ab)use the fact the the prp fields survive if no data
899 * is attached to the request.
901 memset(&c
, 0, sizeof(c
));
902 c
.create_sq
.opcode
= nvme_admin_create_sq
;
903 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
904 c
.create_sq
.sqid
= cpu_to_le16(qid
);
905 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
906 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
907 c
.create_sq
.cqid
= cpu_to_le16(qid
);
909 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
912 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
914 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
917 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
919 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
922 static void abort_endio(struct request
*req
, blk_status_t error
)
924 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
925 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
927 dev_warn(nvmeq
->dev
->ctrl
.device
,
928 "Abort status: 0x%x", nvme_req(req
)->status
);
929 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
930 blk_mq_free_request(req
);
933 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
936 /* If true, indicates loss of adapter communication, possibly by a
937 * NVMe Subsystem reset.
939 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
941 /* If there is a reset ongoing, we shouldn't reset again. */
942 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
945 /* We shouldn't reset unless the controller is on fatal error state
946 * _or_ if we lost the communication with it.
948 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
951 /* If PCI error recovery process is happening, we cannot reset or
952 * the recovery mechanism will surely fail.
954 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
960 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
962 /* Read a config register to help see what died. */
966 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
968 if (result
== PCIBIOS_SUCCESSFUL
)
969 dev_warn(dev
->ctrl
.device
,
970 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
973 dev_warn(dev
->ctrl
.device
,
974 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
978 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
980 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
981 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
982 struct nvme_dev
*dev
= nvmeq
->dev
;
983 struct request
*abort_req
;
984 struct nvme_command cmd
;
985 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
988 * Reset immediately if the controller is failed
990 if (nvme_should_reset(dev
, csts
)) {
991 nvme_warn_reset(dev
, csts
);
992 nvme_dev_disable(dev
, false);
993 nvme_reset_ctrl(&dev
->ctrl
);
994 return BLK_EH_HANDLED
;
998 * Did we miss an interrupt?
1000 if (__nvme_poll(nvmeq
, req
->tag
)) {
1001 dev_warn(dev
->ctrl
.device
,
1002 "I/O %d QID %d timeout, completion polled\n",
1003 req
->tag
, nvmeq
->qid
);
1004 return BLK_EH_HANDLED
;
1008 * Shutdown immediately if controller times out while starting. The
1009 * reset work will see the pci device disabled when it gets the forced
1010 * cancellation error. All outstanding requests are completed on
1011 * shutdown, so we return BLK_EH_HANDLED.
1013 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
1014 dev_warn(dev
->ctrl
.device
,
1015 "I/O %d QID %d timeout, disable controller\n",
1016 req
->tag
, nvmeq
->qid
);
1017 nvme_dev_disable(dev
, false);
1018 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1019 return BLK_EH_HANDLED
;
1023 * Shutdown the controller immediately and schedule a reset if the
1024 * command was already aborted once before and still hasn't been
1025 * returned to the driver, or if this is the admin queue.
1027 if (!nvmeq
->qid
|| iod
->aborted
) {
1028 dev_warn(dev
->ctrl
.device
,
1029 "I/O %d QID %d timeout, reset controller\n",
1030 req
->tag
, nvmeq
->qid
);
1031 nvme_dev_disable(dev
, false);
1032 nvme_reset_ctrl(&dev
->ctrl
);
1035 * Mark the request as handled, since the inline shutdown
1036 * forces all outstanding requests to complete.
1038 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1039 return BLK_EH_HANDLED
;
1042 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1043 atomic_inc(&dev
->ctrl
.abort_limit
);
1044 return BLK_EH_RESET_TIMER
;
1048 memset(&cmd
, 0, sizeof(cmd
));
1049 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1050 cmd
.abort
.cid
= req
->tag
;
1051 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1053 dev_warn(nvmeq
->dev
->ctrl
.device
,
1054 "I/O %d QID %d timeout, aborting\n",
1055 req
->tag
, nvmeq
->qid
);
1057 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1058 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1059 if (IS_ERR(abort_req
)) {
1060 atomic_inc(&dev
->ctrl
.abort_limit
);
1061 return BLK_EH_RESET_TIMER
;
1064 abort_req
->timeout
= ADMIN_TIMEOUT
;
1065 abort_req
->end_io_data
= NULL
;
1066 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1069 * The aborted req will be completed on receiving the abort req.
1070 * We enable the timer again. If hit twice, it'll cause a device reset,
1071 * as the device then is in a faulty state.
1073 return BLK_EH_RESET_TIMER
;
1076 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1078 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1079 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1081 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1082 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1086 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1090 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1091 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1093 dev
->queues
[i
] = NULL
;
1094 nvme_free_queue(nvmeq
);
1099 * nvme_suspend_queue - put queue into suspended state
1100 * @nvmeq - queue to suspend
1102 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1106 spin_lock_irq(&nvmeq
->q_lock
);
1107 if (nvmeq
->cq_vector
== -1) {
1108 spin_unlock_irq(&nvmeq
->q_lock
);
1111 vector
= nvmeq
->cq_vector
;
1112 nvmeq
->dev
->online_queues
--;
1113 nvmeq
->cq_vector
= -1;
1114 spin_unlock_irq(&nvmeq
->q_lock
);
1116 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1117 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1119 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1124 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1126 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1130 if (nvme_suspend_queue(nvmeq
))
1134 nvme_shutdown_ctrl(&dev
->ctrl
);
1136 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1137 dev
->bar
+ NVME_REG_CAP
));
1139 spin_lock_irq(&nvmeq
->q_lock
);
1140 nvme_process_cq(nvmeq
);
1141 spin_unlock_irq(&nvmeq
->q_lock
);
1144 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1147 int q_depth
= dev
->q_depth
;
1148 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1149 dev
->ctrl
.page_size
);
1151 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1152 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1153 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1154 q_depth
= div_u64(mem_per_q
, entry_size
);
1157 * Ensure the reduced q_depth is above some threshold where it
1158 * would be better to map queues in system memory with the
1168 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1171 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1172 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1173 dev
->ctrl
.page_size
);
1174 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1175 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1177 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1178 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1179 if (!nvmeq
->sq_cmds
)
1186 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1187 int depth
, int node
)
1189 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1194 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1195 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1199 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1202 nvmeq
->q_dmadev
= dev
->dev
;
1204 spin_lock_init(&nvmeq
->q_lock
);
1206 nvmeq
->cq_phase
= 1;
1207 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1208 nvmeq
->q_depth
= depth
;
1210 nvmeq
->cq_vector
= -1;
1211 dev
->queues
[qid
] = nvmeq
;
1217 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1218 nvmeq
->cq_dma_addr
);
1224 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1226 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1227 int nr
= nvmeq
->dev
->ctrl
.instance
;
1229 if (use_threaded_interrupts
) {
1230 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1231 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1233 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1234 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1238 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1240 struct nvme_dev
*dev
= nvmeq
->dev
;
1242 spin_lock_irq(&nvmeq
->q_lock
);
1245 nvmeq
->cq_phase
= 1;
1246 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1247 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1248 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1249 dev
->online_queues
++;
1250 spin_unlock_irq(&nvmeq
->q_lock
);
1253 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1255 struct nvme_dev
*dev
= nvmeq
->dev
;
1258 nvmeq
->cq_vector
= qid
- 1;
1259 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1263 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1267 result
= queue_request_irq(nvmeq
);
1271 nvme_init_queue(nvmeq
, qid
);
1275 adapter_delete_sq(dev
, qid
);
1277 adapter_delete_cq(dev
, qid
);
1281 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1282 .queue_rq
= nvme_queue_rq
,
1283 .complete
= nvme_pci_complete_rq
,
1284 .init_hctx
= nvme_admin_init_hctx
,
1285 .exit_hctx
= nvme_admin_exit_hctx
,
1286 .init_request
= nvme_init_request
,
1287 .timeout
= nvme_timeout
,
1290 static const struct blk_mq_ops nvme_mq_ops
= {
1291 .queue_rq
= nvme_queue_rq
,
1292 .complete
= nvme_pci_complete_rq
,
1293 .init_hctx
= nvme_init_hctx
,
1294 .init_request
= nvme_init_request
,
1295 .map_queues
= nvme_pci_map_queues
,
1296 .timeout
= nvme_timeout
,
1300 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1302 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1304 * If the controller was reset during removal, it's possible
1305 * user requests may be waiting on a stopped queue. Start the
1306 * queue to flush these to completion.
1308 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1309 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1310 blk_mq_free_tag_set(&dev
->admin_tagset
);
1314 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1316 if (!dev
->ctrl
.admin_q
) {
1317 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1318 dev
->admin_tagset
.nr_hw_queues
= 1;
1321 * Subtract one to leave an empty queue entry for 'Full Queue'
1322 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1324 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1325 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1326 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1327 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1328 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1329 dev
->admin_tagset
.driver_data
= dev
;
1331 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1334 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1335 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1336 blk_mq_free_tag_set(&dev
->admin_tagset
);
1339 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1340 nvme_dev_remove_admin(dev
);
1341 dev
->ctrl
.admin_q
= NULL
;
1345 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1350 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1352 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1355 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1357 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1359 if (size
<= dev
->bar_mapped_size
)
1361 if (size
> pci_resource_len(pdev
, 0))
1365 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1367 dev
->bar_mapped_size
= 0;
1370 dev
->bar_mapped_size
= size
;
1371 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1376 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1380 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1381 struct nvme_queue
*nvmeq
;
1383 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1387 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1388 NVME_CAP_NSSRC(cap
) : 0;
1390 if (dev
->subsystem
&&
1391 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1392 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1394 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1398 nvmeq
= dev
->queues
[0];
1400 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1401 dev_to_node(dev
->dev
));
1406 aqa
= nvmeq
->q_depth
- 1;
1409 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1410 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1411 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1413 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1417 nvmeq
->cq_vector
= 0;
1418 result
= queue_request_irq(nvmeq
);
1420 nvmeq
->cq_vector
= -1;
1427 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1432 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1433 /* vector == qid - 1, match nvme_create_queue */
1434 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1435 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1441 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1442 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1443 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1449 * Ignore failing Create SQ/CQ commands, we can continue with less
1450 * than the desired aount of queues, and even a controller without
1451 * I/O queues an still be used to issue admin commands. This might
1452 * be useful to upgrade a buggy firmware for example.
1454 return ret
>= 0 ? 0 : ret
;
1457 static ssize_t
nvme_cmb_show(struct device
*dev
,
1458 struct device_attribute
*attr
,
1461 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1463 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1464 ndev
->cmbloc
, ndev
->cmbsz
);
1466 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1468 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1470 u64 szu
, size
, offset
;
1471 resource_size_t bar_size
;
1472 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1474 dma_addr_t dma_addr
;
1476 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1477 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1479 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1484 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1485 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1486 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1487 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1489 if (offset
> bar_size
)
1493 * Controllers may support a CMB size larger than their BAR,
1494 * for example, due to being behind a bridge. Reduce the CMB to
1495 * the reported size of the BAR
1497 if (size
> bar_size
- offset
)
1498 size
= bar_size
- offset
;
1500 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1501 cmb
= ioremap_wc(dma_addr
, size
);
1505 dev
->cmb_dma_addr
= dma_addr
;
1506 dev
->cmb_size
= size
;
1510 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1516 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1517 &dev_attr_cmb
.attr
, NULL
);
1523 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1525 size_t len
= dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
);
1526 struct nvme_command c
;
1530 dma_addr
= dma_map_single(dev
->dev
, dev
->host_mem_descs
, len
,
1532 if (dma_mapping_error(dev
->dev
, dma_addr
))
1535 memset(&c
, 0, sizeof(c
));
1536 c
.features
.opcode
= nvme_admin_set_features
;
1537 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1538 c
.features
.dword11
= cpu_to_le32(bits
);
1539 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1540 ilog2(dev
->ctrl
.page_size
));
1541 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1542 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1543 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1545 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1547 dev_warn(dev
->ctrl
.device
,
1548 "failed to set host mem (err %d, flags %#x).\n",
1551 dma_unmap_single(dev
->dev
, dma_addr
, len
, DMA_TO_DEVICE
);
1555 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1559 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1560 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1561 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1563 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1564 le64_to_cpu(desc
->addr
));
1567 kfree(dev
->host_mem_desc_bufs
);
1568 dev
->host_mem_desc_bufs
= NULL
;
1569 kfree(dev
->host_mem_descs
);
1570 dev
->host_mem_descs
= NULL
;
1573 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1575 struct nvme_host_mem_buf_desc
*descs
;
1576 u32 chunk_size
, max_entries
, i
= 0;
1580 /* start big and work our way down */
1581 chunk_size
= min(preferred
, (u64
)PAGE_SIZE
<< MAX_ORDER
);
1583 tmp
= (preferred
+ chunk_size
- 1);
1584 do_div(tmp
, chunk_size
);
1586 descs
= kcalloc(max_entries
, sizeof(*descs
), GFP_KERNEL
);
1590 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1592 goto out_free_descs
;
1594 for (size
= 0; size
< preferred
; size
+= chunk_size
) {
1595 u32 len
= min_t(u64
, chunk_size
, preferred
- size
);
1596 dma_addr_t dma_addr
;
1598 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1599 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1603 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1604 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1608 if (!size
|| (min
&& size
< min
)) {
1609 dev_warn(dev
->ctrl
.device
,
1610 "failed to allocate host memory buffer.\n");
1614 dev_info(dev
->ctrl
.device
,
1615 "allocated %lld MiB host memory buffer.\n",
1616 size
>> ilog2(SZ_1M
));
1617 dev
->nr_host_mem_descs
= i
;
1618 dev
->host_mem_size
= size
;
1619 dev
->host_mem_descs
= descs
;
1620 dev
->host_mem_desc_bufs
= bufs
;
1625 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1627 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1628 le64_to_cpu(descs
[i
].addr
));
1635 /* try a smaller chunk size if we failed early */
1636 if (chunk_size
>= PAGE_SIZE
* 2 && (i
== 0 || size
< min
)) {
1640 dev
->host_mem_descs
= NULL
;
1644 static void nvme_setup_host_mem(struct nvme_dev
*dev
)
1646 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1647 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1648 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1649 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1651 preferred
= min(preferred
, max
);
1653 dev_warn(dev
->ctrl
.device
,
1654 "min host memory (%lld MiB) above limit (%d MiB).\n",
1655 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1656 nvme_free_host_mem(dev
);
1661 * If we already have a buffer allocated check if we can reuse it.
1663 if (dev
->host_mem_descs
) {
1664 if (dev
->host_mem_size
>= min
)
1665 enable_bits
|= NVME_HOST_MEM_RETURN
;
1667 nvme_free_host_mem(dev
);
1670 if (!dev
->host_mem_descs
) {
1671 if (nvme_alloc_host_mem(dev
, min
, preferred
))
1675 if (nvme_set_host_mem(dev
, enable_bits
))
1676 nvme_free_host_mem(dev
);
1679 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1681 struct nvme_queue
*adminq
= dev
->queues
[0];
1682 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1683 int result
, nr_io_queues
;
1686 nr_io_queues
= num_online_cpus();
1687 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1691 if (nr_io_queues
== 0)
1694 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1695 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1696 sizeof(struct nvme_command
));
1698 dev
->q_depth
= result
;
1700 nvme_release_cmb(dev
);
1704 size
= db_bar_size(dev
, nr_io_queues
);
1705 result
= nvme_remap_bar(dev
, size
);
1708 if (!--nr_io_queues
)
1711 adminq
->q_db
= dev
->dbs
;
1713 /* Deregister the admin queue's interrupt */
1714 pci_free_irq(pdev
, 0, adminq
);
1717 * If we enable msix early due to not intx, disable it again before
1718 * setting up the full range we need.
1720 pci_free_irq_vectors(pdev
);
1721 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1722 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1723 if (nr_io_queues
<= 0)
1725 dev
->max_qid
= nr_io_queues
;
1728 * Should investigate if there's a performance win from allocating
1729 * more queues than interrupt vectors; it might allow the submission
1730 * path to scale better, even if the receive path is limited by the
1731 * number of interrupts.
1734 result
= queue_request_irq(adminq
);
1736 adminq
->cq_vector
= -1;
1739 return nvme_create_io_queues(dev
);
1742 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1744 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1746 blk_mq_free_request(req
);
1747 complete(&nvmeq
->dev
->ioq_wait
);
1750 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1752 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1755 unsigned long flags
;
1758 * We might be called with the AQ q_lock held
1759 * and the I/O queue q_lock should always
1760 * nest inside the AQ one.
1762 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1763 SINGLE_DEPTH_NESTING
);
1764 nvme_process_cq(nvmeq
);
1765 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1768 nvme_del_queue_end(req
, error
);
1771 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1773 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1774 struct request
*req
;
1775 struct nvme_command cmd
;
1777 memset(&cmd
, 0, sizeof(cmd
));
1778 cmd
.delete_queue
.opcode
= opcode
;
1779 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1781 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1783 return PTR_ERR(req
);
1785 req
->timeout
= ADMIN_TIMEOUT
;
1786 req
->end_io_data
= nvmeq
;
1788 blk_execute_rq_nowait(q
, NULL
, req
, false,
1789 opcode
== nvme_admin_delete_cq
?
1790 nvme_del_cq_end
: nvme_del_queue_end
);
1794 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1797 unsigned long timeout
;
1798 u8 opcode
= nvme_admin_delete_sq
;
1800 for (pass
= 0; pass
< 2; pass
++) {
1801 int sent
= 0, i
= queues
;
1803 reinit_completion(&dev
->ioq_wait
);
1805 timeout
= ADMIN_TIMEOUT
;
1806 for (; i
> 0; i
--, sent
++)
1807 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1811 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1817 opcode
= nvme_admin_delete_cq
;
1822 * Return: error value if an error occurred setting up the queues or calling
1823 * Identify Device. 0 if these succeeded, even if adding some of the
1824 * namespaces failed. At the moment, these failures are silent. TBD which
1825 * failures should be reported.
1827 static int nvme_dev_add(struct nvme_dev
*dev
)
1829 if (!dev
->ctrl
.tagset
) {
1830 dev
->tagset
.ops
= &nvme_mq_ops
;
1831 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1832 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1833 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1834 dev
->tagset
.queue_depth
=
1835 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1836 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1837 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1838 dev
->tagset
.driver_data
= dev
;
1840 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1842 dev
->ctrl
.tagset
= &dev
->tagset
;
1844 nvme_dbbuf_set(dev
);
1846 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1848 /* Free previously allocated queues that are no longer usable */
1849 nvme_free_queues(dev
, dev
->online_queues
);
1855 static int nvme_pci_enable(struct nvme_dev
*dev
)
1858 int result
= -ENOMEM
;
1859 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1861 if (pci_enable_device_mem(pdev
))
1864 pci_set_master(pdev
);
1866 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1867 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1870 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1876 * Some devices and/or platforms don't advertise or work with INTx
1877 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1878 * adjust this later.
1880 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1884 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1886 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1887 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1888 dev
->dbs
= dev
->bar
+ 4096;
1891 * Temporary fix for the Apple controller found in the MacBook8,1 and
1892 * some MacBook7,1 to avoid controller resets and data loss.
1894 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1896 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
1897 "set queue depth=%u to work around controller resets\n",
1902 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1903 * populate sysfs if a CMB is implemented. Note that we add the
1904 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1905 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1906 * NULL as final argument to sysfs_add_file_to_group.
1909 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1910 dev
->cmb
= nvme_map_cmb(dev
);
1913 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1914 &dev_attr_cmb
.attr
, NULL
))
1915 dev_warn(dev
->ctrl
.device
,
1916 "failed to add sysfs attribute for CMB\n");
1920 pci_enable_pcie_error_reporting(pdev
);
1921 pci_save_state(pdev
);
1925 pci_disable_device(pdev
);
1929 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1933 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1936 static void nvme_pci_disable(struct nvme_dev
*dev
)
1938 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1940 nvme_release_cmb(dev
);
1941 pci_free_irq_vectors(pdev
);
1943 if (pci_is_enabled(pdev
)) {
1944 pci_disable_pcie_error_reporting(pdev
);
1945 pci_disable_device(pdev
);
1949 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1953 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1955 mutex_lock(&dev
->shutdown_lock
);
1956 if (pci_is_enabled(pdev
)) {
1957 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1959 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
)
1960 nvme_start_freeze(&dev
->ctrl
);
1961 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
1962 pdev
->error_state
!= pci_channel_io_normal
);
1966 * Give the controller a chance to complete all entered requests if
1967 * doing a safe shutdown.
1971 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
1974 * If the controller is still alive tell it to stop using the
1975 * host memory buffer. In theory the shutdown / reset should
1976 * make sure that it doesn't access the host memoery anymore,
1977 * but I'd rather be safe than sorry..
1979 if (dev
->host_mem_descs
)
1980 nvme_set_host_mem(dev
, 0);
1983 nvme_stop_queues(&dev
->ctrl
);
1985 queues
= dev
->online_queues
- 1;
1986 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1987 nvme_suspend_queue(dev
->queues
[i
]);
1990 /* A device might become IO incapable very soon during
1991 * probe, before the admin queue is configured. Thus,
1992 * queue_count can be 0 here.
1994 if (dev
->queue_count
)
1995 nvme_suspend_queue(dev
->queues
[0]);
1997 nvme_disable_io_queues(dev
, queues
);
1998 nvme_disable_admin_queue(dev
, shutdown
);
2000 nvme_pci_disable(dev
);
2002 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2003 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2006 * The driver will not be starting up queues again if shutting down so
2007 * must flush all entered requests to their failed completion to avoid
2008 * deadlocking blk-mq hot-cpu notifier.
2011 nvme_start_queues(&dev
->ctrl
);
2012 mutex_unlock(&dev
->shutdown_lock
);
2015 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2017 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2018 PAGE_SIZE
, PAGE_SIZE
, 0);
2019 if (!dev
->prp_page_pool
)
2022 /* Optimisation for I/Os between 4k and 128k */
2023 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2025 if (!dev
->prp_small_pool
) {
2026 dma_pool_destroy(dev
->prp_page_pool
);
2032 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2034 dma_pool_destroy(dev
->prp_page_pool
);
2035 dma_pool_destroy(dev
->prp_small_pool
);
2038 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2040 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2042 nvme_dbbuf_dma_free(dev
);
2043 put_device(dev
->dev
);
2044 if (dev
->tagset
.tags
)
2045 blk_mq_free_tag_set(&dev
->tagset
);
2046 if (dev
->ctrl
.admin_q
)
2047 blk_put_queue(dev
->ctrl
.admin_q
);
2049 free_opal_dev(dev
->ctrl
.opal_dev
);
2053 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2055 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2057 kref_get(&dev
->ctrl
.kref
);
2058 nvme_dev_disable(dev
, false);
2059 if (!schedule_work(&dev
->remove_work
))
2060 nvme_put_ctrl(&dev
->ctrl
);
2063 static void nvme_reset_work(struct work_struct
*work
)
2065 struct nvme_dev
*dev
=
2066 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2067 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2068 int result
= -ENODEV
;
2070 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2074 * If we're called to reset a live controller first shut it down before
2077 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2078 nvme_dev_disable(dev
, false);
2080 result
= nvme_pci_enable(dev
);
2084 result
= nvme_configure_admin_queue(dev
);
2088 nvme_init_queue(dev
->queues
[0], 0);
2089 result
= nvme_alloc_admin_tags(dev
);
2093 result
= nvme_init_identify(&dev
->ctrl
);
2097 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2098 if (!dev
->ctrl
.opal_dev
)
2099 dev
->ctrl
.opal_dev
=
2100 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2101 else if (was_suspend
)
2102 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2104 free_opal_dev(dev
->ctrl
.opal_dev
);
2105 dev
->ctrl
.opal_dev
= NULL
;
2108 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2109 result
= nvme_dbbuf_dma_alloc(dev
);
2112 "unable to allocate dma for dbbuf\n");
2115 if (dev
->ctrl
.hmpre
)
2116 nvme_setup_host_mem(dev
);
2118 result
= nvme_setup_io_queues(dev
);
2123 * A controller that can not execute IO typically requires user
2124 * intervention to correct. For such degraded controllers, the driver
2125 * should not submit commands the user did not request, so skip
2126 * registering for asynchronous event notification on this condition.
2128 if (dev
->online_queues
> 1)
2129 nvme_queue_async_events(&dev
->ctrl
);
2132 * Keep the controller around but remove all namespaces if we don't have
2133 * any working I/O queue.
2135 if (dev
->online_queues
< 2) {
2136 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2137 nvme_kill_queues(&dev
->ctrl
);
2138 nvme_remove_namespaces(&dev
->ctrl
);
2140 nvme_start_queues(&dev
->ctrl
);
2141 nvme_wait_freeze(&dev
->ctrl
);
2143 nvme_unfreeze(&dev
->ctrl
);
2146 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2147 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2151 if (dev
->online_queues
> 1)
2152 nvme_queue_scan(&dev
->ctrl
);
2156 nvme_remove_dead_ctrl(dev
, result
);
2159 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2161 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2162 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2164 nvme_kill_queues(&dev
->ctrl
);
2165 if (pci_get_drvdata(pdev
))
2166 device_release_driver(&pdev
->dev
);
2167 nvme_put_ctrl(&dev
->ctrl
);
2170 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2172 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2176 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2178 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2182 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2184 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2188 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2190 .module
= THIS_MODULE
,
2191 .flags
= NVME_F_METADATA_SUPPORTED
,
2192 .reg_read32
= nvme_pci_reg_read32
,
2193 .reg_write32
= nvme_pci_reg_write32
,
2194 .reg_read64
= nvme_pci_reg_read64
,
2195 .free_ctrl
= nvme_pci_free_ctrl
,
2196 .submit_async_event
= nvme_pci_submit_async_event
,
2199 static int nvme_dev_map(struct nvme_dev
*dev
)
2201 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2203 if (pci_request_mem_regions(pdev
, "nvme"))
2206 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2211 pci_release_mem_regions(pdev
);
2215 static unsigned long check_dell_samsung_bug(struct pci_dev
*pdev
)
2217 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2219 * Several Samsung devices seem to drop off the PCIe bus
2220 * randomly when APST is on and uses the deepest sleep state.
2221 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2222 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2223 * 950 PRO 256GB", but it seems to be restricted to two Dell
2226 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2227 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2228 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2229 return NVME_QUIRK_NO_DEEPEST_PS
;
2235 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2237 int node
, result
= -ENOMEM
;
2238 struct nvme_dev
*dev
;
2239 unsigned long quirks
= id
->driver_data
;
2241 node
= dev_to_node(&pdev
->dev
);
2242 if (node
== NUMA_NO_NODE
)
2243 set_dev_node(&pdev
->dev
, first_memory_node
);
2245 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2248 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2253 dev
->dev
= get_device(&pdev
->dev
);
2254 pci_set_drvdata(pdev
, dev
);
2256 result
= nvme_dev_map(dev
);
2260 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2261 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2262 mutex_init(&dev
->shutdown_lock
);
2263 init_completion(&dev
->ioq_wait
);
2265 result
= nvme_setup_prp_pools(dev
);
2269 quirks
|= check_dell_samsung_bug(pdev
);
2271 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2276 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2277 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2279 queue_work(nvme_wq
, &dev
->ctrl
.reset_work
);
2283 nvme_release_prp_pools(dev
);
2285 put_device(dev
->dev
);
2286 nvme_dev_unmap(dev
);
2293 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2295 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2298 nvme_dev_disable(dev
, false);
2300 nvme_reset_ctrl(&dev
->ctrl
);
2303 static void nvme_shutdown(struct pci_dev
*pdev
)
2305 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2306 nvme_dev_disable(dev
, true);
2310 * The driver's remove may be called on a device in a partially initialized
2311 * state. This function must not have any dependencies on the device state in
2314 static void nvme_remove(struct pci_dev
*pdev
)
2316 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2318 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2320 cancel_work_sync(&dev
->ctrl
.reset_work
);
2321 pci_set_drvdata(pdev
, NULL
);
2323 if (!pci_device_is_present(pdev
)) {
2324 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2325 nvme_dev_disable(dev
, false);
2328 flush_work(&dev
->ctrl
.reset_work
);
2329 nvme_uninit_ctrl(&dev
->ctrl
);
2330 nvme_dev_disable(dev
, true);
2331 nvme_free_host_mem(dev
);
2332 nvme_dev_remove_admin(dev
);
2333 nvme_free_queues(dev
, 0);
2334 nvme_release_prp_pools(dev
);
2335 nvme_dev_unmap(dev
);
2336 nvme_put_ctrl(&dev
->ctrl
);
2339 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2344 if (pci_vfs_assigned(pdev
)) {
2345 dev_warn(&pdev
->dev
,
2346 "Cannot disable SR-IOV VFs while assigned\n");
2349 pci_disable_sriov(pdev
);
2353 ret
= pci_enable_sriov(pdev
, numvfs
);
2354 return ret
? ret
: numvfs
;
2357 #ifdef CONFIG_PM_SLEEP
2358 static int nvme_suspend(struct device
*dev
)
2360 struct pci_dev
*pdev
= to_pci_dev(dev
);
2361 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2363 nvme_dev_disable(ndev
, true);
2367 static int nvme_resume(struct device
*dev
)
2369 struct pci_dev
*pdev
= to_pci_dev(dev
);
2370 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2372 nvme_reset_ctrl(&ndev
->ctrl
);
2377 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2379 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2380 pci_channel_state_t state
)
2382 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2385 * A frozen channel requires a reset. When detected, this method will
2386 * shutdown the controller to quiesce. The controller will be restarted
2387 * after the slot reset through driver's slot_reset callback.
2390 case pci_channel_io_normal
:
2391 return PCI_ERS_RESULT_CAN_RECOVER
;
2392 case pci_channel_io_frozen
:
2393 dev_warn(dev
->ctrl
.device
,
2394 "frozen state error detected, reset controller\n");
2395 nvme_dev_disable(dev
, false);
2396 return PCI_ERS_RESULT_NEED_RESET
;
2397 case pci_channel_io_perm_failure
:
2398 dev_warn(dev
->ctrl
.device
,
2399 "failure state error detected, request disconnect\n");
2400 return PCI_ERS_RESULT_DISCONNECT
;
2402 return PCI_ERS_RESULT_NEED_RESET
;
2405 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2407 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2409 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2410 pci_restore_state(pdev
);
2411 nvme_reset_ctrl(&dev
->ctrl
);
2412 return PCI_ERS_RESULT_RECOVERED
;
2415 static void nvme_error_resume(struct pci_dev
*pdev
)
2417 pci_cleanup_aer_uncorrect_error_status(pdev
);
2420 static const struct pci_error_handlers nvme_err_handler
= {
2421 .error_detected
= nvme_error_detected
,
2422 .slot_reset
= nvme_slot_reset
,
2423 .resume
= nvme_error_resume
,
2424 .reset_notify
= nvme_reset_notify
,
2427 static const struct pci_device_id nvme_id_table
[] = {
2428 { PCI_VDEVICE(INTEL
, 0x0953),
2429 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2430 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2431 { PCI_VDEVICE(INTEL
, 0x0a53),
2432 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2433 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2434 { PCI_VDEVICE(INTEL
, 0x0a54),
2435 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2436 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2437 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2438 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
},
2439 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2440 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2441 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2442 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2443 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2444 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2445 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2446 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2447 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2450 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2452 static struct pci_driver nvme_driver
= {
2454 .id_table
= nvme_id_table
,
2455 .probe
= nvme_probe
,
2456 .remove
= nvme_remove
,
2457 .shutdown
= nvme_shutdown
,
2459 .pm
= &nvme_dev_pm_ops
,
2461 .sriov_configure
= nvme_pci_sriov_configure
,
2462 .err_handler
= &nvme_err_handler
,
2465 static int __init
nvme_init(void)
2467 return pci_register_driver(&nvme_driver
);
2470 static void __exit
nvme_exit(void)
2472 pci_unregister_driver(&nvme_driver
);
2476 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2477 MODULE_LICENSE("GPL");
2478 MODULE_VERSION("1.0");
2479 module_init(nvme_init
);
2480 module_exit(nvme_exit
);