2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/timer.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_NR_AEN_COMMANDS 1
58 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
60 static int use_threaded_interrupts
;
61 module_param(use_threaded_interrupts
, int, 0);
63 static bool use_cmb_sqes
= true;
64 module_param(use_cmb_sqes
, bool, 0644);
65 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
67 static struct workqueue_struct
*nvme_workq
;
72 static int nvme_reset(struct nvme_dev
*dev
);
73 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
74 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
77 * Represents an NVM Express device. Each nvme_dev is a PCI function.
80 struct nvme_queue
**queues
;
81 struct blk_mq_tag_set tagset
;
82 struct blk_mq_tag_set admin_tagset
;
85 struct dma_pool
*prp_page_pool
;
86 struct dma_pool
*prp_small_pool
;
88 unsigned online_queues
;
92 struct msix_entry
*entry
;
94 struct work_struct reset_work
;
95 struct work_struct scan_work
;
96 struct work_struct remove_work
;
97 struct work_struct async_work
;
98 struct timer_list watchdog_timer
;
99 struct mutex shutdown_lock
;
102 dma_addr_t cmb_dma_addr
;
105 struct nvme_ctrl ctrl
;
106 struct completion ioq_wait
;
109 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
111 return container_of(ctrl
, struct nvme_dev
, ctrl
);
115 * An NVM Express queue. Each device has at least two (one for admin
116 * commands and one for I/O commands).
119 struct device
*q_dmadev
;
120 struct nvme_dev
*dev
;
121 char irqname
[24]; /* nvme4294967295-65535\0 */
123 struct nvme_command
*sq_cmds
;
124 struct nvme_command __iomem
*sq_cmds_io
;
125 volatile struct nvme_completion
*cqes
;
126 struct blk_mq_tags
**tags
;
127 dma_addr_t sq_dma_addr
;
128 dma_addr_t cq_dma_addr
;
140 * The nvme_iod describes the data in an I/O, including the list of PRP
141 * entries. You can't see it in this data structure because C doesn't let
142 * me express that. Use nvme_init_iod to ensure there's enough space
143 * allocated to store the PRP list.
146 struct nvme_queue
*nvmeq
;
148 int npages
; /* In the PRP list. 0 means small pool in use */
149 int nents
; /* Used in scatterlist */
150 int length
; /* Of data, in bytes */
151 dma_addr_t first_dma
;
152 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
153 struct scatterlist
*sg
;
154 struct scatterlist inline_sg
[0];
158 * Check we didin't inadvertently grow the command struct
160 static inline void _nvme_check_size(void)
162 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
163 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
164 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
165 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
166 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
167 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
168 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
169 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
171 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
172 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
173 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
177 * Max size of iod being embedded in the request payload
179 #define NVME_INT_PAGES 2
180 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
183 * Will slightly overestimate the number of pages needed. This is OK
184 * as it only leads to a small amount of wasted memory for the lifetime of
187 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
189 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
190 dev
->ctrl
.page_size
);
191 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
194 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
195 unsigned int size
, unsigned int nseg
)
197 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
198 sizeof(struct scatterlist
) * nseg
;
201 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
203 return sizeof(struct nvme_iod
) +
204 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
207 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
208 unsigned int hctx_idx
)
210 struct nvme_dev
*dev
= data
;
211 struct nvme_queue
*nvmeq
= dev
->queues
[0];
213 WARN_ON(hctx_idx
!= 0);
214 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
215 WARN_ON(nvmeq
->tags
);
217 hctx
->driver_data
= nvmeq
;
218 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
222 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
224 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
229 static int nvme_admin_init_request(void *data
, struct request
*req
,
230 unsigned int hctx_idx
, unsigned int rq_idx
,
231 unsigned int numa_node
)
233 struct nvme_dev
*dev
= data
;
234 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
235 struct nvme_queue
*nvmeq
= dev
->queues
[0];
242 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
243 unsigned int hctx_idx
)
245 struct nvme_dev
*dev
= data
;
246 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
249 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
251 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
252 hctx
->driver_data
= nvmeq
;
256 static int nvme_init_request(void *data
, struct request
*req
,
257 unsigned int hctx_idx
, unsigned int rq_idx
,
258 unsigned int numa_node
)
260 struct nvme_dev
*dev
= data
;
261 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
262 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
269 static void nvme_queue_scan(struct nvme_dev
*dev
)
272 * Do not queue new scan work when a controller is reset during
275 if (dev
->ctrl
.state
!= NVME_CTRL_DELETING
)
276 queue_work(nvme_workq
, &dev
->scan_work
);
279 static void nvme_complete_async_event(struct nvme_dev
*dev
,
280 struct nvme_completion
*cqe
)
282 u16 status
= le16_to_cpu(cqe
->status
) >> 1;
283 u32 result
= le32_to_cpu(cqe
->result
);
285 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
) {
286 ++dev
->ctrl
.event_limit
;
287 queue_work(nvme_workq
, &dev
->async_work
);
290 if (status
!= NVME_SC_SUCCESS
)
293 switch (result
& 0xff07) {
294 case NVME_AER_NOTICE_NS_CHANGED
:
295 dev_info(dev
->ctrl
.device
, "rescanning\n");
296 nvme_queue_scan(dev
);
298 dev_warn(dev
->ctrl
.device
, "async event result %08x\n", result
);
303 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
304 * @nvmeq: The queue to use
305 * @cmd: The command to send
307 * Safe to use from interrupt context
309 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
310 struct nvme_command
*cmd
)
312 u16 tail
= nvmeq
->sq_tail
;
314 if (nvmeq
->sq_cmds_io
)
315 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
317 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
319 if (++tail
== nvmeq
->q_depth
)
321 writel(tail
, nvmeq
->q_db
);
322 nvmeq
->sq_tail
= tail
;
325 static __le64
**iod_list(struct request
*req
)
327 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
328 return (__le64
**)(iod
->sg
+ req
->nr_phys_segments
);
331 static int nvme_init_iod(struct request
*rq
, unsigned size
,
332 struct nvme_dev
*dev
)
334 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
335 int nseg
= rq
->nr_phys_segments
;
337 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
338 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
340 return BLK_MQ_RQ_QUEUE_BUSY
;
342 iod
->sg
= iod
->inline_sg
;
352 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
354 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
355 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
357 __le64
**list
= iod_list(req
);
358 dma_addr_t prp_dma
= iod
->first_dma
;
360 if (req
->cmd_flags
& REQ_DISCARD
)
361 kfree(req
->completion_data
);
363 if (iod
->npages
== 0)
364 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
365 for (i
= 0; i
< iod
->npages
; i
++) {
366 __le64
*prp_list
= list
[i
];
367 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
368 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
369 prp_dma
= next_prp_dma
;
372 if (iod
->sg
!= iod
->inline_sg
)
376 #ifdef CONFIG_BLK_DEV_INTEGRITY
377 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
379 if (be32_to_cpu(pi
->ref_tag
) == v
)
380 pi
->ref_tag
= cpu_to_be32(p
);
383 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
385 if (be32_to_cpu(pi
->ref_tag
) == p
)
386 pi
->ref_tag
= cpu_to_be32(v
);
390 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
392 * The virtual start sector is the one that was originally submitted by the
393 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
394 * start sector may be different. Remap protection information to match the
395 * physical LBA on writes, and back to the original seed on reads.
397 * Type 0 and 3 do not have a ref tag, so no remapping required.
399 static void nvme_dif_remap(struct request
*req
,
400 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
402 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
403 struct bio_integrity_payload
*bip
;
404 struct t10_pi_tuple
*pi
;
406 u32 i
, nlb
, ts
, phys
, virt
;
408 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
411 bip
= bio_integrity(req
->bio
);
415 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
418 virt
= bip_get_seed(bip
);
419 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
420 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
421 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
423 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
424 pi
= (struct t10_pi_tuple
*)p
;
425 dif_swap(phys
, virt
, pi
);
430 #else /* CONFIG_BLK_DEV_INTEGRITY */
431 static void nvme_dif_remap(struct request
*req
,
432 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
435 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
438 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
443 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
,
446 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
447 struct dma_pool
*pool
;
448 int length
= total_len
;
449 struct scatterlist
*sg
= iod
->sg
;
450 int dma_len
= sg_dma_len(sg
);
451 u64 dma_addr
= sg_dma_address(sg
);
452 u32 page_size
= dev
->ctrl
.page_size
;
453 int offset
= dma_addr
& (page_size
- 1);
455 __le64
**list
= iod_list(req
);
459 length
-= (page_size
- offset
);
463 dma_len
-= (page_size
- offset
);
465 dma_addr
+= (page_size
- offset
);
468 dma_addr
= sg_dma_address(sg
);
469 dma_len
= sg_dma_len(sg
);
472 if (length
<= page_size
) {
473 iod
->first_dma
= dma_addr
;
477 nprps
= DIV_ROUND_UP(length
, page_size
);
478 if (nprps
<= (256 / 8)) {
479 pool
= dev
->prp_small_pool
;
482 pool
= dev
->prp_page_pool
;
486 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
488 iod
->first_dma
= dma_addr
;
493 iod
->first_dma
= prp_dma
;
496 if (i
== page_size
>> 3) {
497 __le64
*old_prp_list
= prp_list
;
498 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
501 list
[iod
->npages
++] = prp_list
;
502 prp_list
[0] = old_prp_list
[i
- 1];
503 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
506 prp_list
[i
++] = cpu_to_le64(dma_addr
);
507 dma_len
-= page_size
;
508 dma_addr
+= page_size
;
516 dma_addr
= sg_dma_address(sg
);
517 dma_len
= sg_dma_len(sg
);
523 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
524 unsigned size
, struct nvme_command
*cmnd
)
526 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
527 struct request_queue
*q
= req
->q
;
528 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
529 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
530 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
532 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
533 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
537 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
538 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
541 if (!nvme_setup_prps(dev
, req
, size
))
544 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
545 if (blk_integrity_rq(req
)) {
546 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
549 sg_init_table(&iod
->meta_sg
, 1);
550 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
553 if (rq_data_dir(req
))
554 nvme_dif_remap(req
, nvme_dif_prep
);
556 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
560 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
561 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
562 if (blk_integrity_rq(req
))
563 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
564 return BLK_MQ_RQ_QUEUE_OK
;
567 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
572 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
574 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
575 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
576 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
579 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
580 if (blk_integrity_rq(req
)) {
581 if (!rq_data_dir(req
))
582 nvme_dif_remap(req
, nvme_dif_complete
);
583 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
587 nvme_free_iod(dev
, req
);
591 * NOTE: ns is NULL when called on the admin queue.
593 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
594 const struct blk_mq_queue_data
*bd
)
596 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
597 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
598 struct nvme_dev
*dev
= nvmeq
->dev
;
599 struct request
*req
= bd
->rq
;
600 struct nvme_command cmnd
;
602 int ret
= BLK_MQ_RQ_QUEUE_OK
;
605 * If formated with metadata, require the block layer provide a buffer
606 * unless this namespace is formated such that the metadata can be
607 * stripped/generated by the controller with PRACT=1.
609 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
610 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
611 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
612 blk_mq_end_request(req
, -EFAULT
);
613 return BLK_MQ_RQ_QUEUE_OK
;
617 map_len
= nvme_map_len(req
);
618 ret
= nvme_init_iod(req
, map_len
, dev
);
622 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
626 if (req
->nr_phys_segments
)
627 ret
= nvme_map_data(dev
, req
, map_len
, &cmnd
);
632 cmnd
.common
.command_id
= req
->tag
;
633 blk_mq_start_request(req
);
635 spin_lock_irq(&nvmeq
->q_lock
);
636 if (unlikely(nvmeq
->cq_vector
< 0)) {
637 if (ns
&& !test_bit(NVME_NS_DEAD
, &ns
->flags
))
638 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
640 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
641 spin_unlock_irq(&nvmeq
->q_lock
);
644 __nvme_submit_cmd(nvmeq
, &cmnd
);
645 nvme_process_cq(nvmeq
);
646 spin_unlock_irq(&nvmeq
->q_lock
);
647 return BLK_MQ_RQ_QUEUE_OK
;
649 nvme_free_iod(dev
, req
);
653 static void nvme_complete_rq(struct request
*req
)
655 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
656 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
659 nvme_unmap_data(dev
, req
);
661 if (unlikely(req
->errors
)) {
662 if (nvme_req_needs_retry(req
, req
->errors
)) {
663 nvme_requeue_req(req
);
667 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
670 error
= nvme_error_status(req
->errors
);
673 if (unlikely(iod
->aborted
)) {
674 dev_warn(dev
->ctrl
.device
,
675 "completing aborted command with status: %04x\n",
679 blk_mq_end_request(req
, error
);
682 /* We read the CQE phase first to check if the rest of the entry is valid */
683 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
686 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
689 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
693 head
= nvmeq
->cq_head
;
694 phase
= nvmeq
->cq_phase
;
696 while (nvme_cqe_valid(nvmeq
, head
, phase
)) {
697 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
700 if (++head
== nvmeq
->q_depth
) {
705 if (tag
&& *tag
== cqe
.command_id
)
708 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
709 dev_warn(nvmeq
->dev
->ctrl
.device
,
710 "invalid id %d completed on queue %d\n",
711 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
716 * AEN requests are special as they don't time out and can
717 * survive any kind of queue freeze and often don't respond to
718 * aborts. We don't even bother to allocate a struct request
719 * for them but rather special case them here.
721 if (unlikely(nvmeq
->qid
== 0 &&
722 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
723 nvme_complete_async_event(nvmeq
->dev
, &cqe
);
727 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
728 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
&& req
->special
)
729 memcpy(req
->special
, &cqe
, sizeof(cqe
));
730 blk_mq_complete_request(req
, le16_to_cpu(cqe
.status
) >> 1);
734 /* If the controller ignores the cq head doorbell and continuously
735 * writes to the queue, it is theoretically possible to wrap around
736 * the queue twice and mistakenly return IRQ_NONE. Linux only
737 * requires that 0.1% of your interrupts are handled, so this isn't
740 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
743 if (likely(nvmeq
->cq_vector
>= 0))
744 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
745 nvmeq
->cq_head
= head
;
746 nvmeq
->cq_phase
= phase
;
751 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
753 __nvme_process_cq(nvmeq
, NULL
);
756 static irqreturn_t
nvme_irq(int irq
, void *data
)
759 struct nvme_queue
*nvmeq
= data
;
760 spin_lock(&nvmeq
->q_lock
);
761 nvme_process_cq(nvmeq
);
762 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
764 spin_unlock(&nvmeq
->q_lock
);
768 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
770 struct nvme_queue
*nvmeq
= data
;
771 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
772 return IRQ_WAKE_THREAD
;
776 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
778 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
780 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
781 spin_lock_irq(&nvmeq
->q_lock
);
782 __nvme_process_cq(nvmeq
, &tag
);
783 spin_unlock_irq(&nvmeq
->q_lock
);
792 static void nvme_async_event_work(struct work_struct
*work
)
794 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, async_work
);
795 struct nvme_queue
*nvmeq
= dev
->queues
[0];
796 struct nvme_command c
;
798 memset(&c
, 0, sizeof(c
));
799 c
.common
.opcode
= nvme_admin_async_event
;
801 spin_lock_irq(&nvmeq
->q_lock
);
802 while (dev
->ctrl
.event_limit
> 0) {
803 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+
804 --dev
->ctrl
.event_limit
;
805 __nvme_submit_cmd(nvmeq
, &c
);
807 spin_unlock_irq(&nvmeq
->q_lock
);
810 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
812 struct nvme_command c
;
814 memset(&c
, 0, sizeof(c
));
815 c
.delete_queue
.opcode
= opcode
;
816 c
.delete_queue
.qid
= cpu_to_le16(id
);
818 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
821 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
822 struct nvme_queue
*nvmeq
)
824 struct nvme_command c
;
825 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
828 * Note: we (ab)use the fact the the prp fields survive if no data
829 * is attached to the request.
831 memset(&c
, 0, sizeof(c
));
832 c
.create_cq
.opcode
= nvme_admin_create_cq
;
833 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
834 c
.create_cq
.cqid
= cpu_to_le16(qid
);
835 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
836 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
837 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
839 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
842 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
843 struct nvme_queue
*nvmeq
)
845 struct nvme_command c
;
846 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
849 * Note: we (ab)use the fact the the prp fields survive if no data
850 * is attached to the request.
852 memset(&c
, 0, sizeof(c
));
853 c
.create_sq
.opcode
= nvme_admin_create_sq
;
854 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
855 c
.create_sq
.sqid
= cpu_to_le16(qid
);
856 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
857 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
858 c
.create_sq
.cqid
= cpu_to_le16(qid
);
860 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
863 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
865 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
868 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
870 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
873 static void abort_endio(struct request
*req
, int error
)
875 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
876 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
877 u16 status
= req
->errors
;
879 dev_warn(nvmeq
->dev
->ctrl
.device
, "Abort status: 0x%x", status
);
880 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
881 blk_mq_free_request(req
);
884 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
886 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
887 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
888 struct nvme_dev
*dev
= nvmeq
->dev
;
889 struct request
*abort_req
;
890 struct nvme_command cmd
;
893 * Shutdown immediately if controller times out while starting. The
894 * reset work will see the pci device disabled when it gets the forced
895 * cancellation error. All outstanding requests are completed on
896 * shutdown, so we return BLK_EH_HANDLED.
898 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
899 dev_warn(dev
->ctrl
.device
,
900 "I/O %d QID %d timeout, disable controller\n",
901 req
->tag
, nvmeq
->qid
);
902 nvme_dev_disable(dev
, false);
903 req
->errors
= NVME_SC_CANCELLED
;
904 return BLK_EH_HANDLED
;
908 * Shutdown the controller immediately and schedule a reset if the
909 * command was already aborted once before and still hasn't been
910 * returned to the driver, or if this is the admin queue.
912 if (!nvmeq
->qid
|| iod
->aborted
) {
913 dev_warn(dev
->ctrl
.device
,
914 "I/O %d QID %d timeout, reset controller\n",
915 req
->tag
, nvmeq
->qid
);
916 nvme_dev_disable(dev
, false);
917 queue_work(nvme_workq
, &dev
->reset_work
);
920 * Mark the request as handled, since the inline shutdown
921 * forces all outstanding requests to complete.
923 req
->errors
= NVME_SC_CANCELLED
;
924 return BLK_EH_HANDLED
;
929 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
930 atomic_inc(&dev
->ctrl
.abort_limit
);
931 return BLK_EH_RESET_TIMER
;
934 memset(&cmd
, 0, sizeof(cmd
));
935 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
936 cmd
.abort
.cid
= req
->tag
;
937 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
939 dev_warn(nvmeq
->dev
->ctrl
.device
,
940 "I/O %d QID %d timeout, aborting\n",
941 req
->tag
, nvmeq
->qid
);
943 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
945 if (IS_ERR(abort_req
)) {
946 atomic_inc(&dev
->ctrl
.abort_limit
);
947 return BLK_EH_RESET_TIMER
;
950 abort_req
->timeout
= ADMIN_TIMEOUT
;
951 abort_req
->end_io_data
= NULL
;
952 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
955 * The aborted req will be completed on receiving the abort req.
956 * We enable the timer again. If hit twice, it'll cause a device reset,
957 * as the device then is in a faulty state.
959 return BLK_EH_RESET_TIMER
;
962 static void nvme_cancel_io(struct request
*req
, void *data
, bool reserved
)
966 if (!blk_mq_request_started(req
))
969 dev_dbg_ratelimited(((struct nvme_dev
*) data
)->ctrl
.device
,
970 "Cancelling I/O %d", req
->tag
);
972 status
= NVME_SC_ABORT_REQ
;
973 if (blk_queue_dying(req
->q
))
974 status
|= NVME_SC_DNR
;
975 blk_mq_complete_request(req
, status
);
978 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
980 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
981 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
983 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
984 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
988 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
992 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
993 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
995 dev
->queues
[i
] = NULL
;
996 nvme_free_queue(nvmeq
);
1001 * nvme_suspend_queue - put queue into suspended state
1002 * @nvmeq - queue to suspend
1004 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1008 spin_lock_irq(&nvmeq
->q_lock
);
1009 if (nvmeq
->cq_vector
== -1) {
1010 spin_unlock_irq(&nvmeq
->q_lock
);
1013 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1014 nvmeq
->dev
->online_queues
--;
1015 nvmeq
->cq_vector
= -1;
1016 spin_unlock_irq(&nvmeq
->q_lock
);
1018 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1019 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1021 irq_set_affinity_hint(vector
, NULL
);
1022 free_irq(vector
, nvmeq
);
1027 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1029 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1033 if (nvme_suspend_queue(nvmeq
))
1037 nvme_shutdown_ctrl(&dev
->ctrl
);
1039 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1040 dev
->bar
+ NVME_REG_CAP
));
1042 spin_lock_irq(&nvmeq
->q_lock
);
1043 nvme_process_cq(nvmeq
);
1044 spin_unlock_irq(&nvmeq
->q_lock
);
1047 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1050 int q_depth
= dev
->q_depth
;
1051 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1052 dev
->ctrl
.page_size
);
1054 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1055 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1056 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1057 q_depth
= div_u64(mem_per_q
, entry_size
);
1060 * Ensure the reduced q_depth is above some threshold where it
1061 * would be better to map queues in system memory with the
1071 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1074 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1075 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1076 dev
->ctrl
.page_size
);
1077 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1078 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1080 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1081 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1082 if (!nvmeq
->sq_cmds
)
1089 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1092 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1096 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1097 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1101 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1104 nvmeq
->q_dmadev
= dev
->dev
;
1106 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1107 dev
->ctrl
.instance
, qid
);
1108 spin_lock_init(&nvmeq
->q_lock
);
1110 nvmeq
->cq_phase
= 1;
1111 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1112 nvmeq
->q_depth
= depth
;
1114 nvmeq
->cq_vector
= -1;
1115 dev
->queues
[qid
] = nvmeq
;
1121 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1122 nvmeq
->cq_dma_addr
);
1128 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1131 if (use_threaded_interrupts
)
1132 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1133 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1135 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1136 IRQF_SHARED
, name
, nvmeq
);
1139 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1141 struct nvme_dev
*dev
= nvmeq
->dev
;
1143 spin_lock_irq(&nvmeq
->q_lock
);
1146 nvmeq
->cq_phase
= 1;
1147 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1148 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1149 dev
->online_queues
++;
1150 spin_unlock_irq(&nvmeq
->q_lock
);
1153 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1155 struct nvme_dev
*dev
= nvmeq
->dev
;
1158 nvmeq
->cq_vector
= qid
- 1;
1159 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1163 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1167 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1171 nvme_init_queue(nvmeq
, qid
);
1175 adapter_delete_sq(dev
, qid
);
1177 adapter_delete_cq(dev
, qid
);
1181 static struct blk_mq_ops nvme_mq_admin_ops
= {
1182 .queue_rq
= nvme_queue_rq
,
1183 .complete
= nvme_complete_rq
,
1184 .map_queue
= blk_mq_map_queue
,
1185 .init_hctx
= nvme_admin_init_hctx
,
1186 .exit_hctx
= nvme_admin_exit_hctx
,
1187 .init_request
= nvme_admin_init_request
,
1188 .timeout
= nvme_timeout
,
1191 static struct blk_mq_ops nvme_mq_ops
= {
1192 .queue_rq
= nvme_queue_rq
,
1193 .complete
= nvme_complete_rq
,
1194 .map_queue
= blk_mq_map_queue
,
1195 .init_hctx
= nvme_init_hctx
,
1196 .init_request
= nvme_init_request
,
1197 .timeout
= nvme_timeout
,
1201 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1203 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1205 * If the controller was reset during removal, it's possible
1206 * user requests may be waiting on a stopped queue. Start the
1207 * queue to flush these to completion.
1209 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1210 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1211 blk_mq_free_tag_set(&dev
->admin_tagset
);
1215 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1217 if (!dev
->ctrl
.admin_q
) {
1218 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1219 dev
->admin_tagset
.nr_hw_queues
= 1;
1222 * Subtract one to leave an empty queue entry for 'Full Queue'
1223 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1225 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1226 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1227 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1228 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1229 dev
->admin_tagset
.driver_data
= dev
;
1231 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1234 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1235 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1236 blk_mq_free_tag_set(&dev
->admin_tagset
);
1239 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1240 nvme_dev_remove_admin(dev
);
1241 dev
->ctrl
.admin_q
= NULL
;
1245 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1250 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1254 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1255 struct nvme_queue
*nvmeq
;
1257 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1258 NVME_CAP_NSSRC(cap
) : 0;
1260 if (dev
->subsystem
&&
1261 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1262 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1264 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1268 nvmeq
= dev
->queues
[0];
1270 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1275 aqa
= nvmeq
->q_depth
- 1;
1278 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1279 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1280 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1282 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1286 nvmeq
->cq_vector
= 0;
1287 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1289 nvmeq
->cq_vector
= -1;
1296 nvme_free_queues(dev
, 0);
1300 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1303 /* If true, indicates loss of adapter communication, possibly by a
1304 * NVMe Subsystem reset.
1306 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1308 /* If there is a reset ongoing, we shouldn't reset again. */
1309 if (work_busy(&dev
->reset_work
))
1312 /* We shouldn't reset unless the controller is on fatal error state
1313 * _or_ if we lost the communication with it.
1315 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1318 /* If PCI error recovery process is happening, we cannot reset or
1319 * the recovery mechanism will surely fail.
1321 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1327 static void nvme_watchdog_timer(unsigned long data
)
1329 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1330 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1332 /* Skip controllers under certain specific conditions. */
1333 if (nvme_should_reset(dev
, csts
)) {
1334 if (queue_work(nvme_workq
, &dev
->reset_work
))
1336 "Failed status: 0x%x, reset controller.\n",
1341 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1344 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1349 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1350 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1356 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1357 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1358 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1360 nvme_free_queues(dev
, i
);
1366 * Ignore failing Create SQ/CQ commands, we can continue with less
1367 * than the desired aount of queues, and even a controller without
1368 * I/O queues an still be used to issue admin commands. This might
1369 * be useful to upgrade a buggy firmware for example.
1371 return ret
>= 0 ? 0 : ret
;
1374 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1376 u64 szu
, size
, offset
;
1378 resource_size_t bar_size
;
1379 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1381 dma_addr_t dma_addr
;
1386 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1387 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1390 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1392 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1393 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1394 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1395 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1397 if (offset
> bar_size
)
1401 * Controllers may support a CMB size larger than their BAR,
1402 * for example, due to being behind a bridge. Reduce the CMB to
1403 * the reported size of the BAR
1405 if (size
> bar_size
- offset
)
1406 size
= bar_size
- offset
;
1408 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1409 cmb
= ioremap_wc(dma_addr
, size
);
1413 dev
->cmb_dma_addr
= dma_addr
;
1414 dev
->cmb_size
= size
;
1418 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1426 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1428 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1431 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1433 struct nvme_queue
*adminq
= dev
->queues
[0];
1434 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1435 int result
, i
, vecs
, nr_io_queues
, size
;
1437 nr_io_queues
= num_possible_cpus();
1438 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1443 * Degraded controllers might return an error when setting the queue
1444 * count. We still want to be able to bring them online and offer
1445 * access to the admin queue, as that might be only way to fix them up.
1448 dev_err(dev
->ctrl
.device
,
1449 "Could not set queue count (%d)\n", result
);
1453 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1454 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1455 sizeof(struct nvme_command
));
1457 dev
->q_depth
= result
;
1459 nvme_release_cmb(dev
);
1462 size
= db_bar_size(dev
, nr_io_queues
);
1466 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1469 if (!--nr_io_queues
)
1471 size
= db_bar_size(dev
, nr_io_queues
);
1473 dev
->dbs
= dev
->bar
+ 4096;
1474 adminq
->q_db
= dev
->dbs
;
1477 /* Deregister the admin queue's interrupt */
1478 free_irq(dev
->entry
[0].vector
, adminq
);
1481 * If we enable msix early due to not intx, disable it again before
1482 * setting up the full range we need.
1484 if (pdev
->msi_enabled
)
1485 pci_disable_msi(pdev
);
1486 else if (pdev
->msix_enabled
)
1487 pci_disable_msix(pdev
);
1489 for (i
= 0; i
< nr_io_queues
; i
++)
1490 dev
->entry
[i
].entry
= i
;
1491 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1493 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1497 for (i
= 0; i
< vecs
; i
++)
1498 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1503 * Should investigate if there's a performance win from allocating
1504 * more queues than interrupt vectors; it might allow the submission
1505 * path to scale better, even if the receive path is limited by the
1506 * number of interrupts.
1508 nr_io_queues
= vecs
;
1509 dev
->max_qid
= nr_io_queues
;
1511 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1513 adminq
->cq_vector
= -1;
1516 return nvme_create_io_queues(dev
);
1519 nvme_free_queues(dev
, 1);
1523 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1525 struct nvme_queue
*nvmeq
;
1528 for (i
= 0; i
< dev
->online_queues
; i
++) {
1529 nvmeq
= dev
->queues
[i
];
1531 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1534 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1535 blk_mq_tags_cpumask(*nvmeq
->tags
));
1539 static void nvme_dev_scan(struct work_struct
*work
)
1541 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1543 if (!dev
->tagset
.tags
)
1545 nvme_scan_namespaces(&dev
->ctrl
);
1546 nvme_set_irq_hints(dev
);
1549 static void nvme_del_queue_end(struct request
*req
, int error
)
1551 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1553 blk_mq_free_request(req
);
1554 complete(&nvmeq
->dev
->ioq_wait
);
1557 static void nvme_del_cq_end(struct request
*req
, int error
)
1559 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1562 unsigned long flags
;
1565 * We might be called with the AQ q_lock held
1566 * and the I/O queue q_lock should always
1567 * nest inside the AQ one.
1569 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1570 SINGLE_DEPTH_NESTING
);
1571 nvme_process_cq(nvmeq
);
1572 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1575 nvme_del_queue_end(req
, error
);
1578 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1580 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1581 struct request
*req
;
1582 struct nvme_command cmd
;
1584 memset(&cmd
, 0, sizeof(cmd
));
1585 cmd
.delete_queue
.opcode
= opcode
;
1586 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1588 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
);
1590 return PTR_ERR(req
);
1592 req
->timeout
= ADMIN_TIMEOUT
;
1593 req
->end_io_data
= nvmeq
;
1595 blk_execute_rq_nowait(q
, NULL
, req
, false,
1596 opcode
== nvme_admin_delete_cq
?
1597 nvme_del_cq_end
: nvme_del_queue_end
);
1601 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1604 unsigned long timeout
;
1605 u8 opcode
= nvme_admin_delete_sq
;
1607 for (pass
= 0; pass
< 2; pass
++) {
1608 int sent
= 0, i
= dev
->queue_count
- 1;
1610 reinit_completion(&dev
->ioq_wait
);
1612 timeout
= ADMIN_TIMEOUT
;
1613 for (; i
> 0; i
--) {
1614 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1617 nvme_suspend_queue(nvmeq
);
1618 if (nvme_delete_queue(nvmeq
, opcode
))
1623 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1629 opcode
= nvme_admin_delete_cq
;
1634 * Return: error value if an error occurred setting up the queues or calling
1635 * Identify Device. 0 if these succeeded, even if adding some of the
1636 * namespaces failed. At the moment, these failures are silent. TBD which
1637 * failures should be reported.
1639 static int nvme_dev_add(struct nvme_dev
*dev
)
1641 if (!dev
->ctrl
.tagset
) {
1642 dev
->tagset
.ops
= &nvme_mq_ops
;
1643 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1644 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1645 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1646 dev
->tagset
.queue_depth
=
1647 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1648 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1649 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1650 dev
->tagset
.driver_data
= dev
;
1652 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1654 dev
->ctrl
.tagset
= &dev
->tagset
;
1656 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1658 /* Free previously allocated queues that are no longer usable */
1659 nvme_free_queues(dev
, dev
->online_queues
);
1662 nvme_queue_scan(dev
);
1666 static int nvme_pci_enable(struct nvme_dev
*dev
)
1669 int result
= -ENOMEM
;
1670 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1672 if (pci_enable_device_mem(pdev
))
1675 pci_set_master(pdev
);
1677 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1678 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1681 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1687 * Some devices and/or platforms don't advertise or work with INTx
1688 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1689 * adjust this later.
1691 if (pci_enable_msix(pdev
, dev
->entry
, 1)) {
1692 pci_enable_msi(pdev
);
1693 dev
->entry
[0].vector
= pdev
->irq
;
1696 if (!dev
->entry
[0].vector
) {
1701 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1703 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1704 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1705 dev
->dbs
= dev
->bar
+ 4096;
1708 * Temporary fix for the Apple controller found in the MacBook8,1 and
1709 * some MacBook7,1 to avoid controller resets and data loss.
1711 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1713 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1714 "queue depth=%u to work around controller resets\n",
1718 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1719 dev
->cmb
= nvme_map_cmb(dev
);
1721 pci_enable_pcie_error_reporting(pdev
);
1722 pci_save_state(pdev
);
1726 pci_disable_device(pdev
);
1730 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1734 pci_release_regions(to_pci_dev(dev
->dev
));
1737 static void nvme_pci_disable(struct nvme_dev
*dev
)
1739 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1741 if (pdev
->msi_enabled
)
1742 pci_disable_msi(pdev
);
1743 else if (pdev
->msix_enabled
)
1744 pci_disable_msix(pdev
);
1746 if (pci_is_enabled(pdev
)) {
1747 pci_disable_pcie_error_reporting(pdev
);
1748 pci_disable_device(pdev
);
1752 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1757 del_timer_sync(&dev
->watchdog_timer
);
1759 mutex_lock(&dev
->shutdown_lock
);
1760 if (pci_is_enabled(to_pci_dev(dev
->dev
))) {
1761 nvme_stop_queues(&dev
->ctrl
);
1762 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1764 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1765 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
1766 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1767 nvme_suspend_queue(nvmeq
);
1770 nvme_disable_io_queues(dev
);
1771 nvme_disable_admin_queue(dev
, shutdown
);
1773 nvme_pci_disable(dev
);
1775 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_io
, dev
);
1776 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_io
, dev
);
1777 mutex_unlock(&dev
->shutdown_lock
);
1780 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1782 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1783 PAGE_SIZE
, PAGE_SIZE
, 0);
1784 if (!dev
->prp_page_pool
)
1787 /* Optimisation for I/Os between 4k and 128k */
1788 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1790 if (!dev
->prp_small_pool
) {
1791 dma_pool_destroy(dev
->prp_page_pool
);
1797 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1799 dma_pool_destroy(dev
->prp_page_pool
);
1800 dma_pool_destroy(dev
->prp_small_pool
);
1803 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1805 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1807 put_device(dev
->dev
);
1808 if (dev
->tagset
.tags
)
1809 blk_mq_free_tag_set(&dev
->tagset
);
1810 if (dev
->ctrl
.admin_q
)
1811 blk_put_queue(dev
->ctrl
.admin_q
);
1817 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
1819 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
1821 kref_get(&dev
->ctrl
.kref
);
1822 nvme_dev_disable(dev
, false);
1823 if (!schedule_work(&dev
->remove_work
))
1824 nvme_put_ctrl(&dev
->ctrl
);
1827 static void nvme_reset_work(struct work_struct
*work
)
1829 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1830 int result
= -ENODEV
;
1832 if (WARN_ON(dev
->ctrl
.state
== NVME_CTRL_RESETTING
))
1836 * If we're called to reset a live controller first shut it down before
1839 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
1840 nvme_dev_disable(dev
, false);
1842 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
))
1845 result
= nvme_pci_enable(dev
);
1849 result
= nvme_configure_admin_queue(dev
);
1853 nvme_init_queue(dev
->queues
[0], 0);
1854 result
= nvme_alloc_admin_tags(dev
);
1858 result
= nvme_init_identify(&dev
->ctrl
);
1862 result
= nvme_setup_io_queues(dev
);
1867 * A controller that can not execute IO typically requires user
1868 * intervention to correct. For such degraded controllers, the driver
1869 * should not submit commands the user did not request, so skip
1870 * registering for asynchronous event notification on this condition.
1872 if (dev
->online_queues
> 1) {
1873 dev
->ctrl
.event_limit
= NVME_NR_AEN_COMMANDS
;
1874 queue_work(nvme_workq
, &dev
->async_work
);
1877 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1880 * Keep the controller around but remove all namespaces if we don't have
1881 * any working I/O queue.
1883 if (dev
->online_queues
< 2) {
1884 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
1885 nvme_kill_queues(&dev
->ctrl
);
1886 nvme_remove_namespaces(&dev
->ctrl
);
1888 nvme_start_queues(&dev
->ctrl
);
1892 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
1893 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
1899 nvme_remove_dead_ctrl(dev
, result
);
1902 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1904 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1905 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1907 nvme_kill_queues(&dev
->ctrl
);
1908 if (pci_get_drvdata(pdev
))
1909 pci_stop_and_remove_bus_device_locked(pdev
);
1910 nvme_put_ctrl(&dev
->ctrl
);
1913 static int nvme_reset(struct nvme_dev
*dev
)
1915 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1918 if (!queue_work(nvme_workq
, &dev
->reset_work
))
1921 flush_work(&dev
->reset_work
);
1925 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
1927 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
1931 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
1933 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
1937 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
1939 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
1943 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
1945 return nvme_reset(to_nvme_dev(ctrl
));
1948 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
1949 .module
= THIS_MODULE
,
1950 .reg_read32
= nvme_pci_reg_read32
,
1951 .reg_write32
= nvme_pci_reg_write32
,
1952 .reg_read64
= nvme_pci_reg_read64
,
1953 .reset_ctrl
= nvme_pci_reset_ctrl
,
1954 .free_ctrl
= nvme_pci_free_ctrl
,
1957 static int nvme_dev_map(struct nvme_dev
*dev
)
1960 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1962 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1965 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1968 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1974 pci_release_regions(pdev
);
1978 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1980 int node
, result
= -ENOMEM
;
1981 struct nvme_dev
*dev
;
1983 node
= dev_to_node(&pdev
->dev
);
1984 if (node
== NUMA_NO_NODE
)
1985 set_dev_node(&pdev
->dev
, 0);
1987 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
1990 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
1994 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1999 dev
->dev
= get_device(&pdev
->dev
);
2000 pci_set_drvdata(pdev
, dev
);
2002 result
= nvme_dev_map(dev
);
2006 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
2007 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2008 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2009 INIT_WORK(&dev
->async_work
, nvme_async_event_work
);
2010 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
2011 (unsigned long)dev
);
2012 mutex_init(&dev
->shutdown_lock
);
2013 init_completion(&dev
->ioq_wait
);
2015 result
= nvme_setup_prp_pools(dev
);
2019 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2024 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2026 queue_work(nvme_workq
, &dev
->reset_work
);
2030 nvme_release_prp_pools(dev
);
2032 put_device(dev
->dev
);
2033 nvme_dev_unmap(dev
);
2041 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2043 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2046 nvme_dev_disable(dev
, false);
2048 queue_work(nvme_workq
, &dev
->reset_work
);
2051 static void nvme_shutdown(struct pci_dev
*pdev
)
2053 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2054 nvme_dev_disable(dev
, true);
2058 * The driver's remove may be called on a device in a partially initialized
2059 * state. This function must not have any dependencies on the device state in
2062 static void nvme_remove(struct pci_dev
*pdev
)
2064 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2066 del_timer_sync(&dev
->watchdog_timer
);
2068 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2070 pci_set_drvdata(pdev
, NULL
);
2071 flush_work(&dev
->async_work
);
2072 flush_work(&dev
->scan_work
);
2073 nvme_remove_namespaces(&dev
->ctrl
);
2074 nvme_uninit_ctrl(&dev
->ctrl
);
2075 nvme_dev_disable(dev
, true);
2076 flush_work(&dev
->reset_work
);
2077 nvme_dev_remove_admin(dev
);
2078 nvme_free_queues(dev
, 0);
2079 nvme_release_cmb(dev
);
2080 nvme_release_prp_pools(dev
);
2081 nvme_dev_unmap(dev
);
2082 nvme_put_ctrl(&dev
->ctrl
);
2085 #ifdef CONFIG_PM_SLEEP
2086 static int nvme_suspend(struct device
*dev
)
2088 struct pci_dev
*pdev
= to_pci_dev(dev
);
2089 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2091 nvme_dev_disable(ndev
, true);
2095 static int nvme_resume(struct device
*dev
)
2097 struct pci_dev
*pdev
= to_pci_dev(dev
);
2098 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2100 queue_work(nvme_workq
, &ndev
->reset_work
);
2105 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2107 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2108 pci_channel_state_t state
)
2110 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2113 * A frozen channel requires a reset. When detected, this method will
2114 * shutdown the controller to quiesce. The controller will be restarted
2115 * after the slot reset through driver's slot_reset callback.
2117 dev_warn(dev
->ctrl
.device
, "error detected: state:%d\n", state
);
2119 case pci_channel_io_normal
:
2120 return PCI_ERS_RESULT_CAN_RECOVER
;
2121 case pci_channel_io_frozen
:
2122 nvme_dev_disable(dev
, false);
2123 return PCI_ERS_RESULT_NEED_RESET
;
2124 case pci_channel_io_perm_failure
:
2125 return PCI_ERS_RESULT_DISCONNECT
;
2127 return PCI_ERS_RESULT_NEED_RESET
;
2130 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2132 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2134 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2135 pci_restore_state(pdev
);
2136 queue_work(nvme_workq
, &dev
->reset_work
);
2137 return PCI_ERS_RESULT_RECOVERED
;
2140 static void nvme_error_resume(struct pci_dev
*pdev
)
2142 pci_cleanup_aer_uncorrect_error_status(pdev
);
2145 static const struct pci_error_handlers nvme_err_handler
= {
2146 .error_detected
= nvme_error_detected
,
2147 .slot_reset
= nvme_slot_reset
,
2148 .resume
= nvme_error_resume
,
2149 .reset_notify
= nvme_reset_notify
,
2152 /* Move to pci_ids.h later */
2153 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2155 static const struct pci_device_id nvme_id_table
[] = {
2156 { PCI_VDEVICE(INTEL
, 0x0953),
2157 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2158 NVME_QUIRK_DISCARD_ZEROES
, },
2159 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2160 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2161 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2162 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2165 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2167 static struct pci_driver nvme_driver
= {
2169 .id_table
= nvme_id_table
,
2170 .probe
= nvme_probe
,
2171 .remove
= nvme_remove
,
2172 .shutdown
= nvme_shutdown
,
2174 .pm
= &nvme_dev_pm_ops
,
2176 .err_handler
= &nvme_err_handler
,
2179 static int __init
nvme_init(void)
2183 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2187 result
= pci_register_driver(&nvme_driver
);
2189 destroy_workqueue(nvme_workq
);
2193 static void __exit
nvme_exit(void)
2195 pci_unregister_driver(&nvme_driver
);
2196 destroy_workqueue(nvme_workq
);
2200 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2201 MODULE_LICENSE("GPL");
2202 MODULE_VERSION("1.0");
2203 module_init(nvme_init
);
2204 module_exit(nvme_exit
);