1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
7 #include <linux/acpi.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/once.h>
21 #include <linux/pci.h>
22 #include <linux/suspend.h>
23 #include <linux/t10-pi.h>
24 #include <linux/types.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <linux/io-64-nonatomic-hi-lo.h>
27 #include <linux/sed-opal.h>
28 #include <linux/pci-p2pdma.h>
33 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
34 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
36 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
42 #define NVME_MAX_KB_SZ 4096
43 #define NVME_MAX_SEGS 127
45 static int use_threaded_interrupts
;
46 module_param(use_threaded_interrupts
, int, 0);
48 static bool use_cmb_sqes
= true;
49 module_param(use_cmb_sqes
, bool, 0444);
50 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
52 static unsigned int max_host_mem_size_mb
= 128;
53 module_param(max_host_mem_size_mb
, uint
, 0444);
54 MODULE_PARM_DESC(max_host_mem_size_mb
,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
57 static unsigned int sgl_threshold
= SZ_32K
;
58 module_param(sgl_threshold
, uint
, 0644);
59 MODULE_PARM_DESC(sgl_threshold
,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
63 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
64 static const struct kernel_param_ops io_queue_depth_ops
= {
65 .set
= io_queue_depth_set
,
66 .get
= param_get_uint
,
69 static unsigned int io_queue_depth
= 1024;
70 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
71 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
73 static int io_queue_count_set(const char *val
, const struct kernel_param
*kp
)
78 ret
= kstrtouint(val
, 10, &n
);
79 if (ret
!= 0 || n
> num_possible_cpus())
81 return param_set_uint(val
, kp
);
84 static const struct kernel_param_ops io_queue_count_ops
= {
85 .set
= io_queue_count_set
,
86 .get
= param_get_uint
,
89 static unsigned int write_queues
;
90 module_param_cb(write_queues
, &io_queue_count_ops
, &write_queues
, 0644);
91 MODULE_PARM_DESC(write_queues
,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
95 static unsigned int poll_queues
;
96 module_param_cb(poll_queues
, &io_queue_count_ops
, &poll_queues
, 0644);
97 MODULE_PARM_DESC(poll_queues
, "Number of queues to use for polled IO.");
100 module_param(noacpi
, bool, 0444);
101 MODULE_PARM_DESC(noacpi
, "disable acpi bios quirks");
106 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
107 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
);
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
113 struct nvme_queue
*queues
;
114 struct blk_mq_tag_set tagset
;
115 struct blk_mq_tag_set admin_tagset
;
118 struct dma_pool
*prp_page_pool
;
119 struct dma_pool
*prp_small_pool
;
120 unsigned online_queues
;
122 unsigned io_queues
[HCTX_MAX_TYPES
];
123 unsigned int num_vecs
;
128 unsigned long bar_mapped_size
;
129 struct work_struct remove_work
;
130 struct mutex shutdown_lock
;
136 struct nvme_ctrl ctrl
;
139 mempool_t
*iod_mempool
;
141 /* shadow doorbell buffer support: */
143 dma_addr_t dbbuf_dbs_dma_addr
;
145 dma_addr_t dbbuf_eis_dma_addr
;
147 /* host memory buffer support: */
149 u32 nr_host_mem_descs
;
150 dma_addr_t host_mem_descs_dma
;
151 struct nvme_host_mem_buf_desc
*host_mem_descs
;
152 void **host_mem_desc_bufs
;
153 unsigned int nr_allocated_queues
;
154 unsigned int nr_write_queues
;
155 unsigned int nr_poll_queues
;
158 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
163 ret
= kstrtou32(val
, 10, &n
);
164 if (ret
!= 0 || n
< 2)
167 return param_set_uint(val
, kp
);
170 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
172 return qid
* 2 * stride
;
175 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
177 return (qid
* 2 + 1) * stride
;
180 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
182 return container_of(ctrl
, struct nvme_dev
, ctrl
);
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
190 struct nvme_dev
*dev
;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp
;
195 struct nvme_completion
*cqes
;
196 dma_addr_t sq_dma_addr
;
197 dma_addr_t cq_dma_addr
;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
216 struct completion delete_done
;
220 * The nvme_iod describes the data in an I/O.
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
226 struct nvme_request req
;
227 struct nvme_command cmd
;
228 struct nvme_queue
*nvmeq
;
231 int npages
; /* In the PRP list. 0 means small pool in use */
232 int nents
; /* Used in scatterlist */
233 dma_addr_t first_dma
;
234 unsigned int dma_len
; /* length of single DMA segment mapping */
236 struct scatterlist
*sg
;
239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev
*dev
)
241 return dev
->nr_allocated_queues
* 8 * dev
->db_stride
;
244 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
246 unsigned int mem_size
= nvme_dbbuf_size(dev
);
251 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
252 &dev
->dbbuf_dbs_dma_addr
,
256 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
257 &dev
->dbbuf_eis_dma_addr
,
259 if (!dev
->dbbuf_eis
) {
260 dma_free_coherent(dev
->dev
, mem_size
,
261 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
262 dev
->dbbuf_dbs
= NULL
;
269 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
271 unsigned int mem_size
= nvme_dbbuf_size(dev
);
273 if (dev
->dbbuf_dbs
) {
274 dma_free_coherent(dev
->dev
, mem_size
,
275 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
276 dev
->dbbuf_dbs
= NULL
;
278 if (dev
->dbbuf_eis
) {
279 dma_free_coherent(dev
->dev
, mem_size
,
280 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
281 dev
->dbbuf_eis
= NULL
;
285 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
286 struct nvme_queue
*nvmeq
, int qid
)
288 if (!dev
->dbbuf_dbs
|| !qid
)
291 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
292 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
293 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
294 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
297 static void nvme_dbbuf_free(struct nvme_queue
*nvmeq
)
302 nvmeq
->dbbuf_sq_db
= NULL
;
303 nvmeq
->dbbuf_cq_db
= NULL
;
304 nvmeq
->dbbuf_sq_ei
= NULL
;
305 nvmeq
->dbbuf_cq_ei
= NULL
;
308 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
310 struct nvme_command c
;
316 memset(&c
, 0, sizeof(c
));
317 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
318 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
319 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
321 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
322 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
323 /* Free memory and continue on */
324 nvme_dbbuf_dma_free(dev
);
326 for (i
= 1; i
<= dev
->online_queues
; i
++)
327 nvme_dbbuf_free(&dev
->queues
[i
]);
331 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
333 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
336 /* Update dbbuf and return true if an MMIO is required */
337 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
338 volatile u32
*dbbuf_ei
)
344 * Ensure that the queue is written before updating
345 * the doorbell in memory
349 old_value
= *dbbuf_db
;
353 * Ensure that the doorbell is updated before reading the event
354 * index from memory. The controller needs to provide similar
355 * ordering to ensure the envent index is updated before reading
360 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
368 * Will slightly overestimate the number of pages needed. This is OK
369 * as it only leads to a small amount of wasted memory for the lifetime of
372 static int nvme_pci_npages_prp(void)
374 unsigned nprps
= DIV_ROUND_UP(NVME_MAX_KB_SZ
+ NVME_CTRL_PAGE_SIZE
,
375 NVME_CTRL_PAGE_SIZE
);
376 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
380 * Calculates the number of pages needed for the SGL segments. For example a 4k
381 * page can accommodate 256 SGL descriptors.
383 static int nvme_pci_npages_sgl(void)
385 return DIV_ROUND_UP(NVME_MAX_SEGS
* sizeof(struct nvme_sgl_desc
),
389 static size_t nvme_pci_iod_alloc_size(void)
391 size_t npages
= max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
393 return sizeof(__le64
*) * npages
+
394 sizeof(struct scatterlist
) * NVME_MAX_SEGS
;
397 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
398 unsigned int hctx_idx
)
400 struct nvme_dev
*dev
= data
;
401 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
403 WARN_ON(hctx_idx
!= 0);
404 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
406 hctx
->driver_data
= nvmeq
;
410 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
411 unsigned int hctx_idx
)
413 struct nvme_dev
*dev
= data
;
414 struct nvme_queue
*nvmeq
= &dev
->queues
[hctx_idx
+ 1];
416 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
417 hctx
->driver_data
= nvmeq
;
421 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
422 unsigned int hctx_idx
, unsigned int numa_node
)
424 struct nvme_dev
*dev
= set
->driver_data
;
425 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
426 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
427 struct nvme_queue
*nvmeq
= &dev
->queues
[queue_idx
];
432 nvme_req(req
)->ctrl
= &dev
->ctrl
;
436 static int queue_irq_offset(struct nvme_dev
*dev
)
438 /* if we have more than 1 vec, admin queue offsets us by 1 */
439 if (dev
->num_vecs
> 1)
445 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
447 struct nvme_dev
*dev
= set
->driver_data
;
450 offset
= queue_irq_offset(dev
);
451 for (i
= 0, qoff
= 0; i
< set
->nr_maps
; i
++) {
452 struct blk_mq_queue_map
*map
= &set
->map
[i
];
454 map
->nr_queues
= dev
->io_queues
[i
];
455 if (!map
->nr_queues
) {
456 BUG_ON(i
== HCTX_TYPE_DEFAULT
);
461 * The poll queue(s) doesn't have an IRQ (and hence IRQ
462 * affinity), so use the regular blk-mq cpu mapping
464 map
->queue_offset
= qoff
;
465 if (i
!= HCTX_TYPE_POLL
&& offset
)
466 blk_mq_pci_map_queues(map
, to_pci_dev(dev
->dev
), offset
);
468 blk_mq_map_queues(map
);
469 qoff
+= map
->nr_queues
;
470 offset
+= map
->nr_queues
;
477 * Write sq tail if we are asked to, or if the next command would wrap.
479 static inline void nvme_write_sq_db(struct nvme_queue
*nvmeq
, bool write_sq
)
482 u16 next_tail
= nvmeq
->sq_tail
+ 1;
484 if (next_tail
== nvmeq
->q_depth
)
486 if (next_tail
!= nvmeq
->last_sq_tail
)
490 if (nvme_dbbuf_update_and_check_event(nvmeq
->sq_tail
,
491 nvmeq
->dbbuf_sq_db
, nvmeq
->dbbuf_sq_ei
))
492 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
493 nvmeq
->last_sq_tail
= nvmeq
->sq_tail
;
497 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
498 * @nvmeq: The queue to use
499 * @cmd: The command to send
500 * @write_sq: whether to write to the SQ doorbell
502 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
,
505 spin_lock(&nvmeq
->sq_lock
);
506 memcpy(nvmeq
->sq_cmds
+ (nvmeq
->sq_tail
<< nvmeq
->sqes
),
508 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
510 nvme_write_sq_db(nvmeq
, write_sq
);
511 spin_unlock(&nvmeq
->sq_lock
);
514 static void nvme_commit_rqs(struct blk_mq_hw_ctx
*hctx
)
516 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
518 spin_lock(&nvmeq
->sq_lock
);
519 if (nvmeq
->sq_tail
!= nvmeq
->last_sq_tail
)
520 nvme_write_sq_db(nvmeq
, true);
521 spin_unlock(&nvmeq
->sq_lock
);
524 static void **nvme_pci_iod_list(struct request
*req
)
526 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
527 return (void **)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
530 static inline bool nvme_pci_use_sgls(struct nvme_dev
*dev
, struct request
*req
)
532 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
533 int nseg
= blk_rq_nr_phys_segments(req
);
534 unsigned int avg_seg_size
;
536 avg_seg_size
= DIV_ROUND_UP(blk_rq_payload_bytes(req
), nseg
);
538 if (!(dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))))
540 if (!iod
->nvmeq
->qid
)
542 if (!sgl_threshold
|| avg_seg_size
< sgl_threshold
)
547 static void nvme_free_prps(struct nvme_dev
*dev
, struct request
*req
)
549 const int last_prp
= NVME_CTRL_PAGE_SIZE
/ sizeof(__le64
) - 1;
550 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
551 dma_addr_t dma_addr
= iod
->first_dma
;
554 for (i
= 0; i
< iod
->npages
; i
++) {
555 __le64
*prp_list
= nvme_pci_iod_list(req
)[i
];
556 dma_addr_t next_dma_addr
= le64_to_cpu(prp_list
[last_prp
]);
558 dma_pool_free(dev
->prp_page_pool
, prp_list
, dma_addr
);
559 dma_addr
= next_dma_addr
;
564 static void nvme_free_sgls(struct nvme_dev
*dev
, struct request
*req
)
566 const int last_sg
= SGES_PER_PAGE
- 1;
567 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
568 dma_addr_t dma_addr
= iod
->first_dma
;
571 for (i
= 0; i
< iod
->npages
; i
++) {
572 struct nvme_sgl_desc
*sg_list
= nvme_pci_iod_list(req
)[i
];
573 dma_addr_t next_dma_addr
= le64_to_cpu((sg_list
[last_sg
]).addr
);
575 dma_pool_free(dev
->prp_page_pool
, sg_list
, dma_addr
);
576 dma_addr
= next_dma_addr
;
581 static void nvme_unmap_sg(struct nvme_dev
*dev
, struct request
*req
)
583 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
585 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
586 pci_p2pdma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
,
589 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, rq_dma_dir(req
));
592 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
594 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
597 dma_unmap_page(dev
->dev
, iod
->first_dma
, iod
->dma_len
,
602 WARN_ON_ONCE(!iod
->nents
);
604 nvme_unmap_sg(dev
, req
);
605 if (iod
->npages
== 0)
606 dma_pool_free(dev
->prp_small_pool
, nvme_pci_iod_list(req
)[0],
608 else if (iod
->use_sgl
)
609 nvme_free_sgls(dev
, req
);
611 nvme_free_prps(dev
, req
);
612 mempool_free(iod
->sg
, dev
->iod_mempool
);
615 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
618 struct scatterlist
*sg
;
620 for_each_sg(sgl
, sg
, nents
, i
) {
621 dma_addr_t phys
= sg_phys(sg
);
622 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
623 "dma_address:%pad dma_length:%d\n",
624 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
629 static blk_status_t
nvme_pci_setup_prps(struct nvme_dev
*dev
,
630 struct request
*req
, struct nvme_rw_command
*cmnd
)
632 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
633 struct dma_pool
*pool
;
634 int length
= blk_rq_payload_bytes(req
);
635 struct scatterlist
*sg
= iod
->sg
;
636 int dma_len
= sg_dma_len(sg
);
637 u64 dma_addr
= sg_dma_address(sg
);
638 int offset
= dma_addr
& (NVME_CTRL_PAGE_SIZE
- 1);
640 void **list
= nvme_pci_iod_list(req
);
644 length
-= (NVME_CTRL_PAGE_SIZE
- offset
);
650 dma_len
-= (NVME_CTRL_PAGE_SIZE
- offset
);
652 dma_addr
+= (NVME_CTRL_PAGE_SIZE
- offset
);
655 dma_addr
= sg_dma_address(sg
);
656 dma_len
= sg_dma_len(sg
);
659 if (length
<= NVME_CTRL_PAGE_SIZE
) {
660 iod
->first_dma
= dma_addr
;
664 nprps
= DIV_ROUND_UP(length
, NVME_CTRL_PAGE_SIZE
);
665 if (nprps
<= (256 / 8)) {
666 pool
= dev
->prp_small_pool
;
669 pool
= dev
->prp_page_pool
;
673 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
675 iod
->first_dma
= dma_addr
;
677 return BLK_STS_RESOURCE
;
680 iod
->first_dma
= prp_dma
;
683 if (i
== NVME_CTRL_PAGE_SIZE
>> 3) {
684 __le64
*old_prp_list
= prp_list
;
685 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
688 list
[iod
->npages
++] = prp_list
;
689 prp_list
[0] = old_prp_list
[i
- 1];
690 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
693 prp_list
[i
++] = cpu_to_le64(dma_addr
);
694 dma_len
-= NVME_CTRL_PAGE_SIZE
;
695 dma_addr
+= NVME_CTRL_PAGE_SIZE
;
696 length
-= NVME_CTRL_PAGE_SIZE
;
701 if (unlikely(dma_len
< 0))
704 dma_addr
= sg_dma_address(sg
);
705 dma_len
= sg_dma_len(sg
);
708 cmnd
->dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
709 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
712 nvme_free_prps(dev
, req
);
713 return BLK_STS_RESOURCE
;
715 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
716 "Invalid SGL for payload:%d nents:%d\n",
717 blk_rq_payload_bytes(req
), iod
->nents
);
718 return BLK_STS_IOERR
;
721 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc
*sge
,
722 struct scatterlist
*sg
)
724 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
725 sge
->length
= cpu_to_le32(sg_dma_len(sg
));
726 sge
->type
= NVME_SGL_FMT_DATA_DESC
<< 4;
729 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc
*sge
,
730 dma_addr_t dma_addr
, int entries
)
732 sge
->addr
= cpu_to_le64(dma_addr
);
733 if (entries
< SGES_PER_PAGE
) {
734 sge
->length
= cpu_to_le32(entries
* sizeof(*sge
));
735 sge
->type
= NVME_SGL_FMT_LAST_SEG_DESC
<< 4;
737 sge
->length
= cpu_to_le32(PAGE_SIZE
);
738 sge
->type
= NVME_SGL_FMT_SEG_DESC
<< 4;
742 static blk_status_t
nvme_pci_setup_sgls(struct nvme_dev
*dev
,
743 struct request
*req
, struct nvme_rw_command
*cmd
, int entries
)
745 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
746 struct dma_pool
*pool
;
747 struct nvme_sgl_desc
*sg_list
;
748 struct scatterlist
*sg
= iod
->sg
;
752 /* setting the transfer type as SGL */
753 cmd
->flags
= NVME_CMD_SGL_METABUF
;
756 nvme_pci_sgl_set_data(&cmd
->dptr
.sgl
, sg
);
760 if (entries
<= (256 / sizeof(struct nvme_sgl_desc
))) {
761 pool
= dev
->prp_small_pool
;
764 pool
= dev
->prp_page_pool
;
768 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
771 return BLK_STS_RESOURCE
;
774 nvme_pci_iod_list(req
)[0] = sg_list
;
775 iod
->first_dma
= sgl_dma
;
777 nvme_pci_sgl_set_seg(&cmd
->dptr
.sgl
, sgl_dma
, entries
);
780 if (i
== SGES_PER_PAGE
) {
781 struct nvme_sgl_desc
*old_sg_desc
= sg_list
;
782 struct nvme_sgl_desc
*link
= &old_sg_desc
[i
- 1];
784 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
789 nvme_pci_iod_list(req
)[iod
->npages
++] = sg_list
;
790 sg_list
[i
++] = *link
;
791 nvme_pci_sgl_set_seg(link
, sgl_dma
, entries
);
794 nvme_pci_sgl_set_data(&sg_list
[i
++], sg
);
796 } while (--entries
> 0);
800 nvme_free_sgls(dev
, req
);
801 return BLK_STS_RESOURCE
;
804 static blk_status_t
nvme_setup_prp_simple(struct nvme_dev
*dev
,
805 struct request
*req
, struct nvme_rw_command
*cmnd
,
808 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
809 unsigned int offset
= bv
->bv_offset
& (NVME_CTRL_PAGE_SIZE
- 1);
810 unsigned int first_prp_len
= NVME_CTRL_PAGE_SIZE
- offset
;
812 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
813 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
814 return BLK_STS_RESOURCE
;
815 iod
->dma_len
= bv
->bv_len
;
817 cmnd
->dptr
.prp1
= cpu_to_le64(iod
->first_dma
);
818 if (bv
->bv_len
> first_prp_len
)
819 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
+ first_prp_len
);
823 static blk_status_t
nvme_setup_sgl_simple(struct nvme_dev
*dev
,
824 struct request
*req
, struct nvme_rw_command
*cmnd
,
827 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
829 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
830 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
831 return BLK_STS_RESOURCE
;
832 iod
->dma_len
= bv
->bv_len
;
834 cmnd
->flags
= NVME_CMD_SGL_METABUF
;
835 cmnd
->dptr
.sgl
.addr
= cpu_to_le64(iod
->first_dma
);
836 cmnd
->dptr
.sgl
.length
= cpu_to_le32(iod
->dma_len
);
837 cmnd
->dptr
.sgl
.type
= NVME_SGL_FMT_DATA_DESC
<< 4;
841 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
842 struct nvme_command
*cmnd
)
844 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
845 blk_status_t ret
= BLK_STS_RESOURCE
;
848 if (blk_rq_nr_phys_segments(req
) == 1) {
849 struct bio_vec bv
= req_bvec(req
);
851 if (!is_pci_p2pdma_page(bv
.bv_page
)) {
852 if (bv
.bv_offset
+ bv
.bv_len
<= NVME_CTRL_PAGE_SIZE
* 2)
853 return nvme_setup_prp_simple(dev
, req
,
856 if (iod
->nvmeq
->qid
&&
857 dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1)))
858 return nvme_setup_sgl_simple(dev
, req
,
864 iod
->sg
= mempool_alloc(dev
->iod_mempool
, GFP_ATOMIC
);
866 return BLK_STS_RESOURCE
;
867 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
868 iod
->nents
= blk_rq_map_sg(req
->q
, req
, iod
->sg
);
872 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
873 nr_mapped
= pci_p2pdma_map_sg_attrs(dev
->dev
, iod
->sg
,
874 iod
->nents
, rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
876 nr_mapped
= dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
,
877 rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
881 iod
->use_sgl
= nvme_pci_use_sgls(dev
, req
);
883 ret
= nvme_pci_setup_sgls(dev
, req
, &cmnd
->rw
, nr_mapped
);
885 ret
= nvme_pci_setup_prps(dev
, req
, &cmnd
->rw
);
886 if (ret
!= BLK_STS_OK
)
891 nvme_unmap_sg(dev
, req
);
893 mempool_free(iod
->sg
, dev
->iod_mempool
);
897 static blk_status_t
nvme_map_metadata(struct nvme_dev
*dev
, struct request
*req
,
898 struct nvme_command
*cmnd
)
900 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
902 iod
->meta_dma
= dma_map_bvec(dev
->dev
, rq_integrity_vec(req
),
904 if (dma_mapping_error(dev
->dev
, iod
->meta_dma
))
905 return BLK_STS_IOERR
;
906 cmnd
->rw
.metadata
= cpu_to_le64(iod
->meta_dma
);
911 * NOTE: ns is NULL when called on the admin queue.
913 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
914 const struct blk_mq_queue_data
*bd
)
916 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
917 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
918 struct nvme_dev
*dev
= nvmeq
->dev
;
919 struct request
*req
= bd
->rq
;
920 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
921 struct nvme_command
*cmnd
= &iod
->cmd
;
929 * We should not need to do this, but we're still using this to
930 * ensure we can drain requests on a dying queue.
932 if (unlikely(!test_bit(NVMEQ_ENABLED
, &nvmeq
->flags
)))
933 return BLK_STS_IOERR
;
935 ret
= nvme_setup_cmd(ns
, req
, cmnd
);
939 if (blk_rq_nr_phys_segments(req
)) {
940 ret
= nvme_map_data(dev
, req
, cmnd
);
945 if (blk_integrity_rq(req
)) {
946 ret
= nvme_map_metadata(dev
, req
, cmnd
);
951 blk_mq_start_request(req
);
952 nvme_submit_cmd(nvmeq
, cmnd
, bd
->last
);
955 nvme_unmap_data(dev
, req
);
957 nvme_cleanup_cmd(req
);
961 static void nvme_pci_complete_rq(struct request
*req
)
963 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
964 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
966 if (blk_integrity_rq(req
))
967 dma_unmap_page(dev
->dev
, iod
->meta_dma
,
968 rq_integrity_vec(req
)->bv_len
, rq_data_dir(req
));
969 if (blk_rq_nr_phys_segments(req
))
970 nvme_unmap_data(dev
, req
);
971 nvme_complete_rq(req
);
974 /* We read the CQE phase first to check if the rest of the entry is valid */
975 static inline bool nvme_cqe_pending(struct nvme_queue
*nvmeq
)
977 struct nvme_completion
*hcqe
= &nvmeq
->cqes
[nvmeq
->cq_head
];
979 return (le16_to_cpu(READ_ONCE(hcqe
->status
)) & 1) == nvmeq
->cq_phase
;
982 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
984 u16 head
= nvmeq
->cq_head
;
986 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
988 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
991 static inline struct blk_mq_tags
*nvme_queue_tagset(struct nvme_queue
*nvmeq
)
994 return nvmeq
->dev
->admin_tagset
.tags
[0];
995 return nvmeq
->dev
->tagset
.tags
[nvmeq
->qid
- 1];
998 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
, u16 idx
)
1000 struct nvme_completion
*cqe
= &nvmeq
->cqes
[idx
];
1001 __u16 command_id
= READ_ONCE(cqe
->command_id
);
1002 struct request
*req
;
1005 * AEN requests are special as they don't time out and can
1006 * survive any kind of queue freeze and often don't respond to
1007 * aborts. We don't even bother to allocate a struct request
1008 * for them but rather special case them here.
1010 if (unlikely(nvme_is_aen_req(nvmeq
->qid
, command_id
))) {
1011 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
1012 cqe
->status
, &cqe
->result
);
1016 req
= blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq
), command_id
);
1017 if (unlikely(!req
)) {
1018 dev_warn(nvmeq
->dev
->ctrl
.device
,
1019 "invalid id %d completed on queue %d\n",
1020 command_id
, le16_to_cpu(cqe
->sq_id
));
1024 trace_nvme_sq(req
, cqe
->sq_head
, nvmeq
->sq_tail
);
1025 if (!nvme_try_complete_req(req
, cqe
->status
, cqe
->result
))
1026 nvme_pci_complete_rq(req
);
1029 static inline void nvme_update_cq_head(struct nvme_queue
*nvmeq
)
1031 u16 tmp
= nvmeq
->cq_head
+ 1;
1033 if (tmp
== nvmeq
->q_depth
) {
1035 nvmeq
->cq_phase
^= 1;
1037 nvmeq
->cq_head
= tmp
;
1041 static inline int nvme_process_cq(struct nvme_queue
*nvmeq
)
1045 while (nvme_cqe_pending(nvmeq
)) {
1048 * load-load control dependency between phase and the rest of
1049 * the cqe requires a full read memory barrier
1052 nvme_handle_cqe(nvmeq
, nvmeq
->cq_head
);
1053 nvme_update_cq_head(nvmeq
);
1057 nvme_ring_cq_doorbell(nvmeq
);
1061 static irqreturn_t
nvme_irq(int irq
, void *data
)
1063 struct nvme_queue
*nvmeq
= data
;
1065 if (nvme_process_cq(nvmeq
))
1070 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
1072 struct nvme_queue
*nvmeq
= data
;
1074 if (nvme_cqe_pending(nvmeq
))
1075 return IRQ_WAKE_THREAD
;
1080 * Poll for completions for any interrupt driven queue
1081 * Can be called from any context.
1083 static void nvme_poll_irqdisable(struct nvme_queue
*nvmeq
)
1085 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1087 WARN_ON_ONCE(test_bit(NVMEQ_POLLED
, &nvmeq
->flags
));
1089 disable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1090 nvme_process_cq(nvmeq
);
1091 enable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1094 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
)
1096 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
1099 if (!nvme_cqe_pending(nvmeq
))
1102 spin_lock(&nvmeq
->cq_poll_lock
);
1103 found
= nvme_process_cq(nvmeq
);
1104 spin_unlock(&nvmeq
->cq_poll_lock
);
1109 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
)
1111 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1112 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1113 struct nvme_command c
;
1115 memset(&c
, 0, sizeof(c
));
1116 c
.common
.opcode
= nvme_admin_async_event
;
1117 c
.common
.command_id
= NVME_AQ_BLK_MQ_DEPTH
;
1118 nvme_submit_cmd(nvmeq
, &c
, true);
1121 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1123 struct nvme_command c
;
1125 memset(&c
, 0, sizeof(c
));
1126 c
.delete_queue
.opcode
= opcode
;
1127 c
.delete_queue
.qid
= cpu_to_le16(id
);
1129 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1132 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1133 struct nvme_queue
*nvmeq
, s16 vector
)
1135 struct nvme_command c
;
1136 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1138 if (!test_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1139 flags
|= NVME_CQ_IRQ_ENABLED
;
1142 * Note: we (ab)use the fact that the prp fields survive if no data
1143 * is attached to the request.
1145 memset(&c
, 0, sizeof(c
));
1146 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1147 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1148 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1149 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1150 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1151 c
.create_cq
.irq_vector
= cpu_to_le16(vector
);
1153 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1156 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1157 struct nvme_queue
*nvmeq
)
1159 struct nvme_ctrl
*ctrl
= &dev
->ctrl
;
1160 struct nvme_command c
;
1161 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1164 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1165 * set. Since URGENT priority is zeroes, it makes all queues
1168 if (ctrl
->quirks
& NVME_QUIRK_MEDIUM_PRIO_SQ
)
1169 flags
|= NVME_SQ_PRIO_MEDIUM
;
1172 * Note: we (ab)use the fact that the prp fields survive if no data
1173 * is attached to the request.
1175 memset(&c
, 0, sizeof(c
));
1176 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1177 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1178 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1179 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1180 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1181 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1183 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1186 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1188 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1191 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1193 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1196 static void abort_endio(struct request
*req
, blk_status_t error
)
1198 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1199 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1201 dev_warn(nvmeq
->dev
->ctrl
.device
,
1202 "Abort status: 0x%x", nvme_req(req
)->status
);
1203 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
1204 blk_mq_free_request(req
);
1207 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1209 /* If true, indicates loss of adapter communication, possibly by a
1210 * NVMe Subsystem reset.
1212 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1214 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1215 switch (dev
->ctrl
.state
) {
1216 case NVME_CTRL_RESETTING
:
1217 case NVME_CTRL_CONNECTING
:
1223 /* We shouldn't reset unless the controller is on fatal error state
1224 * _or_ if we lost the communication with it.
1226 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1232 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1234 /* Read a config register to help see what died. */
1238 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1240 if (result
== PCIBIOS_SUCCESSFUL
)
1241 dev_warn(dev
->ctrl
.device
,
1242 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1245 dev_warn(dev
->ctrl
.device
,
1246 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1250 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1252 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1253 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1254 struct nvme_dev
*dev
= nvmeq
->dev
;
1255 struct request
*abort_req
;
1256 struct nvme_command cmd
;
1257 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1259 /* If PCI error recovery process is happening, we cannot reset or
1260 * the recovery mechanism will surely fail.
1263 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1264 return BLK_EH_RESET_TIMER
;
1267 * Reset immediately if the controller is failed
1269 if (nvme_should_reset(dev
, csts
)) {
1270 nvme_warn_reset(dev
, csts
);
1271 nvme_dev_disable(dev
, false);
1272 nvme_reset_ctrl(&dev
->ctrl
);
1277 * Did we miss an interrupt?
1279 if (test_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1280 nvme_poll(req
->mq_hctx
);
1282 nvme_poll_irqdisable(nvmeq
);
1284 if (blk_mq_request_completed(req
)) {
1285 dev_warn(dev
->ctrl
.device
,
1286 "I/O %d QID %d timeout, completion polled\n",
1287 req
->tag
, nvmeq
->qid
);
1292 * Shutdown immediately if controller times out while starting. The
1293 * reset work will see the pci device disabled when it gets the forced
1294 * cancellation error. All outstanding requests are completed on
1295 * shutdown, so we return BLK_EH_DONE.
1297 switch (dev
->ctrl
.state
) {
1298 case NVME_CTRL_CONNECTING
:
1299 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
1301 case NVME_CTRL_DELETING
:
1302 dev_warn_ratelimited(dev
->ctrl
.device
,
1303 "I/O %d QID %d timeout, disable controller\n",
1304 req
->tag
, nvmeq
->qid
);
1305 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1306 nvme_dev_disable(dev
, true);
1308 case NVME_CTRL_RESETTING
:
1309 return BLK_EH_RESET_TIMER
;
1315 * Shutdown the controller immediately and schedule a reset if the
1316 * command was already aborted once before and still hasn't been
1317 * returned to the driver, or if this is the admin queue.
1319 if (!nvmeq
->qid
|| iod
->aborted
) {
1320 dev_warn(dev
->ctrl
.device
,
1321 "I/O %d QID %d timeout, reset controller\n",
1322 req
->tag
, nvmeq
->qid
);
1323 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1324 nvme_dev_disable(dev
, false);
1325 nvme_reset_ctrl(&dev
->ctrl
);
1330 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1331 atomic_inc(&dev
->ctrl
.abort_limit
);
1332 return BLK_EH_RESET_TIMER
;
1336 memset(&cmd
, 0, sizeof(cmd
));
1337 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1338 cmd
.abort
.cid
= req
->tag
;
1339 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1341 dev_warn(nvmeq
->dev
->ctrl
.device
,
1342 "I/O %d QID %d timeout, aborting\n",
1343 req
->tag
, nvmeq
->qid
);
1345 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1347 if (IS_ERR(abort_req
)) {
1348 atomic_inc(&dev
->ctrl
.abort_limit
);
1349 return BLK_EH_RESET_TIMER
;
1352 abort_req
->end_io_data
= NULL
;
1353 blk_execute_rq_nowait(NULL
, abort_req
, 0, abort_endio
);
1356 * The aborted req will be completed on receiving the abort req.
1357 * We enable the timer again. If hit twice, it'll cause a device reset,
1358 * as the device then is in a faulty state.
1360 return BLK_EH_RESET_TIMER
;
1363 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1365 dma_free_coherent(nvmeq
->dev
->dev
, CQ_SIZE(nvmeq
),
1366 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1367 if (!nvmeq
->sq_cmds
)
1370 if (test_and_clear_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
)) {
1371 pci_free_p2pmem(to_pci_dev(nvmeq
->dev
->dev
),
1372 nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1374 dma_free_coherent(nvmeq
->dev
->dev
, SQ_SIZE(nvmeq
),
1375 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1379 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1383 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1384 dev
->ctrl
.queue_count
--;
1385 nvme_free_queue(&dev
->queues
[i
]);
1390 * nvme_suspend_queue - put queue into suspended state
1391 * @nvmeq: queue to suspend
1393 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1395 if (!test_and_clear_bit(NVMEQ_ENABLED
, &nvmeq
->flags
))
1398 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1401 nvmeq
->dev
->online_queues
--;
1402 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1403 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1404 if (!test_and_clear_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1405 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), nvmeq
->cq_vector
, nvmeq
);
1409 static void nvme_suspend_io_queues(struct nvme_dev
*dev
)
1413 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
1414 nvme_suspend_queue(&dev
->queues
[i
]);
1417 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1419 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1422 nvme_shutdown_ctrl(&dev
->ctrl
);
1424 nvme_disable_ctrl(&dev
->ctrl
);
1426 nvme_poll_irqdisable(nvmeq
);
1430 * Called only on a device that has been disabled and after all other threads
1431 * that can check this device's completion queues have synced, except
1432 * nvme_poll(). This is the last chance for the driver to see a natural
1433 * completion before nvme_cancel_request() terminates all incomplete requests.
1435 static void nvme_reap_pending_cqes(struct nvme_dev
*dev
)
1439 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--) {
1440 spin_lock(&dev
->queues
[i
].cq_poll_lock
);
1441 nvme_process_cq(&dev
->queues
[i
]);
1442 spin_unlock(&dev
->queues
[i
].cq_poll_lock
);
1446 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1449 int q_depth
= dev
->q_depth
;
1450 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1451 NVME_CTRL_PAGE_SIZE
);
1453 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1454 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1456 mem_per_q
= round_down(mem_per_q
, NVME_CTRL_PAGE_SIZE
);
1457 q_depth
= div_u64(mem_per_q
, entry_size
);
1460 * Ensure the reduced q_depth is above some threshold where it
1461 * would be better to map queues in system memory with the
1471 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1474 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1476 if (qid
&& dev
->cmb_use_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
)) {
1477 nvmeq
->sq_cmds
= pci_alloc_p2pmem(pdev
, SQ_SIZE(nvmeq
));
1478 if (nvmeq
->sq_cmds
) {
1479 nvmeq
->sq_dma_addr
= pci_p2pmem_virt_to_bus(pdev
,
1481 if (nvmeq
->sq_dma_addr
) {
1482 set_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
);
1486 pci_free_p2pmem(pdev
, nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1490 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(nvmeq
),
1491 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1492 if (!nvmeq
->sq_cmds
)
1497 static int nvme_alloc_queue(struct nvme_dev
*dev
, int qid
, int depth
)
1499 struct nvme_queue
*nvmeq
= &dev
->queues
[qid
];
1501 if (dev
->ctrl
.queue_count
> qid
)
1504 nvmeq
->sqes
= qid
? dev
->io_sqes
: NVME_ADM_SQES
;
1505 nvmeq
->q_depth
= depth
;
1506 nvmeq
->cqes
= dma_alloc_coherent(dev
->dev
, CQ_SIZE(nvmeq
),
1507 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1511 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
))
1515 spin_lock_init(&nvmeq
->sq_lock
);
1516 spin_lock_init(&nvmeq
->cq_poll_lock
);
1518 nvmeq
->cq_phase
= 1;
1519 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1521 dev
->ctrl
.queue_count
++;
1526 dma_free_coherent(dev
->dev
, CQ_SIZE(nvmeq
), (void *)nvmeq
->cqes
,
1527 nvmeq
->cq_dma_addr
);
1532 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1534 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1535 int nr
= nvmeq
->dev
->ctrl
.instance
;
1537 if (use_threaded_interrupts
) {
1538 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1539 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1541 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1542 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1546 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1548 struct nvme_dev
*dev
= nvmeq
->dev
;
1551 nvmeq
->last_sq_tail
= 0;
1553 nvmeq
->cq_phase
= 1;
1554 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1555 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
));
1556 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1557 dev
->online_queues
++;
1558 wmb(); /* ensure the first interrupt sees the initialization */
1561 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
, bool polled
)
1563 struct nvme_dev
*dev
= nvmeq
->dev
;
1567 clear_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
1570 * A queue's vector matches the queue identifier unless the controller
1571 * has only one vector available.
1574 vector
= dev
->num_vecs
== 1 ? 0 : qid
;
1576 set_bit(NVMEQ_POLLED
, &nvmeq
->flags
);
1578 result
= adapter_alloc_cq(dev
, qid
, nvmeq
, vector
);
1582 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1588 nvmeq
->cq_vector
= vector
;
1589 nvme_init_queue(nvmeq
, qid
);
1592 result
= queue_request_irq(nvmeq
);
1597 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1601 dev
->online_queues
--;
1602 adapter_delete_sq(dev
, qid
);
1604 adapter_delete_cq(dev
, qid
);
1608 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1609 .queue_rq
= nvme_queue_rq
,
1610 .complete
= nvme_pci_complete_rq
,
1611 .init_hctx
= nvme_admin_init_hctx
,
1612 .init_request
= nvme_init_request
,
1613 .timeout
= nvme_timeout
,
1616 static const struct blk_mq_ops nvme_mq_ops
= {
1617 .queue_rq
= nvme_queue_rq
,
1618 .complete
= nvme_pci_complete_rq
,
1619 .commit_rqs
= nvme_commit_rqs
,
1620 .init_hctx
= nvme_init_hctx
,
1621 .init_request
= nvme_init_request
,
1622 .map_queues
= nvme_pci_map_queues
,
1623 .timeout
= nvme_timeout
,
1627 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1629 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1631 * If the controller was reset during removal, it's possible
1632 * user requests may be waiting on a stopped queue. Start the
1633 * queue to flush these to completion.
1635 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1636 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1637 blk_mq_free_tag_set(&dev
->admin_tagset
);
1641 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1643 if (!dev
->ctrl
.admin_q
) {
1644 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1645 dev
->admin_tagset
.nr_hw_queues
= 1;
1647 dev
->admin_tagset
.queue_depth
= NVME_AQ_MQ_TAG_DEPTH
;
1648 dev
->admin_tagset
.timeout
= NVME_ADMIN_TIMEOUT
;
1649 dev
->admin_tagset
.numa_node
= dev
->ctrl
.numa_node
;
1650 dev
->admin_tagset
.cmd_size
= sizeof(struct nvme_iod
);
1651 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1652 dev
->admin_tagset
.driver_data
= dev
;
1654 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1656 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1658 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1659 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1660 blk_mq_free_tag_set(&dev
->admin_tagset
);
1663 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1664 nvme_dev_remove_admin(dev
);
1665 dev
->ctrl
.admin_q
= NULL
;
1669 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1674 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1676 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1679 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1681 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1683 if (size
<= dev
->bar_mapped_size
)
1685 if (size
> pci_resource_len(pdev
, 0))
1689 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1691 dev
->bar_mapped_size
= 0;
1694 dev
->bar_mapped_size
= size
;
1695 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1700 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1704 struct nvme_queue
*nvmeq
;
1706 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1710 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1711 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1713 if (dev
->subsystem
&&
1714 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1715 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1717 result
= nvme_disable_ctrl(&dev
->ctrl
);
1721 result
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1725 dev
->ctrl
.numa_node
= dev_to_node(dev
->dev
);
1727 nvmeq
= &dev
->queues
[0];
1728 aqa
= nvmeq
->q_depth
- 1;
1731 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1732 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1733 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1735 result
= nvme_enable_ctrl(&dev
->ctrl
);
1739 nvmeq
->cq_vector
= 0;
1740 nvme_init_queue(nvmeq
, 0);
1741 result
= queue_request_irq(nvmeq
);
1743 dev
->online_queues
--;
1747 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1751 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1753 unsigned i
, max
, rw_queues
;
1756 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1757 if (nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1763 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1764 if (max
!= 1 && dev
->io_queues
[HCTX_TYPE_POLL
]) {
1765 rw_queues
= dev
->io_queues
[HCTX_TYPE_DEFAULT
] +
1766 dev
->io_queues
[HCTX_TYPE_READ
];
1771 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1772 bool polled
= i
> rw_queues
;
1774 ret
= nvme_create_queue(&dev
->queues
[i
], i
, polled
);
1780 * Ignore failing Create SQ/CQ commands, we can continue with less
1781 * than the desired amount of queues, and even a controller without
1782 * I/O queues can still be used to issue admin commands. This might
1783 * be useful to upgrade a buggy firmware for example.
1785 return ret
>= 0 ? 0 : ret
;
1788 static ssize_t
nvme_cmb_show(struct device
*dev
,
1789 struct device_attribute
*attr
,
1792 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1794 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1795 ndev
->cmbloc
, ndev
->cmbsz
);
1797 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1799 static u64
nvme_cmb_size_unit(struct nvme_dev
*dev
)
1801 u8 szu
= (dev
->cmbsz
>> NVME_CMBSZ_SZU_SHIFT
) & NVME_CMBSZ_SZU_MASK
;
1803 return 1ULL << (12 + 4 * szu
);
1806 static u32
nvme_cmb_size(struct nvme_dev
*dev
)
1808 return (dev
->cmbsz
>> NVME_CMBSZ_SZ_SHIFT
) & NVME_CMBSZ_SZ_MASK
;
1811 static void nvme_map_cmb(struct nvme_dev
*dev
)
1814 resource_size_t bar_size
;
1815 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1821 if (NVME_CAP_CMBS(dev
->ctrl
.cap
))
1822 writel(NVME_CMBMSC_CRE
, dev
->bar
+ NVME_REG_CMBMSC
);
1824 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1827 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1829 size
= nvme_cmb_size_unit(dev
) * nvme_cmb_size(dev
);
1830 offset
= nvme_cmb_size_unit(dev
) * NVME_CMB_OFST(dev
->cmbloc
);
1831 bar
= NVME_CMB_BIR(dev
->cmbloc
);
1832 bar_size
= pci_resource_len(pdev
, bar
);
1834 if (offset
> bar_size
)
1838 * Tell the controller about the host side address mapping the CMB,
1839 * and enable CMB decoding for the NVMe 1.4+ scheme:
1841 if (NVME_CAP_CMBS(dev
->ctrl
.cap
)) {
1842 hi_lo_writeq(NVME_CMBMSC_CRE
| NVME_CMBMSC_CMSE
|
1843 (pci_bus_address(pdev
, bar
) + offset
),
1844 dev
->bar
+ NVME_REG_CMBMSC
);
1848 * Controllers may support a CMB size larger than their BAR,
1849 * for example, due to being behind a bridge. Reduce the CMB to
1850 * the reported size of the BAR
1852 if (size
> bar_size
- offset
)
1853 size
= bar_size
- offset
;
1855 if (pci_p2pdma_add_resource(pdev
, bar
, size
, offset
)) {
1856 dev_warn(dev
->ctrl
.device
,
1857 "failed to register the CMB\n");
1861 dev
->cmb_size
= size
;
1862 dev
->cmb_use_sqes
= use_cmb_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
);
1864 if ((dev
->cmbsz
& (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
)) ==
1865 (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
))
1866 pci_p2pmem_publish(pdev
, true);
1868 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1869 &dev_attr_cmb
.attr
, NULL
))
1870 dev_warn(dev
->ctrl
.device
,
1871 "failed to add sysfs attribute for CMB\n");
1874 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1876 if (dev
->cmb_size
) {
1877 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1878 &dev_attr_cmb
.attr
, NULL
);
1883 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1885 u32 host_mem_size
= dev
->host_mem_size
>> NVME_CTRL_PAGE_SHIFT
;
1886 u64 dma_addr
= dev
->host_mem_descs_dma
;
1887 struct nvme_command c
;
1890 memset(&c
, 0, sizeof(c
));
1891 c
.features
.opcode
= nvme_admin_set_features
;
1892 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1893 c
.features
.dword11
= cpu_to_le32(bits
);
1894 c
.features
.dword12
= cpu_to_le32(host_mem_size
);
1895 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1896 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1897 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1899 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1901 dev_warn(dev
->ctrl
.device
,
1902 "failed to set host mem (err %d, flags %#x).\n",
1908 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1912 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1913 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1914 size_t size
= le32_to_cpu(desc
->size
) * NVME_CTRL_PAGE_SIZE
;
1916 dma_free_attrs(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1917 le64_to_cpu(desc
->addr
),
1918 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1921 kfree(dev
->host_mem_desc_bufs
);
1922 dev
->host_mem_desc_bufs
= NULL
;
1923 dma_free_coherent(dev
->dev
,
1924 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1925 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1926 dev
->host_mem_descs
= NULL
;
1927 dev
->nr_host_mem_descs
= 0;
1930 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1933 struct nvme_host_mem_buf_desc
*descs
;
1934 u32 max_entries
, len
;
1935 dma_addr_t descs_dma
;
1940 tmp
= (preferred
+ chunk_size
- 1);
1941 do_div(tmp
, chunk_size
);
1944 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1945 max_entries
= dev
->ctrl
.hmmaxd
;
1947 descs
= dma_alloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1948 &descs_dma
, GFP_KERNEL
);
1952 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1954 goto out_free_descs
;
1956 for (size
= 0; size
< preferred
&& i
< max_entries
; size
+= len
) {
1957 dma_addr_t dma_addr
;
1959 len
= min_t(u64
, chunk_size
, preferred
- size
);
1960 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1961 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1965 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1966 descs
[i
].size
= cpu_to_le32(len
/ NVME_CTRL_PAGE_SIZE
);
1973 dev
->nr_host_mem_descs
= i
;
1974 dev
->host_mem_size
= size
;
1975 dev
->host_mem_descs
= descs
;
1976 dev
->host_mem_descs_dma
= descs_dma
;
1977 dev
->host_mem_desc_bufs
= bufs
;
1982 size_t size
= le32_to_cpu(descs
[i
].size
) * NVME_CTRL_PAGE_SIZE
;
1984 dma_free_attrs(dev
->dev
, size
, bufs
[i
],
1985 le64_to_cpu(descs
[i
].addr
),
1986 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1991 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1994 dev
->host_mem_descs
= NULL
;
1998 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
2000 u64 min_chunk
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
2001 u64 hmminds
= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
2004 /* start big and work our way down */
2005 for (chunk_size
= min_chunk
; chunk_size
>= hmminds
; chunk_size
/= 2) {
2006 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
2007 if (!min
|| dev
->host_mem_size
>= min
)
2009 nvme_free_host_mem(dev
);
2016 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
2018 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
2019 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
2020 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
2021 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
2024 preferred
= min(preferred
, max
);
2026 dev_warn(dev
->ctrl
.device
,
2027 "min host memory (%lld MiB) above limit (%d MiB).\n",
2028 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
2029 nvme_free_host_mem(dev
);
2034 * If we already have a buffer allocated check if we can reuse it.
2036 if (dev
->host_mem_descs
) {
2037 if (dev
->host_mem_size
>= min
)
2038 enable_bits
|= NVME_HOST_MEM_RETURN
;
2040 nvme_free_host_mem(dev
);
2043 if (!dev
->host_mem_descs
) {
2044 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
2045 dev_warn(dev
->ctrl
.device
,
2046 "failed to allocate host memory buffer.\n");
2047 return 0; /* controller must work without HMB */
2050 dev_info(dev
->ctrl
.device
,
2051 "allocated %lld MiB host memory buffer.\n",
2052 dev
->host_mem_size
>> ilog2(SZ_1M
));
2055 ret
= nvme_set_host_mem(dev
, enable_bits
);
2057 nvme_free_host_mem(dev
);
2062 * nirqs is the number of interrupts available for write and read
2063 * queues. The core already reserved an interrupt for the admin queue.
2065 static void nvme_calc_irq_sets(struct irq_affinity
*affd
, unsigned int nrirqs
)
2067 struct nvme_dev
*dev
= affd
->priv
;
2068 unsigned int nr_read_queues
, nr_write_queues
= dev
->nr_write_queues
;
2071 * If there is no interrupt available for queues, ensure that
2072 * the default queue is set to 1. The affinity set size is
2073 * also set to one, but the irq core ignores it for this case.
2075 * If only one interrupt is available or 'write_queue' == 0, combine
2076 * write and read queues.
2078 * If 'write_queues' > 0, ensure it leaves room for at least one read
2084 } else if (nrirqs
== 1 || !nr_write_queues
) {
2086 } else if (nr_write_queues
>= nrirqs
) {
2089 nr_read_queues
= nrirqs
- nr_write_queues
;
2092 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2093 affd
->set_size
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2094 dev
->io_queues
[HCTX_TYPE_READ
] = nr_read_queues
;
2095 affd
->set_size
[HCTX_TYPE_READ
] = nr_read_queues
;
2096 affd
->nr_sets
= nr_read_queues
? 2 : 1;
2099 static int nvme_setup_irqs(struct nvme_dev
*dev
, unsigned int nr_io_queues
)
2101 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2102 struct irq_affinity affd
= {
2104 .calc_sets
= nvme_calc_irq_sets
,
2107 unsigned int irq_queues
, poll_queues
;
2110 * Poll queues don't need interrupts, but we need at least one I/O queue
2111 * left over for non-polled I/O.
2113 poll_queues
= min(dev
->nr_poll_queues
, nr_io_queues
- 1);
2114 dev
->io_queues
[HCTX_TYPE_POLL
] = poll_queues
;
2117 * Initialize for the single interrupt case, will be updated in
2118 * nvme_calc_irq_sets().
2120 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = 1;
2121 dev
->io_queues
[HCTX_TYPE_READ
] = 0;
2124 * We need interrupts for the admin queue and each non-polled I/O queue,
2125 * but some Apple controllers require all queues to use the first
2129 if (!(dev
->ctrl
.quirks
& NVME_QUIRK_SINGLE_VECTOR
))
2130 irq_queues
+= (nr_io_queues
- poll_queues
);
2131 return pci_alloc_irq_vectors_affinity(pdev
, 1, irq_queues
,
2132 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
, &affd
);
2135 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
2137 if (__nvme_disable_io_queues(dev
, nvme_admin_delete_sq
))
2138 __nvme_disable_io_queues(dev
, nvme_admin_delete_cq
);
2141 static unsigned int nvme_max_io_queues(struct nvme_dev
*dev
)
2144 * If tags are shared with admin queue (Apple bug), then
2145 * make sure we only use one IO queue.
2147 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2149 return num_possible_cpus() + dev
->nr_write_queues
+ dev
->nr_poll_queues
;
2152 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
2154 struct nvme_queue
*adminq
= &dev
->queues
[0];
2155 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2156 unsigned int nr_io_queues
;
2161 * Sample the module parameters once at reset time so that we have
2162 * stable values to work with.
2164 dev
->nr_write_queues
= write_queues
;
2165 dev
->nr_poll_queues
= poll_queues
;
2167 nr_io_queues
= dev
->nr_allocated_queues
- 1;
2168 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
2172 if (nr_io_queues
== 0)
2175 clear_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2177 if (dev
->cmb_use_sqes
) {
2178 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
2179 sizeof(struct nvme_command
));
2181 dev
->q_depth
= result
;
2183 dev
->cmb_use_sqes
= false;
2187 size
= db_bar_size(dev
, nr_io_queues
);
2188 result
= nvme_remap_bar(dev
, size
);
2191 if (!--nr_io_queues
)
2194 adminq
->q_db
= dev
->dbs
;
2197 /* Deregister the admin queue's interrupt */
2198 pci_free_irq(pdev
, 0, adminq
);
2201 * If we enable msix early due to not intx, disable it again before
2202 * setting up the full range we need.
2204 pci_free_irq_vectors(pdev
);
2206 result
= nvme_setup_irqs(dev
, nr_io_queues
);
2210 dev
->num_vecs
= result
;
2211 result
= max(result
- 1, 1);
2212 dev
->max_qid
= result
+ dev
->io_queues
[HCTX_TYPE_POLL
];
2215 * Should investigate if there's a performance win from allocating
2216 * more queues than interrupt vectors; it might allow the submission
2217 * path to scale better, even if the receive path is limited by the
2218 * number of interrupts.
2220 result
= queue_request_irq(adminq
);
2223 set_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2225 result
= nvme_create_io_queues(dev
);
2226 if (result
|| dev
->online_queues
< 2)
2229 if (dev
->online_queues
- 1 < dev
->max_qid
) {
2230 nr_io_queues
= dev
->online_queues
- 1;
2231 nvme_disable_io_queues(dev
);
2232 nvme_suspend_io_queues(dev
);
2235 dev_info(dev
->ctrl
.device
, "%d/%d/%d default/read/poll queues\n",
2236 dev
->io_queues
[HCTX_TYPE_DEFAULT
],
2237 dev
->io_queues
[HCTX_TYPE_READ
],
2238 dev
->io_queues
[HCTX_TYPE_POLL
]);
2242 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
2244 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2246 blk_mq_free_request(req
);
2247 complete(&nvmeq
->delete_done
);
2250 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
2252 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2255 set_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
2257 nvme_del_queue_end(req
, error
);
2260 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
2262 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
2263 struct request
*req
;
2264 struct nvme_command cmd
;
2266 memset(&cmd
, 0, sizeof(cmd
));
2267 cmd
.delete_queue
.opcode
= opcode
;
2268 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
2270 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
);
2272 return PTR_ERR(req
);
2274 req
->end_io_data
= nvmeq
;
2276 init_completion(&nvmeq
->delete_done
);
2277 blk_execute_rq_nowait(NULL
, req
, false,
2278 opcode
== nvme_admin_delete_cq
?
2279 nvme_del_cq_end
: nvme_del_queue_end
);
2283 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
)
2285 int nr_queues
= dev
->online_queues
- 1, sent
= 0;
2286 unsigned long timeout
;
2289 timeout
= NVME_ADMIN_TIMEOUT
;
2290 while (nr_queues
> 0) {
2291 if (nvme_delete_queue(&dev
->queues
[nr_queues
], opcode
))
2297 struct nvme_queue
*nvmeq
= &dev
->queues
[nr_queues
+ sent
];
2299 timeout
= wait_for_completion_io_timeout(&nvmeq
->delete_done
,
2311 static void nvme_dev_add(struct nvme_dev
*dev
)
2315 if (!dev
->ctrl
.tagset
) {
2316 dev
->tagset
.ops
= &nvme_mq_ops
;
2317 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
2318 dev
->tagset
.nr_maps
= 2; /* default + read */
2319 if (dev
->io_queues
[HCTX_TYPE_POLL
])
2320 dev
->tagset
.nr_maps
++;
2321 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
2322 dev
->tagset
.numa_node
= dev
->ctrl
.numa_node
;
2323 dev
->tagset
.queue_depth
= min_t(unsigned int, dev
->q_depth
,
2324 BLK_MQ_MAX_DEPTH
) - 1;
2325 dev
->tagset
.cmd_size
= sizeof(struct nvme_iod
);
2326 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
2327 dev
->tagset
.driver_data
= dev
;
2330 * Some Apple controllers requires tags to be unique
2331 * across admin and IO queue, so reserve the first 32
2332 * tags of the IO queue.
2334 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2335 dev
->tagset
.reserved_tags
= NVME_AQ_DEPTH
;
2337 ret
= blk_mq_alloc_tag_set(&dev
->tagset
);
2339 dev_warn(dev
->ctrl
.device
,
2340 "IO queues tagset allocation failed %d\n", ret
);
2343 dev
->ctrl
.tagset
= &dev
->tagset
;
2345 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
2347 /* Free previously allocated queues that are no longer usable */
2348 nvme_free_queues(dev
, dev
->online_queues
);
2351 nvme_dbbuf_set(dev
);
2354 static int nvme_pci_enable(struct nvme_dev
*dev
)
2356 int result
= -ENOMEM
;
2357 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2358 int dma_address_bits
= 64;
2360 if (pci_enable_device_mem(pdev
))
2363 pci_set_master(pdev
);
2365 if (dev
->ctrl
.quirks
& NVME_QUIRK_DMA_ADDRESS_BITS_48
)
2366 dma_address_bits
= 48;
2367 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(dma_address_bits
)))
2370 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
2376 * Some devices and/or platforms don't advertise or work with INTx
2377 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2378 * adjust this later.
2380 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
2384 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
2386 dev
->q_depth
= min_t(u32
, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
2388 dev
->ctrl
.sqsize
= dev
->q_depth
- 1; /* 0's based queue depth */
2389 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
2390 dev
->dbs
= dev
->bar
+ 4096;
2393 * Some Apple controllers require a non-standard SQE size.
2394 * Interestingly they also seem to ignore the CC:IOSQES register
2395 * so we don't bother updating it here.
2397 if (dev
->ctrl
.quirks
& NVME_QUIRK_128_BYTES_SQES
)
2400 dev
->io_sqes
= NVME_NVM_IOSQES
;
2403 * Temporary fix for the Apple controller found in the MacBook8,1 and
2404 * some MacBook7,1 to avoid controller resets and data loss.
2406 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
2408 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
2409 "set queue depth=%u to work around controller resets\n",
2411 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
2412 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
2413 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
2415 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
2416 "set queue depth=%u\n", dev
->q_depth
);
2420 * Controllers with the shared tags quirk need the IO queue to be
2421 * big enough so that we get 32 tags for the admin queue
2423 if ((dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
) &&
2424 (dev
->q_depth
< (NVME_AQ_DEPTH
+ 2))) {
2425 dev
->q_depth
= NVME_AQ_DEPTH
+ 2;
2426 dev_warn(dev
->ctrl
.device
, "IO queue depth clamped to %d\n",
2433 pci_enable_pcie_error_reporting(pdev
);
2434 pci_save_state(pdev
);
2438 pci_disable_device(pdev
);
2442 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2446 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2449 static void nvme_pci_disable(struct nvme_dev
*dev
)
2451 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2453 pci_free_irq_vectors(pdev
);
2455 if (pci_is_enabled(pdev
)) {
2456 pci_disable_pcie_error_reporting(pdev
);
2457 pci_disable_device(pdev
);
2461 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2463 bool dead
= true, freeze
= false;
2464 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2466 mutex_lock(&dev
->shutdown_lock
);
2467 if (pci_is_enabled(pdev
)) {
2468 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2470 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2471 dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
2473 nvme_start_freeze(&dev
->ctrl
);
2475 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2476 pdev
->error_state
!= pci_channel_io_normal
);
2480 * Give the controller a chance to complete all entered requests if
2481 * doing a safe shutdown.
2483 if (!dead
&& shutdown
&& freeze
)
2484 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2486 nvme_stop_queues(&dev
->ctrl
);
2488 if (!dead
&& dev
->ctrl
.queue_count
> 0) {
2489 nvme_disable_io_queues(dev
);
2490 nvme_disable_admin_queue(dev
, shutdown
);
2492 nvme_suspend_io_queues(dev
);
2493 nvme_suspend_queue(&dev
->queues
[0]);
2494 nvme_pci_disable(dev
);
2495 nvme_reap_pending_cqes(dev
);
2497 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2498 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2499 blk_mq_tagset_wait_completed_request(&dev
->tagset
);
2500 blk_mq_tagset_wait_completed_request(&dev
->admin_tagset
);
2503 * The driver will not be starting up queues again if shutting down so
2504 * must flush all entered requests to their failed completion to avoid
2505 * deadlocking blk-mq hot-cpu notifier.
2508 nvme_start_queues(&dev
->ctrl
);
2509 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
))
2510 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
2512 mutex_unlock(&dev
->shutdown_lock
);
2515 static int nvme_disable_prepare_reset(struct nvme_dev
*dev
, bool shutdown
)
2517 if (!nvme_wait_reset(&dev
->ctrl
))
2519 nvme_dev_disable(dev
, shutdown
);
2523 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2525 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2526 NVME_CTRL_PAGE_SIZE
,
2527 NVME_CTRL_PAGE_SIZE
, 0);
2528 if (!dev
->prp_page_pool
)
2531 /* Optimisation for I/Os between 4k and 128k */
2532 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2534 if (!dev
->prp_small_pool
) {
2535 dma_pool_destroy(dev
->prp_page_pool
);
2541 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2543 dma_pool_destroy(dev
->prp_page_pool
);
2544 dma_pool_destroy(dev
->prp_small_pool
);
2547 static void nvme_free_tagset(struct nvme_dev
*dev
)
2549 if (dev
->tagset
.tags
)
2550 blk_mq_free_tag_set(&dev
->tagset
);
2551 dev
->ctrl
.tagset
= NULL
;
2554 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2556 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2558 nvme_dbbuf_dma_free(dev
);
2559 nvme_free_tagset(dev
);
2560 if (dev
->ctrl
.admin_q
)
2561 blk_put_queue(dev
->ctrl
.admin_q
);
2562 free_opal_dev(dev
->ctrl
.opal_dev
);
2563 mempool_destroy(dev
->iod_mempool
);
2564 put_device(dev
->dev
);
2569 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
)
2572 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2573 * may be holding this pci_dev's device lock.
2575 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2576 nvme_get_ctrl(&dev
->ctrl
);
2577 nvme_dev_disable(dev
, false);
2578 nvme_kill_queues(&dev
->ctrl
);
2579 if (!queue_work(nvme_wq
, &dev
->remove_work
))
2580 nvme_put_ctrl(&dev
->ctrl
);
2583 static void nvme_reset_work(struct work_struct
*work
)
2585 struct nvme_dev
*dev
=
2586 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2587 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2590 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
)) {
2596 * If we're called to reset a live controller first shut it down before
2599 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2600 nvme_dev_disable(dev
, false);
2601 nvme_sync_queues(&dev
->ctrl
);
2603 mutex_lock(&dev
->shutdown_lock
);
2604 result
= nvme_pci_enable(dev
);
2608 result
= nvme_pci_configure_admin_queue(dev
);
2612 result
= nvme_alloc_admin_tags(dev
);
2617 * Limit the max command size to prevent iod->sg allocations going
2618 * over a single page.
2620 dev
->ctrl
.max_hw_sectors
= min_t(u32
,
2621 NVME_MAX_KB_SZ
<< 1, dma_max_mapping_size(dev
->dev
) >> 9);
2622 dev
->ctrl
.max_segments
= NVME_MAX_SEGS
;
2625 * Don't limit the IOMMU merged segment size.
2627 dma_set_max_seg_size(dev
->dev
, 0xffffffff);
2628 dma_set_min_align_mask(dev
->dev
, NVME_CTRL_PAGE_SIZE
- 1);
2630 mutex_unlock(&dev
->shutdown_lock
);
2633 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2634 * initializing procedure here.
2636 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_CONNECTING
)) {
2637 dev_warn(dev
->ctrl
.device
,
2638 "failed to mark controller CONNECTING\n");
2644 * We do not support an SGL for metadata (yet), so we are limited to a
2645 * single integrity segment for the separate metadata pointer.
2647 dev
->ctrl
.max_integrity_segments
= 1;
2649 result
= nvme_init_ctrl_finish(&dev
->ctrl
);
2653 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2654 if (!dev
->ctrl
.opal_dev
)
2655 dev
->ctrl
.opal_dev
=
2656 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2657 else if (was_suspend
)
2658 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2660 free_opal_dev(dev
->ctrl
.opal_dev
);
2661 dev
->ctrl
.opal_dev
= NULL
;
2664 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2665 result
= nvme_dbbuf_dma_alloc(dev
);
2668 "unable to allocate dma for dbbuf\n");
2671 if (dev
->ctrl
.hmpre
) {
2672 result
= nvme_setup_host_mem(dev
);
2677 result
= nvme_setup_io_queues(dev
);
2682 * Keep the controller around but remove all namespaces if we don't have
2683 * any working I/O queue.
2685 if (dev
->online_queues
< 2) {
2686 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2687 nvme_kill_queues(&dev
->ctrl
);
2688 nvme_remove_namespaces(&dev
->ctrl
);
2689 nvme_free_tagset(dev
);
2691 nvme_start_queues(&dev
->ctrl
);
2692 nvme_wait_freeze(&dev
->ctrl
);
2694 nvme_unfreeze(&dev
->ctrl
);
2698 * If only admin queue live, keep it to do further investigation or
2701 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2702 dev_warn(dev
->ctrl
.device
,
2703 "failed to mark controller live state\n");
2708 nvme_start_ctrl(&dev
->ctrl
);
2712 mutex_unlock(&dev
->shutdown_lock
);
2715 dev_warn(dev
->ctrl
.device
,
2716 "Removing after probe failure status: %d\n", result
);
2717 nvme_remove_dead_ctrl(dev
);
2720 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2722 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2723 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2725 if (pci_get_drvdata(pdev
))
2726 device_release_driver(&pdev
->dev
);
2727 nvme_put_ctrl(&dev
->ctrl
);
2730 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2732 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2736 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2738 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2742 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2744 *val
= lo_hi_readq(to_nvme_dev(ctrl
)->bar
+ off
);
2748 static int nvme_pci_get_address(struct nvme_ctrl
*ctrl
, char *buf
, int size
)
2750 struct pci_dev
*pdev
= to_pci_dev(to_nvme_dev(ctrl
)->dev
);
2752 return snprintf(buf
, size
, "%s\n", dev_name(&pdev
->dev
));
2755 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2757 .module
= THIS_MODULE
,
2758 .flags
= NVME_F_METADATA_SUPPORTED
|
2760 .reg_read32
= nvme_pci_reg_read32
,
2761 .reg_write32
= nvme_pci_reg_write32
,
2762 .reg_read64
= nvme_pci_reg_read64
,
2763 .free_ctrl
= nvme_pci_free_ctrl
,
2764 .submit_async_event
= nvme_pci_submit_async_event
,
2765 .get_address
= nvme_pci_get_address
,
2768 static int nvme_dev_map(struct nvme_dev
*dev
)
2770 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2772 if (pci_request_mem_regions(pdev
, "nvme"))
2775 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2780 pci_release_mem_regions(pdev
);
2784 static unsigned long check_vendor_combination_bug(struct pci_dev
*pdev
)
2786 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2788 * Several Samsung devices seem to drop off the PCIe bus
2789 * randomly when APST is on and uses the deepest sleep state.
2790 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2791 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2792 * 950 PRO 256GB", but it seems to be restricted to two Dell
2795 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2796 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2797 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2798 return NVME_QUIRK_NO_DEEPEST_PS
;
2799 } else if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa804) {
2801 * Samsung SSD 960 EVO drops off the PCIe bus after system
2802 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2803 * within few minutes after bootup on a Coffee Lake board -
2806 if (dmi_match(DMI_BOARD_VENDOR
, "ASUSTeK COMPUTER INC.") &&
2807 (dmi_match(DMI_BOARD_NAME
, "PRIME B350M-A") ||
2808 dmi_match(DMI_BOARD_NAME
, "PRIME Z370-A")))
2809 return NVME_QUIRK_NO_APST
;
2810 } else if ((pdev
->vendor
== 0x144d && (pdev
->device
== 0xa801 ||
2811 pdev
->device
== 0xa808 || pdev
->device
== 0xa809)) ||
2812 (pdev
->vendor
== 0x1e0f && pdev
->device
== 0x0001)) {
2814 * Forcing to use host managed nvme power settings for
2815 * lowest idle power with quick resume latency on
2816 * Samsung and Toshiba SSDs based on suspend behavior
2817 * on Coffee Lake board for LENOVO C640
2819 if ((dmi_match(DMI_BOARD_VENDOR
, "LENOVO")) &&
2820 dmi_match(DMI_BOARD_NAME
, "LNVNB161216"))
2821 return NVME_QUIRK_SIMPLE_SUSPEND
;
2828 static bool nvme_acpi_storage_d3(struct pci_dev
*dev
)
2830 struct acpi_device
*adev
;
2831 struct pci_dev
*root
;
2837 * Look for _DSD property specifying that the storage device on the port
2838 * must use D3 to support deep platform power savings during
2841 root
= pcie_find_root_port(dev
);
2845 adev
= ACPI_COMPANION(&root
->dev
);
2850 * The property is defined in the PXSX device for South complex ports
2851 * and in the PEGP device for North complex ports.
2853 status
= acpi_get_handle(adev
->handle
, "PXSX", &handle
);
2854 if (ACPI_FAILURE(status
)) {
2855 status
= acpi_get_handle(adev
->handle
, "PEGP", &handle
);
2856 if (ACPI_FAILURE(status
))
2860 if (acpi_bus_get_device(handle
, &adev
))
2863 if (fwnode_property_read_u8(acpi_fwnode_handle(adev
), "StorageD3Enable",
2869 static inline bool nvme_acpi_storage_d3(struct pci_dev
*dev
)
2873 #endif /* CONFIG_ACPI */
2875 static void nvme_async_probe(void *data
, async_cookie_t cookie
)
2877 struct nvme_dev
*dev
= data
;
2879 flush_work(&dev
->ctrl
.reset_work
);
2880 flush_work(&dev
->ctrl
.scan_work
);
2881 nvme_put_ctrl(&dev
->ctrl
);
2884 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2886 int node
, result
= -ENOMEM
;
2887 struct nvme_dev
*dev
;
2888 unsigned long quirks
= id
->driver_data
;
2891 node
= dev_to_node(&pdev
->dev
);
2892 if (node
== NUMA_NO_NODE
)
2893 set_dev_node(&pdev
->dev
, first_memory_node
);
2895 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2899 dev
->nr_write_queues
= write_queues
;
2900 dev
->nr_poll_queues
= poll_queues
;
2901 dev
->nr_allocated_queues
= nvme_max_io_queues(dev
) + 1;
2902 dev
->queues
= kcalloc_node(dev
->nr_allocated_queues
,
2903 sizeof(struct nvme_queue
), GFP_KERNEL
, node
);
2907 dev
->dev
= get_device(&pdev
->dev
);
2908 pci_set_drvdata(pdev
, dev
);
2910 result
= nvme_dev_map(dev
);
2914 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2915 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2916 mutex_init(&dev
->shutdown_lock
);
2918 result
= nvme_setup_prp_pools(dev
);
2922 quirks
|= check_vendor_combination_bug(pdev
);
2924 if (!noacpi
&& nvme_acpi_storage_d3(pdev
)) {
2926 * Some systems use a bios work around to ask for D3 on
2927 * platforms that support kernel managed suspend.
2929 dev_info(&pdev
->dev
,
2930 "platform quirk: setting simple suspend\n");
2931 quirks
|= NVME_QUIRK_SIMPLE_SUSPEND
;
2935 * Double check that our mempool alloc size will cover the biggest
2936 * command we support.
2938 alloc_size
= nvme_pci_iod_alloc_size();
2939 WARN_ON_ONCE(alloc_size
> PAGE_SIZE
);
2941 dev
->iod_mempool
= mempool_create_node(1, mempool_kmalloc
,
2943 (void *) alloc_size
,
2945 if (!dev
->iod_mempool
) {
2950 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2953 goto release_mempool
;
2955 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2957 nvme_reset_ctrl(&dev
->ctrl
);
2958 async_schedule(nvme_async_probe
, dev
);
2963 mempool_destroy(dev
->iod_mempool
);
2965 nvme_release_prp_pools(dev
);
2967 nvme_dev_unmap(dev
);
2969 put_device(dev
->dev
);
2976 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2978 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2981 * We don't need to check the return value from waiting for the reset
2982 * state as pci_dev device lock is held, making it impossible to race
2985 nvme_disable_prepare_reset(dev
, false);
2986 nvme_sync_queues(&dev
->ctrl
);
2989 static void nvme_reset_done(struct pci_dev
*pdev
)
2991 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2993 if (!nvme_try_sched_reset(&dev
->ctrl
))
2994 flush_work(&dev
->ctrl
.reset_work
);
2997 static void nvme_shutdown(struct pci_dev
*pdev
)
2999 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3001 nvme_disable_prepare_reset(dev
, true);
3005 * The driver's remove may be called on a device in a partially initialized
3006 * state. This function must not have any dependencies on the device state in
3009 static void nvme_remove(struct pci_dev
*pdev
)
3011 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3013 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
3014 pci_set_drvdata(pdev
, NULL
);
3016 if (!pci_device_is_present(pdev
)) {
3017 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
3018 nvme_dev_disable(dev
, true);
3019 nvme_dev_remove_admin(dev
);
3022 flush_work(&dev
->ctrl
.reset_work
);
3023 nvme_stop_ctrl(&dev
->ctrl
);
3024 nvme_remove_namespaces(&dev
->ctrl
);
3025 nvme_dev_disable(dev
, true);
3026 nvme_release_cmb(dev
);
3027 nvme_free_host_mem(dev
);
3028 nvme_dev_remove_admin(dev
);
3029 nvme_free_queues(dev
, 0);
3030 nvme_release_prp_pools(dev
);
3031 nvme_dev_unmap(dev
);
3032 nvme_uninit_ctrl(&dev
->ctrl
);
3035 #ifdef CONFIG_PM_SLEEP
3036 static int nvme_get_power_state(struct nvme_ctrl
*ctrl
, u32
*ps
)
3038 return nvme_get_features(ctrl
, NVME_FEAT_POWER_MGMT
, 0, NULL
, 0, ps
);
3041 static int nvme_set_power_state(struct nvme_ctrl
*ctrl
, u32 ps
)
3043 return nvme_set_features(ctrl
, NVME_FEAT_POWER_MGMT
, ps
, NULL
, 0, NULL
);
3046 static int nvme_resume(struct device
*dev
)
3048 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
3049 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
3051 if (ndev
->last_ps
== U32_MAX
||
3052 nvme_set_power_state(ctrl
, ndev
->last_ps
) != 0)
3053 return nvme_try_sched_reset(&ndev
->ctrl
);
3057 static int nvme_suspend(struct device
*dev
)
3059 struct pci_dev
*pdev
= to_pci_dev(dev
);
3060 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
3061 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
3064 ndev
->last_ps
= U32_MAX
;
3067 * The platform does not remove power for a kernel managed suspend so
3068 * use host managed nvme power settings for lowest idle power if
3069 * possible. This should have quicker resume latency than a full device
3070 * shutdown. But if the firmware is involved after the suspend or the
3071 * device does not support any non-default power states, shut down the
3074 * If ASPM is not enabled for the device, shut down the device and allow
3075 * the PCI bus layer to put it into D3 in order to take the PCIe link
3076 * down, so as to allow the platform to achieve its minimum low-power
3077 * state (which may not be possible if the link is up).
3079 * If a host memory buffer is enabled, shut down the device as the NVMe
3080 * specification allows the device to access the host memory buffer in
3081 * host DRAM from all power states, but hosts will fail access to DRAM
3084 if (pm_suspend_via_firmware() || !ctrl
->npss
||
3085 !pcie_aspm_enabled(pdev
) ||
3086 ndev
->nr_host_mem_descs
||
3087 (ndev
->ctrl
.quirks
& NVME_QUIRK_SIMPLE_SUSPEND
))
3088 return nvme_disable_prepare_reset(ndev
, true);
3090 nvme_start_freeze(ctrl
);
3091 nvme_wait_freeze(ctrl
);
3092 nvme_sync_queues(ctrl
);
3094 if (ctrl
->state
!= NVME_CTRL_LIVE
)
3097 ret
= nvme_get_power_state(ctrl
, &ndev
->last_ps
);
3102 * A saved state prevents pci pm from generically controlling the
3103 * device's power. If we're using protocol specific settings, we don't
3104 * want pci interfering.
3106 pci_save_state(pdev
);
3108 ret
= nvme_set_power_state(ctrl
, ctrl
->npss
);
3113 /* discard the saved state */
3114 pci_load_saved_state(pdev
, NULL
);
3117 * Clearing npss forces a controller reset on resume. The
3118 * correct value will be rediscovered then.
3120 ret
= nvme_disable_prepare_reset(ndev
, true);
3124 nvme_unfreeze(ctrl
);
3128 static int nvme_simple_suspend(struct device
*dev
)
3130 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
3132 return nvme_disable_prepare_reset(ndev
, true);
3135 static int nvme_simple_resume(struct device
*dev
)
3137 struct pci_dev
*pdev
= to_pci_dev(dev
);
3138 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
3140 return nvme_try_sched_reset(&ndev
->ctrl
);
3143 static const struct dev_pm_ops nvme_dev_pm_ops
= {
3144 .suspend
= nvme_suspend
,
3145 .resume
= nvme_resume
,
3146 .freeze
= nvme_simple_suspend
,
3147 .thaw
= nvme_simple_resume
,
3148 .poweroff
= nvme_simple_suspend
,
3149 .restore
= nvme_simple_resume
,
3151 #endif /* CONFIG_PM_SLEEP */
3153 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
3154 pci_channel_state_t state
)
3156 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3159 * A frozen channel requires a reset. When detected, this method will
3160 * shutdown the controller to quiesce. The controller will be restarted
3161 * after the slot reset through driver's slot_reset callback.
3164 case pci_channel_io_normal
:
3165 return PCI_ERS_RESULT_CAN_RECOVER
;
3166 case pci_channel_io_frozen
:
3167 dev_warn(dev
->ctrl
.device
,
3168 "frozen state error detected, reset controller\n");
3169 nvme_dev_disable(dev
, false);
3170 return PCI_ERS_RESULT_NEED_RESET
;
3171 case pci_channel_io_perm_failure
:
3172 dev_warn(dev
->ctrl
.device
,
3173 "failure state error detected, request disconnect\n");
3174 return PCI_ERS_RESULT_DISCONNECT
;
3176 return PCI_ERS_RESULT_NEED_RESET
;
3179 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
3181 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3183 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
3184 pci_restore_state(pdev
);
3185 nvme_reset_ctrl(&dev
->ctrl
);
3186 return PCI_ERS_RESULT_RECOVERED
;
3189 static void nvme_error_resume(struct pci_dev
*pdev
)
3191 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3193 flush_work(&dev
->ctrl
.reset_work
);
3196 static const struct pci_error_handlers nvme_err_handler
= {
3197 .error_detected
= nvme_error_detected
,
3198 .slot_reset
= nvme_slot_reset
,
3199 .resume
= nvme_error_resume
,
3200 .reset_prepare
= nvme_reset_prepare
,
3201 .reset_done
= nvme_reset_done
,
3204 static const struct pci_device_id nvme_id_table
[] = {
3205 { PCI_VDEVICE(INTEL
, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3206 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3207 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3208 { PCI_VDEVICE(INTEL
, 0x0a53), /* Intel P3520 */
3209 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3210 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3211 { PCI_VDEVICE(INTEL
, 0x0a54), /* Intel P4500/P4600 */
3212 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3213 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3214 { PCI_VDEVICE(INTEL
, 0x0a55), /* Dell Express Flash P4600 */
3215 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3216 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3217 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
3218 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3219 NVME_QUIRK_MEDIUM_PRIO_SQ
|
3220 NVME_QUIRK_NO_TEMP_THRESH_CHANGE
|
3221 NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3222 { PCI_VDEVICE(INTEL
, 0xf1a6), /* Intel 760p/Pro 7600p */
3223 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3224 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
3225 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
|
3226 NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3227 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3228 .driver_data
= NVME_QUIRK_NO_NS_DESC_LIST
, },
3229 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3230 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
|
3231 NVME_QUIRK_NO_NS_DESC_LIST
, },
3232 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3233 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3234 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3235 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3236 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3237 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3238 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3239 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3240 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3241 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
|
3242 NVME_QUIRK_DISABLE_WRITE_ZEROES
|
3243 NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3244 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3245 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3246 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3247 .driver_data
= NVME_QUIRK_NO_NS_DESC_LIST
|
3248 NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3249 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3250 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3251 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3252 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3253 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3254 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3255 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3256 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3257 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3258 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3259 NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3260 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3261 .driver_data
= NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3262 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3263 .driver_data
= NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3264 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3265 .driver_data
= NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3266 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3267 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
, },
3268 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3269 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
, },
3270 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON
, 0x0061),
3271 .driver_data
= NVME_QUIRK_DMA_ADDRESS_BITS_48
, },
3272 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON
, 0x0065),
3273 .driver_data
= NVME_QUIRK_DMA_ADDRESS_BITS_48
, },
3274 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON
, 0x8061),
3275 .driver_data
= NVME_QUIRK_DMA_ADDRESS_BITS_48
, },
3276 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON
, 0xcd00),
3277 .driver_data
= NVME_QUIRK_DMA_ADDRESS_BITS_48
, },
3278 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON
, 0xcd01),
3279 .driver_data
= NVME_QUIRK_DMA_ADDRESS_BITS_48
, },
3280 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON
, 0xcd02),
3281 .driver_data
= NVME_QUIRK_DMA_ADDRESS_BITS_48
, },
3282 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001),
3283 .driver_data
= NVME_QUIRK_SINGLE_VECTOR
},
3284 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
3285 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2005),
3286 .driver_data
= NVME_QUIRK_SINGLE_VECTOR
|
3287 NVME_QUIRK_128_BYTES_SQES
|
3288 NVME_QUIRK_SHARED_TAGS
},
3290 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
3293 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
3295 static struct pci_driver nvme_driver
= {
3297 .id_table
= nvme_id_table
,
3298 .probe
= nvme_probe
,
3299 .remove
= nvme_remove
,
3300 .shutdown
= nvme_shutdown
,
3301 #ifdef CONFIG_PM_SLEEP
3303 .pm
= &nvme_dev_pm_ops
,
3306 .sriov_configure
= pci_sriov_configure_simple
,
3307 .err_handler
= &nvme_err_handler
,
3310 static int __init
nvme_init(void)
3312 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
3313 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
3314 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
3315 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS
< 2);
3317 return pci_register_driver(&nvme_driver
);
3320 static void __exit
nvme_exit(void)
3322 pci_unregister_driver(&nvme_driver
);
3323 flush_workqueue(nvme_wq
);
3326 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3327 MODULE_LICENSE("GPL");
3328 MODULE_VERSION("1.0");
3329 module_init(nvme_init
);
3330 module_exit(nvme_exit
);