]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/nvme/host/pci.c
Merge branch 'for-4.4/lightnvm' of git://git.kernel.dk/linux-block
[mirror_ubuntu-hirsute-kernel.git] / drivers / nvme / host / pci.c
1 /*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
31 #include <linux/list_sort.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
42 #include <scsi/sg.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
44
45 #include <uapi/linux/nvme_ioctl.h>
46 #include "nvme.h"
47
48 #define NVME_MINORS (1U << MINORBITS)
49 #define NVME_Q_DEPTH 1024
50 #define NVME_AQ_DEPTH 256
51 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
52 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
53 #define ADMIN_TIMEOUT (admin_timeout * HZ)
54 #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
55
56 static unsigned char admin_timeout = 60;
57 module_param(admin_timeout, byte, 0644);
58 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
59
60 unsigned char nvme_io_timeout = 30;
61 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
62 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
63
64 static unsigned char shutdown_timeout = 5;
65 module_param(shutdown_timeout, byte, 0644);
66 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
68 static int nvme_major;
69 module_param(nvme_major, int, 0);
70
71 static int nvme_char_major;
72 module_param(nvme_char_major, int, 0);
73
74 static int use_threaded_interrupts;
75 module_param(use_threaded_interrupts, int, 0);
76
77 static bool use_cmb_sqes = true;
78 module_param(use_cmb_sqes, bool, 0644);
79 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
80
81 static DEFINE_SPINLOCK(dev_list_lock);
82 static LIST_HEAD(dev_list);
83 static struct task_struct *nvme_thread;
84 static struct workqueue_struct *nvme_workq;
85 static wait_queue_head_t nvme_kthread_wait;
86
87 static struct class *nvme_class;
88
89 static int __nvme_reset(struct nvme_dev *dev);
90 static int nvme_reset(struct nvme_dev *dev);
91 static int nvme_process_cq(struct nvme_queue *nvmeq);
92 static void nvme_dead_ctrl(struct nvme_dev *dev);
93
94 struct async_cmd_info {
95 struct kthread_work work;
96 struct kthread_worker *worker;
97 struct request *req;
98 u32 result;
99 int status;
100 void *ctx;
101 };
102
103 /*
104 * An NVM Express queue. Each device has at least two (one for admin
105 * commands and one for I/O commands).
106 */
107 struct nvme_queue {
108 struct device *q_dmadev;
109 struct nvme_dev *dev;
110 char irqname[24]; /* nvme4294967295-65535\0 */
111 spinlock_t q_lock;
112 struct nvme_command *sq_cmds;
113 struct nvme_command __iomem *sq_cmds_io;
114 volatile struct nvme_completion *cqes;
115 struct blk_mq_tags **tags;
116 dma_addr_t sq_dma_addr;
117 dma_addr_t cq_dma_addr;
118 u32 __iomem *q_db;
119 u16 q_depth;
120 s16 cq_vector;
121 u16 sq_head;
122 u16 sq_tail;
123 u16 cq_head;
124 u16 qid;
125 u8 cq_phase;
126 u8 cqe_seen;
127 struct async_cmd_info cmdinfo;
128 };
129
130 /*
131 * Check we didin't inadvertently grow the command struct
132 */
133 static inline void _nvme_check_size(void)
134 {
135 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
137 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
142 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
143 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
144 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
145 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
146 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
147 }
148
149 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
150 struct nvme_completion *);
151
152 struct nvme_cmd_info {
153 nvme_completion_fn fn;
154 void *ctx;
155 int aborted;
156 struct nvme_queue *nvmeq;
157 struct nvme_iod iod[0];
158 };
159
160 /*
161 * Max size of iod being embedded in the request payload
162 */
163 #define NVME_INT_PAGES 2
164 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
165 #define NVME_INT_MASK 0x01
166
167 /*
168 * Will slightly overestimate the number of pages needed. This is OK
169 * as it only leads to a small amount of wasted memory for the lifetime of
170 * the I/O.
171 */
172 static int nvme_npages(unsigned size, struct nvme_dev *dev)
173 {
174 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
175 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
176 }
177
178 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
179 {
180 unsigned int ret = sizeof(struct nvme_cmd_info);
181
182 ret += sizeof(struct nvme_iod);
183 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
184 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
185
186 return ret;
187 }
188
189 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
190 unsigned int hctx_idx)
191 {
192 struct nvme_dev *dev = data;
193 struct nvme_queue *nvmeq = dev->queues[0];
194
195 WARN_ON(hctx_idx != 0);
196 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
197 WARN_ON(nvmeq->tags);
198
199 hctx->driver_data = nvmeq;
200 nvmeq->tags = &dev->admin_tagset.tags[0];
201 return 0;
202 }
203
204 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
205 {
206 struct nvme_queue *nvmeq = hctx->driver_data;
207
208 nvmeq->tags = NULL;
209 }
210
211 static int nvme_admin_init_request(void *data, struct request *req,
212 unsigned int hctx_idx, unsigned int rq_idx,
213 unsigned int numa_node)
214 {
215 struct nvme_dev *dev = data;
216 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
217 struct nvme_queue *nvmeq = dev->queues[0];
218
219 BUG_ON(!nvmeq);
220 cmd->nvmeq = nvmeq;
221 return 0;
222 }
223
224 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
225 unsigned int hctx_idx)
226 {
227 struct nvme_dev *dev = data;
228 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
229
230 if (!nvmeq->tags)
231 nvmeq->tags = &dev->tagset.tags[hctx_idx];
232
233 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
234 hctx->driver_data = nvmeq;
235 return 0;
236 }
237
238 static int nvme_init_request(void *data, struct request *req,
239 unsigned int hctx_idx, unsigned int rq_idx,
240 unsigned int numa_node)
241 {
242 struct nvme_dev *dev = data;
243 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
244 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
245
246 BUG_ON(!nvmeq);
247 cmd->nvmeq = nvmeq;
248 return 0;
249 }
250
251 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
252 nvme_completion_fn handler)
253 {
254 cmd->fn = handler;
255 cmd->ctx = ctx;
256 cmd->aborted = 0;
257 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
258 }
259
260 static void *iod_get_private(struct nvme_iod *iod)
261 {
262 return (void *) (iod->private & ~0x1UL);
263 }
264
265 /*
266 * If bit 0 is set, the iod is embedded in the request payload.
267 */
268 static bool iod_should_kfree(struct nvme_iod *iod)
269 {
270 return (iod->private & NVME_INT_MASK) == 0;
271 }
272
273 /* Special values must be less than 0x1000 */
274 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
275 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
276 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
277 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
278
279 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
280 struct nvme_completion *cqe)
281 {
282 if (ctx == CMD_CTX_CANCELLED)
283 return;
284 if (ctx == CMD_CTX_COMPLETED) {
285 dev_warn(nvmeq->q_dmadev,
286 "completed id %d twice on queue %d\n",
287 cqe->command_id, le16_to_cpup(&cqe->sq_id));
288 return;
289 }
290 if (ctx == CMD_CTX_INVALID) {
291 dev_warn(nvmeq->q_dmadev,
292 "invalid id %d completed on queue %d\n",
293 cqe->command_id, le16_to_cpup(&cqe->sq_id));
294 return;
295 }
296 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
297 }
298
299 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
300 {
301 void *ctx;
302
303 if (fn)
304 *fn = cmd->fn;
305 ctx = cmd->ctx;
306 cmd->fn = special_completion;
307 cmd->ctx = CMD_CTX_CANCELLED;
308 return ctx;
309 }
310
311 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
312 struct nvme_completion *cqe)
313 {
314 u32 result = le32_to_cpup(&cqe->result);
315 u16 status = le16_to_cpup(&cqe->status) >> 1;
316
317 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
318 ++nvmeq->dev->event_limit;
319 if (status != NVME_SC_SUCCESS)
320 return;
321
322 switch (result & 0xff07) {
323 case NVME_AER_NOTICE_NS_CHANGED:
324 dev_info(nvmeq->q_dmadev, "rescanning\n");
325 schedule_work(&nvmeq->dev->scan_work);
326 default:
327 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
328 }
329 }
330
331 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
332 struct nvme_completion *cqe)
333 {
334 struct request *req = ctx;
335
336 u16 status = le16_to_cpup(&cqe->status) >> 1;
337 u32 result = le32_to_cpup(&cqe->result);
338
339 blk_mq_free_request(req);
340
341 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
342 ++nvmeq->dev->abort_limit;
343 }
344
345 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
346 struct nvme_completion *cqe)
347 {
348 struct async_cmd_info *cmdinfo = ctx;
349 cmdinfo->result = le32_to_cpup(&cqe->result);
350 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
351 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
352 blk_mq_free_request(cmdinfo->req);
353 }
354
355 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
356 unsigned int tag)
357 {
358 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
359
360 return blk_mq_rq_to_pdu(req);
361 }
362
363 /*
364 * Called with local interrupts disabled and the q_lock held. May not sleep.
365 */
366 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
367 nvme_completion_fn *fn)
368 {
369 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
370 void *ctx;
371 if (tag >= nvmeq->q_depth) {
372 *fn = special_completion;
373 return CMD_CTX_INVALID;
374 }
375 if (fn)
376 *fn = cmd->fn;
377 ctx = cmd->ctx;
378 cmd->fn = special_completion;
379 cmd->ctx = CMD_CTX_COMPLETED;
380 return ctx;
381 }
382
383 /**
384 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
385 * @nvmeq: The queue to use
386 * @cmd: The command to send
387 *
388 * Safe to use from interrupt context
389 */
390 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
391 struct nvme_command *cmd)
392 {
393 u16 tail = nvmeq->sq_tail;
394
395 if (nvmeq->sq_cmds_io)
396 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
397 else
398 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
399
400 if (++tail == nvmeq->q_depth)
401 tail = 0;
402 writel(tail, nvmeq->q_db);
403 nvmeq->sq_tail = tail;
404 }
405
406 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
407 {
408 unsigned long flags;
409 spin_lock_irqsave(&nvmeq->q_lock, flags);
410 __nvme_submit_cmd(nvmeq, cmd);
411 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
412 }
413
414 static __le64 **iod_list(struct nvme_iod *iod)
415 {
416 return ((void *)iod) + iod->offset;
417 }
418
419 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
420 unsigned nseg, unsigned long private)
421 {
422 iod->private = private;
423 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
424 iod->npages = -1;
425 iod->length = nbytes;
426 iod->nents = 0;
427 }
428
429 static struct nvme_iod *
430 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
431 unsigned long priv, gfp_t gfp)
432 {
433 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
434 sizeof(__le64 *) * nvme_npages(bytes, dev) +
435 sizeof(struct scatterlist) * nseg, gfp);
436
437 if (iod)
438 iod_init(iod, bytes, nseg, priv);
439
440 return iod;
441 }
442
443 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
444 gfp_t gfp)
445 {
446 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
447 sizeof(struct nvme_dsm_range);
448 struct nvme_iod *iod;
449
450 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
451 size <= NVME_INT_BYTES(dev)) {
452 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
453
454 iod = cmd->iod;
455 iod_init(iod, size, rq->nr_phys_segments,
456 (unsigned long) rq | NVME_INT_MASK);
457 return iod;
458 }
459
460 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
461 (unsigned long) rq, gfp);
462 }
463
464 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
465 {
466 const int last_prp = dev->page_size / 8 - 1;
467 int i;
468 __le64 **list = iod_list(iod);
469 dma_addr_t prp_dma = iod->first_dma;
470
471 if (iod->npages == 0)
472 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
473 for (i = 0; i < iod->npages; i++) {
474 __le64 *prp_list = list[i];
475 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
476 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
477 prp_dma = next_prp_dma;
478 }
479
480 if (iod_should_kfree(iod))
481 kfree(iod);
482 }
483
484 static int nvme_error_status(u16 status)
485 {
486 switch (status & 0x7ff) {
487 case NVME_SC_SUCCESS:
488 return 0;
489 case NVME_SC_CAP_EXCEEDED:
490 return -ENOSPC;
491 default:
492 return -EIO;
493 }
494 }
495
496 #ifdef CONFIG_BLK_DEV_INTEGRITY
497 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
498 {
499 if (be32_to_cpu(pi->ref_tag) == v)
500 pi->ref_tag = cpu_to_be32(p);
501 }
502
503 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
504 {
505 if (be32_to_cpu(pi->ref_tag) == p)
506 pi->ref_tag = cpu_to_be32(v);
507 }
508
509 /**
510 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
511 *
512 * The virtual start sector is the one that was originally submitted by the
513 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
514 * start sector may be different. Remap protection information to match the
515 * physical LBA on writes, and back to the original seed on reads.
516 *
517 * Type 0 and 3 do not have a ref tag, so no remapping required.
518 */
519 static void nvme_dif_remap(struct request *req,
520 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
521 {
522 struct nvme_ns *ns = req->rq_disk->private_data;
523 struct bio_integrity_payload *bip;
524 struct t10_pi_tuple *pi;
525 void *p, *pmap;
526 u32 i, nlb, ts, phys, virt;
527
528 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
529 return;
530
531 bip = bio_integrity(req->bio);
532 if (!bip)
533 return;
534
535 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
536
537 p = pmap;
538 virt = bip_get_seed(bip);
539 phys = nvme_block_nr(ns, blk_rq_pos(req));
540 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
541 ts = ns->disk->integrity->tuple_size;
542
543 for (i = 0; i < nlb; i++, virt++, phys++) {
544 pi = (struct t10_pi_tuple *)p;
545 dif_swap(phys, virt, pi);
546 p += ts;
547 }
548 kunmap_atomic(pmap);
549 }
550
551 static int nvme_noop_verify(struct blk_integrity_iter *iter)
552 {
553 return 0;
554 }
555
556 static int nvme_noop_generate(struct blk_integrity_iter *iter)
557 {
558 return 0;
559 }
560
561 struct blk_integrity nvme_meta_noop = {
562 .name = "NVME_META_NOOP",
563 .generate_fn = nvme_noop_generate,
564 .verify_fn = nvme_noop_verify,
565 };
566
567 static void nvme_init_integrity(struct nvme_ns *ns)
568 {
569 struct blk_integrity integrity;
570
571 switch (ns->pi_type) {
572 case NVME_NS_DPS_PI_TYPE3:
573 integrity = t10_pi_type3_crc;
574 break;
575 case NVME_NS_DPS_PI_TYPE1:
576 case NVME_NS_DPS_PI_TYPE2:
577 integrity = t10_pi_type1_crc;
578 break;
579 default:
580 integrity = nvme_meta_noop;
581 break;
582 }
583 integrity.tuple_size = ns->ms;
584 blk_integrity_register(ns->disk, &integrity);
585 blk_queue_max_integrity_segments(ns->queue, 1);
586 }
587 #else /* CONFIG_BLK_DEV_INTEGRITY */
588 static void nvme_dif_remap(struct request *req,
589 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
590 {
591 }
592 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
593 {
594 }
595 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
596 {
597 }
598 static void nvme_init_integrity(struct nvme_ns *ns)
599 {
600 }
601 #endif
602
603 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
604 struct nvme_completion *cqe)
605 {
606 struct nvme_iod *iod = ctx;
607 struct request *req = iod_get_private(iod);
608 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
609 u16 status = le16_to_cpup(&cqe->status) >> 1;
610 bool requeue = false;
611 int error = 0;
612
613 if (unlikely(status)) {
614 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
615 && (jiffies - req->start_time) < req->timeout) {
616 unsigned long flags;
617
618 requeue = true;
619 blk_mq_requeue_request(req);
620 spin_lock_irqsave(req->q->queue_lock, flags);
621 if (!blk_queue_stopped(req->q))
622 blk_mq_kick_requeue_list(req->q);
623 spin_unlock_irqrestore(req->q->queue_lock, flags);
624 goto release_iod;
625 }
626
627 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
628 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
629 error = -EINTR;
630 else
631 error = status;
632 } else {
633 error = nvme_error_status(status);
634 }
635 }
636
637 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
638 u32 result = le32_to_cpup(&cqe->result);
639 req->special = (void *)(uintptr_t)result;
640 }
641
642 if (cmd_rq->aborted)
643 dev_warn(nvmeq->dev->dev,
644 "completing aborted command with status:%04x\n",
645 error);
646
647 release_iod:
648 if (iod->nents) {
649 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
650 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
651 if (blk_integrity_rq(req)) {
652 if (!rq_data_dir(req))
653 nvme_dif_remap(req, nvme_dif_complete);
654 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
655 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
656 }
657 }
658 nvme_free_iod(nvmeq->dev, iod);
659
660 if (likely(!requeue))
661 blk_mq_complete_request(req, error);
662 }
663
664 /* length is in bytes. gfp flags indicates whether we may sleep. */
665 static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
666 int total_len, gfp_t gfp)
667 {
668 struct dma_pool *pool;
669 int length = total_len;
670 struct scatterlist *sg = iod->sg;
671 int dma_len = sg_dma_len(sg);
672 u64 dma_addr = sg_dma_address(sg);
673 u32 page_size = dev->page_size;
674 int offset = dma_addr & (page_size - 1);
675 __le64 *prp_list;
676 __le64 **list = iod_list(iod);
677 dma_addr_t prp_dma;
678 int nprps, i;
679
680 length -= (page_size - offset);
681 if (length <= 0)
682 return total_len;
683
684 dma_len -= (page_size - offset);
685 if (dma_len) {
686 dma_addr += (page_size - offset);
687 } else {
688 sg = sg_next(sg);
689 dma_addr = sg_dma_address(sg);
690 dma_len = sg_dma_len(sg);
691 }
692
693 if (length <= page_size) {
694 iod->first_dma = dma_addr;
695 return total_len;
696 }
697
698 nprps = DIV_ROUND_UP(length, page_size);
699 if (nprps <= (256 / 8)) {
700 pool = dev->prp_small_pool;
701 iod->npages = 0;
702 } else {
703 pool = dev->prp_page_pool;
704 iod->npages = 1;
705 }
706
707 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
708 if (!prp_list) {
709 iod->first_dma = dma_addr;
710 iod->npages = -1;
711 return (total_len - length) + page_size;
712 }
713 list[0] = prp_list;
714 iod->first_dma = prp_dma;
715 i = 0;
716 for (;;) {
717 if (i == page_size >> 3) {
718 __le64 *old_prp_list = prp_list;
719 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
720 if (!prp_list)
721 return total_len - length;
722 list[iod->npages++] = prp_list;
723 prp_list[0] = old_prp_list[i - 1];
724 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
725 i = 1;
726 }
727 prp_list[i++] = cpu_to_le64(dma_addr);
728 dma_len -= page_size;
729 dma_addr += page_size;
730 length -= page_size;
731 if (length <= 0)
732 break;
733 if (dma_len > 0)
734 continue;
735 BUG_ON(dma_len < 0);
736 sg = sg_next(sg);
737 dma_addr = sg_dma_address(sg);
738 dma_len = sg_dma_len(sg);
739 }
740
741 return total_len;
742 }
743
744 static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
745 struct nvme_iod *iod)
746 {
747 struct nvme_command cmnd;
748
749 memcpy(&cmnd, req->cmd, sizeof(cmnd));
750 cmnd.rw.command_id = req->tag;
751 if (req->nr_phys_segments) {
752 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
753 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
754 }
755
756 __nvme_submit_cmd(nvmeq, &cmnd);
757 }
758
759 /*
760 * We reuse the small pool to allocate the 16-byte range here as it is not
761 * worth having a special pool for these or additional cases to handle freeing
762 * the iod.
763 */
764 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
765 struct request *req, struct nvme_iod *iod)
766 {
767 struct nvme_dsm_range *range =
768 (struct nvme_dsm_range *)iod_list(iod)[0];
769 struct nvme_command cmnd;
770
771 range->cattr = cpu_to_le32(0);
772 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
773 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
774
775 memset(&cmnd, 0, sizeof(cmnd));
776 cmnd.dsm.opcode = nvme_cmd_dsm;
777 cmnd.dsm.command_id = req->tag;
778 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
779 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
780 cmnd.dsm.nr = 0;
781 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
782
783 __nvme_submit_cmd(nvmeq, &cmnd);
784 }
785
786 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
787 int cmdid)
788 {
789 struct nvme_command cmnd;
790
791 memset(&cmnd, 0, sizeof(cmnd));
792 cmnd.common.opcode = nvme_cmd_flush;
793 cmnd.common.command_id = cmdid;
794 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
795
796 __nvme_submit_cmd(nvmeq, &cmnd);
797 }
798
799 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
800 struct nvme_ns *ns)
801 {
802 struct request *req = iod_get_private(iod);
803 struct nvme_command cmnd;
804 u16 control = 0;
805 u32 dsmgmt = 0;
806
807 if (req->cmd_flags & REQ_FUA)
808 control |= NVME_RW_FUA;
809 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
810 control |= NVME_RW_LR;
811
812 if (req->cmd_flags & REQ_RAHEAD)
813 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
814
815 memset(&cmnd, 0, sizeof(cmnd));
816 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
817 cmnd.rw.command_id = req->tag;
818 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
819 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
820 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
821 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
822 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
823
824 if (ns->ms) {
825 switch (ns->pi_type) {
826 case NVME_NS_DPS_PI_TYPE3:
827 control |= NVME_RW_PRINFO_PRCHK_GUARD;
828 break;
829 case NVME_NS_DPS_PI_TYPE1:
830 case NVME_NS_DPS_PI_TYPE2:
831 control |= NVME_RW_PRINFO_PRCHK_GUARD |
832 NVME_RW_PRINFO_PRCHK_REF;
833 cmnd.rw.reftag = cpu_to_le32(
834 nvme_block_nr(ns, blk_rq_pos(req)));
835 break;
836 }
837 if (blk_integrity_rq(req))
838 cmnd.rw.metadata =
839 cpu_to_le64(sg_dma_address(iod->meta_sg));
840 else
841 control |= NVME_RW_PRINFO_PRACT;
842 }
843
844 cmnd.rw.control = cpu_to_le16(control);
845 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
846
847 __nvme_submit_cmd(nvmeq, &cmnd);
848
849 return 0;
850 }
851
852 /*
853 * NOTE: ns is NULL when called on the admin queue.
854 */
855 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
856 const struct blk_mq_queue_data *bd)
857 {
858 struct nvme_ns *ns = hctx->queue->queuedata;
859 struct nvme_queue *nvmeq = hctx->driver_data;
860 struct nvme_dev *dev = nvmeq->dev;
861 struct request *req = bd->rq;
862 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
863 struct nvme_iod *iod;
864 enum dma_data_direction dma_dir;
865
866 /*
867 * If formated with metadata, require the block layer provide a buffer
868 * unless this namespace is formated such that the metadata can be
869 * stripped/generated by the controller with PRACT=1.
870 */
871 if (ns && ns->ms && !blk_integrity_rq(req)) {
872 if (!(ns->pi_type && ns->ms == 8) &&
873 req->cmd_type != REQ_TYPE_DRV_PRIV) {
874 blk_mq_complete_request(req, -EFAULT);
875 return BLK_MQ_RQ_QUEUE_OK;
876 }
877 }
878
879 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
880 if (!iod)
881 return BLK_MQ_RQ_QUEUE_BUSY;
882
883 if (req->cmd_flags & REQ_DISCARD) {
884 void *range;
885 /*
886 * We reuse the small pool to allocate the 16-byte range here
887 * as it is not worth having a special pool for these or
888 * additional cases to handle freeing the iod.
889 */
890 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
891 &iod->first_dma);
892 if (!range)
893 goto retry_cmd;
894 iod_list(iod)[0] = (__le64 *)range;
895 iod->npages = 0;
896 } else if (req->nr_phys_segments) {
897 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
898
899 sg_init_table(iod->sg, req->nr_phys_segments);
900 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
901 if (!iod->nents)
902 goto error_cmd;
903
904 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
905 goto retry_cmd;
906
907 if (blk_rq_bytes(req) !=
908 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
909 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
910 goto retry_cmd;
911 }
912 if (blk_integrity_rq(req)) {
913 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
914 goto error_cmd;
915
916 sg_init_table(iod->meta_sg, 1);
917 if (blk_rq_map_integrity_sg(
918 req->q, req->bio, iod->meta_sg) != 1)
919 goto error_cmd;
920
921 if (rq_data_dir(req))
922 nvme_dif_remap(req, nvme_dif_prep);
923
924 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
925 goto error_cmd;
926 }
927 }
928
929 nvme_set_info(cmd, iod, req_completion);
930 spin_lock_irq(&nvmeq->q_lock);
931 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
932 nvme_submit_priv(nvmeq, req, iod);
933 else if (req->cmd_flags & REQ_DISCARD)
934 nvme_submit_discard(nvmeq, ns, req, iod);
935 else if (req->cmd_flags & REQ_FLUSH)
936 nvme_submit_flush(nvmeq, ns, req->tag);
937 else
938 nvme_submit_iod(nvmeq, iod, ns);
939
940 nvme_process_cq(nvmeq);
941 spin_unlock_irq(&nvmeq->q_lock);
942 return BLK_MQ_RQ_QUEUE_OK;
943
944 error_cmd:
945 nvme_free_iod(dev, iod);
946 return BLK_MQ_RQ_QUEUE_ERROR;
947 retry_cmd:
948 nvme_free_iod(dev, iod);
949 return BLK_MQ_RQ_QUEUE_BUSY;
950 }
951
952 static int nvme_process_cq(struct nvme_queue *nvmeq)
953 {
954 u16 head, phase;
955
956 head = nvmeq->cq_head;
957 phase = nvmeq->cq_phase;
958
959 for (;;) {
960 void *ctx;
961 nvme_completion_fn fn;
962 struct nvme_completion cqe = nvmeq->cqes[head];
963 if ((le16_to_cpu(cqe.status) & 1) != phase)
964 break;
965 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
966 if (++head == nvmeq->q_depth) {
967 head = 0;
968 phase = !phase;
969 }
970 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
971 fn(nvmeq, ctx, &cqe);
972 }
973
974 /* If the controller ignores the cq head doorbell and continuously
975 * writes to the queue, it is theoretically possible to wrap around
976 * the queue twice and mistakenly return IRQ_NONE. Linux only
977 * requires that 0.1% of your interrupts are handled, so this isn't
978 * a big problem.
979 */
980 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
981 return 0;
982
983 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
984 nvmeq->cq_head = head;
985 nvmeq->cq_phase = phase;
986
987 nvmeq->cqe_seen = 1;
988 return 1;
989 }
990
991 static irqreturn_t nvme_irq(int irq, void *data)
992 {
993 irqreturn_t result;
994 struct nvme_queue *nvmeq = data;
995 spin_lock(&nvmeq->q_lock);
996 nvme_process_cq(nvmeq);
997 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
998 nvmeq->cqe_seen = 0;
999 spin_unlock(&nvmeq->q_lock);
1000 return result;
1001 }
1002
1003 static irqreturn_t nvme_irq_check(int irq, void *data)
1004 {
1005 struct nvme_queue *nvmeq = data;
1006 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1007 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1008 return IRQ_NONE;
1009 return IRQ_WAKE_THREAD;
1010 }
1011
1012 /*
1013 * Returns 0 on success. If the result is negative, it's a Linux error code;
1014 * if the result is positive, it's an NVM Express status code
1015 */
1016 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1017 void *buffer, void __user *ubuffer, unsigned bufflen,
1018 u32 *result, unsigned timeout)
1019 {
1020 bool write = cmd->common.opcode & 1;
1021 struct bio *bio = NULL;
1022 struct request *req;
1023 int ret;
1024
1025 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
1026 if (IS_ERR(req))
1027 return PTR_ERR(req);
1028
1029 req->cmd_type = REQ_TYPE_DRV_PRIV;
1030 req->cmd_flags |= REQ_FAILFAST_DRIVER;
1031 req->__data_len = 0;
1032 req->__sector = (sector_t) -1;
1033 req->bio = req->biotail = NULL;
1034
1035 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
1036
1037 req->cmd = (unsigned char *)cmd;
1038 req->cmd_len = sizeof(struct nvme_command);
1039 req->special = (void *)0;
1040
1041 if (buffer && bufflen) {
1042 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1043 if (ret)
1044 goto out;
1045 } else if (ubuffer && bufflen) {
1046 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1047 if (ret)
1048 goto out;
1049 bio = req->bio;
1050 }
1051
1052 blk_execute_rq(req->q, NULL, req, 0);
1053 if (bio)
1054 blk_rq_unmap_user(bio);
1055 if (result)
1056 *result = (u32)(uintptr_t)req->special;
1057 ret = req->errors;
1058 out:
1059 blk_mq_free_request(req);
1060 return ret;
1061 }
1062
1063 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1064 void *buffer, unsigned bufflen)
1065 {
1066 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
1067 }
1068
1069 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1070 {
1071 struct nvme_queue *nvmeq = dev->queues[0];
1072 struct nvme_command c;
1073 struct nvme_cmd_info *cmd_info;
1074 struct request *req;
1075
1076 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
1077 if (IS_ERR(req))
1078 return PTR_ERR(req);
1079
1080 req->cmd_flags |= REQ_NO_TIMEOUT;
1081 cmd_info = blk_mq_rq_to_pdu(req);
1082 nvme_set_info(cmd_info, NULL, async_req_completion);
1083
1084 memset(&c, 0, sizeof(c));
1085 c.common.opcode = nvme_admin_async_event;
1086 c.common.command_id = req->tag;
1087
1088 blk_mq_free_request(req);
1089 __nvme_submit_cmd(nvmeq, &c);
1090 return 0;
1091 }
1092
1093 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1094 struct nvme_command *cmd,
1095 struct async_cmd_info *cmdinfo, unsigned timeout)
1096 {
1097 struct nvme_queue *nvmeq = dev->queues[0];
1098 struct request *req;
1099 struct nvme_cmd_info *cmd_rq;
1100
1101 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1102 if (IS_ERR(req))
1103 return PTR_ERR(req);
1104
1105 req->timeout = timeout;
1106 cmd_rq = blk_mq_rq_to_pdu(req);
1107 cmdinfo->req = req;
1108 nvme_set_info(cmd_rq, cmdinfo, async_completion);
1109 cmdinfo->status = -EINTR;
1110
1111 cmd->common.command_id = req->tag;
1112
1113 nvme_submit_cmd(nvmeq, cmd);
1114 return 0;
1115 }
1116
1117 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1118 {
1119 struct nvme_command c;
1120
1121 memset(&c, 0, sizeof(c));
1122 c.delete_queue.opcode = opcode;
1123 c.delete_queue.qid = cpu_to_le16(id);
1124
1125 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1126 }
1127
1128 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1129 struct nvme_queue *nvmeq)
1130 {
1131 struct nvme_command c;
1132 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1133
1134 /*
1135 * Note: we (ab)use the fact the the prp fields survive if no data
1136 * is attached to the request.
1137 */
1138 memset(&c, 0, sizeof(c));
1139 c.create_cq.opcode = nvme_admin_create_cq;
1140 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1141 c.create_cq.cqid = cpu_to_le16(qid);
1142 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1143 c.create_cq.cq_flags = cpu_to_le16(flags);
1144 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1145
1146 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1147 }
1148
1149 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1150 struct nvme_queue *nvmeq)
1151 {
1152 struct nvme_command c;
1153 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1154
1155 /*
1156 * Note: we (ab)use the fact the the prp fields survive if no data
1157 * is attached to the request.
1158 */
1159 memset(&c, 0, sizeof(c));
1160 c.create_sq.opcode = nvme_admin_create_sq;
1161 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1162 c.create_sq.sqid = cpu_to_le16(qid);
1163 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1164 c.create_sq.sq_flags = cpu_to_le16(flags);
1165 c.create_sq.cqid = cpu_to_le16(qid);
1166
1167 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1168 }
1169
1170 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1171 {
1172 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1173 }
1174
1175 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1176 {
1177 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1178 }
1179
1180 int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
1181 {
1182 struct nvme_command c = { };
1183 int error;
1184
1185 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1186 c.identify.opcode = nvme_admin_identify;
1187 c.identify.cns = cpu_to_le32(1);
1188
1189 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1190 if (!*id)
1191 return -ENOMEM;
1192
1193 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1194 sizeof(struct nvme_id_ctrl));
1195 if (error)
1196 kfree(*id);
1197 return error;
1198 }
1199
1200 int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1201 struct nvme_id_ns **id)
1202 {
1203 struct nvme_command c = { };
1204 int error;
1205
1206 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1207 c.identify.opcode = nvme_admin_identify,
1208 c.identify.nsid = cpu_to_le32(nsid),
1209
1210 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1211 if (!*id)
1212 return -ENOMEM;
1213
1214 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1215 sizeof(struct nvme_id_ns));
1216 if (error)
1217 kfree(*id);
1218 return error;
1219 }
1220
1221 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1222 dma_addr_t dma_addr, u32 *result)
1223 {
1224 struct nvme_command c;
1225
1226 memset(&c, 0, sizeof(c));
1227 c.features.opcode = nvme_admin_get_features;
1228 c.features.nsid = cpu_to_le32(nsid);
1229 c.features.prp1 = cpu_to_le64(dma_addr);
1230 c.features.fid = cpu_to_le32(fid);
1231
1232 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1233 result, 0);
1234 }
1235
1236 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1237 dma_addr_t dma_addr, u32 *result)
1238 {
1239 struct nvme_command c;
1240
1241 memset(&c, 0, sizeof(c));
1242 c.features.opcode = nvme_admin_set_features;
1243 c.features.prp1 = cpu_to_le64(dma_addr);
1244 c.features.fid = cpu_to_le32(fid);
1245 c.features.dword11 = cpu_to_le32(dword11);
1246
1247 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1248 result, 0);
1249 }
1250
1251 int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1252 {
1253 struct nvme_command c = { };
1254 int error;
1255
1256 c.common.opcode = nvme_admin_get_log_page,
1257 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1258 c.common.cdw10[0] = cpu_to_le32(
1259 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1260 NVME_LOG_SMART),
1261
1262 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1263 if (!*log)
1264 return -ENOMEM;
1265
1266 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1267 sizeof(struct nvme_smart_log));
1268 if (error)
1269 kfree(*log);
1270 return error;
1271 }
1272
1273 /**
1274 * nvme_abort_req - Attempt aborting a request
1275 *
1276 * Schedule controller reset if the command was already aborted once before and
1277 * still hasn't been returned to the driver, or if this is the admin queue.
1278 */
1279 static void nvme_abort_req(struct request *req)
1280 {
1281 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1282 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1283 struct nvme_dev *dev = nvmeq->dev;
1284 struct request *abort_req;
1285 struct nvme_cmd_info *abort_cmd;
1286 struct nvme_command cmd;
1287
1288 if (!nvmeq->qid || cmd_rq->aborted) {
1289 spin_lock(&dev_list_lock);
1290 if (!__nvme_reset(dev)) {
1291 dev_warn(dev->dev,
1292 "I/O %d QID %d timeout, reset controller\n",
1293 req->tag, nvmeq->qid);
1294 }
1295 spin_unlock(&dev_list_lock);
1296 return;
1297 }
1298
1299 if (!dev->abort_limit)
1300 return;
1301
1302 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1303 false);
1304 if (IS_ERR(abort_req))
1305 return;
1306
1307 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1308 nvme_set_info(abort_cmd, abort_req, abort_completion);
1309
1310 memset(&cmd, 0, sizeof(cmd));
1311 cmd.abort.opcode = nvme_admin_abort_cmd;
1312 cmd.abort.cid = req->tag;
1313 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1314 cmd.abort.command_id = abort_req->tag;
1315
1316 --dev->abort_limit;
1317 cmd_rq->aborted = 1;
1318
1319 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1320 nvmeq->qid);
1321 nvme_submit_cmd(dev->queues[0], &cmd);
1322 }
1323
1324 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1325 {
1326 struct nvme_queue *nvmeq = data;
1327 void *ctx;
1328 nvme_completion_fn fn;
1329 struct nvme_cmd_info *cmd;
1330 struct nvme_completion cqe;
1331
1332 if (!blk_mq_request_started(req))
1333 return;
1334
1335 cmd = blk_mq_rq_to_pdu(req);
1336
1337 if (cmd->ctx == CMD_CTX_CANCELLED)
1338 return;
1339
1340 if (blk_queue_dying(req->q))
1341 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1342 else
1343 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1344
1345
1346 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1347 req->tag, nvmeq->qid);
1348 ctx = cancel_cmd_info(cmd, &fn);
1349 fn(nvmeq, ctx, &cqe);
1350 }
1351
1352 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1353 {
1354 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1355 struct nvme_queue *nvmeq = cmd->nvmeq;
1356
1357 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1358 nvmeq->qid);
1359 spin_lock_irq(&nvmeq->q_lock);
1360 nvme_abort_req(req);
1361 spin_unlock_irq(&nvmeq->q_lock);
1362
1363 /*
1364 * The aborted req will be completed on receiving the abort req.
1365 * We enable the timer again. If hit twice, it'll cause a device reset,
1366 * as the device then is in a faulty state.
1367 */
1368 return BLK_EH_RESET_TIMER;
1369 }
1370
1371 static void nvme_free_queue(struct nvme_queue *nvmeq)
1372 {
1373 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1374 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1375 if (nvmeq->sq_cmds)
1376 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1377 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1378 kfree(nvmeq);
1379 }
1380
1381 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1382 {
1383 int i;
1384
1385 for (i = dev->queue_count - 1; i >= lowest; i--) {
1386 struct nvme_queue *nvmeq = dev->queues[i];
1387 dev->queue_count--;
1388 dev->queues[i] = NULL;
1389 nvme_free_queue(nvmeq);
1390 }
1391 }
1392
1393 /**
1394 * nvme_suspend_queue - put queue into suspended state
1395 * @nvmeq - queue to suspend
1396 */
1397 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1398 {
1399 int vector;
1400
1401 spin_lock_irq(&nvmeq->q_lock);
1402 if (nvmeq->cq_vector == -1) {
1403 spin_unlock_irq(&nvmeq->q_lock);
1404 return 1;
1405 }
1406 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1407 nvmeq->dev->online_queues--;
1408 nvmeq->cq_vector = -1;
1409 spin_unlock_irq(&nvmeq->q_lock);
1410
1411 if (!nvmeq->qid && nvmeq->dev->admin_q)
1412 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1413
1414 irq_set_affinity_hint(vector, NULL);
1415 free_irq(vector, nvmeq);
1416
1417 return 0;
1418 }
1419
1420 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1421 {
1422 spin_lock_irq(&nvmeq->q_lock);
1423 if (nvmeq->tags && *nvmeq->tags)
1424 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1425 spin_unlock_irq(&nvmeq->q_lock);
1426 }
1427
1428 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1429 {
1430 struct nvme_queue *nvmeq = dev->queues[qid];
1431
1432 if (!nvmeq)
1433 return;
1434 if (nvme_suspend_queue(nvmeq))
1435 return;
1436
1437 /* Don't tell the adapter to delete the admin queue.
1438 * Don't tell a removed adapter to delete IO queues. */
1439 if (qid && readl(&dev->bar->csts) != -1) {
1440 adapter_delete_sq(dev, qid);
1441 adapter_delete_cq(dev, qid);
1442 }
1443
1444 spin_lock_irq(&nvmeq->q_lock);
1445 nvme_process_cq(nvmeq);
1446 spin_unlock_irq(&nvmeq->q_lock);
1447 }
1448
1449 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1450 int entry_size)
1451 {
1452 int q_depth = dev->q_depth;
1453 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1454
1455 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1456 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1457 mem_per_q = round_down(mem_per_q, dev->page_size);
1458 q_depth = div_u64(mem_per_q, entry_size);
1459
1460 /*
1461 * Ensure the reduced q_depth is above some threshold where it
1462 * would be better to map queues in system memory with the
1463 * original depth
1464 */
1465 if (q_depth < 64)
1466 return -ENOMEM;
1467 }
1468
1469 return q_depth;
1470 }
1471
1472 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1473 int qid, int depth)
1474 {
1475 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1476 unsigned offset = (qid - 1) *
1477 roundup(SQ_SIZE(depth), dev->page_size);
1478 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1479 nvmeq->sq_cmds_io = dev->cmb + offset;
1480 } else {
1481 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1482 &nvmeq->sq_dma_addr, GFP_KERNEL);
1483 if (!nvmeq->sq_cmds)
1484 return -ENOMEM;
1485 }
1486
1487 return 0;
1488 }
1489
1490 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1491 int depth)
1492 {
1493 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1494 if (!nvmeq)
1495 return NULL;
1496
1497 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1498 &nvmeq->cq_dma_addr, GFP_KERNEL);
1499 if (!nvmeq->cqes)
1500 goto free_nvmeq;
1501
1502 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1503 goto free_cqdma;
1504
1505 nvmeq->q_dmadev = dev->dev;
1506 nvmeq->dev = dev;
1507 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1508 dev->instance, qid);
1509 spin_lock_init(&nvmeq->q_lock);
1510 nvmeq->cq_head = 0;
1511 nvmeq->cq_phase = 1;
1512 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1513 nvmeq->q_depth = depth;
1514 nvmeq->qid = qid;
1515 nvmeq->cq_vector = -1;
1516 dev->queues[qid] = nvmeq;
1517
1518 /* make sure queue descriptor is set before queue count, for kthread */
1519 mb();
1520 dev->queue_count++;
1521
1522 return nvmeq;
1523
1524 free_cqdma:
1525 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1526 nvmeq->cq_dma_addr);
1527 free_nvmeq:
1528 kfree(nvmeq);
1529 return NULL;
1530 }
1531
1532 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1533 const char *name)
1534 {
1535 if (use_threaded_interrupts)
1536 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1537 nvme_irq_check, nvme_irq, IRQF_SHARED,
1538 name, nvmeq);
1539 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1540 IRQF_SHARED, name, nvmeq);
1541 }
1542
1543 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1544 {
1545 struct nvme_dev *dev = nvmeq->dev;
1546
1547 spin_lock_irq(&nvmeq->q_lock);
1548 nvmeq->sq_tail = 0;
1549 nvmeq->cq_head = 0;
1550 nvmeq->cq_phase = 1;
1551 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1552 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1553 dev->online_queues++;
1554 spin_unlock_irq(&nvmeq->q_lock);
1555 }
1556
1557 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1558 {
1559 struct nvme_dev *dev = nvmeq->dev;
1560 int result;
1561
1562 nvmeq->cq_vector = qid - 1;
1563 result = adapter_alloc_cq(dev, qid, nvmeq);
1564 if (result < 0)
1565 return result;
1566
1567 result = adapter_alloc_sq(dev, qid, nvmeq);
1568 if (result < 0)
1569 goto release_cq;
1570
1571 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1572 if (result < 0)
1573 goto release_sq;
1574
1575 nvme_init_queue(nvmeq, qid);
1576 return result;
1577
1578 release_sq:
1579 adapter_delete_sq(dev, qid);
1580 release_cq:
1581 adapter_delete_cq(dev, qid);
1582 return result;
1583 }
1584
1585 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1586 {
1587 unsigned long timeout;
1588 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1589
1590 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1591
1592 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1593 msleep(100);
1594 if (fatal_signal_pending(current))
1595 return -EINTR;
1596 if (time_after(jiffies, timeout)) {
1597 dev_err(dev->dev,
1598 "Device not ready; aborting %s\n", enabled ?
1599 "initialisation" : "reset");
1600 return -ENODEV;
1601 }
1602 }
1603
1604 return 0;
1605 }
1606
1607 /*
1608 * If the device has been passed off to us in an enabled state, just clear
1609 * the enabled bit. The spec says we should set the 'shutdown notification
1610 * bits', but doing so may cause the device to complete commands to the
1611 * admin queue ... and we don't know what memory that might be pointing at!
1612 */
1613 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1614 {
1615 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1616 dev->ctrl_config &= ~NVME_CC_ENABLE;
1617 writel(dev->ctrl_config, &dev->bar->cc);
1618
1619 return nvme_wait_ready(dev, cap, false);
1620 }
1621
1622 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1623 {
1624 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1625 dev->ctrl_config |= NVME_CC_ENABLE;
1626 writel(dev->ctrl_config, &dev->bar->cc);
1627
1628 return nvme_wait_ready(dev, cap, true);
1629 }
1630
1631 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1632 {
1633 unsigned long timeout;
1634
1635 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1636 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1637
1638 writel(dev->ctrl_config, &dev->bar->cc);
1639
1640 timeout = SHUTDOWN_TIMEOUT + jiffies;
1641 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1642 NVME_CSTS_SHST_CMPLT) {
1643 msleep(100);
1644 if (fatal_signal_pending(current))
1645 return -EINTR;
1646 if (time_after(jiffies, timeout)) {
1647 dev_err(dev->dev,
1648 "Device shutdown incomplete; abort shutdown\n");
1649 return -ENODEV;
1650 }
1651 }
1652
1653 return 0;
1654 }
1655
1656 static struct blk_mq_ops nvme_mq_admin_ops = {
1657 .queue_rq = nvme_queue_rq,
1658 .map_queue = blk_mq_map_queue,
1659 .init_hctx = nvme_admin_init_hctx,
1660 .exit_hctx = nvme_admin_exit_hctx,
1661 .init_request = nvme_admin_init_request,
1662 .timeout = nvme_timeout,
1663 };
1664
1665 static struct blk_mq_ops nvme_mq_ops = {
1666 .queue_rq = nvme_queue_rq,
1667 .map_queue = blk_mq_map_queue,
1668 .init_hctx = nvme_init_hctx,
1669 .init_request = nvme_init_request,
1670 .timeout = nvme_timeout,
1671 };
1672
1673 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1674 {
1675 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1676 blk_cleanup_queue(dev->admin_q);
1677 blk_mq_free_tag_set(&dev->admin_tagset);
1678 }
1679 }
1680
1681 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1682 {
1683 if (!dev->admin_q) {
1684 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1685 dev->admin_tagset.nr_hw_queues = 1;
1686 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1687 dev->admin_tagset.reserved_tags = 1;
1688 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1689 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1690 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1691 dev->admin_tagset.driver_data = dev;
1692
1693 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1694 return -ENOMEM;
1695
1696 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1697 if (IS_ERR(dev->admin_q)) {
1698 blk_mq_free_tag_set(&dev->admin_tagset);
1699 return -ENOMEM;
1700 }
1701 if (!blk_get_queue(dev->admin_q)) {
1702 nvme_dev_remove_admin(dev);
1703 dev->admin_q = NULL;
1704 return -ENODEV;
1705 }
1706 } else
1707 blk_mq_unfreeze_queue(dev->admin_q);
1708
1709 return 0;
1710 }
1711
1712 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1713 {
1714 int result;
1715 u32 aqa;
1716 u64 cap = readq(&dev->bar->cap);
1717 struct nvme_queue *nvmeq;
1718 unsigned page_shift = PAGE_SHIFT;
1719 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1720 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1721
1722 if (page_shift < dev_page_min) {
1723 dev_err(dev->dev,
1724 "Minimum device page size (%u) too large for "
1725 "host (%u)\n", 1 << dev_page_min,
1726 1 << page_shift);
1727 return -ENODEV;
1728 }
1729 if (page_shift > dev_page_max) {
1730 dev_info(dev->dev,
1731 "Device maximum page size (%u) smaller than "
1732 "host (%u); enabling work-around\n",
1733 1 << dev_page_max, 1 << page_shift);
1734 page_shift = dev_page_max;
1735 }
1736
1737 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1738 NVME_CAP_NSSRC(cap) : 0;
1739
1740 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1741 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1742
1743 result = nvme_disable_ctrl(dev, cap);
1744 if (result < 0)
1745 return result;
1746
1747 nvmeq = dev->queues[0];
1748 if (!nvmeq) {
1749 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1750 if (!nvmeq)
1751 return -ENOMEM;
1752 }
1753
1754 aqa = nvmeq->q_depth - 1;
1755 aqa |= aqa << 16;
1756
1757 dev->page_size = 1 << page_shift;
1758
1759 dev->ctrl_config = NVME_CC_CSS_NVM;
1760 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1761 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1762 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1763
1764 writel(aqa, &dev->bar->aqa);
1765 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1766 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1767
1768 result = nvme_enable_ctrl(dev, cap);
1769 if (result)
1770 goto free_nvmeq;
1771
1772 nvmeq->cq_vector = 0;
1773 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1774 if (result) {
1775 nvmeq->cq_vector = -1;
1776 goto free_nvmeq;
1777 }
1778
1779 return result;
1780
1781 free_nvmeq:
1782 nvme_free_queues(dev, 0);
1783 return result;
1784 }
1785
1786 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1787 {
1788 struct nvme_dev *dev = ns->dev;
1789 struct nvme_user_io io;
1790 struct nvme_command c;
1791 unsigned length, meta_len;
1792 int status, write;
1793 dma_addr_t meta_dma = 0;
1794 void *meta = NULL;
1795 void __user *metadata;
1796
1797 if (copy_from_user(&io, uio, sizeof(io)))
1798 return -EFAULT;
1799
1800 switch (io.opcode) {
1801 case nvme_cmd_write:
1802 case nvme_cmd_read:
1803 case nvme_cmd_compare:
1804 break;
1805 default:
1806 return -EINVAL;
1807 }
1808
1809 length = (io.nblocks + 1) << ns->lba_shift;
1810 meta_len = (io.nblocks + 1) * ns->ms;
1811 metadata = (void __user *)(uintptr_t)io.metadata;
1812 write = io.opcode & 1;
1813
1814 if (ns->ext) {
1815 length += meta_len;
1816 meta_len = 0;
1817 }
1818 if (meta_len) {
1819 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1820 return -EINVAL;
1821
1822 meta = dma_alloc_coherent(dev->dev, meta_len,
1823 &meta_dma, GFP_KERNEL);
1824
1825 if (!meta) {
1826 status = -ENOMEM;
1827 goto unmap;
1828 }
1829 if (write) {
1830 if (copy_from_user(meta, metadata, meta_len)) {
1831 status = -EFAULT;
1832 goto unmap;
1833 }
1834 }
1835 }
1836
1837 memset(&c, 0, sizeof(c));
1838 c.rw.opcode = io.opcode;
1839 c.rw.flags = io.flags;
1840 c.rw.nsid = cpu_to_le32(ns->ns_id);
1841 c.rw.slba = cpu_to_le64(io.slba);
1842 c.rw.length = cpu_to_le16(io.nblocks);
1843 c.rw.control = cpu_to_le16(io.control);
1844 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1845 c.rw.reftag = cpu_to_le32(io.reftag);
1846 c.rw.apptag = cpu_to_le16(io.apptag);
1847 c.rw.appmask = cpu_to_le16(io.appmask);
1848 c.rw.metadata = cpu_to_le64(meta_dma);
1849
1850 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1851 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
1852 unmap:
1853 if (meta) {
1854 if (status == NVME_SC_SUCCESS && !write) {
1855 if (copy_to_user(metadata, meta, meta_len))
1856 status = -EFAULT;
1857 }
1858 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
1859 }
1860 return status;
1861 }
1862
1863 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1864 struct nvme_passthru_cmd __user *ucmd)
1865 {
1866 struct nvme_passthru_cmd cmd;
1867 struct nvme_command c;
1868 unsigned timeout = 0;
1869 int status;
1870
1871 if (!capable(CAP_SYS_ADMIN))
1872 return -EACCES;
1873 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1874 return -EFAULT;
1875
1876 memset(&c, 0, sizeof(c));
1877 c.common.opcode = cmd.opcode;
1878 c.common.flags = cmd.flags;
1879 c.common.nsid = cpu_to_le32(cmd.nsid);
1880 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1881 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1882 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1883 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1884 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1885 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1886 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1887 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1888
1889 if (cmd.timeout_ms)
1890 timeout = msecs_to_jiffies(cmd.timeout_ms);
1891
1892 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
1893 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1894 &cmd.result, timeout);
1895 if (status >= 0) {
1896 if (put_user(cmd.result, &ucmd->result))
1897 return -EFAULT;
1898 }
1899
1900 return status;
1901 }
1902
1903 static int nvme_subsys_reset(struct nvme_dev *dev)
1904 {
1905 if (!dev->subsystem)
1906 return -ENOTTY;
1907
1908 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1909 return 0;
1910 }
1911
1912 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1913 unsigned long arg)
1914 {
1915 struct nvme_ns *ns = bdev->bd_disk->private_data;
1916
1917 switch (cmd) {
1918 case NVME_IOCTL_ID:
1919 force_successful_syscall_return();
1920 return ns->ns_id;
1921 case NVME_IOCTL_ADMIN_CMD:
1922 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1923 case NVME_IOCTL_IO_CMD:
1924 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1925 case NVME_IOCTL_SUBMIT_IO:
1926 return nvme_submit_io(ns, (void __user *)arg);
1927 case SG_GET_VERSION_NUM:
1928 return nvme_sg_get_version_num((void __user *)arg);
1929 case SG_IO:
1930 return nvme_sg_io(ns, (void __user *)arg);
1931 default:
1932 return -ENOTTY;
1933 }
1934 }
1935
1936 #ifdef CONFIG_COMPAT
1937 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1938 unsigned int cmd, unsigned long arg)
1939 {
1940 switch (cmd) {
1941 case SG_IO:
1942 return -ENOIOCTLCMD;
1943 }
1944 return nvme_ioctl(bdev, mode, cmd, arg);
1945 }
1946 #else
1947 #define nvme_compat_ioctl NULL
1948 #endif
1949
1950 static void nvme_free_dev(struct kref *kref);
1951 static void nvme_free_ns(struct kref *kref)
1952 {
1953 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1954
1955 if (ns->type == NVME_NS_LIGHTNVM)
1956 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1957
1958 spin_lock(&dev_list_lock);
1959 ns->disk->private_data = NULL;
1960 spin_unlock(&dev_list_lock);
1961
1962 kref_put(&ns->dev->kref, nvme_free_dev);
1963 put_disk(ns->disk);
1964 kfree(ns);
1965 }
1966
1967 static int nvme_open(struct block_device *bdev, fmode_t mode)
1968 {
1969 int ret = 0;
1970 struct nvme_ns *ns;
1971
1972 spin_lock(&dev_list_lock);
1973 ns = bdev->bd_disk->private_data;
1974 if (!ns)
1975 ret = -ENXIO;
1976 else if (!kref_get_unless_zero(&ns->kref))
1977 ret = -ENXIO;
1978 spin_unlock(&dev_list_lock);
1979
1980 return ret;
1981 }
1982
1983 static void nvme_release(struct gendisk *disk, fmode_t mode)
1984 {
1985 struct nvme_ns *ns = disk->private_data;
1986 kref_put(&ns->kref, nvme_free_ns);
1987 }
1988
1989 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1990 {
1991 /* some standard values */
1992 geo->heads = 1 << 6;
1993 geo->sectors = 1 << 5;
1994 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1995 return 0;
1996 }
1997
1998 static void nvme_config_discard(struct nvme_ns *ns)
1999 {
2000 u32 logical_block_size = queue_logical_block_size(ns->queue);
2001 ns->queue->limits.discard_zeroes_data = 0;
2002 ns->queue->limits.discard_alignment = logical_block_size;
2003 ns->queue->limits.discard_granularity = logical_block_size;
2004 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
2005 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2006 }
2007
2008 static int nvme_revalidate_disk(struct gendisk *disk)
2009 {
2010 struct nvme_ns *ns = disk->private_data;
2011 struct nvme_dev *dev = ns->dev;
2012 struct nvme_id_ns *id;
2013 u8 lbaf, pi_type;
2014 u16 old_ms;
2015 unsigned short bs;
2016
2017 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
2018 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2019 dev->instance, ns->ns_id);
2020 return -ENODEV;
2021 }
2022 if (id->ncap == 0) {
2023 kfree(id);
2024 return -ENODEV;
2025 }
2026
2027 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2028 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2029 dev_warn(dev->dev,
2030 "%s: LightNVM init failure\n", __func__);
2031 kfree(id);
2032 return -ENODEV;
2033 }
2034 ns->type = NVME_NS_LIGHTNVM;
2035 }
2036
2037 old_ms = ns->ms;
2038 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2039 ns->lba_shift = id->lbaf[lbaf].ds;
2040 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2041 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
2042
2043 /*
2044 * If identify namespace failed, use default 512 byte block size so
2045 * block layer can use before failing read/write for 0 capacity.
2046 */
2047 if (ns->lba_shift == 0)
2048 ns->lba_shift = 9;
2049 bs = 1 << ns->lba_shift;
2050
2051 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2052 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2053 id->dps & NVME_NS_DPS_PI_MASK : 0;
2054
2055 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2056 ns->ms != old_ms ||
2057 bs != queue_logical_block_size(disk->queue) ||
2058 (ns->ms && ns->ext)))
2059 blk_integrity_unregister(disk);
2060
2061 ns->pi_type = pi_type;
2062 blk_queue_logical_block_size(ns->queue, bs);
2063
2064 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
2065 !ns->ext)
2066 nvme_init_integrity(ns);
2067
2068 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2069 !blk_get_integrity(disk)) ||
2070 ns->type == NVME_NS_LIGHTNVM)
2071 set_capacity(disk, 0);
2072 else
2073 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2074
2075 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2076 nvme_config_discard(ns);
2077
2078 kfree(id);
2079 return 0;
2080 }
2081
2082 static const struct block_device_operations nvme_fops = {
2083 .owner = THIS_MODULE,
2084 .ioctl = nvme_ioctl,
2085 .compat_ioctl = nvme_compat_ioctl,
2086 .open = nvme_open,
2087 .release = nvme_release,
2088 .getgeo = nvme_getgeo,
2089 .revalidate_disk= nvme_revalidate_disk,
2090 };
2091
2092 static int nvme_kthread(void *data)
2093 {
2094 struct nvme_dev *dev, *next;
2095
2096 while (!kthread_should_stop()) {
2097 set_current_state(TASK_INTERRUPTIBLE);
2098 spin_lock(&dev_list_lock);
2099 list_for_each_entry_safe(dev, next, &dev_list, node) {
2100 int i;
2101 u32 csts = readl(&dev->bar->csts);
2102
2103 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2104 csts & NVME_CSTS_CFS) {
2105 if (!__nvme_reset(dev)) {
2106 dev_warn(dev->dev,
2107 "Failed status: %x, reset controller\n",
2108 readl(&dev->bar->csts));
2109 }
2110 continue;
2111 }
2112 for (i = 0; i < dev->queue_count; i++) {
2113 struct nvme_queue *nvmeq = dev->queues[i];
2114 if (!nvmeq)
2115 continue;
2116 spin_lock_irq(&nvmeq->q_lock);
2117 nvme_process_cq(nvmeq);
2118
2119 while ((i == 0) && (dev->event_limit > 0)) {
2120 if (nvme_submit_async_admin_req(dev))
2121 break;
2122 dev->event_limit--;
2123 }
2124 spin_unlock_irq(&nvmeq->q_lock);
2125 }
2126 }
2127 spin_unlock(&dev_list_lock);
2128 schedule_timeout(round_jiffies_relative(HZ));
2129 }
2130 return 0;
2131 }
2132
2133 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2134 {
2135 struct nvme_ns *ns;
2136 struct gendisk *disk;
2137 int node = dev_to_node(dev->dev);
2138
2139 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2140 if (!ns)
2141 return;
2142
2143 ns->queue = blk_mq_init_queue(&dev->tagset);
2144 if (IS_ERR(ns->queue))
2145 goto out_free_ns;
2146 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2147 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2148 ns->dev = dev;
2149 ns->queue->queuedata = ns;
2150
2151 disk = alloc_disk_node(0, node);
2152 if (!disk)
2153 goto out_free_queue;
2154
2155 kref_init(&ns->kref);
2156 ns->ns_id = nsid;
2157 ns->disk = disk;
2158 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2159 list_add_tail(&ns->list, &dev->namespaces);
2160
2161 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2162 if (dev->max_hw_sectors) {
2163 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2164 blk_queue_max_segments(ns->queue,
2165 ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
2166 }
2167 if (dev->stripe_size)
2168 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2169 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2170 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2171 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
2172
2173 disk->major = nvme_major;
2174 disk->first_minor = 0;
2175 disk->fops = &nvme_fops;
2176 disk->private_data = ns;
2177 disk->queue = ns->queue;
2178 disk->driverfs_dev = dev->device;
2179 disk->flags = GENHD_FL_EXT_DEVT;
2180 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2181
2182 /*
2183 * Initialize capacity to 0 until we establish the namespace format and
2184 * setup integrity extentions if necessary. The revalidate_disk after
2185 * add_disk allows the driver to register with integrity if the format
2186 * requires it.
2187 */
2188 set_capacity(disk, 0);
2189 if (nvme_revalidate_disk(ns->disk))
2190 goto out_free_disk;
2191
2192 kref_get(&dev->kref);
2193 if (ns->type != NVME_NS_LIGHTNVM) {
2194 add_disk(ns->disk);
2195 if (ns->ms) {
2196 struct block_device *bd = bdget_disk(ns->disk, 0);
2197 if (!bd)
2198 return;
2199 if (blkdev_get(bd, FMODE_READ, NULL)) {
2200 bdput(bd);
2201 return;
2202 }
2203 blkdev_reread_part(bd);
2204 blkdev_put(bd, FMODE_READ);
2205 }
2206 }
2207 return;
2208 out_free_disk:
2209 kfree(disk);
2210 list_del(&ns->list);
2211 out_free_queue:
2212 blk_cleanup_queue(ns->queue);
2213 out_free_ns:
2214 kfree(ns);
2215 }
2216
2217 /*
2218 * Create I/O queues. Failing to create an I/O queue is not an issue,
2219 * we can continue with less than the desired amount of queues, and
2220 * even a controller without I/O queues an still be used to issue
2221 * admin commands. This might be useful to upgrade a buggy firmware
2222 * for example.
2223 */
2224 static void nvme_create_io_queues(struct nvme_dev *dev)
2225 {
2226 unsigned i;
2227
2228 for (i = dev->queue_count; i <= dev->max_qid; i++)
2229 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2230 break;
2231
2232 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2233 if (nvme_create_queue(dev->queues[i], i)) {
2234 nvme_free_queues(dev, i);
2235 break;
2236 }
2237 }
2238
2239 static int set_queue_count(struct nvme_dev *dev, int count)
2240 {
2241 int status;
2242 u32 result;
2243 u32 q_count = (count - 1) | ((count - 1) << 16);
2244
2245 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2246 &result);
2247 if (status < 0)
2248 return status;
2249 if (status > 0) {
2250 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
2251 return 0;
2252 }
2253 return min(result & 0xffff, result >> 16) + 1;
2254 }
2255
2256 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2257 {
2258 u64 szu, size, offset;
2259 u32 cmbloc;
2260 resource_size_t bar_size;
2261 struct pci_dev *pdev = to_pci_dev(dev->dev);
2262 void __iomem *cmb;
2263 dma_addr_t dma_addr;
2264
2265 if (!use_cmb_sqes)
2266 return NULL;
2267
2268 dev->cmbsz = readl(&dev->bar->cmbsz);
2269 if (!(NVME_CMB_SZ(dev->cmbsz)))
2270 return NULL;
2271
2272 cmbloc = readl(&dev->bar->cmbloc);
2273
2274 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2275 size = szu * NVME_CMB_SZ(dev->cmbsz);
2276 offset = szu * NVME_CMB_OFST(cmbloc);
2277 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2278
2279 if (offset > bar_size)
2280 return NULL;
2281
2282 /*
2283 * Controllers may support a CMB size larger than their BAR,
2284 * for example, due to being behind a bridge. Reduce the CMB to
2285 * the reported size of the BAR
2286 */
2287 if (size > bar_size - offset)
2288 size = bar_size - offset;
2289
2290 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2291 cmb = ioremap_wc(dma_addr, size);
2292 if (!cmb)
2293 return NULL;
2294
2295 dev->cmb_dma_addr = dma_addr;
2296 dev->cmb_size = size;
2297 return cmb;
2298 }
2299
2300 static inline void nvme_release_cmb(struct nvme_dev *dev)
2301 {
2302 if (dev->cmb) {
2303 iounmap(dev->cmb);
2304 dev->cmb = NULL;
2305 }
2306 }
2307
2308 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2309 {
2310 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2311 }
2312
2313 static int nvme_setup_io_queues(struct nvme_dev *dev)
2314 {
2315 struct nvme_queue *adminq = dev->queues[0];
2316 struct pci_dev *pdev = to_pci_dev(dev->dev);
2317 int result, i, vecs, nr_io_queues, size;
2318
2319 nr_io_queues = num_possible_cpus();
2320 result = set_queue_count(dev, nr_io_queues);
2321 if (result <= 0)
2322 return result;
2323 if (result < nr_io_queues)
2324 nr_io_queues = result;
2325
2326 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2327 result = nvme_cmb_qdepth(dev, nr_io_queues,
2328 sizeof(struct nvme_command));
2329 if (result > 0)
2330 dev->q_depth = result;
2331 else
2332 nvme_release_cmb(dev);
2333 }
2334
2335 size = db_bar_size(dev, nr_io_queues);
2336 if (size > 8192) {
2337 iounmap(dev->bar);
2338 do {
2339 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2340 if (dev->bar)
2341 break;
2342 if (!--nr_io_queues)
2343 return -ENOMEM;
2344 size = db_bar_size(dev, nr_io_queues);
2345 } while (1);
2346 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2347 adminq->q_db = dev->dbs;
2348 }
2349
2350 /* Deregister the admin queue's interrupt */
2351 free_irq(dev->entry[0].vector, adminq);
2352
2353 /*
2354 * If we enable msix early due to not intx, disable it again before
2355 * setting up the full range we need.
2356 */
2357 if (!pdev->irq)
2358 pci_disable_msix(pdev);
2359
2360 for (i = 0; i < nr_io_queues; i++)
2361 dev->entry[i].entry = i;
2362 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2363 if (vecs < 0) {
2364 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2365 if (vecs < 0) {
2366 vecs = 1;
2367 } else {
2368 for (i = 0; i < vecs; i++)
2369 dev->entry[i].vector = i + pdev->irq;
2370 }
2371 }
2372
2373 /*
2374 * Should investigate if there's a performance win from allocating
2375 * more queues than interrupt vectors; it might allow the submission
2376 * path to scale better, even if the receive path is limited by the
2377 * number of interrupts.
2378 */
2379 nr_io_queues = vecs;
2380 dev->max_qid = nr_io_queues;
2381
2382 result = queue_request_irq(dev, adminq, adminq->irqname);
2383 if (result) {
2384 adminq->cq_vector = -1;
2385 goto free_queues;
2386 }
2387
2388 /* Free previously allocated queues that are no longer usable */
2389 nvme_free_queues(dev, nr_io_queues + 1);
2390 nvme_create_io_queues(dev);
2391
2392 return 0;
2393
2394 free_queues:
2395 nvme_free_queues(dev, 1);
2396 return result;
2397 }
2398
2399 static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2400 {
2401 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2402 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2403
2404 return nsa->ns_id - nsb->ns_id;
2405 }
2406
2407 static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2408 {
2409 struct nvme_ns *ns;
2410
2411 list_for_each_entry(ns, &dev->namespaces, list) {
2412 if (ns->ns_id == nsid)
2413 return ns;
2414 if (ns->ns_id > nsid)
2415 break;
2416 }
2417 return NULL;
2418 }
2419
2420 static inline bool nvme_io_incapable(struct nvme_dev *dev)
2421 {
2422 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2423 dev->online_queues < 2);
2424 }
2425
2426 static void nvme_ns_remove(struct nvme_ns *ns)
2427 {
2428 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2429
2430 if (kill)
2431 blk_set_queue_dying(ns->queue);
2432 if (ns->disk->flags & GENHD_FL_UP) {
2433 if (blk_get_integrity(ns->disk))
2434 blk_integrity_unregister(ns->disk);
2435 del_gendisk(ns->disk);
2436 }
2437 if (kill || !blk_queue_dying(ns->queue)) {
2438 blk_mq_abort_requeue_list(ns->queue);
2439 blk_cleanup_queue(ns->queue);
2440 }
2441 list_del_init(&ns->list);
2442 kref_put(&ns->kref, nvme_free_ns);
2443 }
2444
2445 static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2446 {
2447 struct nvme_ns *ns, *next;
2448 unsigned i;
2449
2450 for (i = 1; i <= nn; i++) {
2451 ns = nvme_find_ns(dev, i);
2452 if (ns) {
2453 if (revalidate_disk(ns->disk))
2454 nvme_ns_remove(ns);
2455 } else
2456 nvme_alloc_ns(dev, i);
2457 }
2458 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2459 if (ns->ns_id > nn)
2460 nvme_ns_remove(ns);
2461 }
2462 list_sort(NULL, &dev->namespaces, ns_cmp);
2463 }
2464
2465 static void nvme_set_irq_hints(struct nvme_dev *dev)
2466 {
2467 struct nvme_queue *nvmeq;
2468 int i;
2469
2470 for (i = 0; i < dev->online_queues; i++) {
2471 nvmeq = dev->queues[i];
2472
2473 if (!nvmeq->tags || !(*nvmeq->tags))
2474 continue;
2475
2476 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2477 blk_mq_tags_cpumask(*nvmeq->tags));
2478 }
2479 }
2480
2481 static void nvme_dev_scan(struct work_struct *work)
2482 {
2483 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2484 struct nvme_id_ctrl *ctrl;
2485
2486 if (!dev->tagset.tags)
2487 return;
2488 if (nvme_identify_ctrl(dev, &ctrl))
2489 return;
2490 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2491 kfree(ctrl);
2492 nvme_set_irq_hints(dev);
2493 }
2494
2495 /*
2496 * Return: error value if an error occurred setting up the queues or calling
2497 * Identify Device. 0 if these succeeded, even if adding some of the
2498 * namespaces failed. At the moment, these failures are silent. TBD which
2499 * failures should be reported.
2500 */
2501 static int nvme_dev_add(struct nvme_dev *dev)
2502 {
2503 struct pci_dev *pdev = to_pci_dev(dev->dev);
2504 int res;
2505 struct nvme_id_ctrl *ctrl;
2506 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2507
2508 res = nvme_identify_ctrl(dev, &ctrl);
2509 if (res) {
2510 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
2511 return -EIO;
2512 }
2513
2514 dev->oncs = le16_to_cpup(&ctrl->oncs);
2515 dev->abort_limit = ctrl->acl + 1;
2516 dev->vwc = ctrl->vwc;
2517 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2518 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2519 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2520 if (ctrl->mdts)
2521 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2522 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2523 (pdev->device == 0x0953) && ctrl->vs[3]) {
2524 unsigned int max_hw_sectors;
2525
2526 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2527 max_hw_sectors = dev->stripe_size >> (shift - 9);
2528 if (dev->max_hw_sectors) {
2529 dev->max_hw_sectors = min(max_hw_sectors,
2530 dev->max_hw_sectors);
2531 } else
2532 dev->max_hw_sectors = max_hw_sectors;
2533 }
2534 kfree(ctrl);
2535
2536 if (!dev->tagset.tags) {
2537 dev->tagset.ops = &nvme_mq_ops;
2538 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2539 dev->tagset.timeout = NVME_IO_TIMEOUT;
2540 dev->tagset.numa_node = dev_to_node(dev->dev);
2541 dev->tagset.queue_depth =
2542 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2543 dev->tagset.cmd_size = nvme_cmd_size(dev);
2544 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2545 dev->tagset.driver_data = dev;
2546
2547 if (blk_mq_alloc_tag_set(&dev->tagset))
2548 return 0;
2549 }
2550 schedule_work(&dev->scan_work);
2551 return 0;
2552 }
2553
2554 static int nvme_dev_map(struct nvme_dev *dev)
2555 {
2556 u64 cap;
2557 int bars, result = -ENOMEM;
2558 struct pci_dev *pdev = to_pci_dev(dev->dev);
2559
2560 if (pci_enable_device_mem(pdev))
2561 return result;
2562
2563 dev->entry[0].vector = pdev->irq;
2564 pci_set_master(pdev);
2565 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2566 if (!bars)
2567 goto disable_pci;
2568
2569 if (pci_request_selected_regions(pdev, bars, "nvme"))
2570 goto disable_pci;
2571
2572 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2573 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2574 goto disable;
2575
2576 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2577 if (!dev->bar)
2578 goto disable;
2579
2580 if (readl(&dev->bar->csts) == -1) {
2581 result = -ENODEV;
2582 goto unmap;
2583 }
2584
2585 /*
2586 * Some devices don't advertse INTx interrupts, pre-enable a single
2587 * MSIX vec for setup. We'll adjust this later.
2588 */
2589 if (!pdev->irq) {
2590 result = pci_enable_msix(pdev, dev->entry, 1);
2591 if (result < 0)
2592 goto unmap;
2593 }
2594
2595 cap = readq(&dev->bar->cap);
2596 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2597 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2598 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2599 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2600 dev->cmb = nvme_map_cmb(dev);
2601
2602 return 0;
2603
2604 unmap:
2605 iounmap(dev->bar);
2606 dev->bar = NULL;
2607 disable:
2608 pci_release_regions(pdev);
2609 disable_pci:
2610 pci_disable_device(pdev);
2611 return result;
2612 }
2613
2614 static void nvme_dev_unmap(struct nvme_dev *dev)
2615 {
2616 struct pci_dev *pdev = to_pci_dev(dev->dev);
2617
2618 if (pdev->msi_enabled)
2619 pci_disable_msi(pdev);
2620 else if (pdev->msix_enabled)
2621 pci_disable_msix(pdev);
2622
2623 if (dev->bar) {
2624 iounmap(dev->bar);
2625 dev->bar = NULL;
2626 pci_release_regions(pdev);
2627 }
2628
2629 if (pci_is_enabled(pdev))
2630 pci_disable_device(pdev);
2631 }
2632
2633 struct nvme_delq_ctx {
2634 struct task_struct *waiter;
2635 struct kthread_worker *worker;
2636 atomic_t refcount;
2637 };
2638
2639 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2640 {
2641 dq->waiter = current;
2642 mb();
2643
2644 for (;;) {
2645 set_current_state(TASK_KILLABLE);
2646 if (!atomic_read(&dq->refcount))
2647 break;
2648 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2649 fatal_signal_pending(current)) {
2650 /*
2651 * Disable the controller first since we can't trust it
2652 * at this point, but leave the admin queue enabled
2653 * until all queue deletion requests are flushed.
2654 * FIXME: This may take a while if there are more h/w
2655 * queues than admin tags.
2656 */
2657 set_current_state(TASK_RUNNING);
2658 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2659 nvme_clear_queue(dev->queues[0]);
2660 flush_kthread_worker(dq->worker);
2661 nvme_disable_queue(dev, 0);
2662 return;
2663 }
2664 }
2665 set_current_state(TASK_RUNNING);
2666 }
2667
2668 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2669 {
2670 atomic_dec(&dq->refcount);
2671 if (dq->waiter)
2672 wake_up_process(dq->waiter);
2673 }
2674
2675 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2676 {
2677 atomic_inc(&dq->refcount);
2678 return dq;
2679 }
2680
2681 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2682 {
2683 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2684 nvme_put_dq(dq);
2685 }
2686
2687 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2688 kthread_work_func_t fn)
2689 {
2690 struct nvme_command c;
2691
2692 memset(&c, 0, sizeof(c));
2693 c.delete_queue.opcode = opcode;
2694 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2695
2696 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2697 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2698 ADMIN_TIMEOUT);
2699 }
2700
2701 static void nvme_del_cq_work_handler(struct kthread_work *work)
2702 {
2703 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2704 cmdinfo.work);
2705 nvme_del_queue_end(nvmeq);
2706 }
2707
2708 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2709 {
2710 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2711 nvme_del_cq_work_handler);
2712 }
2713
2714 static void nvme_del_sq_work_handler(struct kthread_work *work)
2715 {
2716 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2717 cmdinfo.work);
2718 int status = nvmeq->cmdinfo.status;
2719
2720 if (!status)
2721 status = nvme_delete_cq(nvmeq);
2722 if (status)
2723 nvme_del_queue_end(nvmeq);
2724 }
2725
2726 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2727 {
2728 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2729 nvme_del_sq_work_handler);
2730 }
2731
2732 static void nvme_del_queue_start(struct kthread_work *work)
2733 {
2734 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2735 cmdinfo.work);
2736 if (nvme_delete_sq(nvmeq))
2737 nvme_del_queue_end(nvmeq);
2738 }
2739
2740 static void nvme_disable_io_queues(struct nvme_dev *dev)
2741 {
2742 int i;
2743 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2744 struct nvme_delq_ctx dq;
2745 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2746 &worker, "nvme%d", dev->instance);
2747
2748 if (IS_ERR(kworker_task)) {
2749 dev_err(dev->dev,
2750 "Failed to create queue del task\n");
2751 for (i = dev->queue_count - 1; i > 0; i--)
2752 nvme_disable_queue(dev, i);
2753 return;
2754 }
2755
2756 dq.waiter = NULL;
2757 atomic_set(&dq.refcount, 0);
2758 dq.worker = &worker;
2759 for (i = dev->queue_count - 1; i > 0; i--) {
2760 struct nvme_queue *nvmeq = dev->queues[i];
2761
2762 if (nvme_suspend_queue(nvmeq))
2763 continue;
2764 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2765 nvmeq->cmdinfo.worker = dq.worker;
2766 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2767 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2768 }
2769 nvme_wait_dq(&dq, dev);
2770 kthread_stop(kworker_task);
2771 }
2772
2773 /*
2774 * Remove the node from the device list and check
2775 * for whether or not we need to stop the nvme_thread.
2776 */
2777 static void nvme_dev_list_remove(struct nvme_dev *dev)
2778 {
2779 struct task_struct *tmp = NULL;
2780
2781 spin_lock(&dev_list_lock);
2782 list_del_init(&dev->node);
2783 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2784 tmp = nvme_thread;
2785 nvme_thread = NULL;
2786 }
2787 spin_unlock(&dev_list_lock);
2788
2789 if (tmp)
2790 kthread_stop(tmp);
2791 }
2792
2793 static void nvme_freeze_queues(struct nvme_dev *dev)
2794 {
2795 struct nvme_ns *ns;
2796
2797 list_for_each_entry(ns, &dev->namespaces, list) {
2798 blk_mq_freeze_queue_start(ns->queue);
2799
2800 spin_lock_irq(ns->queue->queue_lock);
2801 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2802 spin_unlock_irq(ns->queue->queue_lock);
2803
2804 blk_mq_cancel_requeue_work(ns->queue);
2805 blk_mq_stop_hw_queues(ns->queue);
2806 }
2807 }
2808
2809 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2810 {
2811 struct nvme_ns *ns;
2812
2813 list_for_each_entry(ns, &dev->namespaces, list) {
2814 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2815 blk_mq_unfreeze_queue(ns->queue);
2816 blk_mq_start_stopped_hw_queues(ns->queue, true);
2817 blk_mq_kick_requeue_list(ns->queue);
2818 }
2819 }
2820
2821 static void nvme_dev_shutdown(struct nvme_dev *dev)
2822 {
2823 int i;
2824 u32 csts = -1;
2825
2826 nvme_dev_list_remove(dev);
2827
2828 if (dev->bar) {
2829 nvme_freeze_queues(dev);
2830 csts = readl(&dev->bar->csts);
2831 }
2832 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2833 for (i = dev->queue_count - 1; i >= 0; i--) {
2834 struct nvme_queue *nvmeq = dev->queues[i];
2835 nvme_suspend_queue(nvmeq);
2836 }
2837 } else {
2838 nvme_disable_io_queues(dev);
2839 nvme_shutdown_ctrl(dev);
2840 nvme_disable_queue(dev, 0);
2841 }
2842 nvme_dev_unmap(dev);
2843
2844 for (i = dev->queue_count - 1; i >= 0; i--)
2845 nvme_clear_queue(dev->queues[i]);
2846 }
2847
2848 static void nvme_dev_remove(struct nvme_dev *dev)
2849 {
2850 struct nvme_ns *ns, *next;
2851
2852 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2853 nvme_ns_remove(ns);
2854 }
2855
2856 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2857 {
2858 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2859 PAGE_SIZE, PAGE_SIZE, 0);
2860 if (!dev->prp_page_pool)
2861 return -ENOMEM;
2862
2863 /* Optimisation for I/Os between 4k and 128k */
2864 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2865 256, 256, 0);
2866 if (!dev->prp_small_pool) {
2867 dma_pool_destroy(dev->prp_page_pool);
2868 return -ENOMEM;
2869 }
2870 return 0;
2871 }
2872
2873 static void nvme_release_prp_pools(struct nvme_dev *dev)
2874 {
2875 dma_pool_destroy(dev->prp_page_pool);
2876 dma_pool_destroy(dev->prp_small_pool);
2877 }
2878
2879 static DEFINE_IDA(nvme_instance_ida);
2880
2881 static int nvme_set_instance(struct nvme_dev *dev)
2882 {
2883 int instance, error;
2884
2885 do {
2886 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2887 return -ENODEV;
2888
2889 spin_lock(&dev_list_lock);
2890 error = ida_get_new(&nvme_instance_ida, &instance);
2891 spin_unlock(&dev_list_lock);
2892 } while (error == -EAGAIN);
2893
2894 if (error)
2895 return -ENODEV;
2896
2897 dev->instance = instance;
2898 return 0;
2899 }
2900
2901 static void nvme_release_instance(struct nvme_dev *dev)
2902 {
2903 spin_lock(&dev_list_lock);
2904 ida_remove(&nvme_instance_ida, dev->instance);
2905 spin_unlock(&dev_list_lock);
2906 }
2907
2908 static void nvme_free_dev(struct kref *kref)
2909 {
2910 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2911
2912 put_device(dev->dev);
2913 put_device(dev->device);
2914 nvme_release_instance(dev);
2915 if (dev->tagset.tags)
2916 blk_mq_free_tag_set(&dev->tagset);
2917 if (dev->admin_q)
2918 blk_put_queue(dev->admin_q);
2919 kfree(dev->queues);
2920 kfree(dev->entry);
2921 kfree(dev);
2922 }
2923
2924 static int nvme_dev_open(struct inode *inode, struct file *f)
2925 {
2926 struct nvme_dev *dev;
2927 int instance = iminor(inode);
2928 int ret = -ENODEV;
2929
2930 spin_lock(&dev_list_lock);
2931 list_for_each_entry(dev, &dev_list, node) {
2932 if (dev->instance == instance) {
2933 if (!dev->admin_q) {
2934 ret = -EWOULDBLOCK;
2935 break;
2936 }
2937 if (!kref_get_unless_zero(&dev->kref))
2938 break;
2939 f->private_data = dev;
2940 ret = 0;
2941 break;
2942 }
2943 }
2944 spin_unlock(&dev_list_lock);
2945
2946 return ret;
2947 }
2948
2949 static int nvme_dev_release(struct inode *inode, struct file *f)
2950 {
2951 struct nvme_dev *dev = f->private_data;
2952 kref_put(&dev->kref, nvme_free_dev);
2953 return 0;
2954 }
2955
2956 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2957 {
2958 struct nvme_dev *dev = f->private_data;
2959 struct nvme_ns *ns;
2960
2961 switch (cmd) {
2962 case NVME_IOCTL_ADMIN_CMD:
2963 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2964 case NVME_IOCTL_IO_CMD:
2965 if (list_empty(&dev->namespaces))
2966 return -ENOTTY;
2967 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2968 return nvme_user_cmd(dev, ns, (void __user *)arg);
2969 case NVME_IOCTL_RESET:
2970 dev_warn(dev->dev, "resetting controller\n");
2971 return nvme_reset(dev);
2972 case NVME_IOCTL_SUBSYS_RESET:
2973 return nvme_subsys_reset(dev);
2974 default:
2975 return -ENOTTY;
2976 }
2977 }
2978
2979 static const struct file_operations nvme_dev_fops = {
2980 .owner = THIS_MODULE,
2981 .open = nvme_dev_open,
2982 .release = nvme_dev_release,
2983 .unlocked_ioctl = nvme_dev_ioctl,
2984 .compat_ioctl = nvme_dev_ioctl,
2985 };
2986
2987 static void nvme_probe_work(struct work_struct *work)
2988 {
2989 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2990 bool start_thread = false;
2991 int result;
2992
2993 result = nvme_dev_map(dev);
2994 if (result)
2995 goto out;
2996
2997 result = nvme_configure_admin_queue(dev);
2998 if (result)
2999 goto unmap;
3000
3001 spin_lock(&dev_list_lock);
3002 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3003 start_thread = true;
3004 nvme_thread = NULL;
3005 }
3006 list_add(&dev->node, &dev_list);
3007 spin_unlock(&dev_list_lock);
3008
3009 if (start_thread) {
3010 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
3011 wake_up_all(&nvme_kthread_wait);
3012 } else
3013 wait_event_killable(nvme_kthread_wait, nvme_thread);
3014
3015 if (IS_ERR_OR_NULL(nvme_thread)) {
3016 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3017 goto disable;
3018 }
3019
3020 nvme_init_queue(dev->queues[0], 0);
3021 result = nvme_alloc_admin_tags(dev);
3022 if (result)
3023 goto disable;
3024
3025 result = nvme_setup_io_queues(dev);
3026 if (result)
3027 goto free_tags;
3028
3029 dev->event_limit = 1;
3030
3031 /*
3032 * Keep the controller around but remove all namespaces if we don't have
3033 * any working I/O queue.
3034 */
3035 if (dev->online_queues < 2) {
3036 dev_warn(dev->dev, "IO queues not created\n");
3037 nvme_dev_remove(dev);
3038 } else {
3039 nvme_unfreeze_queues(dev);
3040 nvme_dev_add(dev);
3041 }
3042
3043 return;
3044
3045 free_tags:
3046 nvme_dev_remove_admin(dev);
3047 blk_put_queue(dev->admin_q);
3048 dev->admin_q = NULL;
3049 dev->queues[0]->tags = NULL;
3050 disable:
3051 nvme_disable_queue(dev, 0);
3052 nvme_dev_list_remove(dev);
3053 unmap:
3054 nvme_dev_unmap(dev);
3055 out:
3056 if (!work_busy(&dev->reset_work))
3057 nvme_dead_ctrl(dev);
3058 }
3059
3060 static int nvme_remove_dead_ctrl(void *arg)
3061 {
3062 struct nvme_dev *dev = (struct nvme_dev *)arg;
3063 struct pci_dev *pdev = to_pci_dev(dev->dev);
3064
3065 if (pci_get_drvdata(pdev))
3066 pci_stop_and_remove_bus_device_locked(pdev);
3067 kref_put(&dev->kref, nvme_free_dev);
3068 return 0;
3069 }
3070
3071 static void nvme_dead_ctrl(struct nvme_dev *dev)
3072 {
3073 dev_warn(dev->dev, "Device failed to resume\n");
3074 kref_get(&dev->kref);
3075 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3076 dev->instance))) {
3077 dev_err(dev->dev,
3078 "Failed to start controller remove task\n");
3079 kref_put(&dev->kref, nvme_free_dev);
3080 }
3081 }
3082
3083 static void nvme_reset_work(struct work_struct *ws)
3084 {
3085 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
3086 bool in_probe = work_busy(&dev->probe_work);
3087
3088 nvme_dev_shutdown(dev);
3089
3090 /* Synchronize with device probe so that work will see failure status
3091 * and exit gracefully without trying to schedule another reset */
3092 flush_work(&dev->probe_work);
3093
3094 /* Fail this device if reset occured during probe to avoid
3095 * infinite initialization loops. */
3096 if (in_probe) {
3097 nvme_dead_ctrl(dev);
3098 return;
3099 }
3100 /* Schedule device resume asynchronously so the reset work is available
3101 * to cleanup errors that may occur during reinitialization */
3102 schedule_work(&dev->probe_work);
3103 }
3104
3105 static int __nvme_reset(struct nvme_dev *dev)
3106 {
3107 if (work_pending(&dev->reset_work))
3108 return -EBUSY;
3109 list_del_init(&dev->node);
3110 queue_work(nvme_workq, &dev->reset_work);
3111 return 0;
3112 }
3113
3114 static int nvme_reset(struct nvme_dev *dev)
3115 {
3116 int ret;
3117
3118 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3119 return -ENODEV;
3120
3121 spin_lock(&dev_list_lock);
3122 ret = __nvme_reset(dev);
3123 spin_unlock(&dev_list_lock);
3124
3125 if (!ret) {
3126 flush_work(&dev->reset_work);
3127 flush_work(&dev->probe_work);
3128 return 0;
3129 }
3130
3131 return ret;
3132 }
3133
3134 static ssize_t nvme_sysfs_reset(struct device *dev,
3135 struct device_attribute *attr, const char *buf,
3136 size_t count)
3137 {
3138 struct nvme_dev *ndev = dev_get_drvdata(dev);
3139 int ret;
3140
3141 ret = nvme_reset(ndev);
3142 if (ret < 0)
3143 return ret;
3144
3145 return count;
3146 }
3147 static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3148
3149 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3150 {
3151 int node, result = -ENOMEM;
3152 struct nvme_dev *dev;
3153
3154 node = dev_to_node(&pdev->dev);
3155 if (node == NUMA_NO_NODE)
3156 set_dev_node(&pdev->dev, 0);
3157
3158 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3159 if (!dev)
3160 return -ENOMEM;
3161 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3162 GFP_KERNEL, node);
3163 if (!dev->entry)
3164 goto free;
3165 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3166 GFP_KERNEL, node);
3167 if (!dev->queues)
3168 goto free;
3169
3170 INIT_LIST_HEAD(&dev->namespaces);
3171 INIT_WORK(&dev->reset_work, nvme_reset_work);
3172 dev->dev = get_device(&pdev->dev);
3173 pci_set_drvdata(pdev, dev);
3174 result = nvme_set_instance(dev);
3175 if (result)
3176 goto put_pci;
3177
3178 result = nvme_setup_prp_pools(dev);
3179 if (result)
3180 goto release;
3181
3182 kref_init(&dev->kref);
3183 dev->device = device_create(nvme_class, &pdev->dev,
3184 MKDEV(nvme_char_major, dev->instance),
3185 dev, "nvme%d", dev->instance);
3186 if (IS_ERR(dev->device)) {
3187 result = PTR_ERR(dev->device);
3188 goto release_pools;
3189 }
3190 get_device(dev->device);
3191 dev_set_drvdata(dev->device, dev);
3192
3193 result = device_create_file(dev->device, &dev_attr_reset_controller);
3194 if (result)
3195 goto put_dev;
3196
3197 INIT_LIST_HEAD(&dev->node);
3198 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3199 INIT_WORK(&dev->probe_work, nvme_probe_work);
3200 schedule_work(&dev->probe_work);
3201 return 0;
3202
3203 put_dev:
3204 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3205 put_device(dev->device);
3206 release_pools:
3207 nvme_release_prp_pools(dev);
3208 release:
3209 nvme_release_instance(dev);
3210 put_pci:
3211 put_device(dev->dev);
3212 free:
3213 kfree(dev->queues);
3214 kfree(dev->entry);
3215 kfree(dev);
3216 return result;
3217 }
3218
3219 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3220 {
3221 struct nvme_dev *dev = pci_get_drvdata(pdev);
3222
3223 if (prepare)
3224 nvme_dev_shutdown(dev);
3225 else
3226 schedule_work(&dev->probe_work);
3227 }
3228
3229 static void nvme_shutdown(struct pci_dev *pdev)
3230 {
3231 struct nvme_dev *dev = pci_get_drvdata(pdev);
3232 nvme_dev_shutdown(dev);
3233 }
3234
3235 static void nvme_remove(struct pci_dev *pdev)
3236 {
3237 struct nvme_dev *dev = pci_get_drvdata(pdev);
3238
3239 spin_lock(&dev_list_lock);
3240 list_del_init(&dev->node);
3241 spin_unlock(&dev_list_lock);
3242
3243 pci_set_drvdata(pdev, NULL);
3244 flush_work(&dev->probe_work);
3245 flush_work(&dev->reset_work);
3246 flush_work(&dev->scan_work);
3247 device_remove_file(dev->device, &dev_attr_reset_controller);
3248 nvme_dev_remove(dev);
3249 nvme_dev_shutdown(dev);
3250 nvme_dev_remove_admin(dev);
3251 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3252 nvme_free_queues(dev, 0);
3253 nvme_release_cmb(dev);
3254 nvme_release_prp_pools(dev);
3255 kref_put(&dev->kref, nvme_free_dev);
3256 }
3257
3258 /* These functions are yet to be implemented */
3259 #define nvme_error_detected NULL
3260 #define nvme_dump_registers NULL
3261 #define nvme_link_reset NULL
3262 #define nvme_slot_reset NULL
3263 #define nvme_error_resume NULL
3264
3265 #ifdef CONFIG_PM_SLEEP
3266 static int nvme_suspend(struct device *dev)
3267 {
3268 struct pci_dev *pdev = to_pci_dev(dev);
3269 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3270
3271 nvme_dev_shutdown(ndev);
3272 return 0;
3273 }
3274
3275 static int nvme_resume(struct device *dev)
3276 {
3277 struct pci_dev *pdev = to_pci_dev(dev);
3278 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3279
3280 schedule_work(&ndev->probe_work);
3281 return 0;
3282 }
3283 #endif
3284
3285 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3286
3287 static const struct pci_error_handlers nvme_err_handler = {
3288 .error_detected = nvme_error_detected,
3289 .mmio_enabled = nvme_dump_registers,
3290 .link_reset = nvme_link_reset,
3291 .slot_reset = nvme_slot_reset,
3292 .resume = nvme_error_resume,
3293 .reset_notify = nvme_reset_notify,
3294 };
3295
3296 /* Move to pci_ids.h later */
3297 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
3298
3299 static const struct pci_device_id nvme_id_table[] = {
3300 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3301 { 0, }
3302 };
3303 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3304
3305 static struct pci_driver nvme_driver = {
3306 .name = "nvme",
3307 .id_table = nvme_id_table,
3308 .probe = nvme_probe,
3309 .remove = nvme_remove,
3310 .shutdown = nvme_shutdown,
3311 .driver = {
3312 .pm = &nvme_dev_pm_ops,
3313 },
3314 .err_handler = &nvme_err_handler,
3315 };
3316
3317 static int __init nvme_init(void)
3318 {
3319 int result;
3320
3321 init_waitqueue_head(&nvme_kthread_wait);
3322
3323 nvme_workq = create_singlethread_workqueue("nvme");
3324 if (!nvme_workq)
3325 return -ENOMEM;
3326
3327 result = register_blkdev(nvme_major, "nvme");
3328 if (result < 0)
3329 goto kill_workq;
3330 else if (result > 0)
3331 nvme_major = result;
3332
3333 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3334 &nvme_dev_fops);
3335 if (result < 0)
3336 goto unregister_blkdev;
3337 else if (result > 0)
3338 nvme_char_major = result;
3339
3340 nvme_class = class_create(THIS_MODULE, "nvme");
3341 if (IS_ERR(nvme_class)) {
3342 result = PTR_ERR(nvme_class);
3343 goto unregister_chrdev;
3344 }
3345
3346 result = pci_register_driver(&nvme_driver);
3347 if (result)
3348 goto destroy_class;
3349 return 0;
3350
3351 destroy_class:
3352 class_destroy(nvme_class);
3353 unregister_chrdev:
3354 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3355 unregister_blkdev:
3356 unregister_blkdev(nvme_major, "nvme");
3357 kill_workq:
3358 destroy_workqueue(nvme_workq);
3359 return result;
3360 }
3361
3362 static void __exit nvme_exit(void)
3363 {
3364 pci_unregister_driver(&nvme_driver);
3365 unregister_blkdev(nvme_major, "nvme");
3366 destroy_workqueue(nvme_workq);
3367 class_destroy(nvme_class);
3368 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3369 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3370 _nvme_check_size();
3371 }
3372
3373 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3374 MODULE_LICENSE("GPL");
3375 MODULE_VERSION("1.0");
3376 module_init(nvme_init);
3377 module_exit(nvme_exit);