2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/pci.h>
28 #include <linux/poison.h>
29 #include <linux/t10-pi.h>
30 #include <linux/timer.h>
31 #include <linux/types.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #include <asm/unaligned.h>
34 #include <linux/sed-opal.h>
38 #define NVME_Q_DEPTH 1024
39 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
40 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43 * We handle AEN commands ourselves and don't even let the
44 * block layer know about them.
46 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
48 static int use_threaded_interrupts
;
49 module_param(use_threaded_interrupts
, int, 0);
51 static bool use_cmb_sqes
= true;
52 module_param(use_cmb_sqes
, bool, 0644);
53 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
55 static unsigned int max_host_mem_size_mb
= 128;
56 module_param(max_host_mem_size_mb
, uint
, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb
,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
63 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
64 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
67 * Represents an NVM Express device. Each nvme_dev is a PCI function.
70 struct nvme_queue
**queues
;
71 struct blk_mq_tag_set tagset
;
72 struct blk_mq_tag_set admin_tagset
;
75 struct dma_pool
*prp_page_pool
;
76 struct dma_pool
*prp_small_pool
;
77 unsigned online_queues
;
82 unsigned long bar_mapped_size
;
83 struct work_struct remove_work
;
84 struct mutex shutdown_lock
;
87 dma_addr_t cmb_dma_addr
;
91 struct nvme_ctrl ctrl
;
92 struct completion ioq_wait
;
94 /* shadow doorbell buffer support: */
96 dma_addr_t dbbuf_dbs_dma_addr
;
98 dma_addr_t dbbuf_eis_dma_addr
;
100 /* host memory buffer support: */
102 u32 nr_host_mem_descs
;
103 struct nvme_host_mem_buf_desc
*host_mem_descs
;
104 void **host_mem_desc_bufs
;
107 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
109 return qid
* 2 * stride
;
112 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
114 return (qid
* 2 + 1) * stride
;
117 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
119 return container_of(ctrl
, struct nvme_dev
, ctrl
);
123 * An NVM Express queue. Each device has at least two (one for admin
124 * commands and one for I/O commands).
127 struct device
*q_dmadev
;
128 struct nvme_dev
*dev
;
130 struct nvme_command
*sq_cmds
;
131 struct nvme_command __iomem
*sq_cmds_io
;
132 volatile struct nvme_completion
*cqes
;
133 struct blk_mq_tags
**tags
;
134 dma_addr_t sq_dma_addr
;
135 dma_addr_t cq_dma_addr
;
151 * The nvme_iod describes the data in an I/O, including the list of PRP
152 * entries. You can't see it in this data structure because C doesn't let
153 * me express that. Use nvme_init_iod to ensure there's enough space
154 * allocated to store the PRP list.
157 struct nvme_request req
;
158 struct nvme_queue
*nvmeq
;
160 int npages
; /* In the PRP list. 0 means small pool in use */
161 int nents
; /* Used in scatterlist */
162 int length
; /* Of data, in bytes */
163 dma_addr_t first_dma
;
164 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
165 struct scatterlist
*sg
;
166 struct scatterlist inline_sg
[0];
170 * Check we didin't inadvertently grow the command struct
172 static inline void _nvme_check_size(void)
174 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
175 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
176 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
177 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
178 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
179 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
180 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
181 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
183 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
184 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
186 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
189 static inline unsigned int nvme_dbbuf_size(u32 stride
)
191 return ((num_possible_cpus() + 1) * 8 * stride
);
194 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
196 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
201 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
202 &dev
->dbbuf_dbs_dma_addr
,
206 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
207 &dev
->dbbuf_eis_dma_addr
,
209 if (!dev
->dbbuf_eis
) {
210 dma_free_coherent(dev
->dev
, mem_size
,
211 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
212 dev
->dbbuf_dbs
= NULL
;
219 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
221 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
223 if (dev
->dbbuf_dbs
) {
224 dma_free_coherent(dev
->dev
, mem_size
,
225 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
226 dev
->dbbuf_dbs
= NULL
;
228 if (dev
->dbbuf_eis
) {
229 dma_free_coherent(dev
->dev
, mem_size
,
230 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
231 dev
->dbbuf_eis
= NULL
;
235 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
236 struct nvme_queue
*nvmeq
, int qid
)
238 if (!dev
->dbbuf_dbs
|| !qid
)
241 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
242 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
243 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
244 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
247 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
249 struct nvme_command c
;
254 memset(&c
, 0, sizeof(c
));
255 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
256 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
257 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
259 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
260 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
261 /* Free memory and continue on */
262 nvme_dbbuf_dma_free(dev
);
266 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
268 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
271 /* Update dbbuf and return true if an MMIO is required */
272 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
273 volatile u32
*dbbuf_ei
)
279 * Ensure that the queue is written before updating
280 * the doorbell in memory
284 old_value
= *dbbuf_db
;
287 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
295 * Max size of iod being embedded in the request payload
297 #define NVME_INT_PAGES 2
298 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
301 * Will slightly overestimate the number of pages needed. This is OK
302 * as it only leads to a small amount of wasted memory for the lifetime of
305 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
307 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
308 dev
->ctrl
.page_size
);
309 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
312 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
313 unsigned int size
, unsigned int nseg
)
315 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
316 sizeof(struct scatterlist
) * nseg
;
319 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
321 return sizeof(struct nvme_iod
) +
322 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
325 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
326 unsigned int hctx_idx
)
328 struct nvme_dev
*dev
= data
;
329 struct nvme_queue
*nvmeq
= dev
->queues
[0];
331 WARN_ON(hctx_idx
!= 0);
332 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
333 WARN_ON(nvmeq
->tags
);
335 hctx
->driver_data
= nvmeq
;
336 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
340 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
342 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
347 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
348 unsigned int hctx_idx
)
350 struct nvme_dev
*dev
= data
;
351 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
354 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
356 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
357 hctx
->driver_data
= nvmeq
;
361 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
362 unsigned int hctx_idx
, unsigned int numa_node
)
364 struct nvme_dev
*dev
= set
->driver_data
;
365 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
366 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
367 struct nvme_queue
*nvmeq
= dev
->queues
[queue_idx
];
374 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
376 struct nvme_dev
*dev
= set
->driver_data
;
378 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
382 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
383 * @nvmeq: The queue to use
384 * @cmd: The command to send
386 * Safe to use from interrupt context
388 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
389 struct nvme_command
*cmd
)
391 u16 tail
= nvmeq
->sq_tail
;
393 if (nvmeq
->sq_cmds_io
)
394 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
396 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
398 if (++tail
== nvmeq
->q_depth
)
400 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
402 writel(tail
, nvmeq
->q_db
);
403 nvmeq
->sq_tail
= tail
;
406 static __le64
**iod_list(struct request
*req
)
408 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
409 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
412 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
414 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
415 int nseg
= blk_rq_nr_phys_segments(rq
);
416 unsigned int size
= blk_rq_payload_bytes(rq
);
418 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
419 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
421 return BLK_STS_RESOURCE
;
423 iod
->sg
= iod
->inline_sg
;
434 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
436 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
437 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
439 __le64
**list
= iod_list(req
);
440 dma_addr_t prp_dma
= iod
->first_dma
;
442 if (iod
->npages
== 0)
443 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
444 for (i
= 0; i
< iod
->npages
; i
++) {
445 __le64
*prp_list
= list
[i
];
446 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
447 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
448 prp_dma
= next_prp_dma
;
451 if (iod
->sg
!= iod
->inline_sg
)
455 #ifdef CONFIG_BLK_DEV_INTEGRITY
456 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
458 if (be32_to_cpu(pi
->ref_tag
) == v
)
459 pi
->ref_tag
= cpu_to_be32(p
);
462 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
464 if (be32_to_cpu(pi
->ref_tag
) == p
)
465 pi
->ref_tag
= cpu_to_be32(v
);
469 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
471 * The virtual start sector is the one that was originally submitted by the
472 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
473 * start sector may be different. Remap protection information to match the
474 * physical LBA on writes, and back to the original seed on reads.
476 * Type 0 and 3 do not have a ref tag, so no remapping required.
478 static void nvme_dif_remap(struct request
*req
,
479 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
481 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
482 struct bio_integrity_payload
*bip
;
483 struct t10_pi_tuple
*pi
;
485 u32 i
, nlb
, ts
, phys
, virt
;
487 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
490 bip
= bio_integrity(req
->bio
);
494 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
497 virt
= bip_get_seed(bip
);
498 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
499 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
500 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
502 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
503 pi
= (struct t10_pi_tuple
*)p
;
504 dif_swap(phys
, virt
, pi
);
509 #else /* CONFIG_BLK_DEV_INTEGRITY */
510 static void nvme_dif_remap(struct request
*req
,
511 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
514 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
517 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
522 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
524 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
525 struct dma_pool
*pool
;
526 int length
= blk_rq_payload_bytes(req
);
527 struct scatterlist
*sg
= iod
->sg
;
528 int dma_len
= sg_dma_len(sg
);
529 u64 dma_addr
= sg_dma_address(sg
);
530 u32 page_size
= dev
->ctrl
.page_size
;
531 int offset
= dma_addr
& (page_size
- 1);
533 __le64
**list
= iod_list(req
);
537 length
-= (page_size
- offset
);
541 dma_len
-= (page_size
- offset
);
543 dma_addr
+= (page_size
- offset
);
546 dma_addr
= sg_dma_address(sg
);
547 dma_len
= sg_dma_len(sg
);
550 if (length
<= page_size
) {
551 iod
->first_dma
= dma_addr
;
555 nprps
= DIV_ROUND_UP(length
, page_size
);
556 if (nprps
<= (256 / 8)) {
557 pool
= dev
->prp_small_pool
;
560 pool
= dev
->prp_page_pool
;
564 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
566 iod
->first_dma
= dma_addr
;
571 iod
->first_dma
= prp_dma
;
574 if (i
== page_size
>> 3) {
575 __le64
*old_prp_list
= prp_list
;
576 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
579 list
[iod
->npages
++] = prp_list
;
580 prp_list
[0] = old_prp_list
[i
- 1];
581 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
584 prp_list
[i
++] = cpu_to_le64(dma_addr
);
585 dma_len
-= page_size
;
586 dma_addr
+= page_size
;
594 dma_addr
= sg_dma_address(sg
);
595 dma_len
= sg_dma_len(sg
);
601 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
602 struct nvme_command
*cmnd
)
604 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
605 struct request_queue
*q
= req
->q
;
606 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
607 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
608 blk_status_t ret
= BLK_STS_IOERR
;
610 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
611 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
615 ret
= BLK_STS_RESOURCE
;
616 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
620 if (!nvme_setup_prps(dev
, req
))
624 if (blk_integrity_rq(req
)) {
625 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
628 sg_init_table(&iod
->meta_sg
, 1);
629 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
632 if (rq_data_dir(req
))
633 nvme_dif_remap(req
, nvme_dif_prep
);
635 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
639 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
640 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
641 if (blk_integrity_rq(req
))
642 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
646 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
651 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
653 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
654 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
655 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
658 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
659 if (blk_integrity_rq(req
)) {
660 if (!rq_data_dir(req
))
661 nvme_dif_remap(req
, nvme_dif_complete
);
662 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
666 nvme_cleanup_cmd(req
);
667 nvme_free_iod(dev
, req
);
671 * NOTE: ns is NULL when called on the admin queue.
673 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
674 const struct blk_mq_queue_data
*bd
)
676 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
677 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
678 struct nvme_dev
*dev
= nvmeq
->dev
;
679 struct request
*req
= bd
->rq
;
680 struct nvme_command cmnd
;
683 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
687 ret
= nvme_init_iod(req
, dev
);
691 if (blk_rq_nr_phys_segments(req
)) {
692 ret
= nvme_map_data(dev
, req
, &cmnd
);
694 goto out_cleanup_iod
;
697 blk_mq_start_request(req
);
699 spin_lock_irq(&nvmeq
->q_lock
);
700 if (unlikely(nvmeq
->cq_vector
< 0)) {
702 spin_unlock_irq(&nvmeq
->q_lock
);
703 goto out_cleanup_iod
;
705 __nvme_submit_cmd(nvmeq
, &cmnd
);
706 nvme_process_cq(nvmeq
);
707 spin_unlock_irq(&nvmeq
->q_lock
);
710 nvme_free_iod(dev
, req
);
712 nvme_cleanup_cmd(req
);
716 static void nvme_pci_complete_rq(struct request
*req
)
718 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
720 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
721 nvme_complete_rq(req
);
724 /* We read the CQE phase first to check if the rest of the entry is valid */
725 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
728 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
731 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
733 u16 head
= nvmeq
->cq_head
;
735 if (likely(nvmeq
->cq_vector
>= 0)) {
736 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
738 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
742 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
,
743 struct nvme_completion
*cqe
)
747 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
748 dev_warn(nvmeq
->dev
->ctrl
.device
,
749 "invalid id %d completed on queue %d\n",
750 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
755 * AEN requests are special as they don't time out and can
756 * survive any kind of queue freeze and often don't respond to
757 * aborts. We don't even bother to allocate a struct request
758 * for them but rather special case them here.
760 if (unlikely(nvmeq
->qid
== 0 &&
761 cqe
->command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
762 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
763 cqe
->status
, &cqe
->result
);
767 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
768 nvme_end_request(req
, cqe
->status
, cqe
->result
);
771 static inline bool nvme_read_cqe(struct nvme_queue
*nvmeq
,
772 struct nvme_completion
*cqe
)
774 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
775 *cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
777 if (++nvmeq
->cq_head
== nvmeq
->q_depth
) {
779 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
786 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
788 struct nvme_completion cqe
;
791 while (nvme_read_cqe(nvmeq
, &cqe
)) {
792 nvme_handle_cqe(nvmeq
, &cqe
);
797 nvme_ring_cq_doorbell(nvmeq
);
802 static irqreturn_t
nvme_irq(int irq
, void *data
)
805 struct nvme_queue
*nvmeq
= data
;
806 spin_lock(&nvmeq
->q_lock
);
807 nvme_process_cq(nvmeq
);
808 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
810 spin_unlock(&nvmeq
->q_lock
);
814 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
816 struct nvme_queue
*nvmeq
= data
;
817 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
818 return IRQ_WAKE_THREAD
;
822 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
824 struct nvme_completion cqe
;
825 int found
= 0, consumed
= 0;
827 if (!nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
830 spin_lock_irq(&nvmeq
->q_lock
);
831 while (nvme_read_cqe(nvmeq
, &cqe
)) {
832 nvme_handle_cqe(nvmeq
, &cqe
);
835 if (tag
== cqe
.command_id
) {
842 nvme_ring_cq_doorbell(nvmeq
);
843 spin_unlock_irq(&nvmeq
->q_lock
);
848 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
850 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
852 return __nvme_poll(nvmeq
, tag
);
855 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
857 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
858 struct nvme_queue
*nvmeq
= dev
->queues
[0];
859 struct nvme_command c
;
861 memset(&c
, 0, sizeof(c
));
862 c
.common
.opcode
= nvme_admin_async_event
;
863 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
865 spin_lock_irq(&nvmeq
->q_lock
);
866 __nvme_submit_cmd(nvmeq
, &c
);
867 spin_unlock_irq(&nvmeq
->q_lock
);
870 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
872 struct nvme_command c
;
874 memset(&c
, 0, sizeof(c
));
875 c
.delete_queue
.opcode
= opcode
;
876 c
.delete_queue
.qid
= cpu_to_le16(id
);
878 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
881 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
882 struct nvme_queue
*nvmeq
)
884 struct nvme_command c
;
885 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
888 * Note: we (ab)use the fact the the prp fields survive if no data
889 * is attached to the request.
891 memset(&c
, 0, sizeof(c
));
892 c
.create_cq
.opcode
= nvme_admin_create_cq
;
893 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
894 c
.create_cq
.cqid
= cpu_to_le16(qid
);
895 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
896 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
897 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
899 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
902 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
903 struct nvme_queue
*nvmeq
)
905 struct nvme_command c
;
906 int flags
= NVME_QUEUE_PHYS_CONTIG
;
909 * Note: we (ab)use the fact the the prp fields survive if no data
910 * is attached to the request.
912 memset(&c
, 0, sizeof(c
));
913 c
.create_sq
.opcode
= nvme_admin_create_sq
;
914 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
915 c
.create_sq
.sqid
= cpu_to_le16(qid
);
916 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
917 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
918 c
.create_sq
.cqid
= cpu_to_le16(qid
);
920 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
923 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
925 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
928 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
930 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
933 static void abort_endio(struct request
*req
, blk_status_t error
)
935 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
936 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
938 dev_warn(nvmeq
->dev
->ctrl
.device
,
939 "Abort status: 0x%x", nvme_req(req
)->status
);
940 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
941 blk_mq_free_request(req
);
944 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
947 /* If true, indicates loss of adapter communication, possibly by a
948 * NVMe Subsystem reset.
950 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
952 /* If there is a reset ongoing, we shouldn't reset again. */
953 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
956 /* We shouldn't reset unless the controller is on fatal error state
957 * _or_ if we lost the communication with it.
959 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
962 /* If PCI error recovery process is happening, we cannot reset or
963 * the recovery mechanism will surely fail.
965 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
971 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
973 /* Read a config register to help see what died. */
977 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
979 if (result
== PCIBIOS_SUCCESSFUL
)
980 dev_warn(dev
->ctrl
.device
,
981 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
984 dev_warn(dev
->ctrl
.device
,
985 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
989 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
991 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
992 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
993 struct nvme_dev
*dev
= nvmeq
->dev
;
994 struct request
*abort_req
;
995 struct nvme_command cmd
;
996 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
999 * Reset immediately if the controller is failed
1001 if (nvme_should_reset(dev
, csts
)) {
1002 nvme_warn_reset(dev
, csts
);
1003 nvme_dev_disable(dev
, false);
1004 nvme_reset_ctrl(&dev
->ctrl
);
1005 return BLK_EH_HANDLED
;
1009 * Did we miss an interrupt?
1011 if (__nvme_poll(nvmeq
, req
->tag
)) {
1012 dev_warn(dev
->ctrl
.device
,
1013 "I/O %d QID %d timeout, completion polled\n",
1014 req
->tag
, nvmeq
->qid
);
1015 return BLK_EH_HANDLED
;
1019 * Shutdown immediately if controller times out while starting. The
1020 * reset work will see the pci device disabled when it gets the forced
1021 * cancellation error. All outstanding requests are completed on
1022 * shutdown, so we return BLK_EH_HANDLED.
1024 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
1025 dev_warn(dev
->ctrl
.device
,
1026 "I/O %d QID %d timeout, disable controller\n",
1027 req
->tag
, nvmeq
->qid
);
1028 nvme_dev_disable(dev
, false);
1029 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1030 return BLK_EH_HANDLED
;
1034 * Shutdown the controller immediately and schedule a reset if the
1035 * command was already aborted once before and still hasn't been
1036 * returned to the driver, or if this is the admin queue.
1038 if (!nvmeq
->qid
|| iod
->aborted
) {
1039 dev_warn(dev
->ctrl
.device
,
1040 "I/O %d QID %d timeout, reset controller\n",
1041 req
->tag
, nvmeq
->qid
);
1042 nvme_dev_disable(dev
, false);
1043 nvme_reset_ctrl(&dev
->ctrl
);
1046 * Mark the request as handled, since the inline shutdown
1047 * forces all outstanding requests to complete.
1049 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1050 return BLK_EH_HANDLED
;
1053 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1054 atomic_inc(&dev
->ctrl
.abort_limit
);
1055 return BLK_EH_RESET_TIMER
;
1059 memset(&cmd
, 0, sizeof(cmd
));
1060 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1061 cmd
.abort
.cid
= req
->tag
;
1062 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1064 dev_warn(nvmeq
->dev
->ctrl
.device
,
1065 "I/O %d QID %d timeout, aborting\n",
1066 req
->tag
, nvmeq
->qid
);
1068 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1069 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1070 if (IS_ERR(abort_req
)) {
1071 atomic_inc(&dev
->ctrl
.abort_limit
);
1072 return BLK_EH_RESET_TIMER
;
1075 abort_req
->timeout
= ADMIN_TIMEOUT
;
1076 abort_req
->end_io_data
= NULL
;
1077 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1080 * The aborted req will be completed on receiving the abort req.
1081 * We enable the timer again. If hit twice, it'll cause a device reset,
1082 * as the device then is in a faulty state.
1084 return BLK_EH_RESET_TIMER
;
1087 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1089 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1090 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1092 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1093 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1097 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1101 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1102 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1103 dev
->ctrl
.queue_count
--;
1104 dev
->queues
[i
] = NULL
;
1105 nvme_free_queue(nvmeq
);
1110 * nvme_suspend_queue - put queue into suspended state
1111 * @nvmeq - queue to suspend
1113 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1117 spin_lock_irq(&nvmeq
->q_lock
);
1118 if (nvmeq
->cq_vector
== -1) {
1119 spin_unlock_irq(&nvmeq
->q_lock
);
1122 vector
= nvmeq
->cq_vector
;
1123 nvmeq
->dev
->online_queues
--;
1124 nvmeq
->cq_vector
= -1;
1125 spin_unlock_irq(&nvmeq
->q_lock
);
1127 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1128 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1130 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1135 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1137 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1141 if (nvme_suspend_queue(nvmeq
))
1145 nvme_shutdown_ctrl(&dev
->ctrl
);
1147 nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1149 spin_lock_irq(&nvmeq
->q_lock
);
1150 nvme_process_cq(nvmeq
);
1151 spin_unlock_irq(&nvmeq
->q_lock
);
1154 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1157 int q_depth
= dev
->q_depth
;
1158 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1159 dev
->ctrl
.page_size
);
1161 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1162 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1163 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1164 q_depth
= div_u64(mem_per_q
, entry_size
);
1167 * Ensure the reduced q_depth is above some threshold where it
1168 * would be better to map queues in system memory with the
1178 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1181 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1182 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1183 dev
->ctrl
.page_size
);
1184 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1185 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1187 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1188 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1189 if (!nvmeq
->sq_cmds
)
1196 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1197 int depth
, int node
)
1199 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1204 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1205 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1209 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1212 nvmeq
->q_dmadev
= dev
->dev
;
1214 spin_lock_init(&nvmeq
->q_lock
);
1216 nvmeq
->cq_phase
= 1;
1217 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1218 nvmeq
->q_depth
= depth
;
1220 nvmeq
->cq_vector
= -1;
1221 dev
->queues
[qid
] = nvmeq
;
1222 dev
->ctrl
.queue_count
++;
1227 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1228 nvmeq
->cq_dma_addr
);
1234 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1236 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1237 int nr
= nvmeq
->dev
->ctrl
.instance
;
1239 if (use_threaded_interrupts
) {
1240 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1241 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1243 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1244 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1248 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1250 struct nvme_dev
*dev
= nvmeq
->dev
;
1252 spin_lock_irq(&nvmeq
->q_lock
);
1255 nvmeq
->cq_phase
= 1;
1256 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1257 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1258 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1259 dev
->online_queues
++;
1260 spin_unlock_irq(&nvmeq
->q_lock
);
1263 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1265 struct nvme_dev
*dev
= nvmeq
->dev
;
1268 nvmeq
->cq_vector
= qid
- 1;
1269 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1273 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1277 result
= queue_request_irq(nvmeq
);
1281 nvme_init_queue(nvmeq
, qid
);
1285 adapter_delete_sq(dev
, qid
);
1287 adapter_delete_cq(dev
, qid
);
1291 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1292 .queue_rq
= nvme_queue_rq
,
1293 .complete
= nvme_pci_complete_rq
,
1294 .init_hctx
= nvme_admin_init_hctx
,
1295 .exit_hctx
= nvme_admin_exit_hctx
,
1296 .init_request
= nvme_init_request
,
1297 .timeout
= nvme_timeout
,
1300 static const struct blk_mq_ops nvme_mq_ops
= {
1301 .queue_rq
= nvme_queue_rq
,
1302 .complete
= nvme_pci_complete_rq
,
1303 .init_hctx
= nvme_init_hctx
,
1304 .init_request
= nvme_init_request
,
1305 .map_queues
= nvme_pci_map_queues
,
1306 .timeout
= nvme_timeout
,
1310 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1312 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1314 * If the controller was reset during removal, it's possible
1315 * user requests may be waiting on a stopped queue. Start the
1316 * queue to flush these to completion.
1318 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1319 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1320 blk_mq_free_tag_set(&dev
->admin_tagset
);
1324 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1326 if (!dev
->ctrl
.admin_q
) {
1327 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1328 dev
->admin_tagset
.nr_hw_queues
= 1;
1331 * Subtract one to leave an empty queue entry for 'Full Queue'
1332 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1334 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1335 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1336 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1337 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1338 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1339 dev
->admin_tagset
.driver_data
= dev
;
1341 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1344 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1345 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1346 blk_mq_free_tag_set(&dev
->admin_tagset
);
1349 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1350 nvme_dev_remove_admin(dev
);
1351 dev
->ctrl
.admin_q
= NULL
;
1355 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1360 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1362 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1365 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1367 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1369 if (size
<= dev
->bar_mapped_size
)
1371 if (size
> pci_resource_len(pdev
, 0))
1375 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1377 dev
->bar_mapped_size
= 0;
1380 dev
->bar_mapped_size
= size
;
1381 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1386 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1390 struct nvme_queue
*nvmeq
;
1392 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1396 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1397 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1399 if (dev
->subsystem
&&
1400 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1401 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1403 result
= nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1407 nvmeq
= dev
->queues
[0];
1409 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1410 dev_to_node(dev
->dev
));
1415 aqa
= nvmeq
->q_depth
- 1;
1418 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1419 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1420 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1422 result
= nvme_enable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1426 nvmeq
->cq_vector
= 0;
1427 result
= queue_request_irq(nvmeq
);
1429 nvmeq
->cq_vector
= -1;
1436 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1441 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1442 /* vector == qid - 1, match nvme_create_queue */
1443 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1444 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1450 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1451 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1452 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1458 * Ignore failing Create SQ/CQ commands, we can continue with less
1459 * than the desired aount of queues, and even a controller without
1460 * I/O queues an still be used to issue admin commands. This might
1461 * be useful to upgrade a buggy firmware for example.
1463 return ret
>= 0 ? 0 : ret
;
1466 static ssize_t
nvme_cmb_show(struct device
*dev
,
1467 struct device_attribute
*attr
,
1470 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1472 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1473 ndev
->cmbloc
, ndev
->cmbsz
);
1475 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1477 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1479 u64 szu
, size
, offset
;
1480 resource_size_t bar_size
;
1481 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1483 dma_addr_t dma_addr
;
1485 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1486 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1488 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1493 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1494 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1495 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1496 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1498 if (offset
> bar_size
)
1502 * Controllers may support a CMB size larger than their BAR,
1503 * for example, due to being behind a bridge. Reduce the CMB to
1504 * the reported size of the BAR
1506 if (size
> bar_size
- offset
)
1507 size
= bar_size
- offset
;
1509 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1510 cmb
= ioremap_wc(dma_addr
, size
);
1514 dev
->cmb_dma_addr
= dma_addr
;
1515 dev
->cmb_size
= size
;
1519 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1525 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1526 &dev_attr_cmb
.attr
, NULL
);
1532 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1534 size_t len
= dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
);
1535 struct nvme_command c
;
1539 dma_addr
= dma_map_single(dev
->dev
, dev
->host_mem_descs
, len
,
1541 if (dma_mapping_error(dev
->dev
, dma_addr
))
1544 memset(&c
, 0, sizeof(c
));
1545 c
.features
.opcode
= nvme_admin_set_features
;
1546 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1547 c
.features
.dword11
= cpu_to_le32(bits
);
1548 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1549 ilog2(dev
->ctrl
.page_size
));
1550 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1551 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1552 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1554 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1556 dev_warn(dev
->ctrl
.device
,
1557 "failed to set host mem (err %d, flags %#x).\n",
1560 dma_unmap_single(dev
->dev
, dma_addr
, len
, DMA_TO_DEVICE
);
1564 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1568 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1569 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1570 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1572 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1573 le64_to_cpu(desc
->addr
));
1576 kfree(dev
->host_mem_desc_bufs
);
1577 dev
->host_mem_desc_bufs
= NULL
;
1578 kfree(dev
->host_mem_descs
);
1579 dev
->host_mem_descs
= NULL
;
1582 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1584 struct nvme_host_mem_buf_desc
*descs
;
1585 u32 chunk_size
, max_entries
, i
= 0;
1589 /* start big and work our way down */
1590 chunk_size
= min(preferred
, (u64
)PAGE_SIZE
<< MAX_ORDER
);
1592 tmp
= (preferred
+ chunk_size
- 1);
1593 do_div(tmp
, chunk_size
);
1595 descs
= kcalloc(max_entries
, sizeof(*descs
), GFP_KERNEL
);
1599 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1601 goto out_free_descs
;
1603 for (size
= 0; size
< preferred
; size
+= chunk_size
) {
1604 u32 len
= min_t(u64
, chunk_size
, preferred
- size
);
1605 dma_addr_t dma_addr
;
1607 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1608 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1612 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1613 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1617 if (!size
|| (min
&& size
< min
)) {
1618 dev_warn(dev
->ctrl
.device
,
1619 "failed to allocate host memory buffer.\n");
1623 dev_info(dev
->ctrl
.device
,
1624 "allocated %lld MiB host memory buffer.\n",
1625 size
>> ilog2(SZ_1M
));
1626 dev
->nr_host_mem_descs
= i
;
1627 dev
->host_mem_size
= size
;
1628 dev
->host_mem_descs
= descs
;
1629 dev
->host_mem_desc_bufs
= bufs
;
1634 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1636 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1637 le64_to_cpu(descs
[i
].addr
));
1644 /* try a smaller chunk size if we failed early */
1645 if (chunk_size
>= PAGE_SIZE
* 2 && (i
== 0 || size
< min
)) {
1649 dev
->host_mem_descs
= NULL
;
1653 static void nvme_setup_host_mem(struct nvme_dev
*dev
)
1655 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1656 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1657 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1658 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1660 preferred
= min(preferred
, max
);
1662 dev_warn(dev
->ctrl
.device
,
1663 "min host memory (%lld MiB) above limit (%d MiB).\n",
1664 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1665 nvme_free_host_mem(dev
);
1670 * If we already have a buffer allocated check if we can reuse it.
1672 if (dev
->host_mem_descs
) {
1673 if (dev
->host_mem_size
>= min
)
1674 enable_bits
|= NVME_HOST_MEM_RETURN
;
1676 nvme_free_host_mem(dev
);
1679 if (!dev
->host_mem_descs
) {
1680 if (nvme_alloc_host_mem(dev
, min
, preferred
))
1684 if (nvme_set_host_mem(dev
, enable_bits
))
1685 nvme_free_host_mem(dev
);
1688 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1690 struct nvme_queue
*adminq
= dev
->queues
[0];
1691 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1692 int result
, nr_io_queues
;
1695 nr_io_queues
= num_online_cpus();
1696 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1700 if (nr_io_queues
== 0)
1703 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1704 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1705 sizeof(struct nvme_command
));
1707 dev
->q_depth
= result
;
1709 nvme_release_cmb(dev
);
1713 size
= db_bar_size(dev
, nr_io_queues
);
1714 result
= nvme_remap_bar(dev
, size
);
1717 if (!--nr_io_queues
)
1720 adminq
->q_db
= dev
->dbs
;
1722 /* Deregister the admin queue's interrupt */
1723 pci_free_irq(pdev
, 0, adminq
);
1726 * If we enable msix early due to not intx, disable it again before
1727 * setting up the full range we need.
1729 pci_free_irq_vectors(pdev
);
1730 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1731 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1732 if (nr_io_queues
<= 0)
1734 dev
->max_qid
= nr_io_queues
;
1737 * Should investigate if there's a performance win from allocating
1738 * more queues than interrupt vectors; it might allow the submission
1739 * path to scale better, even if the receive path is limited by the
1740 * number of interrupts.
1743 result
= queue_request_irq(adminq
);
1745 adminq
->cq_vector
= -1;
1748 return nvme_create_io_queues(dev
);
1751 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1753 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1755 blk_mq_free_request(req
);
1756 complete(&nvmeq
->dev
->ioq_wait
);
1759 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1761 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1764 unsigned long flags
;
1767 * We might be called with the AQ q_lock held
1768 * and the I/O queue q_lock should always
1769 * nest inside the AQ one.
1771 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1772 SINGLE_DEPTH_NESTING
);
1773 nvme_process_cq(nvmeq
);
1774 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1777 nvme_del_queue_end(req
, error
);
1780 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1782 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1783 struct request
*req
;
1784 struct nvme_command cmd
;
1786 memset(&cmd
, 0, sizeof(cmd
));
1787 cmd
.delete_queue
.opcode
= opcode
;
1788 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1790 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1792 return PTR_ERR(req
);
1794 req
->timeout
= ADMIN_TIMEOUT
;
1795 req
->end_io_data
= nvmeq
;
1797 blk_execute_rq_nowait(q
, NULL
, req
, false,
1798 opcode
== nvme_admin_delete_cq
?
1799 nvme_del_cq_end
: nvme_del_queue_end
);
1803 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1806 unsigned long timeout
;
1807 u8 opcode
= nvme_admin_delete_sq
;
1809 for (pass
= 0; pass
< 2; pass
++) {
1810 int sent
= 0, i
= queues
;
1812 reinit_completion(&dev
->ioq_wait
);
1814 timeout
= ADMIN_TIMEOUT
;
1815 for (; i
> 0; i
--, sent
++)
1816 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1820 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1826 opcode
= nvme_admin_delete_cq
;
1831 * Return: error value if an error occurred setting up the queues or calling
1832 * Identify Device. 0 if these succeeded, even if adding some of the
1833 * namespaces failed. At the moment, these failures are silent. TBD which
1834 * failures should be reported.
1836 static int nvme_dev_add(struct nvme_dev
*dev
)
1838 if (!dev
->ctrl
.tagset
) {
1839 dev
->tagset
.ops
= &nvme_mq_ops
;
1840 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1841 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1842 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1843 dev
->tagset
.queue_depth
=
1844 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1845 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1846 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1847 dev
->tagset
.driver_data
= dev
;
1849 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1851 dev
->ctrl
.tagset
= &dev
->tagset
;
1853 nvme_dbbuf_set(dev
);
1855 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1857 /* Free previously allocated queues that are no longer usable */
1858 nvme_free_queues(dev
, dev
->online_queues
);
1864 static int nvme_pci_enable(struct nvme_dev
*dev
)
1866 int result
= -ENOMEM
;
1867 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1869 if (pci_enable_device_mem(pdev
))
1872 pci_set_master(pdev
);
1874 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1875 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1878 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1884 * Some devices and/or platforms don't advertise or work with INTx
1885 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1886 * adjust this later.
1888 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1892 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1894 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
1896 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
1897 dev
->dbs
= dev
->bar
+ 4096;
1900 * Temporary fix for the Apple controller found in the MacBook8,1 and
1901 * some MacBook7,1 to avoid controller resets and data loss.
1903 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1905 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
1906 "set queue depth=%u to work around controller resets\n",
1908 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
1909 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
1910 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
1912 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
1913 "set queue depth=%u\n", dev
->q_depth
);
1917 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1918 * populate sysfs if a CMB is implemented. Note that we add the
1919 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1920 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1921 * NULL as final argument to sysfs_add_file_to_group.
1924 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1925 dev
->cmb
= nvme_map_cmb(dev
);
1928 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1929 &dev_attr_cmb
.attr
, NULL
))
1930 dev_warn(dev
->ctrl
.device
,
1931 "failed to add sysfs attribute for CMB\n");
1935 pci_enable_pcie_error_reporting(pdev
);
1936 pci_save_state(pdev
);
1940 pci_disable_device(pdev
);
1944 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1948 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1951 static void nvme_pci_disable(struct nvme_dev
*dev
)
1953 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1955 nvme_release_cmb(dev
);
1956 pci_free_irq_vectors(pdev
);
1958 if (pci_is_enabled(pdev
)) {
1959 pci_disable_pcie_error_reporting(pdev
);
1960 pci_disable_device(pdev
);
1964 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1968 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1970 mutex_lock(&dev
->shutdown_lock
);
1971 if (pci_is_enabled(pdev
)) {
1972 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1974 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
)
1975 nvme_start_freeze(&dev
->ctrl
);
1976 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
1977 pdev
->error_state
!= pci_channel_io_normal
);
1981 * Give the controller a chance to complete all entered requests if
1982 * doing a safe shutdown.
1986 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
1989 * If the controller is still alive tell it to stop using the
1990 * host memory buffer. In theory the shutdown / reset should
1991 * make sure that it doesn't access the host memoery anymore,
1992 * but I'd rather be safe than sorry..
1994 if (dev
->host_mem_descs
)
1995 nvme_set_host_mem(dev
, 0);
1998 nvme_stop_queues(&dev
->ctrl
);
2000 queues
= dev
->online_queues
- 1;
2001 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
2002 nvme_suspend_queue(dev
->queues
[i
]);
2005 /* A device might become IO incapable very soon during
2006 * probe, before the admin queue is configured. Thus,
2007 * queue_count can be 0 here.
2009 if (dev
->ctrl
.queue_count
)
2010 nvme_suspend_queue(dev
->queues
[0]);
2012 nvme_disable_io_queues(dev
, queues
);
2013 nvme_disable_admin_queue(dev
, shutdown
);
2015 nvme_pci_disable(dev
);
2017 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2018 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2021 * The driver will not be starting up queues again if shutting down so
2022 * must flush all entered requests to their failed completion to avoid
2023 * deadlocking blk-mq hot-cpu notifier.
2026 nvme_start_queues(&dev
->ctrl
);
2027 mutex_unlock(&dev
->shutdown_lock
);
2030 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2032 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2033 PAGE_SIZE
, PAGE_SIZE
, 0);
2034 if (!dev
->prp_page_pool
)
2037 /* Optimisation for I/Os between 4k and 128k */
2038 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2040 if (!dev
->prp_small_pool
) {
2041 dma_pool_destroy(dev
->prp_page_pool
);
2047 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2049 dma_pool_destroy(dev
->prp_page_pool
);
2050 dma_pool_destroy(dev
->prp_small_pool
);
2053 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2055 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2057 nvme_dbbuf_dma_free(dev
);
2058 put_device(dev
->dev
);
2059 if (dev
->tagset
.tags
)
2060 blk_mq_free_tag_set(&dev
->tagset
);
2061 if (dev
->ctrl
.admin_q
)
2062 blk_put_queue(dev
->ctrl
.admin_q
);
2064 free_opal_dev(dev
->ctrl
.opal_dev
);
2068 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2070 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2072 kref_get(&dev
->ctrl
.kref
);
2073 nvme_dev_disable(dev
, false);
2074 if (!schedule_work(&dev
->remove_work
))
2075 nvme_put_ctrl(&dev
->ctrl
);
2078 static void nvme_reset_work(struct work_struct
*work
)
2080 struct nvme_dev
*dev
=
2081 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2082 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2083 int result
= -ENODEV
;
2085 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2089 * If we're called to reset a live controller first shut it down before
2092 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2093 nvme_dev_disable(dev
, false);
2095 result
= nvme_pci_enable(dev
);
2099 result
= nvme_pci_configure_admin_queue(dev
);
2103 nvme_init_queue(dev
->queues
[0], 0);
2104 result
= nvme_alloc_admin_tags(dev
);
2108 result
= nvme_init_identify(&dev
->ctrl
);
2112 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2113 if (!dev
->ctrl
.opal_dev
)
2114 dev
->ctrl
.opal_dev
=
2115 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2116 else if (was_suspend
)
2117 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2119 free_opal_dev(dev
->ctrl
.opal_dev
);
2120 dev
->ctrl
.opal_dev
= NULL
;
2123 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2124 result
= nvme_dbbuf_dma_alloc(dev
);
2127 "unable to allocate dma for dbbuf\n");
2130 if (dev
->ctrl
.hmpre
)
2131 nvme_setup_host_mem(dev
);
2133 result
= nvme_setup_io_queues(dev
);
2138 * Keep the controller around but remove all namespaces if we don't have
2139 * any working I/O queue.
2141 if (dev
->online_queues
< 2) {
2142 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2143 nvme_kill_queues(&dev
->ctrl
);
2144 nvme_remove_namespaces(&dev
->ctrl
);
2146 nvme_start_queues(&dev
->ctrl
);
2147 nvme_wait_freeze(&dev
->ctrl
);
2149 nvme_unfreeze(&dev
->ctrl
);
2152 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2153 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2157 nvme_start_ctrl(&dev
->ctrl
);
2161 nvme_remove_dead_ctrl(dev
, result
);
2164 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2166 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2167 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2169 nvme_kill_queues(&dev
->ctrl
);
2170 if (pci_get_drvdata(pdev
))
2171 device_release_driver(&pdev
->dev
);
2172 nvme_put_ctrl(&dev
->ctrl
);
2175 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2177 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2181 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2183 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2187 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2189 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2193 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2195 .module
= THIS_MODULE
,
2196 .flags
= NVME_F_METADATA_SUPPORTED
,
2197 .reg_read32
= nvme_pci_reg_read32
,
2198 .reg_write32
= nvme_pci_reg_write32
,
2199 .reg_read64
= nvme_pci_reg_read64
,
2200 .free_ctrl
= nvme_pci_free_ctrl
,
2201 .submit_async_event
= nvme_pci_submit_async_event
,
2204 static int nvme_dev_map(struct nvme_dev
*dev
)
2206 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2208 if (pci_request_mem_regions(pdev
, "nvme"))
2211 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2216 pci_release_mem_regions(pdev
);
2220 static unsigned long check_dell_samsung_bug(struct pci_dev
*pdev
)
2222 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2224 * Several Samsung devices seem to drop off the PCIe bus
2225 * randomly when APST is on and uses the deepest sleep state.
2226 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2227 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2228 * 950 PRO 256GB", but it seems to be restricted to two Dell
2231 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2232 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2233 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2234 return NVME_QUIRK_NO_DEEPEST_PS
;
2240 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2242 int node
, result
= -ENOMEM
;
2243 struct nvme_dev
*dev
;
2244 unsigned long quirks
= id
->driver_data
;
2246 node
= dev_to_node(&pdev
->dev
);
2247 if (node
== NUMA_NO_NODE
)
2248 set_dev_node(&pdev
->dev
, first_memory_node
);
2250 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2253 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2258 dev
->dev
= get_device(&pdev
->dev
);
2259 pci_set_drvdata(pdev
, dev
);
2261 result
= nvme_dev_map(dev
);
2265 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2266 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2267 mutex_init(&dev
->shutdown_lock
);
2268 init_completion(&dev
->ioq_wait
);
2270 result
= nvme_setup_prp_pools(dev
);
2274 quirks
|= check_dell_samsung_bug(pdev
);
2276 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2281 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2282 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2284 queue_work(nvme_wq
, &dev
->ctrl
.reset_work
);
2288 nvme_release_prp_pools(dev
);
2290 put_device(dev
->dev
);
2291 nvme_dev_unmap(dev
);
2298 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2300 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2303 nvme_dev_disable(dev
, false);
2305 nvme_reset_ctrl(&dev
->ctrl
);
2308 static void nvme_shutdown(struct pci_dev
*pdev
)
2310 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2311 nvme_dev_disable(dev
, true);
2315 * The driver's remove may be called on a device in a partially initialized
2316 * state. This function must not have any dependencies on the device state in
2319 static void nvme_remove(struct pci_dev
*pdev
)
2321 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2323 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2325 cancel_work_sync(&dev
->ctrl
.reset_work
);
2326 pci_set_drvdata(pdev
, NULL
);
2328 if (!pci_device_is_present(pdev
)) {
2329 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2330 nvme_dev_disable(dev
, false);
2333 flush_work(&dev
->ctrl
.reset_work
);
2334 nvme_stop_ctrl(&dev
->ctrl
);
2335 nvme_remove_namespaces(&dev
->ctrl
);
2336 nvme_dev_disable(dev
, true);
2337 nvme_free_host_mem(dev
);
2338 nvme_dev_remove_admin(dev
);
2339 nvme_free_queues(dev
, 0);
2340 nvme_uninit_ctrl(&dev
->ctrl
);
2341 nvme_release_prp_pools(dev
);
2342 nvme_dev_unmap(dev
);
2343 nvme_put_ctrl(&dev
->ctrl
);
2346 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2351 if (pci_vfs_assigned(pdev
)) {
2352 dev_warn(&pdev
->dev
,
2353 "Cannot disable SR-IOV VFs while assigned\n");
2356 pci_disable_sriov(pdev
);
2360 ret
= pci_enable_sriov(pdev
, numvfs
);
2361 return ret
? ret
: numvfs
;
2364 #ifdef CONFIG_PM_SLEEP
2365 static int nvme_suspend(struct device
*dev
)
2367 struct pci_dev
*pdev
= to_pci_dev(dev
);
2368 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2370 nvme_dev_disable(ndev
, true);
2374 static int nvme_resume(struct device
*dev
)
2376 struct pci_dev
*pdev
= to_pci_dev(dev
);
2377 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2379 nvme_reset_ctrl(&ndev
->ctrl
);
2384 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2386 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2387 pci_channel_state_t state
)
2389 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2392 * A frozen channel requires a reset. When detected, this method will
2393 * shutdown the controller to quiesce. The controller will be restarted
2394 * after the slot reset through driver's slot_reset callback.
2397 case pci_channel_io_normal
:
2398 return PCI_ERS_RESULT_CAN_RECOVER
;
2399 case pci_channel_io_frozen
:
2400 dev_warn(dev
->ctrl
.device
,
2401 "frozen state error detected, reset controller\n");
2402 nvme_dev_disable(dev
, false);
2403 return PCI_ERS_RESULT_NEED_RESET
;
2404 case pci_channel_io_perm_failure
:
2405 dev_warn(dev
->ctrl
.device
,
2406 "failure state error detected, request disconnect\n");
2407 return PCI_ERS_RESULT_DISCONNECT
;
2409 return PCI_ERS_RESULT_NEED_RESET
;
2412 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2414 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2416 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2417 pci_restore_state(pdev
);
2418 nvme_reset_ctrl(&dev
->ctrl
);
2419 return PCI_ERS_RESULT_RECOVERED
;
2422 static void nvme_error_resume(struct pci_dev
*pdev
)
2424 pci_cleanup_aer_uncorrect_error_status(pdev
);
2427 static const struct pci_error_handlers nvme_err_handler
= {
2428 .error_detected
= nvme_error_detected
,
2429 .slot_reset
= nvme_slot_reset
,
2430 .resume
= nvme_error_resume
,
2431 .reset_notify
= nvme_reset_notify
,
2434 static const struct pci_device_id nvme_id_table
[] = {
2435 { PCI_VDEVICE(INTEL
, 0x0953),
2436 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2437 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2438 { PCI_VDEVICE(INTEL
, 0x0a53),
2439 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2440 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2441 { PCI_VDEVICE(INTEL
, 0x0a54),
2442 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2443 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2444 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2445 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
},
2446 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2447 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2448 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2449 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2450 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2451 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2452 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2453 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2454 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2455 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2456 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2457 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2458 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2461 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2463 static struct pci_driver nvme_driver
= {
2465 .id_table
= nvme_id_table
,
2466 .probe
= nvme_probe
,
2467 .remove
= nvme_remove
,
2468 .shutdown
= nvme_shutdown
,
2470 .pm
= &nvme_dev_pm_ops
,
2472 .sriov_configure
= nvme_pci_sriov_configure
,
2473 .err_handler
= &nvme_err_handler
,
2476 static int __init
nvme_init(void)
2478 return pci_register_driver(&nvme_driver
);
2481 static void __exit
nvme_exit(void)
2483 pci_unregister_driver(&nvme_driver
);
2487 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2488 MODULE_LICENSE("GPL");
2489 MODULE_VERSION("1.0");
2490 module_init(nvme_init
);
2491 module_exit(nvme_exit
);