1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
43 static int use_threaded_interrupts
;
44 module_param(use_threaded_interrupts
, int, 0);
46 static bool use_cmb_sqes
= true;
47 module_param(use_cmb_sqes
, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
50 static unsigned int max_host_mem_size_mb
= 128;
51 module_param(max_host_mem_size_mb
, uint
, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb
,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
55 static unsigned int sgl_threshold
= SZ_32K
;
56 module_param(sgl_threshold
, uint
, 0644);
57 MODULE_PARM_DESC(sgl_threshold
,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
61 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
62 static const struct kernel_param_ops io_queue_depth_ops
= {
63 .set
= io_queue_depth_set
,
67 static int io_queue_depth
= 1024;
68 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
69 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
71 static unsigned int write_queues
;
72 module_param(write_queues
, uint
, 0644);
73 MODULE_PARM_DESC(write_queues
,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
77 static unsigned int poll_queues
;
78 module_param(poll_queues
, uint
, 0644);
79 MODULE_PARM_DESC(poll_queues
, "Number of queues to use for polled IO.");
84 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
85 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
);
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
91 struct nvme_queue
*queues
;
92 struct blk_mq_tag_set tagset
;
93 struct blk_mq_tag_set admin_tagset
;
96 struct dma_pool
*prp_page_pool
;
97 struct dma_pool
*prp_small_pool
;
98 unsigned online_queues
;
100 unsigned io_queues
[HCTX_MAX_TYPES
];
101 unsigned int num_vecs
;
106 unsigned long bar_mapped_size
;
107 struct work_struct remove_work
;
108 struct mutex shutdown_lock
;
114 struct nvme_ctrl ctrl
;
117 mempool_t
*iod_mempool
;
119 /* shadow doorbell buffer support: */
121 dma_addr_t dbbuf_dbs_dma_addr
;
123 dma_addr_t dbbuf_eis_dma_addr
;
125 /* host memory buffer support: */
127 u32 nr_host_mem_descs
;
128 dma_addr_t host_mem_descs_dma
;
129 struct nvme_host_mem_buf_desc
*host_mem_descs
;
130 void **host_mem_desc_bufs
;
133 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
137 ret
= kstrtoint(val
, 10, &n
);
138 if (ret
!= 0 || n
< 2)
141 return param_set_int(val
, kp
);
144 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
146 return qid
* 2 * stride
;
149 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
151 return (qid
* 2 + 1) * stride
;
154 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
156 return container_of(ctrl
, struct nvme_dev
, ctrl
);
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
164 struct nvme_dev
*dev
;
167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp
;
169 volatile struct nvme_completion
*cqes
;
170 dma_addr_t sq_dma_addr
;
171 dma_addr_t cq_dma_addr
;
182 #define NVMEQ_ENABLED 0
183 #define NVMEQ_SQ_CMB 1
184 #define NVMEQ_DELETE_ERROR 2
185 #define NVMEQ_POLLED 3
190 struct completion delete_done
;
194 * The nvme_iod describes the data in an I/O.
196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
197 * to the actual struct scatterlist.
200 struct nvme_request req
;
201 struct nvme_queue
*nvmeq
;
204 int npages
; /* In the PRP list. 0 means small pool in use */
205 int nents
; /* Used in scatterlist */
206 dma_addr_t first_dma
;
207 unsigned int dma_len
; /* length of single DMA segment mapping */
209 struct scatterlist
*sg
;
212 static unsigned int max_io_queues(void)
214 return num_possible_cpus() + write_queues
+ poll_queues
;
217 static unsigned int max_queue_count(void)
219 /* IO queues + admin queue */
220 return 1 + max_io_queues();
223 static inline unsigned int nvme_dbbuf_size(u32 stride
)
225 return (max_queue_count() * 8 * stride
);
228 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
230 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
235 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
236 &dev
->dbbuf_dbs_dma_addr
,
240 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
241 &dev
->dbbuf_eis_dma_addr
,
243 if (!dev
->dbbuf_eis
) {
244 dma_free_coherent(dev
->dev
, mem_size
,
245 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
246 dev
->dbbuf_dbs
= NULL
;
253 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
255 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
257 if (dev
->dbbuf_dbs
) {
258 dma_free_coherent(dev
->dev
, mem_size
,
259 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
260 dev
->dbbuf_dbs
= NULL
;
262 if (dev
->dbbuf_eis
) {
263 dma_free_coherent(dev
->dev
, mem_size
,
264 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
265 dev
->dbbuf_eis
= NULL
;
269 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
270 struct nvme_queue
*nvmeq
, int qid
)
272 if (!dev
->dbbuf_dbs
|| !qid
)
275 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
276 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
277 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
278 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
281 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
283 struct nvme_command c
;
288 memset(&c
, 0, sizeof(c
));
289 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
290 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
291 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
293 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
294 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
295 /* Free memory and continue on */
296 nvme_dbbuf_dma_free(dev
);
300 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
302 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
305 /* Update dbbuf and return true if an MMIO is required */
306 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
307 volatile u32
*dbbuf_ei
)
313 * Ensure that the queue is written before updating
314 * the doorbell in memory
318 old_value
= *dbbuf_db
;
322 * Ensure that the doorbell is updated before reading the event
323 * index from memory. The controller needs to provide similar
324 * ordering to ensure the envent index is updated before reading
329 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
337 * Will slightly overestimate the number of pages needed. This is OK
338 * as it only leads to a small amount of wasted memory for the lifetime of
341 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
343 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
344 dev
->ctrl
.page_size
);
345 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
349 * Calculates the number of pages needed for the SGL segments. For example a 4k
350 * page can accommodate 256 SGL descriptors.
352 static int nvme_pci_npages_sgl(unsigned int num_seg
)
354 return DIV_ROUND_UP(num_seg
* sizeof(struct nvme_sgl_desc
), PAGE_SIZE
);
357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev
*dev
,
358 unsigned int size
, unsigned int nseg
, bool use_sgl
)
363 alloc_size
= sizeof(__le64
*) * nvme_pci_npages_sgl(nseg
);
365 alloc_size
= sizeof(__le64
*) * nvme_npages(size
, dev
);
367 return alloc_size
+ sizeof(struct scatterlist
) * nseg
;
370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
371 unsigned int hctx_idx
)
373 struct nvme_dev
*dev
= data
;
374 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
376 WARN_ON(hctx_idx
!= 0);
377 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
379 hctx
->driver_data
= nvmeq
;
383 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
384 unsigned int hctx_idx
)
386 struct nvme_dev
*dev
= data
;
387 struct nvme_queue
*nvmeq
= &dev
->queues
[hctx_idx
+ 1];
389 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
390 hctx
->driver_data
= nvmeq
;
394 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
395 unsigned int hctx_idx
, unsigned int numa_node
)
397 struct nvme_dev
*dev
= set
->driver_data
;
398 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
399 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
400 struct nvme_queue
*nvmeq
= &dev
->queues
[queue_idx
];
405 nvme_req(req
)->ctrl
= &dev
->ctrl
;
409 static int queue_irq_offset(struct nvme_dev
*dev
)
411 /* if we have more than 1 vec, admin queue offsets us by 1 */
412 if (dev
->num_vecs
> 1)
418 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
420 struct nvme_dev
*dev
= set
->driver_data
;
423 offset
= queue_irq_offset(dev
);
424 for (i
= 0, qoff
= 0; i
< set
->nr_maps
; i
++) {
425 struct blk_mq_queue_map
*map
= &set
->map
[i
];
427 map
->nr_queues
= dev
->io_queues
[i
];
428 if (!map
->nr_queues
) {
429 BUG_ON(i
== HCTX_TYPE_DEFAULT
);
434 * The poll queue(s) doesn't have an IRQ (and hence IRQ
435 * affinity), so use the regular blk-mq cpu mapping
437 map
->queue_offset
= qoff
;
438 if (i
!= HCTX_TYPE_POLL
&& offset
)
439 blk_mq_pci_map_queues(map
, to_pci_dev(dev
->dev
), offset
);
441 blk_mq_map_queues(map
);
442 qoff
+= map
->nr_queues
;
443 offset
+= map
->nr_queues
;
450 * Write sq tail if we are asked to, or if the next command would wrap.
452 static inline void nvme_write_sq_db(struct nvme_queue
*nvmeq
, bool write_sq
)
455 u16 next_tail
= nvmeq
->sq_tail
+ 1;
457 if (next_tail
== nvmeq
->q_depth
)
459 if (next_tail
!= nvmeq
->last_sq_tail
)
463 if (nvme_dbbuf_update_and_check_event(nvmeq
->sq_tail
,
464 nvmeq
->dbbuf_sq_db
, nvmeq
->dbbuf_sq_ei
))
465 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
466 nvmeq
->last_sq_tail
= nvmeq
->sq_tail
;
470 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
471 * @nvmeq: The queue to use
472 * @cmd: The command to send
473 * @write_sq: whether to write to the SQ doorbell
475 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
,
478 spin_lock(&nvmeq
->sq_lock
);
479 memcpy(nvmeq
->sq_cmds
+ (nvmeq
->sq_tail
<< nvmeq
->sqes
),
481 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
483 nvme_write_sq_db(nvmeq
, write_sq
);
484 spin_unlock(&nvmeq
->sq_lock
);
487 static void nvme_commit_rqs(struct blk_mq_hw_ctx
*hctx
)
489 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
491 spin_lock(&nvmeq
->sq_lock
);
492 if (nvmeq
->sq_tail
!= nvmeq
->last_sq_tail
)
493 nvme_write_sq_db(nvmeq
, true);
494 spin_unlock(&nvmeq
->sq_lock
);
497 static void **nvme_pci_iod_list(struct request
*req
)
499 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
500 return (void **)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
503 static inline bool nvme_pci_use_sgls(struct nvme_dev
*dev
, struct request
*req
)
505 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
506 int nseg
= blk_rq_nr_phys_segments(req
);
507 unsigned int avg_seg_size
;
512 avg_seg_size
= DIV_ROUND_UP(blk_rq_payload_bytes(req
), nseg
);
514 if (!(dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))))
516 if (!iod
->nvmeq
->qid
)
518 if (!sgl_threshold
|| avg_seg_size
< sgl_threshold
)
523 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
525 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
526 const int last_prp
= dev
->ctrl
.page_size
/ sizeof(__le64
) - 1;
527 dma_addr_t dma_addr
= iod
->first_dma
, next_dma_addr
;
531 dma_unmap_page(dev
->dev
, dma_addr
, iod
->dma_len
,
536 WARN_ON_ONCE(!iod
->nents
);
538 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
539 pci_p2pdma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
,
542 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, rq_dma_dir(req
));
545 if (iod
->npages
== 0)
546 dma_pool_free(dev
->prp_small_pool
, nvme_pci_iod_list(req
)[0],
549 for (i
= 0; i
< iod
->npages
; i
++) {
550 void *addr
= nvme_pci_iod_list(req
)[i
];
553 struct nvme_sgl_desc
*sg_list
= addr
;
556 le64_to_cpu((sg_list
[SGES_PER_PAGE
- 1]).addr
);
558 __le64
*prp_list
= addr
;
560 next_dma_addr
= le64_to_cpu(prp_list
[last_prp
]);
563 dma_pool_free(dev
->prp_page_pool
, addr
, dma_addr
);
564 dma_addr
= next_dma_addr
;
567 mempool_free(iod
->sg
, dev
->iod_mempool
);
570 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
573 struct scatterlist
*sg
;
575 for_each_sg(sgl
, sg
, nents
, i
) {
576 dma_addr_t phys
= sg_phys(sg
);
577 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
578 "dma_address:%pad dma_length:%d\n",
579 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
584 static blk_status_t
nvme_pci_setup_prps(struct nvme_dev
*dev
,
585 struct request
*req
, struct nvme_rw_command
*cmnd
)
587 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
588 struct dma_pool
*pool
;
589 int length
= blk_rq_payload_bytes(req
);
590 struct scatterlist
*sg
= iod
->sg
;
591 int dma_len
= sg_dma_len(sg
);
592 u64 dma_addr
= sg_dma_address(sg
);
593 u32 page_size
= dev
->ctrl
.page_size
;
594 int offset
= dma_addr
& (page_size
- 1);
596 void **list
= nvme_pci_iod_list(req
);
600 length
-= (page_size
- offset
);
606 dma_len
-= (page_size
- offset
);
608 dma_addr
+= (page_size
- offset
);
611 dma_addr
= sg_dma_address(sg
);
612 dma_len
= sg_dma_len(sg
);
615 if (length
<= page_size
) {
616 iod
->first_dma
= dma_addr
;
620 nprps
= DIV_ROUND_UP(length
, page_size
);
621 if (nprps
<= (256 / 8)) {
622 pool
= dev
->prp_small_pool
;
625 pool
= dev
->prp_page_pool
;
629 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
631 iod
->first_dma
= dma_addr
;
633 return BLK_STS_RESOURCE
;
636 iod
->first_dma
= prp_dma
;
639 if (i
== page_size
>> 3) {
640 __le64
*old_prp_list
= prp_list
;
641 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
643 return BLK_STS_RESOURCE
;
644 list
[iod
->npages
++] = prp_list
;
645 prp_list
[0] = old_prp_list
[i
- 1];
646 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
649 prp_list
[i
++] = cpu_to_le64(dma_addr
);
650 dma_len
-= page_size
;
651 dma_addr
+= page_size
;
657 if (unlikely(dma_len
< 0))
660 dma_addr
= sg_dma_address(sg
);
661 dma_len
= sg_dma_len(sg
);
665 cmnd
->dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
666 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
671 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
672 "Invalid SGL for payload:%d nents:%d\n",
673 blk_rq_payload_bytes(req
), iod
->nents
);
674 return BLK_STS_IOERR
;
677 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc
*sge
,
678 struct scatterlist
*sg
)
680 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
681 sge
->length
= cpu_to_le32(sg_dma_len(sg
));
682 sge
->type
= NVME_SGL_FMT_DATA_DESC
<< 4;
685 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc
*sge
,
686 dma_addr_t dma_addr
, int entries
)
688 sge
->addr
= cpu_to_le64(dma_addr
);
689 if (entries
< SGES_PER_PAGE
) {
690 sge
->length
= cpu_to_le32(entries
* sizeof(*sge
));
691 sge
->type
= NVME_SGL_FMT_LAST_SEG_DESC
<< 4;
693 sge
->length
= cpu_to_le32(PAGE_SIZE
);
694 sge
->type
= NVME_SGL_FMT_SEG_DESC
<< 4;
698 static blk_status_t
nvme_pci_setup_sgls(struct nvme_dev
*dev
,
699 struct request
*req
, struct nvme_rw_command
*cmd
, int entries
)
701 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
702 struct dma_pool
*pool
;
703 struct nvme_sgl_desc
*sg_list
;
704 struct scatterlist
*sg
= iod
->sg
;
708 /* setting the transfer type as SGL */
709 cmd
->flags
= NVME_CMD_SGL_METABUF
;
712 nvme_pci_sgl_set_data(&cmd
->dptr
.sgl
, sg
);
716 if (entries
<= (256 / sizeof(struct nvme_sgl_desc
))) {
717 pool
= dev
->prp_small_pool
;
720 pool
= dev
->prp_page_pool
;
724 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
727 return BLK_STS_RESOURCE
;
730 nvme_pci_iod_list(req
)[0] = sg_list
;
731 iod
->first_dma
= sgl_dma
;
733 nvme_pci_sgl_set_seg(&cmd
->dptr
.sgl
, sgl_dma
, entries
);
736 if (i
== SGES_PER_PAGE
) {
737 struct nvme_sgl_desc
*old_sg_desc
= sg_list
;
738 struct nvme_sgl_desc
*link
= &old_sg_desc
[i
- 1];
740 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
742 return BLK_STS_RESOURCE
;
745 nvme_pci_iod_list(req
)[iod
->npages
++] = sg_list
;
746 sg_list
[i
++] = *link
;
747 nvme_pci_sgl_set_seg(link
, sgl_dma
, entries
);
750 nvme_pci_sgl_set_data(&sg_list
[i
++], sg
);
752 } while (--entries
> 0);
757 static blk_status_t
nvme_setup_prp_simple(struct nvme_dev
*dev
,
758 struct request
*req
, struct nvme_rw_command
*cmnd
,
761 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
762 unsigned int offset
= bv
->bv_offset
& (dev
->ctrl
.page_size
- 1);
763 unsigned int first_prp_len
= dev
->ctrl
.page_size
- offset
;
765 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
766 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
767 return BLK_STS_RESOURCE
;
768 iod
->dma_len
= bv
->bv_len
;
770 cmnd
->dptr
.prp1
= cpu_to_le64(iod
->first_dma
);
771 if (bv
->bv_len
> first_prp_len
)
772 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
+ first_prp_len
);
776 static blk_status_t
nvme_setup_sgl_simple(struct nvme_dev
*dev
,
777 struct request
*req
, struct nvme_rw_command
*cmnd
,
780 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
782 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
783 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
784 return BLK_STS_RESOURCE
;
785 iod
->dma_len
= bv
->bv_len
;
787 cmnd
->flags
= NVME_CMD_SGL_METABUF
;
788 cmnd
->dptr
.sgl
.addr
= cpu_to_le64(iod
->first_dma
);
789 cmnd
->dptr
.sgl
.length
= cpu_to_le32(iod
->dma_len
);
790 cmnd
->dptr
.sgl
.type
= NVME_SGL_FMT_DATA_DESC
<< 4;
794 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
795 struct nvme_command
*cmnd
)
797 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
798 blk_status_t ret
= BLK_STS_RESOURCE
;
801 if (blk_rq_nr_phys_segments(req
) == 1) {
802 struct bio_vec bv
= req_bvec(req
);
804 if (!is_pci_p2pdma_page(bv
.bv_page
)) {
805 if (bv
.bv_offset
+ bv
.bv_len
<= dev
->ctrl
.page_size
* 2)
806 return nvme_setup_prp_simple(dev
, req
,
809 if (iod
->nvmeq
->qid
&&
810 dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1)))
811 return nvme_setup_sgl_simple(dev
, req
,
817 iod
->sg
= mempool_alloc(dev
->iod_mempool
, GFP_ATOMIC
);
819 return BLK_STS_RESOURCE
;
820 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
821 iod
->nents
= blk_rq_map_sg(req
->q
, req
, iod
->sg
);
825 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
826 nr_mapped
= pci_p2pdma_map_sg_attrs(dev
->dev
, iod
->sg
,
827 iod
->nents
, rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
829 nr_mapped
= dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
,
830 rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
834 iod
->use_sgl
= nvme_pci_use_sgls(dev
, req
);
836 ret
= nvme_pci_setup_sgls(dev
, req
, &cmnd
->rw
, nr_mapped
);
838 ret
= nvme_pci_setup_prps(dev
, req
, &cmnd
->rw
);
840 if (ret
!= BLK_STS_OK
)
841 nvme_unmap_data(dev
, req
);
845 static blk_status_t
nvme_map_metadata(struct nvme_dev
*dev
, struct request
*req
,
846 struct nvme_command
*cmnd
)
848 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
850 iod
->meta_dma
= dma_map_bvec(dev
->dev
, rq_integrity_vec(req
),
852 if (dma_mapping_error(dev
->dev
, iod
->meta_dma
))
853 return BLK_STS_IOERR
;
854 cmnd
->rw
.metadata
= cpu_to_le64(iod
->meta_dma
);
859 * NOTE: ns is NULL when called on the admin queue.
861 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
862 const struct blk_mq_queue_data
*bd
)
864 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
865 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
866 struct nvme_dev
*dev
= nvmeq
->dev
;
867 struct request
*req
= bd
->rq
;
868 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
869 struct nvme_command cmnd
;
877 * We should not need to do this, but we're still using this to
878 * ensure we can drain requests on a dying queue.
880 if (unlikely(!test_bit(NVMEQ_ENABLED
, &nvmeq
->flags
)))
881 return BLK_STS_IOERR
;
883 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
887 if (blk_rq_nr_phys_segments(req
)) {
888 ret
= nvme_map_data(dev
, req
, &cmnd
);
893 if (blk_integrity_rq(req
)) {
894 ret
= nvme_map_metadata(dev
, req
, &cmnd
);
899 blk_mq_start_request(req
);
900 nvme_submit_cmd(nvmeq
, &cmnd
, bd
->last
);
903 nvme_unmap_data(dev
, req
);
905 nvme_cleanup_cmd(req
);
909 static void nvme_pci_complete_rq(struct request
*req
)
911 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
912 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
914 if (blk_integrity_rq(req
))
915 dma_unmap_page(dev
->dev
, iod
->meta_dma
,
916 rq_integrity_vec(req
)->bv_len
, rq_data_dir(req
));
917 if (blk_rq_nr_phys_segments(req
))
918 nvme_unmap_data(dev
, req
);
919 nvme_complete_rq(req
);
922 /* We read the CQE phase first to check if the rest of the entry is valid */
923 static inline bool nvme_cqe_pending(struct nvme_queue
*nvmeq
)
925 return (le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
929 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
931 u16 head
= nvmeq
->cq_head
;
933 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
935 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
938 static inline struct blk_mq_tags
*nvme_queue_tagset(struct nvme_queue
*nvmeq
)
941 return nvmeq
->dev
->admin_tagset
.tags
[0];
942 return nvmeq
->dev
->tagset
.tags
[nvmeq
->qid
- 1];
945 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
, u16 idx
)
947 volatile struct nvme_completion
*cqe
= &nvmeq
->cqes
[idx
];
950 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
951 dev_warn(nvmeq
->dev
->ctrl
.device
,
952 "invalid id %d completed on queue %d\n",
953 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
958 * AEN requests are special as they don't time out and can
959 * survive any kind of queue freeze and often don't respond to
960 * aborts. We don't even bother to allocate a struct request
961 * for them but rather special case them here.
963 if (unlikely(nvme_is_aen_req(nvmeq
->qid
, cqe
->command_id
))) {
964 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
965 cqe
->status
, &cqe
->result
);
969 req
= blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq
), cqe
->command_id
);
970 trace_nvme_sq(req
, cqe
->sq_head
, nvmeq
->sq_tail
);
971 nvme_end_request(req
, cqe
->status
, cqe
->result
);
974 static void nvme_complete_cqes(struct nvme_queue
*nvmeq
, u16 start
, u16 end
)
976 while (start
!= end
) {
977 nvme_handle_cqe(nvmeq
, start
);
978 if (++start
== nvmeq
->q_depth
)
983 static inline void nvme_update_cq_head(struct nvme_queue
*nvmeq
)
985 if (++nvmeq
->cq_head
== nvmeq
->q_depth
) {
987 nvmeq
->cq_phase
^= 1;
991 static inline int nvme_process_cq(struct nvme_queue
*nvmeq
, u16
*start
,
996 *start
= nvmeq
->cq_head
;
997 while (nvme_cqe_pending(nvmeq
)) {
999 nvme_update_cq_head(nvmeq
);
1001 *end
= nvmeq
->cq_head
;
1004 nvme_ring_cq_doorbell(nvmeq
);
1008 static irqreturn_t
nvme_irq(int irq
, void *data
)
1010 struct nvme_queue
*nvmeq
= data
;
1011 irqreturn_t ret
= IRQ_NONE
;
1015 * The rmb/wmb pair ensures we see all updates from a previous run of
1016 * the irq handler, even if that was on another CPU.
1019 nvme_process_cq(nvmeq
, &start
, &end
);
1023 nvme_complete_cqes(nvmeq
, start
, end
);
1030 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
1032 struct nvme_queue
*nvmeq
= data
;
1033 if (nvme_cqe_pending(nvmeq
))
1034 return IRQ_WAKE_THREAD
;
1039 * Poll for completions any queue, including those not dedicated to polling.
1040 * Can be called from any context.
1042 static int nvme_poll_irqdisable(struct nvme_queue
*nvmeq
)
1044 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1049 * For a poll queue we need to protect against the polling thread
1050 * using the CQ lock. For normal interrupt driven threads we have
1051 * to disable the interrupt to avoid racing with it.
1053 if (test_bit(NVMEQ_POLLED
, &nvmeq
->flags
)) {
1054 spin_lock(&nvmeq
->cq_poll_lock
);
1055 found
= nvme_process_cq(nvmeq
, &start
, &end
);
1056 spin_unlock(&nvmeq
->cq_poll_lock
);
1058 disable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1059 found
= nvme_process_cq(nvmeq
, &start
, &end
);
1060 enable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1063 nvme_complete_cqes(nvmeq
, start
, end
);
1067 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
)
1069 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
1073 if (!nvme_cqe_pending(nvmeq
))
1076 spin_lock(&nvmeq
->cq_poll_lock
);
1077 found
= nvme_process_cq(nvmeq
, &start
, &end
);
1078 spin_unlock(&nvmeq
->cq_poll_lock
);
1083 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
)
1085 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1086 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1087 struct nvme_command c
;
1089 memset(&c
, 0, sizeof(c
));
1090 c
.common
.opcode
= nvme_admin_async_event
;
1091 c
.common
.command_id
= NVME_AQ_BLK_MQ_DEPTH
;
1092 nvme_submit_cmd(nvmeq
, &c
, true);
1095 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1097 struct nvme_command c
;
1099 memset(&c
, 0, sizeof(c
));
1100 c
.delete_queue
.opcode
= opcode
;
1101 c
.delete_queue
.qid
= cpu_to_le16(id
);
1103 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1106 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1107 struct nvme_queue
*nvmeq
, s16 vector
)
1109 struct nvme_command c
;
1110 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1112 if (!test_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1113 flags
|= NVME_CQ_IRQ_ENABLED
;
1116 * Note: we (ab)use the fact that the prp fields survive if no data
1117 * is attached to the request.
1119 memset(&c
, 0, sizeof(c
));
1120 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1121 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1122 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1123 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1124 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1125 c
.create_cq
.irq_vector
= cpu_to_le16(vector
);
1127 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1130 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1131 struct nvme_queue
*nvmeq
)
1133 struct nvme_ctrl
*ctrl
= &dev
->ctrl
;
1134 struct nvme_command c
;
1135 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1138 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1139 * set. Since URGENT priority is zeroes, it makes all queues
1142 if (ctrl
->quirks
& NVME_QUIRK_MEDIUM_PRIO_SQ
)
1143 flags
|= NVME_SQ_PRIO_MEDIUM
;
1146 * Note: we (ab)use the fact that the prp fields survive if no data
1147 * is attached to the request.
1149 memset(&c
, 0, sizeof(c
));
1150 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1151 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1152 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1153 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1154 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1155 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1157 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1160 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1162 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1165 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1167 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1170 static void abort_endio(struct request
*req
, blk_status_t error
)
1172 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1173 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1175 dev_warn(nvmeq
->dev
->ctrl
.device
,
1176 "Abort status: 0x%x", nvme_req(req
)->status
);
1177 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
1178 blk_mq_free_request(req
);
1181 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1184 /* If true, indicates loss of adapter communication, possibly by a
1185 * NVMe Subsystem reset.
1187 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1189 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1190 switch (dev
->ctrl
.state
) {
1191 case NVME_CTRL_RESETTING
:
1192 case NVME_CTRL_CONNECTING
:
1198 /* We shouldn't reset unless the controller is on fatal error state
1199 * _or_ if we lost the communication with it.
1201 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1207 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1209 /* Read a config register to help see what died. */
1213 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1215 if (result
== PCIBIOS_SUCCESSFUL
)
1216 dev_warn(dev
->ctrl
.device
,
1217 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1220 dev_warn(dev
->ctrl
.device
,
1221 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1225 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1227 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1228 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1229 struct nvme_dev
*dev
= nvmeq
->dev
;
1230 struct request
*abort_req
;
1231 struct nvme_command cmd
;
1232 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1234 /* If PCI error recovery process is happening, we cannot reset or
1235 * the recovery mechanism will surely fail.
1238 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1239 return BLK_EH_RESET_TIMER
;
1242 * Reset immediately if the controller is failed
1244 if (nvme_should_reset(dev
, csts
)) {
1245 nvme_warn_reset(dev
, csts
);
1246 nvme_dev_disable(dev
, false);
1247 nvme_reset_ctrl(&dev
->ctrl
);
1252 * Did we miss an interrupt?
1254 nvme_poll_irqdisable(nvmeq
);
1255 if (blk_mq_request_completed(req
)) {
1256 dev_warn(dev
->ctrl
.device
,
1257 "I/O %d QID %d timeout, completion polled\n",
1258 req
->tag
, nvmeq
->qid
);
1263 * Shutdown immediately if controller times out while starting. The
1264 * reset work will see the pci device disabled when it gets the forced
1265 * cancellation error. All outstanding requests are completed on
1266 * shutdown, so we return BLK_EH_DONE.
1268 switch (dev
->ctrl
.state
) {
1269 case NVME_CTRL_CONNECTING
:
1270 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
1272 case NVME_CTRL_DELETING
:
1273 dev_warn_ratelimited(dev
->ctrl
.device
,
1274 "I/O %d QID %d timeout, disable controller\n",
1275 req
->tag
, nvmeq
->qid
);
1276 nvme_dev_disable(dev
, true);
1277 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1279 case NVME_CTRL_RESETTING
:
1280 return BLK_EH_RESET_TIMER
;
1286 * Shutdown the controller immediately and schedule a reset if the
1287 * command was already aborted once before and still hasn't been
1288 * returned to the driver, or if this is the admin queue.
1290 if (!nvmeq
->qid
|| iod
->aborted
) {
1291 dev_warn(dev
->ctrl
.device
,
1292 "I/O %d QID %d timeout, reset controller\n",
1293 req
->tag
, nvmeq
->qid
);
1294 nvme_dev_disable(dev
, false);
1295 nvme_reset_ctrl(&dev
->ctrl
);
1297 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1301 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1302 atomic_inc(&dev
->ctrl
.abort_limit
);
1303 return BLK_EH_RESET_TIMER
;
1307 memset(&cmd
, 0, sizeof(cmd
));
1308 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1309 cmd
.abort
.cid
= req
->tag
;
1310 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1312 dev_warn(nvmeq
->dev
->ctrl
.device
,
1313 "I/O %d QID %d timeout, aborting\n",
1314 req
->tag
, nvmeq
->qid
);
1316 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1317 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1318 if (IS_ERR(abort_req
)) {
1319 atomic_inc(&dev
->ctrl
.abort_limit
);
1320 return BLK_EH_RESET_TIMER
;
1323 abort_req
->timeout
= ADMIN_TIMEOUT
;
1324 abort_req
->end_io_data
= NULL
;
1325 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1328 * The aborted req will be completed on receiving the abort req.
1329 * We enable the timer again. If hit twice, it'll cause a device reset,
1330 * as the device then is in a faulty state.
1332 return BLK_EH_RESET_TIMER
;
1335 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1337 dma_free_coherent(nvmeq
->dev
->dev
, CQ_SIZE(nvmeq
),
1338 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1339 if (!nvmeq
->sq_cmds
)
1342 if (test_and_clear_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
)) {
1343 pci_free_p2pmem(to_pci_dev(nvmeq
->dev
->dev
),
1344 nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1346 dma_free_coherent(nvmeq
->dev
->dev
, SQ_SIZE(nvmeq
),
1347 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1351 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1355 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1356 dev
->ctrl
.queue_count
--;
1357 nvme_free_queue(&dev
->queues
[i
]);
1362 * nvme_suspend_queue - put queue into suspended state
1363 * @nvmeq: queue to suspend
1365 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1367 if (!test_and_clear_bit(NVMEQ_ENABLED
, &nvmeq
->flags
))
1370 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1373 nvmeq
->dev
->online_queues
--;
1374 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1375 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1376 if (!test_and_clear_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1377 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), nvmeq
->cq_vector
, nvmeq
);
1381 static void nvme_suspend_io_queues(struct nvme_dev
*dev
)
1385 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
1386 nvme_suspend_queue(&dev
->queues
[i
]);
1389 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1391 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1394 nvme_shutdown_ctrl(&dev
->ctrl
);
1396 nvme_disable_ctrl(&dev
->ctrl
);
1398 nvme_poll_irqdisable(nvmeq
);
1402 * Called only on a device that has been disabled and after all other threads
1403 * that can check this device's completion queues have synced. This is the
1404 * last chance for the driver to see a natural completion before
1405 * nvme_cancel_request() terminates all incomplete requests.
1407 static void nvme_reap_pending_cqes(struct nvme_dev
*dev
)
1412 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--) {
1413 nvme_process_cq(&dev
->queues
[i
], &start
, &end
);
1414 nvme_complete_cqes(&dev
->queues
[i
], start
, end
);
1418 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1421 int q_depth
= dev
->q_depth
;
1422 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1423 dev
->ctrl
.page_size
);
1425 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1426 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1427 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1428 q_depth
= div_u64(mem_per_q
, entry_size
);
1431 * Ensure the reduced q_depth is above some threshold where it
1432 * would be better to map queues in system memory with the
1442 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1445 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1447 if (qid
&& dev
->cmb_use_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
)) {
1448 nvmeq
->sq_cmds
= pci_alloc_p2pmem(pdev
, SQ_SIZE(nvmeq
));
1449 if (nvmeq
->sq_cmds
) {
1450 nvmeq
->sq_dma_addr
= pci_p2pmem_virt_to_bus(pdev
,
1452 if (nvmeq
->sq_dma_addr
) {
1453 set_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
);
1457 pci_free_p2pmem(pdev
, nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1461 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(nvmeq
),
1462 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1463 if (!nvmeq
->sq_cmds
)
1468 static int nvme_alloc_queue(struct nvme_dev
*dev
, int qid
, int depth
)
1470 struct nvme_queue
*nvmeq
= &dev
->queues
[qid
];
1472 if (dev
->ctrl
.queue_count
> qid
)
1475 nvmeq
->sqes
= qid
? dev
->io_sqes
: NVME_ADM_SQES
;
1476 nvmeq
->q_depth
= depth
;
1477 nvmeq
->cqes
= dma_alloc_coherent(dev
->dev
, CQ_SIZE(nvmeq
),
1478 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1482 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
))
1486 spin_lock_init(&nvmeq
->sq_lock
);
1487 spin_lock_init(&nvmeq
->cq_poll_lock
);
1489 nvmeq
->cq_phase
= 1;
1490 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1492 dev
->ctrl
.queue_count
++;
1497 dma_free_coherent(dev
->dev
, CQ_SIZE(nvmeq
), (void *)nvmeq
->cqes
,
1498 nvmeq
->cq_dma_addr
);
1503 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1505 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1506 int nr
= nvmeq
->dev
->ctrl
.instance
;
1508 if (use_threaded_interrupts
) {
1509 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1510 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1512 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1513 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1517 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1519 struct nvme_dev
*dev
= nvmeq
->dev
;
1522 nvmeq
->last_sq_tail
= 0;
1524 nvmeq
->cq_phase
= 1;
1525 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1526 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
));
1527 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1528 dev
->online_queues
++;
1529 wmb(); /* ensure the first interrupt sees the initialization */
1532 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
, bool polled
)
1534 struct nvme_dev
*dev
= nvmeq
->dev
;
1538 clear_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
1541 * A queue's vector matches the queue identifier unless the controller
1542 * has only one vector available.
1545 vector
= dev
->num_vecs
== 1 ? 0 : qid
;
1547 set_bit(NVMEQ_POLLED
, &nvmeq
->flags
);
1549 result
= adapter_alloc_cq(dev
, qid
, nvmeq
, vector
);
1553 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1559 nvmeq
->cq_vector
= vector
;
1560 nvme_init_queue(nvmeq
, qid
);
1563 result
= queue_request_irq(nvmeq
);
1568 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1572 dev
->online_queues
--;
1573 adapter_delete_sq(dev
, qid
);
1575 adapter_delete_cq(dev
, qid
);
1579 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1580 .queue_rq
= nvme_queue_rq
,
1581 .complete
= nvme_pci_complete_rq
,
1582 .init_hctx
= nvme_admin_init_hctx
,
1583 .init_request
= nvme_init_request
,
1584 .timeout
= nvme_timeout
,
1587 static const struct blk_mq_ops nvme_mq_ops
= {
1588 .queue_rq
= nvme_queue_rq
,
1589 .complete
= nvme_pci_complete_rq
,
1590 .commit_rqs
= nvme_commit_rqs
,
1591 .init_hctx
= nvme_init_hctx
,
1592 .init_request
= nvme_init_request
,
1593 .map_queues
= nvme_pci_map_queues
,
1594 .timeout
= nvme_timeout
,
1598 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1600 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1602 * If the controller was reset during removal, it's possible
1603 * user requests may be waiting on a stopped queue. Start the
1604 * queue to flush these to completion.
1606 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1607 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1608 blk_mq_free_tag_set(&dev
->admin_tagset
);
1612 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1614 if (!dev
->ctrl
.admin_q
) {
1615 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1616 dev
->admin_tagset
.nr_hw_queues
= 1;
1618 dev
->admin_tagset
.queue_depth
= NVME_AQ_MQ_TAG_DEPTH
;
1619 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1620 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1621 dev
->admin_tagset
.cmd_size
= sizeof(struct nvme_iod
);
1622 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1623 dev
->admin_tagset
.driver_data
= dev
;
1625 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1627 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1629 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1630 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1631 blk_mq_free_tag_set(&dev
->admin_tagset
);
1634 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1635 nvme_dev_remove_admin(dev
);
1636 dev
->ctrl
.admin_q
= NULL
;
1640 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1645 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1647 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1650 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1652 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1654 if (size
<= dev
->bar_mapped_size
)
1656 if (size
> pci_resource_len(pdev
, 0))
1660 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1662 dev
->bar_mapped_size
= 0;
1665 dev
->bar_mapped_size
= size
;
1666 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1671 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1675 struct nvme_queue
*nvmeq
;
1677 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1681 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1682 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1684 if (dev
->subsystem
&&
1685 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1686 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1688 result
= nvme_disable_ctrl(&dev
->ctrl
);
1692 result
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1696 nvmeq
= &dev
->queues
[0];
1697 aqa
= nvmeq
->q_depth
- 1;
1700 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1701 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1702 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1704 result
= nvme_enable_ctrl(&dev
->ctrl
);
1708 nvmeq
->cq_vector
= 0;
1709 nvme_init_queue(nvmeq
, 0);
1710 result
= queue_request_irq(nvmeq
);
1712 dev
->online_queues
--;
1716 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1720 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1722 unsigned i
, max
, rw_queues
;
1725 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1726 if (nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1732 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1733 if (max
!= 1 && dev
->io_queues
[HCTX_TYPE_POLL
]) {
1734 rw_queues
= dev
->io_queues
[HCTX_TYPE_DEFAULT
] +
1735 dev
->io_queues
[HCTX_TYPE_READ
];
1740 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1741 bool polled
= i
> rw_queues
;
1743 ret
= nvme_create_queue(&dev
->queues
[i
], i
, polled
);
1749 * Ignore failing Create SQ/CQ commands, we can continue with less
1750 * than the desired amount of queues, and even a controller without
1751 * I/O queues can still be used to issue admin commands. This might
1752 * be useful to upgrade a buggy firmware for example.
1754 return ret
>= 0 ? 0 : ret
;
1757 static ssize_t
nvme_cmb_show(struct device
*dev
,
1758 struct device_attribute
*attr
,
1761 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1763 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1764 ndev
->cmbloc
, ndev
->cmbsz
);
1766 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1768 static u64
nvme_cmb_size_unit(struct nvme_dev
*dev
)
1770 u8 szu
= (dev
->cmbsz
>> NVME_CMBSZ_SZU_SHIFT
) & NVME_CMBSZ_SZU_MASK
;
1772 return 1ULL << (12 + 4 * szu
);
1775 static u32
nvme_cmb_size(struct nvme_dev
*dev
)
1777 return (dev
->cmbsz
>> NVME_CMBSZ_SZ_SHIFT
) & NVME_CMBSZ_SZ_MASK
;
1780 static void nvme_map_cmb(struct nvme_dev
*dev
)
1783 resource_size_t bar_size
;
1784 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1790 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1793 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1795 size
= nvme_cmb_size_unit(dev
) * nvme_cmb_size(dev
);
1796 offset
= nvme_cmb_size_unit(dev
) * NVME_CMB_OFST(dev
->cmbloc
);
1797 bar
= NVME_CMB_BIR(dev
->cmbloc
);
1798 bar_size
= pci_resource_len(pdev
, bar
);
1800 if (offset
> bar_size
)
1804 * Controllers may support a CMB size larger than their BAR,
1805 * for example, due to being behind a bridge. Reduce the CMB to
1806 * the reported size of the BAR
1808 if (size
> bar_size
- offset
)
1809 size
= bar_size
- offset
;
1811 if (pci_p2pdma_add_resource(pdev
, bar
, size
, offset
)) {
1812 dev_warn(dev
->ctrl
.device
,
1813 "failed to register the CMB\n");
1817 dev
->cmb_size
= size
;
1818 dev
->cmb_use_sqes
= use_cmb_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
);
1820 if ((dev
->cmbsz
& (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
)) ==
1821 (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
))
1822 pci_p2pmem_publish(pdev
, true);
1824 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1825 &dev_attr_cmb
.attr
, NULL
))
1826 dev_warn(dev
->ctrl
.device
,
1827 "failed to add sysfs attribute for CMB\n");
1830 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1832 if (dev
->cmb_size
) {
1833 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1834 &dev_attr_cmb
.attr
, NULL
);
1839 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1841 u64 dma_addr
= dev
->host_mem_descs_dma
;
1842 struct nvme_command c
;
1845 memset(&c
, 0, sizeof(c
));
1846 c
.features
.opcode
= nvme_admin_set_features
;
1847 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1848 c
.features
.dword11
= cpu_to_le32(bits
);
1849 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1850 ilog2(dev
->ctrl
.page_size
));
1851 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1852 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1853 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1855 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1857 dev_warn(dev
->ctrl
.device
,
1858 "failed to set host mem (err %d, flags %#x).\n",
1864 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1868 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1869 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1870 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1872 dma_free_attrs(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1873 le64_to_cpu(desc
->addr
),
1874 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1877 kfree(dev
->host_mem_desc_bufs
);
1878 dev
->host_mem_desc_bufs
= NULL
;
1879 dma_free_coherent(dev
->dev
,
1880 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1881 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1882 dev
->host_mem_descs
= NULL
;
1883 dev
->nr_host_mem_descs
= 0;
1886 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1889 struct nvme_host_mem_buf_desc
*descs
;
1890 u32 max_entries
, len
;
1891 dma_addr_t descs_dma
;
1896 tmp
= (preferred
+ chunk_size
- 1);
1897 do_div(tmp
, chunk_size
);
1900 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1901 max_entries
= dev
->ctrl
.hmmaxd
;
1903 descs
= dma_alloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1904 &descs_dma
, GFP_KERNEL
);
1908 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1910 goto out_free_descs
;
1912 for (size
= 0; size
< preferred
&& i
< max_entries
; size
+= len
) {
1913 dma_addr_t dma_addr
;
1915 len
= min_t(u64
, chunk_size
, preferred
- size
);
1916 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1917 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1921 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1922 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1929 dev
->nr_host_mem_descs
= i
;
1930 dev
->host_mem_size
= size
;
1931 dev
->host_mem_descs
= descs
;
1932 dev
->host_mem_descs_dma
= descs_dma
;
1933 dev
->host_mem_desc_bufs
= bufs
;
1938 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1940 dma_free_attrs(dev
->dev
, size
, bufs
[i
],
1941 le64_to_cpu(descs
[i
].addr
),
1942 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1947 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1950 dev
->host_mem_descs
= NULL
;
1954 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1958 /* start big and work our way down */
1959 for (chunk_size
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
1960 chunk_size
>= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
1962 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
1963 if (!min
|| dev
->host_mem_size
>= min
)
1965 nvme_free_host_mem(dev
);
1972 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
1974 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1975 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1976 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1977 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1980 preferred
= min(preferred
, max
);
1982 dev_warn(dev
->ctrl
.device
,
1983 "min host memory (%lld MiB) above limit (%d MiB).\n",
1984 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1985 nvme_free_host_mem(dev
);
1990 * If we already have a buffer allocated check if we can reuse it.
1992 if (dev
->host_mem_descs
) {
1993 if (dev
->host_mem_size
>= min
)
1994 enable_bits
|= NVME_HOST_MEM_RETURN
;
1996 nvme_free_host_mem(dev
);
1999 if (!dev
->host_mem_descs
) {
2000 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
2001 dev_warn(dev
->ctrl
.device
,
2002 "failed to allocate host memory buffer.\n");
2003 return 0; /* controller must work without HMB */
2006 dev_info(dev
->ctrl
.device
,
2007 "allocated %lld MiB host memory buffer.\n",
2008 dev
->host_mem_size
>> ilog2(SZ_1M
));
2011 ret
= nvme_set_host_mem(dev
, enable_bits
);
2013 nvme_free_host_mem(dev
);
2018 * nirqs is the number of interrupts available for write and read
2019 * queues. The core already reserved an interrupt for the admin queue.
2021 static void nvme_calc_irq_sets(struct irq_affinity
*affd
, unsigned int nrirqs
)
2023 struct nvme_dev
*dev
= affd
->priv
;
2024 unsigned int nr_read_queues
;
2027 * If there is no interupt available for queues, ensure that
2028 * the default queue is set to 1. The affinity set size is
2029 * also set to one, but the irq core ignores it for this case.
2031 * If only one interrupt is available or 'write_queue' == 0, combine
2032 * write and read queues.
2034 * If 'write_queues' > 0, ensure it leaves room for at least one read
2040 } else if (nrirqs
== 1 || !write_queues
) {
2042 } else if (write_queues
>= nrirqs
) {
2045 nr_read_queues
= nrirqs
- write_queues
;
2048 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2049 affd
->set_size
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2050 dev
->io_queues
[HCTX_TYPE_READ
] = nr_read_queues
;
2051 affd
->set_size
[HCTX_TYPE_READ
] = nr_read_queues
;
2052 affd
->nr_sets
= nr_read_queues
? 2 : 1;
2055 static int nvme_setup_irqs(struct nvme_dev
*dev
, unsigned int nr_io_queues
)
2057 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2058 struct irq_affinity affd
= {
2060 .calc_sets
= nvme_calc_irq_sets
,
2063 unsigned int irq_queues
, this_p_queues
;
2066 * Poll queues don't need interrupts, but we need at least one IO
2067 * queue left over for non-polled IO.
2069 this_p_queues
= poll_queues
;
2070 if (this_p_queues
>= nr_io_queues
) {
2071 this_p_queues
= nr_io_queues
- 1;
2074 irq_queues
= nr_io_queues
- this_p_queues
+ 1;
2076 dev
->io_queues
[HCTX_TYPE_POLL
] = this_p_queues
;
2078 /* Initialize for the single interrupt case */
2079 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = 1;
2080 dev
->io_queues
[HCTX_TYPE_READ
] = 0;
2083 * Some Apple controllers require all queues to use the
2086 if (dev
->ctrl
.quirks
& NVME_QUIRK_SINGLE_VECTOR
)
2089 return pci_alloc_irq_vectors_affinity(pdev
, 1, irq_queues
,
2090 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
, &affd
);
2093 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
2095 if (__nvme_disable_io_queues(dev
, nvme_admin_delete_sq
))
2096 __nvme_disable_io_queues(dev
, nvme_admin_delete_cq
);
2099 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
2101 struct nvme_queue
*adminq
= &dev
->queues
[0];
2102 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2103 int result
, nr_io_queues
;
2106 nr_io_queues
= max_io_queues();
2109 * If tags are shared with admin queue (Apple bug), then
2110 * make sure we only use one IO queue.
2112 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2115 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
2119 if (nr_io_queues
== 0)
2122 clear_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2124 if (dev
->cmb_use_sqes
) {
2125 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
2126 sizeof(struct nvme_command
));
2128 dev
->q_depth
= result
;
2130 dev
->cmb_use_sqes
= false;
2134 size
= db_bar_size(dev
, nr_io_queues
);
2135 result
= nvme_remap_bar(dev
, size
);
2138 if (!--nr_io_queues
)
2141 adminq
->q_db
= dev
->dbs
;
2144 /* Deregister the admin queue's interrupt */
2145 pci_free_irq(pdev
, 0, adminq
);
2148 * If we enable msix early due to not intx, disable it again before
2149 * setting up the full range we need.
2151 pci_free_irq_vectors(pdev
);
2153 result
= nvme_setup_irqs(dev
, nr_io_queues
);
2157 dev
->num_vecs
= result
;
2158 result
= max(result
- 1, 1);
2159 dev
->max_qid
= result
+ dev
->io_queues
[HCTX_TYPE_POLL
];
2162 * Should investigate if there's a performance win from allocating
2163 * more queues than interrupt vectors; it might allow the submission
2164 * path to scale better, even if the receive path is limited by the
2165 * number of interrupts.
2167 result
= queue_request_irq(adminq
);
2170 set_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2172 result
= nvme_create_io_queues(dev
);
2173 if (result
|| dev
->online_queues
< 2)
2176 if (dev
->online_queues
- 1 < dev
->max_qid
) {
2177 nr_io_queues
= dev
->online_queues
- 1;
2178 nvme_disable_io_queues(dev
);
2179 nvme_suspend_io_queues(dev
);
2182 dev_info(dev
->ctrl
.device
, "%d/%d/%d default/read/poll queues\n",
2183 dev
->io_queues
[HCTX_TYPE_DEFAULT
],
2184 dev
->io_queues
[HCTX_TYPE_READ
],
2185 dev
->io_queues
[HCTX_TYPE_POLL
]);
2189 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
2191 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2193 blk_mq_free_request(req
);
2194 complete(&nvmeq
->delete_done
);
2197 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
2199 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2202 set_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
2204 nvme_del_queue_end(req
, error
);
2207 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
2209 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
2210 struct request
*req
;
2211 struct nvme_command cmd
;
2213 memset(&cmd
, 0, sizeof(cmd
));
2214 cmd
.delete_queue
.opcode
= opcode
;
2215 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
2217 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
2219 return PTR_ERR(req
);
2221 req
->timeout
= ADMIN_TIMEOUT
;
2222 req
->end_io_data
= nvmeq
;
2224 init_completion(&nvmeq
->delete_done
);
2225 blk_execute_rq_nowait(q
, NULL
, req
, false,
2226 opcode
== nvme_admin_delete_cq
?
2227 nvme_del_cq_end
: nvme_del_queue_end
);
2231 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
)
2233 int nr_queues
= dev
->online_queues
- 1, sent
= 0;
2234 unsigned long timeout
;
2237 timeout
= ADMIN_TIMEOUT
;
2238 while (nr_queues
> 0) {
2239 if (nvme_delete_queue(&dev
->queues
[nr_queues
], opcode
))
2245 struct nvme_queue
*nvmeq
= &dev
->queues
[nr_queues
+ sent
];
2247 timeout
= wait_for_completion_io_timeout(&nvmeq
->delete_done
,
2259 static void nvme_dev_add(struct nvme_dev
*dev
)
2263 if (!dev
->ctrl
.tagset
) {
2264 dev
->tagset
.ops
= &nvme_mq_ops
;
2265 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
2266 dev
->tagset
.nr_maps
= 2; /* default + read */
2267 if (dev
->io_queues
[HCTX_TYPE_POLL
])
2268 dev
->tagset
.nr_maps
++;
2269 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
2270 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
2271 dev
->tagset
.queue_depth
=
2272 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
2273 dev
->tagset
.cmd_size
= sizeof(struct nvme_iod
);
2274 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
2275 dev
->tagset
.driver_data
= dev
;
2278 * Some Apple controllers requires tags to be unique
2279 * across admin and IO queue, so reserve the first 32
2280 * tags of the IO queue.
2282 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2283 dev
->tagset
.reserved_tags
= NVME_AQ_DEPTH
;
2285 ret
= blk_mq_alloc_tag_set(&dev
->tagset
);
2287 dev_warn(dev
->ctrl
.device
,
2288 "IO queues tagset allocation failed %d\n", ret
);
2291 dev
->ctrl
.tagset
= &dev
->tagset
;
2293 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
2295 /* Free previously allocated queues that are no longer usable */
2296 nvme_free_queues(dev
, dev
->online_queues
);
2299 nvme_dbbuf_set(dev
);
2302 static int nvme_pci_enable(struct nvme_dev
*dev
)
2304 int result
= -ENOMEM
;
2305 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2307 if (pci_enable_device_mem(pdev
))
2310 pci_set_master(pdev
);
2312 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)))
2315 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
2321 * Some devices and/or platforms don't advertise or work with INTx
2322 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2323 * adjust this later.
2325 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
2329 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
2331 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
2333 dev
->ctrl
.sqsize
= dev
->q_depth
- 1; /* 0's based queue depth */
2334 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
2335 dev
->dbs
= dev
->bar
+ 4096;
2338 * Some Apple controllers require a non-standard SQE size.
2339 * Interestingly they also seem to ignore the CC:IOSQES register
2340 * so we don't bother updating it here.
2342 if (dev
->ctrl
.quirks
& NVME_QUIRK_128_BYTES_SQES
)
2345 dev
->io_sqes
= NVME_NVM_IOSQES
;
2348 * Temporary fix for the Apple controller found in the MacBook8,1 and
2349 * some MacBook7,1 to avoid controller resets and data loss.
2351 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
2353 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
2354 "set queue depth=%u to work around controller resets\n",
2356 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
2357 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
2358 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
2360 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
2361 "set queue depth=%u\n", dev
->q_depth
);
2365 * Controllers with the shared tags quirk need the IO queue to be
2366 * big enough so that we get 32 tags for the admin queue
2368 if ((dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
) &&
2369 (dev
->q_depth
< (NVME_AQ_DEPTH
+ 2))) {
2370 dev
->q_depth
= NVME_AQ_DEPTH
+ 2;
2371 dev_warn(dev
->ctrl
.device
, "IO queue depth clamped to %d\n",
2378 pci_enable_pcie_error_reporting(pdev
);
2379 pci_save_state(pdev
);
2383 pci_disable_device(pdev
);
2387 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2391 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2394 static void nvme_pci_disable(struct nvme_dev
*dev
)
2396 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2398 pci_free_irq_vectors(pdev
);
2400 if (pci_is_enabled(pdev
)) {
2401 pci_disable_pcie_error_reporting(pdev
);
2402 pci_disable_device(pdev
);
2406 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2408 bool dead
= true, freeze
= false;
2409 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2411 mutex_lock(&dev
->shutdown_lock
);
2412 if (pci_is_enabled(pdev
)) {
2413 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2415 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2416 dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
2418 nvme_start_freeze(&dev
->ctrl
);
2420 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2421 pdev
->error_state
!= pci_channel_io_normal
);
2425 * Give the controller a chance to complete all entered requests if
2426 * doing a safe shutdown.
2428 if (!dead
&& shutdown
&& freeze
)
2429 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2431 nvme_stop_queues(&dev
->ctrl
);
2433 if (!dead
&& dev
->ctrl
.queue_count
> 0) {
2434 nvme_disable_io_queues(dev
);
2435 nvme_disable_admin_queue(dev
, shutdown
);
2437 nvme_suspend_io_queues(dev
);
2438 nvme_suspend_queue(&dev
->queues
[0]);
2439 nvme_pci_disable(dev
);
2440 nvme_reap_pending_cqes(dev
);
2442 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2443 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2444 blk_mq_tagset_wait_completed_request(&dev
->tagset
);
2445 blk_mq_tagset_wait_completed_request(&dev
->admin_tagset
);
2448 * The driver will not be starting up queues again if shutting down so
2449 * must flush all entered requests to their failed completion to avoid
2450 * deadlocking blk-mq hot-cpu notifier.
2453 nvme_start_queues(&dev
->ctrl
);
2454 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
))
2455 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
2457 mutex_unlock(&dev
->shutdown_lock
);
2460 static int nvme_disable_prepare_reset(struct nvme_dev
*dev
, bool shutdown
)
2462 if (!nvme_wait_reset(&dev
->ctrl
))
2464 nvme_dev_disable(dev
, shutdown
);
2468 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2470 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2471 PAGE_SIZE
, PAGE_SIZE
, 0);
2472 if (!dev
->prp_page_pool
)
2475 /* Optimisation for I/Os between 4k and 128k */
2476 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2478 if (!dev
->prp_small_pool
) {
2479 dma_pool_destroy(dev
->prp_page_pool
);
2485 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2487 dma_pool_destroy(dev
->prp_page_pool
);
2488 dma_pool_destroy(dev
->prp_small_pool
);
2491 static void nvme_free_tagset(struct nvme_dev
*dev
)
2493 if (dev
->tagset
.tags
)
2494 blk_mq_free_tag_set(&dev
->tagset
);
2495 dev
->ctrl
.tagset
= NULL
;
2498 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2500 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2502 nvme_dbbuf_dma_free(dev
);
2503 put_device(dev
->dev
);
2504 nvme_free_tagset(dev
);
2505 if (dev
->ctrl
.admin_q
)
2506 blk_put_queue(dev
->ctrl
.admin_q
);
2508 free_opal_dev(dev
->ctrl
.opal_dev
);
2509 mempool_destroy(dev
->iod_mempool
);
2513 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
)
2516 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2517 * may be holding this pci_dev's device lock.
2519 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2520 nvme_get_ctrl(&dev
->ctrl
);
2521 nvme_dev_disable(dev
, false);
2522 nvme_kill_queues(&dev
->ctrl
);
2523 if (!queue_work(nvme_wq
, &dev
->remove_work
))
2524 nvme_put_ctrl(&dev
->ctrl
);
2527 static void nvme_reset_work(struct work_struct
*work
)
2529 struct nvme_dev
*dev
=
2530 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2531 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2534 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
)) {
2540 * If we're called to reset a live controller first shut it down before
2543 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2544 nvme_dev_disable(dev
, false);
2545 nvme_sync_queues(&dev
->ctrl
);
2547 mutex_lock(&dev
->shutdown_lock
);
2548 result
= nvme_pci_enable(dev
);
2552 result
= nvme_pci_configure_admin_queue(dev
);
2556 result
= nvme_alloc_admin_tags(dev
);
2561 * Limit the max command size to prevent iod->sg allocations going
2562 * over a single page.
2564 dev
->ctrl
.max_hw_sectors
= min_t(u32
,
2565 NVME_MAX_KB_SZ
<< 1, dma_max_mapping_size(dev
->dev
) >> 9);
2566 dev
->ctrl
.max_segments
= NVME_MAX_SEGS
;
2569 * Don't limit the IOMMU merged segment size.
2571 dma_set_max_seg_size(dev
->dev
, 0xffffffff);
2573 mutex_unlock(&dev
->shutdown_lock
);
2576 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2577 * initializing procedure here.
2579 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_CONNECTING
)) {
2580 dev_warn(dev
->ctrl
.device
,
2581 "failed to mark controller CONNECTING\n");
2586 result
= nvme_init_identify(&dev
->ctrl
);
2590 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2591 if (!dev
->ctrl
.opal_dev
)
2592 dev
->ctrl
.opal_dev
=
2593 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2594 else if (was_suspend
)
2595 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2597 free_opal_dev(dev
->ctrl
.opal_dev
);
2598 dev
->ctrl
.opal_dev
= NULL
;
2601 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2602 result
= nvme_dbbuf_dma_alloc(dev
);
2605 "unable to allocate dma for dbbuf\n");
2608 if (dev
->ctrl
.hmpre
) {
2609 result
= nvme_setup_host_mem(dev
);
2614 result
= nvme_setup_io_queues(dev
);
2619 * Keep the controller around but remove all namespaces if we don't have
2620 * any working I/O queue.
2622 if (dev
->online_queues
< 2) {
2623 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2624 nvme_kill_queues(&dev
->ctrl
);
2625 nvme_remove_namespaces(&dev
->ctrl
);
2626 nvme_free_tagset(dev
);
2628 nvme_start_queues(&dev
->ctrl
);
2629 nvme_wait_freeze(&dev
->ctrl
);
2631 nvme_unfreeze(&dev
->ctrl
);
2635 * If only admin queue live, keep it to do further investigation or
2638 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2639 dev_warn(dev
->ctrl
.device
,
2640 "failed to mark controller live state\n");
2645 nvme_start_ctrl(&dev
->ctrl
);
2649 mutex_unlock(&dev
->shutdown_lock
);
2652 dev_warn(dev
->ctrl
.device
,
2653 "Removing after probe failure status: %d\n", result
);
2654 nvme_remove_dead_ctrl(dev
);
2657 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2659 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2660 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2662 if (pci_get_drvdata(pdev
))
2663 device_release_driver(&pdev
->dev
);
2664 nvme_put_ctrl(&dev
->ctrl
);
2667 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2669 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2673 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2675 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2679 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2681 *val
= lo_hi_readq(to_nvme_dev(ctrl
)->bar
+ off
);
2685 static int nvme_pci_get_address(struct nvme_ctrl
*ctrl
, char *buf
, int size
)
2687 struct pci_dev
*pdev
= to_pci_dev(to_nvme_dev(ctrl
)->dev
);
2689 return snprintf(buf
, size
, "%s", dev_name(&pdev
->dev
));
2692 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2694 .module
= THIS_MODULE
,
2695 .flags
= NVME_F_METADATA_SUPPORTED
|
2697 .reg_read32
= nvme_pci_reg_read32
,
2698 .reg_write32
= nvme_pci_reg_write32
,
2699 .reg_read64
= nvme_pci_reg_read64
,
2700 .free_ctrl
= nvme_pci_free_ctrl
,
2701 .submit_async_event
= nvme_pci_submit_async_event
,
2702 .get_address
= nvme_pci_get_address
,
2705 static int nvme_dev_map(struct nvme_dev
*dev
)
2707 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2709 if (pci_request_mem_regions(pdev
, "nvme"))
2712 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2717 pci_release_mem_regions(pdev
);
2721 static unsigned long check_vendor_combination_bug(struct pci_dev
*pdev
)
2723 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2725 * Several Samsung devices seem to drop off the PCIe bus
2726 * randomly when APST is on and uses the deepest sleep state.
2727 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2728 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2729 * 950 PRO 256GB", but it seems to be restricted to two Dell
2732 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2733 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2734 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2735 return NVME_QUIRK_NO_DEEPEST_PS
;
2736 } else if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa804) {
2738 * Samsung SSD 960 EVO drops off the PCIe bus after system
2739 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2740 * within few minutes after bootup on a Coffee Lake board -
2743 if (dmi_match(DMI_BOARD_VENDOR
, "ASUSTeK COMPUTER INC.") &&
2744 (dmi_match(DMI_BOARD_NAME
, "PRIME B350M-A") ||
2745 dmi_match(DMI_BOARD_NAME
, "PRIME Z370-A")))
2746 return NVME_QUIRK_NO_APST
;
2747 } else if ((pdev
->vendor
== 0x144d && (pdev
->device
== 0xa801 ||
2748 pdev
->device
== 0xa808 || pdev
->device
== 0xa809)) ||
2749 (pdev
->vendor
== 0x1e0f && pdev
->device
== 0x0001)) {
2751 * Forcing to use host managed nvme power settings for
2752 * lowest idle power with quick resume latency on
2753 * Samsung and Toshiba SSDs based on suspend behavior
2754 * on Coffee Lake board for LENOVO C640
2756 if ((dmi_match(DMI_BOARD_VENDOR
, "LENOVO")) &&
2757 dmi_match(DMI_BOARD_NAME
, "LNVNB161216"))
2758 return NVME_QUIRK_SIMPLE_SUSPEND
;
2764 static void nvme_async_probe(void *data
, async_cookie_t cookie
)
2766 struct nvme_dev
*dev
= data
;
2768 flush_work(&dev
->ctrl
.reset_work
);
2769 flush_work(&dev
->ctrl
.scan_work
);
2770 nvme_put_ctrl(&dev
->ctrl
);
2773 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2775 int node
, result
= -ENOMEM
;
2776 struct nvme_dev
*dev
;
2777 unsigned long quirks
= id
->driver_data
;
2780 node
= dev_to_node(&pdev
->dev
);
2781 if (node
== NUMA_NO_NODE
)
2782 set_dev_node(&pdev
->dev
, first_memory_node
);
2784 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2788 dev
->queues
= kcalloc_node(max_queue_count(), sizeof(struct nvme_queue
),
2793 dev
->dev
= get_device(&pdev
->dev
);
2794 pci_set_drvdata(pdev
, dev
);
2796 result
= nvme_dev_map(dev
);
2800 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2801 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2802 mutex_init(&dev
->shutdown_lock
);
2804 result
= nvme_setup_prp_pools(dev
);
2808 quirks
|= check_vendor_combination_bug(pdev
);
2811 * Double check that our mempool alloc size will cover the biggest
2812 * command we support.
2814 alloc_size
= nvme_pci_iod_alloc_size(dev
, NVME_MAX_KB_SZ
,
2815 NVME_MAX_SEGS
, true);
2816 WARN_ON_ONCE(alloc_size
> PAGE_SIZE
);
2818 dev
->iod_mempool
= mempool_create_node(1, mempool_kmalloc
,
2820 (void *) alloc_size
,
2822 if (!dev
->iod_mempool
) {
2827 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2830 goto release_mempool
;
2832 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2834 nvme_reset_ctrl(&dev
->ctrl
);
2835 nvme_get_ctrl(&dev
->ctrl
);
2836 async_schedule(nvme_async_probe
, dev
);
2841 mempool_destroy(dev
->iod_mempool
);
2843 nvme_release_prp_pools(dev
);
2845 nvme_dev_unmap(dev
);
2847 put_device(dev
->dev
);
2854 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2856 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2859 * We don't need to check the return value from waiting for the reset
2860 * state as pci_dev device lock is held, making it impossible to race
2863 nvme_disable_prepare_reset(dev
, false);
2864 nvme_sync_queues(&dev
->ctrl
);
2867 static void nvme_reset_done(struct pci_dev
*pdev
)
2869 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2871 if (!nvme_try_sched_reset(&dev
->ctrl
))
2872 flush_work(&dev
->ctrl
.reset_work
);
2875 static void nvme_shutdown(struct pci_dev
*pdev
)
2877 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2878 nvme_disable_prepare_reset(dev
, true);
2882 * The driver's remove may be called on a device in a partially initialized
2883 * state. This function must not have any dependencies on the device state in
2886 static void nvme_remove(struct pci_dev
*pdev
)
2888 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2890 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2891 pci_set_drvdata(pdev
, NULL
);
2893 if (!pci_device_is_present(pdev
)) {
2894 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2895 nvme_dev_disable(dev
, true);
2896 nvme_dev_remove_admin(dev
);
2899 flush_work(&dev
->ctrl
.reset_work
);
2900 nvme_stop_ctrl(&dev
->ctrl
);
2901 nvme_remove_namespaces(&dev
->ctrl
);
2902 nvme_dev_disable(dev
, true);
2903 nvme_release_cmb(dev
);
2904 nvme_free_host_mem(dev
);
2905 nvme_dev_remove_admin(dev
);
2906 nvme_free_queues(dev
, 0);
2907 nvme_uninit_ctrl(&dev
->ctrl
);
2908 nvme_release_prp_pools(dev
);
2909 nvme_dev_unmap(dev
);
2910 nvme_put_ctrl(&dev
->ctrl
);
2913 #ifdef CONFIG_PM_SLEEP
2914 static int nvme_get_power_state(struct nvme_ctrl
*ctrl
, u32
*ps
)
2916 return nvme_get_features(ctrl
, NVME_FEAT_POWER_MGMT
, 0, NULL
, 0, ps
);
2919 static int nvme_set_power_state(struct nvme_ctrl
*ctrl
, u32 ps
)
2921 return nvme_set_features(ctrl
, NVME_FEAT_POWER_MGMT
, ps
, NULL
, 0, NULL
);
2924 static int nvme_resume(struct device
*dev
)
2926 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
2927 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2929 if (ndev
->last_ps
== U32_MAX
||
2930 nvme_set_power_state(ctrl
, ndev
->last_ps
) != 0)
2931 return nvme_try_sched_reset(&ndev
->ctrl
);
2935 static int nvme_suspend(struct device
*dev
)
2937 struct pci_dev
*pdev
= to_pci_dev(dev
);
2938 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2939 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2942 ndev
->last_ps
= U32_MAX
;
2945 * The platform does not remove power for a kernel managed suspend so
2946 * use host managed nvme power settings for lowest idle power if
2947 * possible. This should have quicker resume latency than a full device
2948 * shutdown. But if the firmware is involved after the suspend or the
2949 * device does not support any non-default power states, shut down the
2952 * If ASPM is not enabled for the device, shut down the device and allow
2953 * the PCI bus layer to put it into D3 in order to take the PCIe link
2954 * down, so as to allow the platform to achieve its minimum low-power
2955 * state (which may not be possible if the link is up).
2957 if (pm_suspend_via_firmware() || !ctrl
->npss
||
2958 !pcie_aspm_enabled(pdev
) ||
2959 (ndev
->ctrl
.quirks
& NVME_QUIRK_SIMPLE_SUSPEND
))
2960 return nvme_disable_prepare_reset(ndev
, true);
2962 nvme_start_freeze(ctrl
);
2963 nvme_wait_freeze(ctrl
);
2964 nvme_sync_queues(ctrl
);
2966 if (ctrl
->state
!= NVME_CTRL_LIVE
)
2969 ret
= nvme_get_power_state(ctrl
, &ndev
->last_ps
);
2974 * A saved state prevents pci pm from generically controlling the
2975 * device's power. If we're using protocol specific settings, we don't
2976 * want pci interfering.
2978 pci_save_state(pdev
);
2980 ret
= nvme_set_power_state(ctrl
, ctrl
->npss
);
2985 /* discard the saved state */
2986 pci_load_saved_state(pdev
, NULL
);
2989 * Clearing npss forces a controller reset on resume. The
2990 * correct value will be rediscovered then.
2992 ret
= nvme_disable_prepare_reset(ndev
, true);
2996 nvme_unfreeze(ctrl
);
3000 static int nvme_simple_suspend(struct device
*dev
)
3002 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
3003 return nvme_disable_prepare_reset(ndev
, true);
3006 static int nvme_simple_resume(struct device
*dev
)
3008 struct pci_dev
*pdev
= to_pci_dev(dev
);
3009 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
3011 return nvme_try_sched_reset(&ndev
->ctrl
);
3014 static const struct dev_pm_ops nvme_dev_pm_ops
= {
3015 .suspend
= nvme_suspend
,
3016 .resume
= nvme_resume
,
3017 .freeze
= nvme_simple_suspend
,
3018 .thaw
= nvme_simple_resume
,
3019 .poweroff
= nvme_simple_suspend
,
3020 .restore
= nvme_simple_resume
,
3022 #endif /* CONFIG_PM_SLEEP */
3024 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
3025 pci_channel_state_t state
)
3027 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3030 * A frozen channel requires a reset. When detected, this method will
3031 * shutdown the controller to quiesce. The controller will be restarted
3032 * after the slot reset through driver's slot_reset callback.
3035 case pci_channel_io_normal
:
3036 return PCI_ERS_RESULT_CAN_RECOVER
;
3037 case pci_channel_io_frozen
:
3038 dev_warn(dev
->ctrl
.device
,
3039 "frozen state error detected, reset controller\n");
3040 nvme_dev_disable(dev
, false);
3041 return PCI_ERS_RESULT_NEED_RESET
;
3042 case pci_channel_io_perm_failure
:
3043 dev_warn(dev
->ctrl
.device
,
3044 "failure state error detected, request disconnect\n");
3045 return PCI_ERS_RESULT_DISCONNECT
;
3047 return PCI_ERS_RESULT_NEED_RESET
;
3050 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
3052 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3054 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
3055 pci_restore_state(pdev
);
3056 nvme_reset_ctrl(&dev
->ctrl
);
3057 return PCI_ERS_RESULT_RECOVERED
;
3060 static void nvme_error_resume(struct pci_dev
*pdev
)
3062 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3064 flush_work(&dev
->ctrl
.reset_work
);
3067 static const struct pci_error_handlers nvme_err_handler
= {
3068 .error_detected
= nvme_error_detected
,
3069 .slot_reset
= nvme_slot_reset
,
3070 .resume
= nvme_error_resume
,
3071 .reset_prepare
= nvme_reset_prepare
,
3072 .reset_done
= nvme_reset_done
,
3075 static const struct pci_device_id nvme_id_table
[] = {
3076 { PCI_VDEVICE(INTEL
, 0x0953),
3077 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3078 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3079 { PCI_VDEVICE(INTEL
, 0x0a53),
3080 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3081 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3082 { PCI_VDEVICE(INTEL
, 0x0a54),
3083 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3084 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3085 { PCI_VDEVICE(INTEL
, 0x0a55),
3086 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3087 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3088 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
3089 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3090 NVME_QUIRK_MEDIUM_PRIO_SQ
|
3091 NVME_QUIRK_NO_TEMP_THRESH_CHANGE
},
3092 { PCI_VDEVICE(INTEL
, 0xf1a6), /* Intel 760p/Pro 7600p */
3093 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3094 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
3095 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
|
3096 NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3097 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3098 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3099 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3100 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3101 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3102 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3103 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3104 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3105 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3106 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3107 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3108 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3109 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3110 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3111 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3112 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3113 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3114 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3115 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3116 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3117 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3118 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3119 NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3120 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
3121 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001),
3122 .driver_data
= NVME_QUIRK_SINGLE_VECTOR
},
3123 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
3124 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2005),
3125 .driver_data
= NVME_QUIRK_SINGLE_VECTOR
|
3126 NVME_QUIRK_128_BYTES_SQES
|
3127 NVME_QUIRK_SHARED_TAGS
},
3130 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
3132 static struct pci_driver nvme_driver
= {
3134 .id_table
= nvme_id_table
,
3135 .probe
= nvme_probe
,
3136 .remove
= nvme_remove
,
3137 .shutdown
= nvme_shutdown
,
3138 #ifdef CONFIG_PM_SLEEP
3140 .pm
= &nvme_dev_pm_ops
,
3143 .sriov_configure
= pci_sriov_configure_simple
,
3144 .err_handler
= &nvme_err_handler
,
3147 static int __init
nvme_init(void)
3149 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
3150 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
3151 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
3152 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS
< 2);
3154 write_queues
= min(write_queues
, num_possible_cpus());
3155 poll_queues
= min(poll_queues
, num_possible_cpus());
3156 return pci_register_driver(&nvme_driver
);
3159 static void __exit
nvme_exit(void)
3161 pci_unregister_driver(&nvme_driver
);
3162 flush_workqueue(nvme_wq
);
3165 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3166 MODULE_LICENSE("GPL");
3167 MODULE_VERSION("1.0");
3168 module_init(nvme_init
);
3169 module_exit(nvme_exit
);