2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/poison.h>
36 #include <linux/ptrace.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/t10-pi.h>
40 #include <linux/types.h>
41 #include <linux/io-64-nonatomic-lo-hi.h>
42 #include <asm/unaligned.h>
46 #define NVME_Q_DEPTH 1024
47 #define NVME_AQ_DEPTH 256
48 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
51 unsigned char admin_timeout
= 60;
52 module_param(admin_timeout
, byte
, 0644);
53 MODULE_PARM_DESC(admin_timeout
, "timeout in seconds for admin commands");
55 unsigned char nvme_io_timeout
= 30;
56 module_param_named(io_timeout
, nvme_io_timeout
, byte
, 0644);
57 MODULE_PARM_DESC(io_timeout
, "timeout in seconds for I/O");
59 unsigned char shutdown_timeout
= 5;
60 module_param(shutdown_timeout
, byte
, 0644);
61 MODULE_PARM_DESC(shutdown_timeout
, "timeout in seconds for controller shutdown");
63 static int use_threaded_interrupts
;
64 module_param(use_threaded_interrupts
, int, 0);
66 static bool use_cmb_sqes
= true;
67 module_param(use_cmb_sqes
, bool, 0644);
68 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
70 static LIST_HEAD(dev_list
);
71 static struct task_struct
*nvme_thread
;
72 static struct workqueue_struct
*nvme_workq
;
73 static wait_queue_head_t nvme_kthread_wait
;
79 static int __nvme_reset(struct nvme_dev
*dev
);
80 static int nvme_reset(struct nvme_dev
*dev
);
81 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
82 static void nvme_unmap_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
);
83 static void nvme_dead_ctrl(struct nvme_dev
*dev
);
85 struct async_cmd_info
{
86 struct kthread_work work
;
87 struct kthread_worker
*worker
;
95 * Represents an NVM Express device. Each nvme_dev is a PCI function.
98 struct list_head node
;
99 struct nvme_queue
**queues
;
100 struct blk_mq_tag_set tagset
;
101 struct blk_mq_tag_set admin_tagset
;
104 struct dma_pool
*prp_page_pool
;
105 struct dma_pool
*prp_small_pool
;
106 unsigned queue_count
;
107 unsigned online_queues
;
111 struct msix_entry
*entry
;
113 struct work_struct reset_work
;
114 struct work_struct probe_work
;
115 struct work_struct scan_work
;
118 dma_addr_t cmb_dma_addr
;
122 struct nvme_ctrl ctrl
;
125 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
127 return container_of(ctrl
, struct nvme_dev
, ctrl
);
131 * An NVM Express queue. Each device has at least two (one for admin
132 * commands and one for I/O commands).
135 struct device
*q_dmadev
;
136 struct nvme_dev
*dev
;
137 char irqname
[24]; /* nvme4294967295-65535\0 */
139 struct nvme_command
*sq_cmds
;
140 struct nvme_command __iomem
*sq_cmds_io
;
141 volatile struct nvme_completion
*cqes
;
142 struct blk_mq_tags
**tags
;
143 dma_addr_t sq_dma_addr
;
144 dma_addr_t cq_dma_addr
;
154 struct async_cmd_info cmdinfo
;
158 * The nvme_iod describes the data in an I/O, including the list of PRP
159 * entries. You can't see it in this data structure because C doesn't let
160 * me express that. Use nvme_alloc_iod to ensure there's enough space
161 * allocated to store the PRP list.
164 unsigned long private; /* For the use of the submitter of the I/O */
165 int npages
; /* In the PRP list. 0 means small pool in use */
166 int offset
; /* Of PRP list */
167 int nents
; /* Used in scatterlist */
168 int length
; /* Of data, in bytes */
169 dma_addr_t first_dma
;
170 struct scatterlist meta_sg
[1]; /* metadata requires single contiguous buffer */
171 struct scatterlist sg
[0];
175 * Check we didin't inadvertently grow the command struct
177 static inline void _nvme_check_size(void)
179 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
180 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
181 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
188 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
189 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
190 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
193 typedef void (*nvme_completion_fn
)(struct nvme_queue
*, void *,
194 struct nvme_completion
*);
196 struct nvme_cmd_info
{
197 nvme_completion_fn fn
;
200 struct nvme_queue
*nvmeq
;
201 struct nvme_iod iod
[0];
205 * Max size of iod being embedded in the request payload
207 #define NVME_INT_PAGES 2
208 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
209 #define NVME_INT_MASK 0x01
212 * Will slightly overestimate the number of pages needed. This is OK
213 * as it only leads to a small amount of wasted memory for the lifetime of
216 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
218 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
219 dev
->ctrl
.page_size
);
220 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
223 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
225 unsigned int ret
= sizeof(struct nvme_cmd_info
);
227 ret
+= sizeof(struct nvme_iod
);
228 ret
+= sizeof(__le64
*) * nvme_npages(NVME_INT_BYTES(dev
), dev
);
229 ret
+= sizeof(struct scatterlist
) * NVME_INT_PAGES
;
234 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
235 unsigned int hctx_idx
)
237 struct nvme_dev
*dev
= data
;
238 struct nvme_queue
*nvmeq
= dev
->queues
[0];
240 WARN_ON(hctx_idx
!= 0);
241 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
242 WARN_ON(nvmeq
->tags
);
244 hctx
->driver_data
= nvmeq
;
245 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
249 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
251 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
256 static int nvme_admin_init_request(void *data
, struct request
*req
,
257 unsigned int hctx_idx
, unsigned int rq_idx
,
258 unsigned int numa_node
)
260 struct nvme_dev
*dev
= data
;
261 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
262 struct nvme_queue
*nvmeq
= dev
->queues
[0];
269 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
270 unsigned int hctx_idx
)
272 struct nvme_dev
*dev
= data
;
273 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
276 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
278 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
279 hctx
->driver_data
= nvmeq
;
283 static int nvme_init_request(void *data
, struct request
*req
,
284 unsigned int hctx_idx
, unsigned int rq_idx
,
285 unsigned int numa_node
)
287 struct nvme_dev
*dev
= data
;
288 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
289 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
296 static void nvme_set_info(struct nvme_cmd_info
*cmd
, void *ctx
,
297 nvme_completion_fn handler
)
302 blk_mq_start_request(blk_mq_rq_from_pdu(cmd
));
305 static void *iod_get_private(struct nvme_iod
*iod
)
307 return (void *) (iod
->private & ~0x1UL
);
311 * If bit 0 is set, the iod is embedded in the request payload.
313 static bool iod_should_kfree(struct nvme_iod
*iod
)
315 return (iod
->private & NVME_INT_MASK
) == 0;
318 /* Special values must be less than 0x1000 */
319 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
320 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
321 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
322 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
324 static void special_completion(struct nvme_queue
*nvmeq
, void *ctx
,
325 struct nvme_completion
*cqe
)
327 if (ctx
== CMD_CTX_CANCELLED
)
329 if (ctx
== CMD_CTX_COMPLETED
) {
330 dev_warn(nvmeq
->q_dmadev
,
331 "completed id %d twice on queue %d\n",
332 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
335 if (ctx
== CMD_CTX_INVALID
) {
336 dev_warn(nvmeq
->q_dmadev
,
337 "invalid id %d completed on queue %d\n",
338 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
341 dev_warn(nvmeq
->q_dmadev
, "Unknown special completion %p\n", ctx
);
344 static void *cancel_cmd_info(struct nvme_cmd_info
*cmd
, nvme_completion_fn
*fn
)
351 cmd
->fn
= special_completion
;
352 cmd
->ctx
= CMD_CTX_CANCELLED
;
356 static void async_req_completion(struct nvme_queue
*nvmeq
, void *ctx
,
357 struct nvme_completion
*cqe
)
359 u32 result
= le32_to_cpup(&cqe
->result
);
360 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
362 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
)
363 ++nvmeq
->dev
->ctrl
.event_limit
;
364 if (status
!= NVME_SC_SUCCESS
)
367 switch (result
& 0xff07) {
368 case NVME_AER_NOTICE_NS_CHANGED
:
369 dev_info(nvmeq
->q_dmadev
, "rescanning\n");
370 schedule_work(&nvmeq
->dev
->scan_work
);
372 dev_warn(nvmeq
->q_dmadev
, "async event result %08x\n", result
);
376 static void abort_completion(struct nvme_queue
*nvmeq
, void *ctx
,
377 struct nvme_completion
*cqe
)
379 struct request
*req
= ctx
;
381 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
382 u32 result
= le32_to_cpup(&cqe
->result
);
384 blk_mq_free_request(req
);
386 dev_warn(nvmeq
->q_dmadev
, "Abort status:%x result:%x", status
, result
);
387 ++nvmeq
->dev
->ctrl
.abort_limit
;
390 static void async_completion(struct nvme_queue
*nvmeq
, void *ctx
,
391 struct nvme_completion
*cqe
)
393 struct async_cmd_info
*cmdinfo
= ctx
;
394 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
395 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
396 queue_kthread_work(cmdinfo
->worker
, &cmdinfo
->work
);
397 blk_mq_free_request(cmdinfo
->req
);
400 static inline struct nvme_cmd_info
*get_cmd_from_tag(struct nvme_queue
*nvmeq
,
403 struct request
*req
= blk_mq_tag_to_rq(*nvmeq
->tags
, tag
);
405 return blk_mq_rq_to_pdu(req
);
409 * Called with local interrupts disabled and the q_lock held. May not sleep.
411 static void *nvme_finish_cmd(struct nvme_queue
*nvmeq
, int tag
,
412 nvme_completion_fn
*fn
)
414 struct nvme_cmd_info
*cmd
= get_cmd_from_tag(nvmeq
, tag
);
416 if (tag
>= nvmeq
->q_depth
) {
417 *fn
= special_completion
;
418 return CMD_CTX_INVALID
;
423 cmd
->fn
= special_completion
;
424 cmd
->ctx
= CMD_CTX_COMPLETED
;
429 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
430 * @nvmeq: The queue to use
431 * @cmd: The command to send
433 * Safe to use from interrupt context
435 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
436 struct nvme_command
*cmd
)
438 u16 tail
= nvmeq
->sq_tail
;
440 if (nvmeq
->sq_cmds_io
)
441 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
443 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
445 if (++tail
== nvmeq
->q_depth
)
447 writel(tail
, nvmeq
->q_db
);
448 nvmeq
->sq_tail
= tail
;
451 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
454 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
455 __nvme_submit_cmd(nvmeq
, cmd
);
456 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
459 static __le64
**iod_list(struct nvme_iod
*iod
)
461 return ((void *)iod
) + iod
->offset
;
464 static inline void iod_init(struct nvme_iod
*iod
, unsigned nbytes
,
465 unsigned nseg
, unsigned long private)
467 iod
->private = private;
468 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
470 iod
->length
= nbytes
;
474 static struct nvme_iod
*
475 __nvme_alloc_iod(unsigned nseg
, unsigned bytes
, struct nvme_dev
*dev
,
476 unsigned long priv
, gfp_t gfp
)
478 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
479 sizeof(__le64
*) * nvme_npages(bytes
, dev
) +
480 sizeof(struct scatterlist
) * nseg
, gfp
);
483 iod_init(iod
, bytes
, nseg
, priv
);
488 static struct nvme_iod
*nvme_alloc_iod(struct request
*rq
, struct nvme_dev
*dev
,
491 unsigned size
= !(rq
->cmd_flags
& REQ_DISCARD
) ? blk_rq_bytes(rq
) :
492 sizeof(struct nvme_dsm_range
);
493 struct nvme_iod
*iod
;
495 if (rq
->nr_phys_segments
<= NVME_INT_PAGES
&&
496 size
<= NVME_INT_BYTES(dev
)) {
497 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(rq
);
500 iod_init(iod
, size
, rq
->nr_phys_segments
,
501 (unsigned long) rq
| NVME_INT_MASK
);
505 return __nvme_alloc_iod(rq
->nr_phys_segments
, size
, dev
,
506 (unsigned long) rq
, gfp
);
509 static void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
511 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
513 __le64
**list
= iod_list(iod
);
514 dma_addr_t prp_dma
= iod
->first_dma
;
516 if (iod
->npages
== 0)
517 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
518 for (i
= 0; i
< iod
->npages
; i
++) {
519 __le64
*prp_list
= list
[i
];
520 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
521 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
522 prp_dma
= next_prp_dma
;
525 if (iod_should_kfree(iod
))
529 #ifdef CONFIG_BLK_DEV_INTEGRITY
530 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
532 if (be32_to_cpu(pi
->ref_tag
) == v
)
533 pi
->ref_tag
= cpu_to_be32(p
);
536 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
538 if (be32_to_cpu(pi
->ref_tag
) == p
)
539 pi
->ref_tag
= cpu_to_be32(v
);
543 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
545 * The virtual start sector is the one that was originally submitted by the
546 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
547 * start sector may be different. Remap protection information to match the
548 * physical LBA on writes, and back to the original seed on reads.
550 * Type 0 and 3 do not have a ref tag, so no remapping required.
552 static void nvme_dif_remap(struct request
*req
,
553 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
555 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
556 struct bio_integrity_payload
*bip
;
557 struct t10_pi_tuple
*pi
;
559 u32 i
, nlb
, ts
, phys
, virt
;
561 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
564 bip
= bio_integrity(req
->bio
);
568 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
571 virt
= bip_get_seed(bip
);
572 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
573 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
574 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
576 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
577 pi
= (struct t10_pi_tuple
*)p
;
578 dif_swap(phys
, virt
, pi
);
583 #else /* CONFIG_BLK_DEV_INTEGRITY */
584 static void nvme_dif_remap(struct request
*req
,
585 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
588 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
591 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
596 static void req_completion(struct nvme_queue
*nvmeq
, void *ctx
,
597 struct nvme_completion
*cqe
)
599 struct nvme_iod
*iod
= ctx
;
600 struct request
*req
= iod_get_private(iod
);
601 struct nvme_cmd_info
*cmd_rq
= blk_mq_rq_to_pdu(req
);
602 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
605 if (unlikely(status
)) {
606 if (!(status
& NVME_SC_DNR
|| blk_noretry_request(req
))
607 && (jiffies
- req
->start_time
) < req
->timeout
) {
610 nvme_unmap_data(nvmeq
->dev
, iod
);
612 blk_mq_requeue_request(req
);
613 spin_lock_irqsave(req
->q
->queue_lock
, flags
);
614 if (!blk_queue_stopped(req
->q
))
615 blk_mq_kick_requeue_list(req
->q
);
616 spin_unlock_irqrestore(req
->q
->queue_lock
, flags
);
620 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
621 if (cmd_rq
->ctx
== CMD_CTX_CANCELLED
)
626 error
= nvme_error_status(status
);
630 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
631 u32 result
= le32_to_cpup(&cqe
->result
);
632 req
->special
= (void *)(uintptr_t)result
;
636 dev_warn(nvmeq
->dev
->dev
,
637 "completing aborted command with status:%04x\n",
640 nvme_unmap_data(nvmeq
->dev
, iod
);
641 blk_mq_complete_request(req
, error
);
644 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct nvme_iod
*iod
,
647 struct dma_pool
*pool
;
648 int length
= total_len
;
649 struct scatterlist
*sg
= iod
->sg
;
650 int dma_len
= sg_dma_len(sg
);
651 u64 dma_addr
= sg_dma_address(sg
);
652 u32 page_size
= dev
->ctrl
.page_size
;
653 int offset
= dma_addr
& (page_size
- 1);
655 __le64
**list
= iod_list(iod
);
659 length
-= (page_size
- offset
);
663 dma_len
-= (page_size
- offset
);
665 dma_addr
+= (page_size
- offset
);
668 dma_addr
= sg_dma_address(sg
);
669 dma_len
= sg_dma_len(sg
);
672 if (length
<= page_size
) {
673 iod
->first_dma
= dma_addr
;
677 nprps
= DIV_ROUND_UP(length
, page_size
);
678 if (nprps
<= (256 / 8)) {
679 pool
= dev
->prp_small_pool
;
682 pool
= dev
->prp_page_pool
;
686 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
688 iod
->first_dma
= dma_addr
;
693 iod
->first_dma
= prp_dma
;
696 if (i
== page_size
>> 3) {
697 __le64
*old_prp_list
= prp_list
;
698 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
701 list
[iod
->npages
++] = prp_list
;
702 prp_list
[0] = old_prp_list
[i
- 1];
703 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
706 prp_list
[i
++] = cpu_to_le64(dma_addr
);
707 dma_len
-= page_size
;
708 dma_addr
+= page_size
;
716 dma_addr
= sg_dma_address(sg
);
717 dma_len
= sg_dma_len(sg
);
723 static int nvme_map_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
,
724 struct nvme_command
*cmnd
)
726 struct request
*req
= iod_get_private(iod
);
727 struct request_queue
*q
= req
->q
;
728 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
729 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
730 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
732 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
733 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
737 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
738 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
741 if (!nvme_setup_prps(dev
, iod
, blk_rq_bytes(req
)))
744 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
745 if (blk_integrity_rq(req
)) {
746 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
749 sg_init_table(iod
->meta_sg
, 1);
750 if (blk_rq_map_integrity_sg(q
, req
->bio
, iod
->meta_sg
) != 1)
753 if (rq_data_dir(req
))
754 nvme_dif_remap(req
, nvme_dif_prep
);
756 if (!dma_map_sg(dev
->dev
, iod
->meta_sg
, 1, dma_dir
))
760 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
761 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
762 if (blk_integrity_rq(req
))
763 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(iod
->meta_sg
));
764 return BLK_MQ_RQ_QUEUE_OK
;
767 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
772 static void nvme_unmap_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
774 struct request
*req
= iod_get_private(iod
);
775 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
776 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
779 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
780 if (blk_integrity_rq(req
)) {
781 if (!rq_data_dir(req
))
782 nvme_dif_remap(req
, nvme_dif_complete
);
783 dma_unmap_sg(dev
->dev
, iod
->meta_sg
, 1, dma_dir
);
787 nvme_free_iod(dev
, iod
);
791 * We reuse the small pool to allocate the 16-byte range here as it is not
792 * worth having a special pool for these or additional cases to handle freeing
795 static int nvme_setup_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
796 struct nvme_iod
*iod
, struct nvme_command
*cmnd
)
798 struct request
*req
= iod_get_private(iod
);
799 struct nvme_dsm_range
*range
;
801 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
804 return BLK_MQ_RQ_QUEUE_BUSY
;
805 iod_list(iod
)[0] = (__le64
*)range
;
808 range
->cattr
= cpu_to_le32(0);
809 range
->nlb
= cpu_to_le32(blk_rq_bytes(req
) >> ns
->lba_shift
);
810 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, blk_rq_pos(req
)));
812 memset(cmnd
, 0, sizeof(*cmnd
));
813 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
814 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
815 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
817 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
818 return BLK_MQ_RQ_QUEUE_OK
;
822 * NOTE: ns is NULL when called on the admin queue.
824 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
825 const struct blk_mq_queue_data
*bd
)
827 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
828 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
829 struct nvme_dev
*dev
= nvmeq
->dev
;
830 struct request
*req
= bd
->rq
;
831 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
832 struct nvme_iod
*iod
;
833 struct nvme_command cmnd
;
834 int ret
= BLK_MQ_RQ_QUEUE_OK
;
837 * If formated with metadata, require the block layer provide a buffer
838 * unless this namespace is formated such that the metadata can be
839 * stripped/generated by the controller with PRACT=1.
841 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
842 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
843 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
844 blk_mq_complete_request(req
, -EFAULT
);
845 return BLK_MQ_RQ_QUEUE_OK
;
849 iod
= nvme_alloc_iod(req
, dev
, GFP_ATOMIC
);
851 return BLK_MQ_RQ_QUEUE_BUSY
;
853 if (req
->cmd_flags
& REQ_DISCARD
) {
854 ret
= nvme_setup_discard(nvmeq
, ns
, iod
, &cmnd
);
856 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
857 memcpy(&cmnd
, req
->cmd
, sizeof(cmnd
));
858 else if (req
->cmd_flags
& REQ_FLUSH
)
859 nvme_setup_flush(ns
, &cmnd
);
861 nvme_setup_rw(ns
, req
, &cmnd
);
863 if (req
->nr_phys_segments
)
864 ret
= nvme_map_data(dev
, iod
, &cmnd
);
870 cmnd
.common
.command_id
= req
->tag
;
871 nvme_set_info(cmd
, iod
, req_completion
);
873 spin_lock_irq(&nvmeq
->q_lock
);
874 __nvme_submit_cmd(nvmeq
, &cmnd
);
875 nvme_process_cq(nvmeq
);
876 spin_unlock_irq(&nvmeq
->q_lock
);
877 return BLK_MQ_RQ_QUEUE_OK
;
879 nvme_free_iod(dev
, iod
);
883 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
887 head
= nvmeq
->cq_head
;
888 phase
= nvmeq
->cq_phase
;
892 nvme_completion_fn fn
;
893 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
894 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
896 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
897 if (++head
== nvmeq
->q_depth
) {
901 if (tag
&& *tag
== cqe
.command_id
)
903 ctx
= nvme_finish_cmd(nvmeq
, cqe
.command_id
, &fn
);
904 fn(nvmeq
, ctx
, &cqe
);
907 /* If the controller ignores the cq head doorbell and continuously
908 * writes to the queue, it is theoretically possible to wrap around
909 * the queue twice and mistakenly return IRQ_NONE. Linux only
910 * requires that 0.1% of your interrupts are handled, so this isn't
913 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
916 if (likely(nvmeq
->cq_vector
>= 0))
917 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
918 nvmeq
->cq_head
= head
;
919 nvmeq
->cq_phase
= phase
;
924 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
926 __nvme_process_cq(nvmeq
, NULL
);
929 static irqreturn_t
nvme_irq(int irq
, void *data
)
932 struct nvme_queue
*nvmeq
= data
;
933 spin_lock(&nvmeq
->q_lock
);
934 nvme_process_cq(nvmeq
);
935 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
937 spin_unlock(&nvmeq
->q_lock
);
941 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
943 struct nvme_queue
*nvmeq
= data
;
944 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
945 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
947 return IRQ_WAKE_THREAD
;
950 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
952 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
954 if ((le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
956 spin_lock_irq(&nvmeq
->q_lock
);
957 __nvme_process_cq(nvmeq
, &tag
);
958 spin_unlock_irq(&nvmeq
->q_lock
);
967 static int nvme_submit_async_admin_req(struct nvme_dev
*dev
)
969 struct nvme_queue
*nvmeq
= dev
->queues
[0];
970 struct nvme_command c
;
971 struct nvme_cmd_info
*cmd_info
;
974 req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
,
975 BLK_MQ_REQ_NOWAIT
| BLK_MQ_REQ_RESERVED
);
979 req
->cmd_flags
|= REQ_NO_TIMEOUT
;
980 cmd_info
= blk_mq_rq_to_pdu(req
);
981 nvme_set_info(cmd_info
, NULL
, async_req_completion
);
983 memset(&c
, 0, sizeof(c
));
984 c
.common
.opcode
= nvme_admin_async_event
;
985 c
.common
.command_id
= req
->tag
;
987 blk_mq_free_request(req
);
988 __nvme_submit_cmd(nvmeq
, &c
);
992 static int nvme_submit_admin_async_cmd(struct nvme_dev
*dev
,
993 struct nvme_command
*cmd
,
994 struct async_cmd_info
*cmdinfo
, unsigned timeout
)
996 struct nvme_queue
*nvmeq
= dev
->queues
[0];
998 struct nvme_cmd_info
*cmd_rq
;
1000 req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
, 0);
1002 return PTR_ERR(req
);
1004 req
->timeout
= timeout
;
1005 cmd_rq
= blk_mq_rq_to_pdu(req
);
1007 nvme_set_info(cmd_rq
, cmdinfo
, async_completion
);
1008 cmdinfo
->status
= -EINTR
;
1010 cmd
->common
.command_id
= req
->tag
;
1012 nvme_submit_cmd(nvmeq
, cmd
);
1016 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1018 struct nvme_command c
;
1020 memset(&c
, 0, sizeof(c
));
1021 c
.delete_queue
.opcode
= opcode
;
1022 c
.delete_queue
.qid
= cpu_to_le16(id
);
1024 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1027 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1028 struct nvme_queue
*nvmeq
)
1030 struct nvme_command c
;
1031 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
1034 * Note: we (ab)use the fact the the prp fields survive if no data
1035 * is attached to the request.
1037 memset(&c
, 0, sizeof(c
));
1038 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1039 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1040 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1041 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1042 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1043 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
1045 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1048 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1049 struct nvme_queue
*nvmeq
)
1051 struct nvme_command c
;
1052 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
1055 * Note: we (ab)use the fact the the prp fields survive if no data
1056 * is attached to the request.
1058 memset(&c
, 0, sizeof(c
));
1059 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1060 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1061 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1062 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1063 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1064 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1066 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1069 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1071 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1074 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1076 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1080 * nvme_abort_req - Attempt aborting a request
1082 * Schedule controller reset if the command was already aborted once before and
1083 * still hasn't been returned to the driver, or if this is the admin queue.
1085 static void nvme_abort_req(struct request
*req
)
1087 struct nvme_cmd_info
*cmd_rq
= blk_mq_rq_to_pdu(req
);
1088 struct nvme_queue
*nvmeq
= cmd_rq
->nvmeq
;
1089 struct nvme_dev
*dev
= nvmeq
->dev
;
1090 struct request
*abort_req
;
1091 struct nvme_cmd_info
*abort_cmd
;
1092 struct nvme_command cmd
;
1094 if (!nvmeq
->qid
|| cmd_rq
->aborted
) {
1095 spin_lock(&dev_list_lock
);
1096 if (!__nvme_reset(dev
)) {
1098 "I/O %d QID %d timeout, reset controller\n",
1099 req
->tag
, nvmeq
->qid
);
1101 spin_unlock(&dev_list_lock
);
1105 if (!dev
->ctrl
.abort_limit
)
1108 abort_req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
,
1110 if (IS_ERR(abort_req
))
1113 abort_cmd
= blk_mq_rq_to_pdu(abort_req
);
1114 nvme_set_info(abort_cmd
, abort_req
, abort_completion
);
1116 memset(&cmd
, 0, sizeof(cmd
));
1117 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1118 cmd
.abort
.cid
= req
->tag
;
1119 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1120 cmd
.abort
.command_id
= abort_req
->tag
;
1122 --dev
->ctrl
.abort_limit
;
1123 cmd_rq
->aborted
= 1;
1125 dev_warn(nvmeq
->q_dmadev
, "Aborting I/O %d QID %d\n", req
->tag
,
1127 nvme_submit_cmd(dev
->queues
[0], &cmd
);
1130 static void nvme_cancel_queue_ios(struct request
*req
, void *data
, bool reserved
)
1132 struct nvme_queue
*nvmeq
= data
;
1134 nvme_completion_fn fn
;
1135 struct nvme_cmd_info
*cmd
;
1136 struct nvme_completion cqe
;
1138 if (!blk_mq_request_started(req
))
1141 cmd
= blk_mq_rq_to_pdu(req
);
1143 if (cmd
->ctx
== CMD_CTX_CANCELLED
)
1146 if (blk_queue_dying(req
->q
))
1147 cqe
.status
= cpu_to_le16((NVME_SC_ABORT_REQ
| NVME_SC_DNR
) << 1);
1149 cqe
.status
= cpu_to_le16(NVME_SC_ABORT_REQ
<< 1);
1152 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d QID %d\n",
1153 req
->tag
, nvmeq
->qid
);
1154 ctx
= cancel_cmd_info(cmd
, &fn
);
1155 fn(nvmeq
, ctx
, &cqe
);
1158 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1160 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
1161 struct nvme_queue
*nvmeq
= cmd
->nvmeq
;
1163 dev_warn(nvmeq
->q_dmadev
, "Timeout I/O %d QID %d\n", req
->tag
,
1165 spin_lock_irq(&nvmeq
->q_lock
);
1166 nvme_abort_req(req
);
1167 spin_unlock_irq(&nvmeq
->q_lock
);
1170 * The aborted req will be completed on receiving the abort req.
1171 * We enable the timer again. If hit twice, it'll cause a device reset,
1172 * as the device then is in a faulty state.
1174 return BLK_EH_RESET_TIMER
;
1177 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1179 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1180 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1182 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1183 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1187 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1191 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1192 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1194 dev
->queues
[i
] = NULL
;
1195 nvme_free_queue(nvmeq
);
1200 * nvme_suspend_queue - put queue into suspended state
1201 * @nvmeq - queue to suspend
1203 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1207 spin_lock_irq(&nvmeq
->q_lock
);
1208 if (nvmeq
->cq_vector
== -1) {
1209 spin_unlock_irq(&nvmeq
->q_lock
);
1212 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1213 nvmeq
->dev
->online_queues
--;
1214 nvmeq
->cq_vector
= -1;
1215 spin_unlock_irq(&nvmeq
->q_lock
);
1217 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1218 blk_mq_freeze_queue_start(nvmeq
->dev
->ctrl
.admin_q
);
1220 irq_set_affinity_hint(vector
, NULL
);
1221 free_irq(vector
, nvmeq
);
1226 static void nvme_clear_queue(struct nvme_queue
*nvmeq
)
1228 spin_lock_irq(&nvmeq
->q_lock
);
1229 if (nvmeq
->tags
&& *nvmeq
->tags
)
1230 blk_mq_all_tag_busy_iter(*nvmeq
->tags
, nvme_cancel_queue_ios
, nvmeq
);
1231 spin_unlock_irq(&nvmeq
->q_lock
);
1234 static void nvme_disable_queue(struct nvme_dev
*dev
, int qid
)
1236 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
1240 if (nvme_suspend_queue(nvmeq
))
1243 /* Don't tell the adapter to delete the admin queue.
1244 * Don't tell a removed adapter to delete IO queues. */
1245 if (qid
&& readl(dev
->bar
+ NVME_REG_CSTS
) != -1) {
1246 adapter_delete_sq(dev
, qid
);
1247 adapter_delete_cq(dev
, qid
);
1250 spin_lock_irq(&nvmeq
->q_lock
);
1251 nvme_process_cq(nvmeq
);
1252 spin_unlock_irq(&nvmeq
->q_lock
);
1255 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1258 int q_depth
= dev
->q_depth
;
1259 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1260 dev
->ctrl
.page_size
);
1262 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1263 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1264 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1265 q_depth
= div_u64(mem_per_q
, entry_size
);
1268 * Ensure the reduced q_depth is above some threshold where it
1269 * would be better to map queues in system memory with the
1279 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1282 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1283 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1284 dev
->ctrl
.page_size
);
1285 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1286 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1288 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1289 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1290 if (!nvmeq
->sq_cmds
)
1297 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1300 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1304 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1305 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1309 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1312 nvmeq
->q_dmadev
= dev
->dev
;
1314 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1315 dev
->ctrl
.instance
, qid
);
1316 spin_lock_init(&nvmeq
->q_lock
);
1318 nvmeq
->cq_phase
= 1;
1319 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1320 nvmeq
->q_depth
= depth
;
1322 nvmeq
->cq_vector
= -1;
1323 dev
->queues
[qid
] = nvmeq
;
1325 /* make sure queue descriptor is set before queue count, for kthread */
1332 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1333 nvmeq
->cq_dma_addr
);
1339 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1342 if (use_threaded_interrupts
)
1343 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1344 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1346 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1347 IRQF_SHARED
, name
, nvmeq
);
1350 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1352 struct nvme_dev
*dev
= nvmeq
->dev
;
1354 spin_lock_irq(&nvmeq
->q_lock
);
1357 nvmeq
->cq_phase
= 1;
1358 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1359 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1360 dev
->online_queues
++;
1361 spin_unlock_irq(&nvmeq
->q_lock
);
1364 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1366 struct nvme_dev
*dev
= nvmeq
->dev
;
1369 nvmeq
->cq_vector
= qid
- 1;
1370 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1374 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1378 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1382 nvme_init_queue(nvmeq
, qid
);
1386 adapter_delete_sq(dev
, qid
);
1388 adapter_delete_cq(dev
, qid
);
1392 static struct blk_mq_ops nvme_mq_admin_ops
= {
1393 .queue_rq
= nvme_queue_rq
,
1394 .map_queue
= blk_mq_map_queue
,
1395 .init_hctx
= nvme_admin_init_hctx
,
1396 .exit_hctx
= nvme_admin_exit_hctx
,
1397 .init_request
= nvme_admin_init_request
,
1398 .timeout
= nvme_timeout
,
1401 static struct blk_mq_ops nvme_mq_ops
= {
1402 .queue_rq
= nvme_queue_rq
,
1403 .map_queue
= blk_mq_map_queue
,
1404 .init_hctx
= nvme_init_hctx
,
1405 .init_request
= nvme_init_request
,
1406 .timeout
= nvme_timeout
,
1410 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1412 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1413 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1414 blk_mq_free_tag_set(&dev
->admin_tagset
);
1418 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1420 if (!dev
->ctrl
.admin_q
) {
1421 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1422 dev
->admin_tagset
.nr_hw_queues
= 1;
1423 dev
->admin_tagset
.queue_depth
= NVME_AQ_DEPTH
- 1;
1424 dev
->admin_tagset
.reserved_tags
= 1;
1425 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1426 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1427 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1428 dev
->admin_tagset
.driver_data
= dev
;
1430 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1433 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1434 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1435 blk_mq_free_tag_set(&dev
->admin_tagset
);
1438 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1439 nvme_dev_remove_admin(dev
);
1440 dev
->ctrl
.admin_q
= NULL
;
1444 blk_mq_unfreeze_queue(dev
->ctrl
.admin_q
);
1449 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1453 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1454 struct nvme_queue
*nvmeq
;
1456 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1457 NVME_CAP_NSSRC(cap
) : 0;
1459 if (dev
->subsystem
&&
1460 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1461 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1463 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1467 nvmeq
= dev
->queues
[0];
1469 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1474 aqa
= nvmeq
->q_depth
- 1;
1477 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1478 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1479 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1481 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1485 nvmeq
->cq_vector
= 0;
1486 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1488 nvmeq
->cq_vector
= -1;
1495 nvme_free_queues(dev
, 0);
1499 static int nvme_kthread(void *data
)
1501 struct nvme_dev
*dev
, *next
;
1503 while (!kthread_should_stop()) {
1504 set_current_state(TASK_INTERRUPTIBLE
);
1505 spin_lock(&dev_list_lock
);
1506 list_for_each_entry_safe(dev
, next
, &dev_list
, node
) {
1508 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1510 if ((dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
)) ||
1511 csts
& NVME_CSTS_CFS
) {
1512 if (!__nvme_reset(dev
)) {
1514 "Failed status: %x, reset controller\n",
1515 readl(dev
->bar
+ NVME_REG_CSTS
));
1519 for (i
= 0; i
< dev
->queue_count
; i
++) {
1520 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1523 spin_lock_irq(&nvmeq
->q_lock
);
1524 nvme_process_cq(nvmeq
);
1526 while (i
== 0 && dev
->ctrl
.event_limit
> 0) {
1527 if (nvme_submit_async_admin_req(dev
))
1529 dev
->ctrl
.event_limit
--;
1531 spin_unlock_irq(&nvmeq
->q_lock
);
1534 spin_unlock(&dev_list_lock
);
1535 schedule_timeout(round_jiffies_relative(HZ
));
1541 * Create I/O queues. Failing to create an I/O queue is not an issue,
1542 * we can continue with less than the desired amount of queues, and
1543 * even a controller without I/O queues an still be used to issue
1544 * admin commands. This might be useful to upgrade a buggy firmware
1547 static void nvme_create_io_queues(struct nvme_dev
*dev
)
1551 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++)
1552 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
))
1555 for (i
= dev
->online_queues
; i
<= dev
->queue_count
- 1; i
++)
1556 if (nvme_create_queue(dev
->queues
[i
], i
)) {
1557 nvme_free_queues(dev
, i
);
1562 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1564 u64 szu
, size
, offset
;
1566 resource_size_t bar_size
;
1567 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1569 dma_addr_t dma_addr
;
1574 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1575 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1578 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1580 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1581 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1582 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1583 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1585 if (offset
> bar_size
)
1589 * Controllers may support a CMB size larger than their BAR,
1590 * for example, due to being behind a bridge. Reduce the CMB to
1591 * the reported size of the BAR
1593 if (size
> bar_size
- offset
)
1594 size
= bar_size
- offset
;
1596 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1597 cmb
= ioremap_wc(dma_addr
, size
);
1601 dev
->cmb_dma_addr
= dma_addr
;
1602 dev
->cmb_size
= size
;
1606 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1614 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1616 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1619 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1621 struct nvme_queue
*adminq
= dev
->queues
[0];
1622 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1623 int result
, i
, vecs
, nr_io_queues
, size
;
1625 nr_io_queues
= num_possible_cpus();
1626 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1631 * Degraded controllers might return an error when setting the queue
1632 * count. We still want to be able to bring them online and offer
1633 * access to the admin queue, as that might be only way to fix them up.
1636 dev_err(dev
->dev
, "Could not set queue count (%d)\n", result
);
1641 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1642 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1643 sizeof(struct nvme_command
));
1645 dev
->q_depth
= result
;
1647 nvme_release_cmb(dev
);
1650 size
= db_bar_size(dev
, nr_io_queues
);
1654 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1657 if (!--nr_io_queues
)
1659 size
= db_bar_size(dev
, nr_io_queues
);
1661 dev
->dbs
= dev
->bar
+ 4096;
1662 adminq
->q_db
= dev
->dbs
;
1665 /* Deregister the admin queue's interrupt */
1666 free_irq(dev
->entry
[0].vector
, adminq
);
1669 * If we enable msix early due to not intx, disable it again before
1670 * setting up the full range we need.
1673 pci_disable_msix(pdev
);
1675 for (i
= 0; i
< nr_io_queues
; i
++)
1676 dev
->entry
[i
].entry
= i
;
1677 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1679 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1683 for (i
= 0; i
< vecs
; i
++)
1684 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1689 * Should investigate if there's a performance win from allocating
1690 * more queues than interrupt vectors; it might allow the submission
1691 * path to scale better, even if the receive path is limited by the
1692 * number of interrupts.
1694 nr_io_queues
= vecs
;
1695 dev
->max_qid
= nr_io_queues
;
1697 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1699 adminq
->cq_vector
= -1;
1703 /* Free previously allocated queues that are no longer usable */
1704 nvme_free_queues(dev
, nr_io_queues
+ 1);
1705 nvme_create_io_queues(dev
);
1710 nvme_free_queues(dev
, 1);
1714 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1716 struct nvme_queue
*nvmeq
;
1719 for (i
= 0; i
< dev
->online_queues
; i
++) {
1720 nvmeq
= dev
->queues
[i
];
1722 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1725 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1726 blk_mq_tags_cpumask(*nvmeq
->tags
));
1730 static void nvme_dev_scan(struct work_struct
*work
)
1732 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1734 if (!dev
->tagset
.tags
)
1736 nvme_scan_namespaces(&dev
->ctrl
);
1737 nvme_set_irq_hints(dev
);
1741 * Return: error value if an error occurred setting up the queues or calling
1742 * Identify Device. 0 if these succeeded, even if adding some of the
1743 * namespaces failed. At the moment, these failures are silent. TBD which
1744 * failures should be reported.
1746 static int nvme_dev_add(struct nvme_dev
*dev
)
1748 if (!dev
->ctrl
.tagset
) {
1749 dev
->tagset
.ops
= &nvme_mq_ops
;
1750 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1751 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1752 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1753 dev
->tagset
.queue_depth
=
1754 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1755 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1756 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1757 dev
->tagset
.driver_data
= dev
;
1759 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1761 dev
->ctrl
.tagset
= &dev
->tagset
;
1763 schedule_work(&dev
->scan_work
);
1767 static int nvme_dev_map(struct nvme_dev
*dev
)
1770 int bars
, result
= -ENOMEM
;
1771 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1773 if (pci_enable_device_mem(pdev
))
1776 dev
->entry
[0].vector
= pdev
->irq
;
1777 pci_set_master(pdev
);
1778 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1782 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1785 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1786 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1789 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1793 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1799 * Some devices don't advertse INTx interrupts, pre-enable a single
1800 * MSIX vec for setup. We'll adjust this later.
1803 result
= pci_enable_msix(pdev
, dev
->entry
, 1);
1808 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1810 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1811 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1812 dev
->dbs
= dev
->bar
+ 4096;
1813 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1814 dev
->cmb
= nvme_map_cmb(dev
);
1822 pci_release_regions(pdev
);
1824 pci_disable_device(pdev
);
1828 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1830 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1832 if (pdev
->msi_enabled
)
1833 pci_disable_msi(pdev
);
1834 else if (pdev
->msix_enabled
)
1835 pci_disable_msix(pdev
);
1840 pci_release_regions(pdev
);
1843 if (pci_is_enabled(pdev
))
1844 pci_disable_device(pdev
);
1847 struct nvme_delq_ctx
{
1848 struct task_struct
*waiter
;
1849 struct kthread_worker
*worker
;
1853 static void nvme_wait_dq(struct nvme_delq_ctx
*dq
, struct nvme_dev
*dev
)
1855 dq
->waiter
= current
;
1859 set_current_state(TASK_KILLABLE
);
1860 if (!atomic_read(&dq
->refcount
))
1862 if (!schedule_timeout(ADMIN_TIMEOUT
) ||
1863 fatal_signal_pending(current
)) {
1865 * Disable the controller first since we can't trust it
1866 * at this point, but leave the admin queue enabled
1867 * until all queue deletion requests are flushed.
1868 * FIXME: This may take a while if there are more h/w
1869 * queues than admin tags.
1871 set_current_state(TASK_RUNNING
);
1872 nvme_disable_ctrl(&dev
->ctrl
,
1873 lo_hi_readq(dev
->bar
+ NVME_REG_CAP
));
1874 nvme_clear_queue(dev
->queues
[0]);
1875 flush_kthread_worker(dq
->worker
);
1876 nvme_disable_queue(dev
, 0);
1880 set_current_state(TASK_RUNNING
);
1883 static void nvme_put_dq(struct nvme_delq_ctx
*dq
)
1885 atomic_dec(&dq
->refcount
);
1887 wake_up_process(dq
->waiter
);
1890 static struct nvme_delq_ctx
*nvme_get_dq(struct nvme_delq_ctx
*dq
)
1892 atomic_inc(&dq
->refcount
);
1896 static void nvme_del_queue_end(struct nvme_queue
*nvmeq
)
1898 struct nvme_delq_ctx
*dq
= nvmeq
->cmdinfo
.ctx
;
1901 spin_lock_irq(&nvmeq
->q_lock
);
1902 nvme_process_cq(nvmeq
);
1903 spin_unlock_irq(&nvmeq
->q_lock
);
1906 static int adapter_async_del_queue(struct nvme_queue
*nvmeq
, u8 opcode
,
1907 kthread_work_func_t fn
)
1909 struct nvme_command c
;
1911 memset(&c
, 0, sizeof(c
));
1912 c
.delete_queue
.opcode
= opcode
;
1913 c
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1915 init_kthread_work(&nvmeq
->cmdinfo
.work
, fn
);
1916 return nvme_submit_admin_async_cmd(nvmeq
->dev
, &c
, &nvmeq
->cmdinfo
,
1920 static void nvme_del_cq_work_handler(struct kthread_work
*work
)
1922 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1924 nvme_del_queue_end(nvmeq
);
1927 static int nvme_delete_cq(struct nvme_queue
*nvmeq
)
1929 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_cq
,
1930 nvme_del_cq_work_handler
);
1933 static void nvme_del_sq_work_handler(struct kthread_work
*work
)
1935 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1937 int status
= nvmeq
->cmdinfo
.status
;
1940 status
= nvme_delete_cq(nvmeq
);
1942 nvme_del_queue_end(nvmeq
);
1945 static int nvme_delete_sq(struct nvme_queue
*nvmeq
)
1947 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_sq
,
1948 nvme_del_sq_work_handler
);
1951 static void nvme_del_queue_start(struct kthread_work
*work
)
1953 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1955 if (nvme_delete_sq(nvmeq
))
1956 nvme_del_queue_end(nvmeq
);
1959 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1962 DEFINE_KTHREAD_WORKER_ONSTACK(worker
);
1963 struct nvme_delq_ctx dq
;
1964 struct task_struct
*kworker_task
= kthread_run(kthread_worker_fn
,
1965 &worker
, "nvme%d", dev
->ctrl
.instance
);
1967 if (IS_ERR(kworker_task
)) {
1969 "Failed to create queue del task\n");
1970 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1971 nvme_disable_queue(dev
, i
);
1976 atomic_set(&dq
.refcount
, 0);
1977 dq
.worker
= &worker
;
1978 for (i
= dev
->queue_count
- 1; i
> 0; i
--) {
1979 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1981 if (nvme_suspend_queue(nvmeq
))
1983 nvmeq
->cmdinfo
.ctx
= nvme_get_dq(&dq
);
1984 nvmeq
->cmdinfo
.worker
= dq
.worker
;
1985 init_kthread_work(&nvmeq
->cmdinfo
.work
, nvme_del_queue_start
);
1986 queue_kthread_work(dq
.worker
, &nvmeq
->cmdinfo
.work
);
1988 nvme_wait_dq(&dq
, dev
);
1989 kthread_stop(kworker_task
);
1993 * Remove the node from the device list and check
1994 * for whether or not we need to stop the nvme_thread.
1996 static void nvme_dev_list_remove(struct nvme_dev
*dev
)
1998 struct task_struct
*tmp
= NULL
;
2000 spin_lock(&dev_list_lock
);
2001 list_del_init(&dev
->node
);
2002 if (list_empty(&dev_list
) && !IS_ERR_OR_NULL(nvme_thread
)) {
2006 spin_unlock(&dev_list_lock
);
2012 static void nvme_freeze_queues(struct nvme_dev
*dev
)
2016 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
2017 blk_mq_freeze_queue_start(ns
->queue
);
2019 spin_lock_irq(ns
->queue
->queue_lock
);
2020 queue_flag_set(QUEUE_FLAG_STOPPED
, ns
->queue
);
2021 spin_unlock_irq(ns
->queue
->queue_lock
);
2023 blk_mq_cancel_requeue_work(ns
->queue
);
2024 blk_mq_stop_hw_queues(ns
->queue
);
2028 static void nvme_unfreeze_queues(struct nvme_dev
*dev
)
2032 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
2033 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED
, ns
->queue
);
2034 blk_mq_unfreeze_queue(ns
->queue
);
2035 blk_mq_start_stopped_hw_queues(ns
->queue
, true);
2036 blk_mq_kick_requeue_list(ns
->queue
);
2040 static void nvme_dev_shutdown(struct nvme_dev
*dev
)
2045 nvme_dev_list_remove(dev
);
2048 nvme_freeze_queues(dev
);
2049 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2051 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
2052 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
2053 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
2054 nvme_suspend_queue(nvmeq
);
2057 nvme_disable_io_queues(dev
);
2058 nvme_shutdown_ctrl(&dev
->ctrl
);
2059 nvme_disable_queue(dev
, 0);
2061 nvme_dev_unmap(dev
);
2063 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
2064 nvme_clear_queue(dev
->queues
[i
]);
2067 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2069 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2070 PAGE_SIZE
, PAGE_SIZE
, 0);
2071 if (!dev
->prp_page_pool
)
2074 /* Optimisation for I/Os between 4k and 128k */
2075 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2077 if (!dev
->prp_small_pool
) {
2078 dma_pool_destroy(dev
->prp_page_pool
);
2084 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2086 dma_pool_destroy(dev
->prp_page_pool
);
2087 dma_pool_destroy(dev
->prp_small_pool
);
2090 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2092 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2094 put_device(dev
->dev
);
2095 if (dev
->tagset
.tags
)
2096 blk_mq_free_tag_set(&dev
->tagset
);
2097 if (dev
->ctrl
.admin_q
)
2098 blk_put_queue(dev
->ctrl
.admin_q
);
2104 static void nvme_probe_work(struct work_struct
*work
)
2106 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, probe_work
);
2107 bool start_thread
= false;
2110 result
= nvme_dev_map(dev
);
2114 result
= nvme_configure_admin_queue(dev
);
2118 spin_lock(&dev_list_lock
);
2119 if (list_empty(&dev_list
) && IS_ERR_OR_NULL(nvme_thread
)) {
2120 start_thread
= true;
2123 list_add(&dev
->node
, &dev_list
);
2124 spin_unlock(&dev_list_lock
);
2127 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
2128 wake_up_all(&nvme_kthread_wait
);
2130 wait_event_killable(nvme_kthread_wait
, nvme_thread
);
2132 if (IS_ERR_OR_NULL(nvme_thread
)) {
2133 result
= nvme_thread
? PTR_ERR(nvme_thread
) : -EINTR
;
2137 nvme_init_queue(dev
->queues
[0], 0);
2138 result
= nvme_alloc_admin_tags(dev
);
2142 result
= nvme_init_identify(&dev
->ctrl
);
2146 result
= nvme_setup_io_queues(dev
);
2150 dev
->ctrl
.event_limit
= 1;
2153 * Keep the controller around but remove all namespaces if we don't have
2154 * any working I/O queue.
2156 if (dev
->online_queues
< 2) {
2157 dev_warn(dev
->dev
, "IO queues not created\n");
2158 nvme_remove_namespaces(&dev
->ctrl
);
2160 nvme_unfreeze_queues(dev
);
2167 nvme_dev_remove_admin(dev
);
2168 blk_put_queue(dev
->ctrl
.admin_q
);
2169 dev
->ctrl
.admin_q
= NULL
;
2170 dev
->queues
[0]->tags
= NULL
;
2172 nvme_disable_queue(dev
, 0);
2173 nvme_dev_list_remove(dev
);
2175 nvme_dev_unmap(dev
);
2177 if (!work_busy(&dev
->reset_work
))
2178 nvme_dead_ctrl(dev
);
2181 static int nvme_remove_dead_ctrl(void *arg
)
2183 struct nvme_dev
*dev
= (struct nvme_dev
*)arg
;
2184 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2186 if (pci_get_drvdata(pdev
))
2187 pci_stop_and_remove_bus_device_locked(pdev
);
2188 nvme_put_ctrl(&dev
->ctrl
);
2192 static void nvme_dead_ctrl(struct nvme_dev
*dev
)
2194 dev_warn(dev
->dev
, "Device failed to resume\n");
2195 kref_get(&dev
->ctrl
.kref
);
2196 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl
, dev
, "nvme%d",
2197 dev
->ctrl
.instance
))) {
2199 "Failed to start controller remove task\n");
2200 nvme_put_ctrl(&dev
->ctrl
);
2204 static void nvme_reset_work(struct work_struct
*ws
)
2206 struct nvme_dev
*dev
= container_of(ws
, struct nvme_dev
, reset_work
);
2207 bool in_probe
= work_busy(&dev
->probe_work
);
2209 nvme_dev_shutdown(dev
);
2211 /* Synchronize with device probe so that work will see failure status
2212 * and exit gracefully without trying to schedule another reset */
2213 flush_work(&dev
->probe_work
);
2215 /* Fail this device if reset occured during probe to avoid
2216 * infinite initialization loops. */
2218 nvme_dead_ctrl(dev
);
2221 /* Schedule device resume asynchronously so the reset work is available
2222 * to cleanup errors that may occur during reinitialization */
2223 schedule_work(&dev
->probe_work
);
2226 static int __nvme_reset(struct nvme_dev
*dev
)
2228 if (work_pending(&dev
->reset_work
))
2230 list_del_init(&dev
->node
);
2231 queue_work(nvme_workq
, &dev
->reset_work
);
2235 static int nvme_reset(struct nvme_dev
*dev
)
2239 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
2242 spin_lock(&dev_list_lock
);
2243 ret
= __nvme_reset(dev
);
2244 spin_unlock(&dev_list_lock
);
2247 flush_work(&dev
->reset_work
);
2248 flush_work(&dev
->probe_work
);
2255 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2257 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2261 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2263 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2267 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2269 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2273 static bool nvme_pci_io_incapable(struct nvme_ctrl
*ctrl
)
2275 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2277 return !dev
->bar
|| dev
->online_queues
< 2;
2280 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
2282 return nvme_reset(to_nvme_dev(ctrl
));
2285 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2286 .reg_read32
= nvme_pci_reg_read32
,
2287 .reg_write32
= nvme_pci_reg_write32
,
2288 .reg_read64
= nvme_pci_reg_read64
,
2289 .io_incapable
= nvme_pci_io_incapable
,
2290 .reset_ctrl
= nvme_pci_reset_ctrl
,
2291 .free_ctrl
= nvme_pci_free_ctrl
,
2294 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2296 int node
, result
= -ENOMEM
;
2297 struct nvme_dev
*dev
;
2299 node
= dev_to_node(&pdev
->dev
);
2300 if (node
== NUMA_NO_NODE
)
2301 set_dev_node(&pdev
->dev
, 0);
2303 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2306 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
2310 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2315 dev
->dev
= get_device(&pdev
->dev
);
2316 pci_set_drvdata(pdev
, dev
);
2318 INIT_LIST_HEAD(&dev
->node
);
2319 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
2320 INIT_WORK(&dev
->probe_work
, nvme_probe_work
);
2321 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2323 result
= nvme_setup_prp_pools(dev
);
2327 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2332 schedule_work(&dev
->probe_work
);
2336 nvme_release_prp_pools(dev
);
2338 put_device(dev
->dev
);
2346 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2348 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2351 nvme_dev_shutdown(dev
);
2353 schedule_work(&dev
->probe_work
);
2356 static void nvme_shutdown(struct pci_dev
*pdev
)
2358 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2359 nvme_dev_shutdown(dev
);
2362 static void nvme_remove(struct pci_dev
*pdev
)
2364 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2366 spin_lock(&dev_list_lock
);
2367 list_del_init(&dev
->node
);
2368 spin_unlock(&dev_list_lock
);
2370 pci_set_drvdata(pdev
, NULL
);
2371 flush_work(&dev
->probe_work
);
2372 flush_work(&dev
->reset_work
);
2373 flush_work(&dev
->scan_work
);
2374 nvme_remove_namespaces(&dev
->ctrl
);
2375 nvme_dev_shutdown(dev
);
2376 nvme_dev_remove_admin(dev
);
2377 nvme_free_queues(dev
, 0);
2378 nvme_release_cmb(dev
);
2379 nvme_release_prp_pools(dev
);
2380 nvme_put_ctrl(&dev
->ctrl
);
2383 /* These functions are yet to be implemented */
2384 #define nvme_error_detected NULL
2385 #define nvme_dump_registers NULL
2386 #define nvme_link_reset NULL
2387 #define nvme_slot_reset NULL
2388 #define nvme_error_resume NULL
2390 #ifdef CONFIG_PM_SLEEP
2391 static int nvme_suspend(struct device
*dev
)
2393 struct pci_dev
*pdev
= to_pci_dev(dev
);
2394 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2396 nvme_dev_shutdown(ndev
);
2400 static int nvme_resume(struct device
*dev
)
2402 struct pci_dev
*pdev
= to_pci_dev(dev
);
2403 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2405 schedule_work(&ndev
->probe_work
);
2410 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2412 static const struct pci_error_handlers nvme_err_handler
= {
2413 .error_detected
= nvme_error_detected
,
2414 .mmio_enabled
= nvme_dump_registers
,
2415 .link_reset
= nvme_link_reset
,
2416 .slot_reset
= nvme_slot_reset
,
2417 .resume
= nvme_error_resume
,
2418 .reset_notify
= nvme_reset_notify
,
2421 /* Move to pci_ids.h later */
2422 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2424 static const struct pci_device_id nvme_id_table
[] = {
2425 { PCI_VDEVICE(INTEL
, 0x0953),
2426 .driver_data
= NVME_QUIRK_STRIPE_SIZE
, },
2427 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2428 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2431 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2433 static struct pci_driver nvme_driver
= {
2435 .id_table
= nvme_id_table
,
2436 .probe
= nvme_probe
,
2437 .remove
= nvme_remove
,
2438 .shutdown
= nvme_shutdown
,
2440 .pm
= &nvme_dev_pm_ops
,
2442 .err_handler
= &nvme_err_handler
,
2445 static int __init
nvme_init(void)
2449 init_waitqueue_head(&nvme_kthread_wait
);
2451 nvme_workq
= create_singlethread_workqueue("nvme");
2455 result
= nvme_core_init();
2459 result
= pci_register_driver(&nvme_driver
);
2467 destroy_workqueue(nvme_workq
);
2471 static void __exit
nvme_exit(void)
2473 pci_unregister_driver(&nvme_driver
);
2475 destroy_workqueue(nvme_workq
);
2476 BUG_ON(nvme_thread
&& !IS_ERR(nvme_thread
));
2480 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2481 MODULE_LICENSE("GPL");
2482 MODULE_VERSION("1.0");
2483 module_init(nvme_init
);
2484 module_exit(nvme_exit
);