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nvme: introduce max_integrity_segments ctrl attribute
[mirror_ubuntu-hirsute-kernel.git] / drivers / nvme / host / pci.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #include <linux/aer.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
27
28 #include "trace.h"
29 #include "nvme.h"
30
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
33
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
35
36 /*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
42
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
45
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
54
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65 };
66
67 static int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
71 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
72 {
73 unsigned int n;
74 int ret;
75
76 ret = kstrtouint(val, 10, &n);
77 if (ret != 0 || n > num_possible_cpus())
78 return -EINVAL;
79 return param_set_uint(val, kp);
80 }
81
82 static const struct kernel_param_ops io_queue_count_ops = {
83 .set = io_queue_count_set,
84 .get = param_get_uint,
85 };
86
87 static unsigned int write_queues;
88 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
89 MODULE_PARM_DESC(write_queues,
90 "Number of queues to use for writes. If not set, reads and writes "
91 "will share a queue set.");
92
93 static unsigned int poll_queues;
94 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
95 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
96
97 struct nvme_dev;
98 struct nvme_queue;
99
100 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
101 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
102
103 /*
104 * Represents an NVM Express device. Each nvme_dev is a PCI function.
105 */
106 struct nvme_dev {
107 struct nvme_queue *queues;
108 struct blk_mq_tag_set tagset;
109 struct blk_mq_tag_set admin_tagset;
110 u32 __iomem *dbs;
111 struct device *dev;
112 struct dma_pool *prp_page_pool;
113 struct dma_pool *prp_small_pool;
114 unsigned online_queues;
115 unsigned max_qid;
116 unsigned io_queues[HCTX_MAX_TYPES];
117 unsigned int num_vecs;
118 int q_depth;
119 int io_sqes;
120 u32 db_stride;
121 void __iomem *bar;
122 unsigned long bar_mapped_size;
123 struct work_struct remove_work;
124 struct mutex shutdown_lock;
125 bool subsystem;
126 u64 cmb_size;
127 bool cmb_use_sqes;
128 u32 cmbsz;
129 u32 cmbloc;
130 struct nvme_ctrl ctrl;
131 u32 last_ps;
132
133 mempool_t *iod_mempool;
134
135 /* shadow doorbell buffer support: */
136 u32 *dbbuf_dbs;
137 dma_addr_t dbbuf_dbs_dma_addr;
138 u32 *dbbuf_eis;
139 dma_addr_t dbbuf_eis_dma_addr;
140
141 /* host memory buffer support: */
142 u64 host_mem_size;
143 u32 nr_host_mem_descs;
144 dma_addr_t host_mem_descs_dma;
145 struct nvme_host_mem_buf_desc *host_mem_descs;
146 void **host_mem_desc_bufs;
147 unsigned int nr_allocated_queues;
148 unsigned int nr_write_queues;
149 unsigned int nr_poll_queues;
150 };
151
152 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
153 {
154 int n = 0, ret;
155
156 ret = kstrtoint(val, 10, &n);
157 if (ret != 0 || n < 2)
158 return -EINVAL;
159
160 return param_set_int(val, kp);
161 }
162
163 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
164 {
165 return qid * 2 * stride;
166 }
167
168 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
169 {
170 return (qid * 2 + 1) * stride;
171 }
172
173 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
174 {
175 return container_of(ctrl, struct nvme_dev, ctrl);
176 }
177
178 /*
179 * An NVM Express queue. Each device has at least two (one for admin
180 * commands and one for I/O commands).
181 */
182 struct nvme_queue {
183 struct nvme_dev *dev;
184 spinlock_t sq_lock;
185 void *sq_cmds;
186 /* only used for poll queues: */
187 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
188 struct nvme_completion *cqes;
189 dma_addr_t sq_dma_addr;
190 dma_addr_t cq_dma_addr;
191 u32 __iomem *q_db;
192 u16 q_depth;
193 u16 cq_vector;
194 u16 sq_tail;
195 u16 cq_head;
196 u16 qid;
197 u8 cq_phase;
198 u8 sqes;
199 unsigned long flags;
200 #define NVMEQ_ENABLED 0
201 #define NVMEQ_SQ_CMB 1
202 #define NVMEQ_DELETE_ERROR 2
203 #define NVMEQ_POLLED 3
204 u32 *dbbuf_sq_db;
205 u32 *dbbuf_cq_db;
206 u32 *dbbuf_sq_ei;
207 u32 *dbbuf_cq_ei;
208 struct completion delete_done;
209 };
210
211 /*
212 * The nvme_iod describes the data in an I/O.
213 *
214 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
215 * to the actual struct scatterlist.
216 */
217 struct nvme_iod {
218 struct nvme_request req;
219 struct nvme_queue *nvmeq;
220 bool use_sgl;
221 int aborted;
222 int npages; /* In the PRP list. 0 means small pool in use */
223 int nents; /* Used in scatterlist */
224 dma_addr_t first_dma;
225 unsigned int dma_len; /* length of single DMA segment mapping */
226 dma_addr_t meta_dma;
227 struct scatterlist *sg;
228 };
229
230 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
231 {
232 return dev->nr_allocated_queues * 8 * dev->db_stride;
233 }
234
235 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
236 {
237 unsigned int mem_size = nvme_dbbuf_size(dev);
238
239 if (dev->dbbuf_dbs)
240 return 0;
241
242 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
243 &dev->dbbuf_dbs_dma_addr,
244 GFP_KERNEL);
245 if (!dev->dbbuf_dbs)
246 return -ENOMEM;
247 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
248 &dev->dbbuf_eis_dma_addr,
249 GFP_KERNEL);
250 if (!dev->dbbuf_eis) {
251 dma_free_coherent(dev->dev, mem_size,
252 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
253 dev->dbbuf_dbs = NULL;
254 return -ENOMEM;
255 }
256
257 return 0;
258 }
259
260 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
261 {
262 unsigned int mem_size = nvme_dbbuf_size(dev);
263
264 if (dev->dbbuf_dbs) {
265 dma_free_coherent(dev->dev, mem_size,
266 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
267 dev->dbbuf_dbs = NULL;
268 }
269 if (dev->dbbuf_eis) {
270 dma_free_coherent(dev->dev, mem_size,
271 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
272 dev->dbbuf_eis = NULL;
273 }
274 }
275
276 static void nvme_dbbuf_init(struct nvme_dev *dev,
277 struct nvme_queue *nvmeq, int qid)
278 {
279 if (!dev->dbbuf_dbs || !qid)
280 return;
281
282 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
283 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
284 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
285 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
286 }
287
288 static void nvme_dbbuf_set(struct nvme_dev *dev)
289 {
290 struct nvme_command c;
291
292 if (!dev->dbbuf_dbs)
293 return;
294
295 memset(&c, 0, sizeof(c));
296 c.dbbuf.opcode = nvme_admin_dbbuf;
297 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
298 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
299
300 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
301 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
302 /* Free memory and continue on */
303 nvme_dbbuf_dma_free(dev);
304 }
305 }
306
307 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
308 {
309 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
310 }
311
312 /* Update dbbuf and return true if an MMIO is required */
313 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
314 volatile u32 *dbbuf_ei)
315 {
316 if (dbbuf_db) {
317 u16 old_value;
318
319 /*
320 * Ensure that the queue is written before updating
321 * the doorbell in memory
322 */
323 wmb();
324
325 old_value = *dbbuf_db;
326 *dbbuf_db = value;
327
328 /*
329 * Ensure that the doorbell is updated before reading the event
330 * index from memory. The controller needs to provide similar
331 * ordering to ensure the envent index is updated before reading
332 * the doorbell.
333 */
334 mb();
335
336 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
337 return false;
338 }
339
340 return true;
341 }
342
343 /*
344 * Will slightly overestimate the number of pages needed. This is OK
345 * as it only leads to a small amount of wasted memory for the lifetime of
346 * the I/O.
347 */
348 static int nvme_npages(unsigned size, struct nvme_dev *dev)
349 {
350 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
351 dev->ctrl.page_size);
352 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
353 }
354
355 /*
356 * Calculates the number of pages needed for the SGL segments. For example a 4k
357 * page can accommodate 256 SGL descriptors.
358 */
359 static int nvme_pci_npages_sgl(unsigned int num_seg)
360 {
361 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
362 }
363
364 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
365 unsigned int size, unsigned int nseg, bool use_sgl)
366 {
367 size_t alloc_size;
368
369 if (use_sgl)
370 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
371 else
372 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
373
374 return alloc_size + sizeof(struct scatterlist) * nseg;
375 }
376
377 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
378 unsigned int hctx_idx)
379 {
380 struct nvme_dev *dev = data;
381 struct nvme_queue *nvmeq = &dev->queues[0];
382
383 WARN_ON(hctx_idx != 0);
384 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
385
386 hctx->driver_data = nvmeq;
387 return 0;
388 }
389
390 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
391 unsigned int hctx_idx)
392 {
393 struct nvme_dev *dev = data;
394 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
395
396 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
397 hctx->driver_data = nvmeq;
398 return 0;
399 }
400
401 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
402 unsigned int hctx_idx, unsigned int numa_node)
403 {
404 struct nvme_dev *dev = set->driver_data;
405 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
406 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
407 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
408
409 BUG_ON(!nvmeq);
410 iod->nvmeq = nvmeq;
411
412 nvme_req(req)->ctrl = &dev->ctrl;
413 return 0;
414 }
415
416 static int queue_irq_offset(struct nvme_dev *dev)
417 {
418 /* if we have more than 1 vec, admin queue offsets us by 1 */
419 if (dev->num_vecs > 1)
420 return 1;
421
422 return 0;
423 }
424
425 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
426 {
427 struct nvme_dev *dev = set->driver_data;
428 int i, qoff, offset;
429
430 offset = queue_irq_offset(dev);
431 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
432 struct blk_mq_queue_map *map = &set->map[i];
433
434 map->nr_queues = dev->io_queues[i];
435 if (!map->nr_queues) {
436 BUG_ON(i == HCTX_TYPE_DEFAULT);
437 continue;
438 }
439
440 /*
441 * The poll queue(s) doesn't have an IRQ (and hence IRQ
442 * affinity), so use the regular blk-mq cpu mapping
443 */
444 map->queue_offset = qoff;
445 if (i != HCTX_TYPE_POLL && offset)
446 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
447 else
448 blk_mq_map_queues(map);
449 qoff += map->nr_queues;
450 offset += map->nr_queues;
451 }
452
453 return 0;
454 }
455
456 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq)
457 {
458 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
459 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
460 writel(nvmeq->sq_tail, nvmeq->q_db);
461 }
462
463 /**
464 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
465 * @nvmeq: The queue to use
466 * @cmd: The command to send
467 * @write_sq: whether to write to the SQ doorbell
468 */
469 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
470 bool write_sq)
471 {
472 spin_lock(&nvmeq->sq_lock);
473 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
474 cmd, sizeof(*cmd));
475 if (++nvmeq->sq_tail == nvmeq->q_depth)
476 nvmeq->sq_tail = 0;
477 if (write_sq)
478 nvme_write_sq_db(nvmeq);
479 spin_unlock(&nvmeq->sq_lock);
480 }
481
482 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
483 {
484 struct nvme_queue *nvmeq = hctx->driver_data;
485
486 spin_lock(&nvmeq->sq_lock);
487 nvme_write_sq_db(nvmeq);
488 spin_unlock(&nvmeq->sq_lock);
489 }
490
491 static void **nvme_pci_iod_list(struct request *req)
492 {
493 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
494 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
495 }
496
497 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
498 {
499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
500 int nseg = blk_rq_nr_phys_segments(req);
501 unsigned int avg_seg_size;
502
503 if (nseg == 0)
504 return false;
505
506 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
507
508 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
509 return false;
510 if (!iod->nvmeq->qid)
511 return false;
512 if (!sgl_threshold || avg_seg_size < sgl_threshold)
513 return false;
514 return true;
515 }
516
517 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
518 {
519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
520 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
521 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
522 int i;
523
524 if (iod->dma_len) {
525 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
526 rq_dma_dir(req));
527 return;
528 }
529
530 WARN_ON_ONCE(!iod->nents);
531
532 if (is_pci_p2pdma_page(sg_page(iod->sg)))
533 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
534 rq_dma_dir(req));
535 else
536 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
537
538
539 if (iod->npages == 0)
540 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
541 dma_addr);
542
543 for (i = 0; i < iod->npages; i++) {
544 void *addr = nvme_pci_iod_list(req)[i];
545
546 if (iod->use_sgl) {
547 struct nvme_sgl_desc *sg_list = addr;
548
549 next_dma_addr =
550 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
551 } else {
552 __le64 *prp_list = addr;
553
554 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
555 }
556
557 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
558 dma_addr = next_dma_addr;
559 }
560
561 mempool_free(iod->sg, dev->iod_mempool);
562 }
563
564 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
565 {
566 int i;
567 struct scatterlist *sg;
568
569 for_each_sg(sgl, sg, nents, i) {
570 dma_addr_t phys = sg_phys(sg);
571 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
572 "dma_address:%pad dma_length:%d\n",
573 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
574 sg_dma_len(sg));
575 }
576 }
577
578 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
579 struct request *req, struct nvme_rw_command *cmnd)
580 {
581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
582 struct dma_pool *pool;
583 int length = blk_rq_payload_bytes(req);
584 struct scatterlist *sg = iod->sg;
585 int dma_len = sg_dma_len(sg);
586 u64 dma_addr = sg_dma_address(sg);
587 u32 page_size = dev->ctrl.page_size;
588 int offset = dma_addr & (page_size - 1);
589 __le64 *prp_list;
590 void **list = nvme_pci_iod_list(req);
591 dma_addr_t prp_dma;
592 int nprps, i;
593
594 length -= (page_size - offset);
595 if (length <= 0) {
596 iod->first_dma = 0;
597 goto done;
598 }
599
600 dma_len -= (page_size - offset);
601 if (dma_len) {
602 dma_addr += (page_size - offset);
603 } else {
604 sg = sg_next(sg);
605 dma_addr = sg_dma_address(sg);
606 dma_len = sg_dma_len(sg);
607 }
608
609 if (length <= page_size) {
610 iod->first_dma = dma_addr;
611 goto done;
612 }
613
614 nprps = DIV_ROUND_UP(length, page_size);
615 if (nprps <= (256 / 8)) {
616 pool = dev->prp_small_pool;
617 iod->npages = 0;
618 } else {
619 pool = dev->prp_page_pool;
620 iod->npages = 1;
621 }
622
623 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
624 if (!prp_list) {
625 iod->first_dma = dma_addr;
626 iod->npages = -1;
627 return BLK_STS_RESOURCE;
628 }
629 list[0] = prp_list;
630 iod->first_dma = prp_dma;
631 i = 0;
632 for (;;) {
633 if (i == page_size >> 3) {
634 __le64 *old_prp_list = prp_list;
635 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
636 if (!prp_list)
637 return BLK_STS_RESOURCE;
638 list[iod->npages++] = prp_list;
639 prp_list[0] = old_prp_list[i - 1];
640 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
641 i = 1;
642 }
643 prp_list[i++] = cpu_to_le64(dma_addr);
644 dma_len -= page_size;
645 dma_addr += page_size;
646 length -= page_size;
647 if (length <= 0)
648 break;
649 if (dma_len > 0)
650 continue;
651 if (unlikely(dma_len < 0))
652 goto bad_sgl;
653 sg = sg_next(sg);
654 dma_addr = sg_dma_address(sg);
655 dma_len = sg_dma_len(sg);
656 }
657
658 done:
659 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
660 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
661
662 return BLK_STS_OK;
663
664 bad_sgl:
665 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
666 "Invalid SGL for payload:%d nents:%d\n",
667 blk_rq_payload_bytes(req), iod->nents);
668 return BLK_STS_IOERR;
669 }
670
671 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
672 struct scatterlist *sg)
673 {
674 sge->addr = cpu_to_le64(sg_dma_address(sg));
675 sge->length = cpu_to_le32(sg_dma_len(sg));
676 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
677 }
678
679 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
680 dma_addr_t dma_addr, int entries)
681 {
682 sge->addr = cpu_to_le64(dma_addr);
683 if (entries < SGES_PER_PAGE) {
684 sge->length = cpu_to_le32(entries * sizeof(*sge));
685 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
686 } else {
687 sge->length = cpu_to_le32(PAGE_SIZE);
688 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
689 }
690 }
691
692 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
693 struct request *req, struct nvme_rw_command *cmd, int entries)
694 {
695 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
696 struct dma_pool *pool;
697 struct nvme_sgl_desc *sg_list;
698 struct scatterlist *sg = iod->sg;
699 dma_addr_t sgl_dma;
700 int i = 0;
701
702 /* setting the transfer type as SGL */
703 cmd->flags = NVME_CMD_SGL_METABUF;
704
705 if (entries == 1) {
706 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
707 return BLK_STS_OK;
708 }
709
710 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
711 pool = dev->prp_small_pool;
712 iod->npages = 0;
713 } else {
714 pool = dev->prp_page_pool;
715 iod->npages = 1;
716 }
717
718 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
719 if (!sg_list) {
720 iod->npages = -1;
721 return BLK_STS_RESOURCE;
722 }
723
724 nvme_pci_iod_list(req)[0] = sg_list;
725 iod->first_dma = sgl_dma;
726
727 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
728
729 do {
730 if (i == SGES_PER_PAGE) {
731 struct nvme_sgl_desc *old_sg_desc = sg_list;
732 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
733
734 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
735 if (!sg_list)
736 return BLK_STS_RESOURCE;
737
738 i = 0;
739 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
740 sg_list[i++] = *link;
741 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
742 }
743
744 nvme_pci_sgl_set_data(&sg_list[i++], sg);
745 sg = sg_next(sg);
746 } while (--entries > 0);
747
748 return BLK_STS_OK;
749 }
750
751 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754 {
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
757 unsigned int first_prp_len = dev->ctrl.page_size - offset;
758
759 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
760 if (dma_mapping_error(dev->dev, iod->first_dma))
761 return BLK_STS_RESOURCE;
762 iod->dma_len = bv->bv_len;
763
764 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
765 if (bv->bv_len > first_prp_len)
766 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
767 return 0;
768 }
769
770 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
771 struct request *req, struct nvme_rw_command *cmnd,
772 struct bio_vec *bv)
773 {
774 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
775
776 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
777 if (dma_mapping_error(dev->dev, iod->first_dma))
778 return BLK_STS_RESOURCE;
779 iod->dma_len = bv->bv_len;
780
781 cmnd->flags = NVME_CMD_SGL_METABUF;
782 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
783 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
784 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
785 return 0;
786 }
787
788 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
789 struct nvme_command *cmnd)
790 {
791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
792 blk_status_t ret = BLK_STS_RESOURCE;
793 int nr_mapped;
794
795 if (blk_rq_nr_phys_segments(req) == 1) {
796 struct bio_vec bv = req_bvec(req);
797
798 if (!is_pci_p2pdma_page(bv.bv_page)) {
799 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
800 return nvme_setup_prp_simple(dev, req,
801 &cmnd->rw, &bv);
802
803 if (iod->nvmeq->qid &&
804 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
805 return nvme_setup_sgl_simple(dev, req,
806 &cmnd->rw, &bv);
807 }
808 }
809
810 iod->dma_len = 0;
811 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
812 if (!iod->sg)
813 return BLK_STS_RESOURCE;
814 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
815 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
816 if (!iod->nents)
817 goto out;
818
819 if (is_pci_p2pdma_page(sg_page(iod->sg)))
820 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
821 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
822 else
823 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
824 rq_dma_dir(req), DMA_ATTR_NO_WARN);
825 if (!nr_mapped)
826 goto out;
827
828 iod->use_sgl = nvme_pci_use_sgls(dev, req);
829 if (iod->use_sgl)
830 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
831 else
832 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
833 out:
834 if (ret != BLK_STS_OK)
835 nvme_unmap_data(dev, req);
836 return ret;
837 }
838
839 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
840 struct nvme_command *cmnd)
841 {
842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
843
844 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
845 rq_dma_dir(req), 0);
846 if (dma_mapping_error(dev->dev, iod->meta_dma))
847 return BLK_STS_IOERR;
848 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
849 return 0;
850 }
851
852 /*
853 * NOTE: ns is NULL when called on the admin queue.
854 */
855 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
856 const struct blk_mq_queue_data *bd)
857 {
858 struct nvme_ns *ns = hctx->queue->queuedata;
859 struct nvme_queue *nvmeq = hctx->driver_data;
860 struct nvme_dev *dev = nvmeq->dev;
861 struct request *req = bd->rq;
862 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
863 struct nvme_command cmnd;
864 blk_status_t ret;
865
866 iod->aborted = 0;
867 iod->npages = -1;
868 iod->nents = 0;
869
870 /*
871 * We should not need to do this, but we're still using this to
872 * ensure we can drain requests on a dying queue.
873 */
874 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
875 return BLK_STS_IOERR;
876
877 ret = nvme_setup_cmd(ns, req, &cmnd);
878 if (ret)
879 return ret;
880
881 if (blk_rq_nr_phys_segments(req)) {
882 ret = nvme_map_data(dev, req, &cmnd);
883 if (ret)
884 goto out_free_cmd;
885 }
886
887 if (blk_integrity_rq(req)) {
888 ret = nvme_map_metadata(dev, req, &cmnd);
889 if (ret)
890 goto out_unmap_data;
891 }
892
893 blk_mq_start_request(req);
894 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
895 return BLK_STS_OK;
896 out_unmap_data:
897 nvme_unmap_data(dev, req);
898 out_free_cmd:
899 nvme_cleanup_cmd(req);
900 return ret;
901 }
902
903 static void nvme_pci_complete_rq(struct request *req)
904 {
905 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
906 struct nvme_dev *dev = iod->nvmeq->dev;
907
908 if (blk_integrity_rq(req))
909 dma_unmap_page(dev->dev, iod->meta_dma,
910 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
911 if (blk_rq_nr_phys_segments(req))
912 nvme_unmap_data(dev, req);
913 nvme_complete_rq(req);
914 }
915
916 /* We read the CQE phase first to check if the rest of the entry is valid */
917 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
918 {
919 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
920
921 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
922 }
923
924 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
925 {
926 u16 head = nvmeq->cq_head;
927
928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
929 nvmeq->dbbuf_cq_ei))
930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
931 }
932
933 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
934 {
935 if (!nvmeq->qid)
936 return nvmeq->dev->admin_tagset.tags[0];
937 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
938 }
939
940 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
941 {
942 struct nvme_completion *cqe = &nvmeq->cqes[idx];
943 struct request *req;
944
945 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
946 dev_warn(nvmeq->dev->ctrl.device,
947 "invalid id %d completed on queue %d\n",
948 cqe->command_id, le16_to_cpu(cqe->sq_id));
949 return;
950 }
951
952 /*
953 * AEN requests are special as they don't time out and can
954 * survive any kind of queue freeze and often don't respond to
955 * aborts. We don't even bother to allocate a struct request
956 * for them but rather special case them here.
957 */
958 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
959 nvme_complete_async_event(&nvmeq->dev->ctrl,
960 cqe->status, &cqe->result);
961 return;
962 }
963
964 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
965 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
966 nvme_end_request(req, cqe->status, cqe->result);
967 }
968
969 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
970 {
971 u16 tmp = nvmeq->cq_head + 1;
972
973 if (tmp == nvmeq->q_depth) {
974 nvmeq->cq_head = 0;
975 nvmeq->cq_phase ^= 1;
976 } else {
977 nvmeq->cq_head = tmp;
978 }
979 }
980
981 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
982 {
983 int found = 0;
984
985 while (nvme_cqe_pending(nvmeq)) {
986 found++;
987 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
988 nvme_update_cq_head(nvmeq);
989 }
990
991 if (found)
992 nvme_ring_cq_doorbell(nvmeq);
993 return found;
994 }
995
996 static irqreturn_t nvme_irq(int irq, void *data)
997 {
998 struct nvme_queue *nvmeq = data;
999 irqreturn_t ret = IRQ_NONE;
1000
1001 /*
1002 * The rmb/wmb pair ensures we see all updates from a previous run of
1003 * the irq handler, even if that was on another CPU.
1004 */
1005 rmb();
1006 if (nvme_process_cq(nvmeq))
1007 ret = IRQ_HANDLED;
1008 wmb();
1009
1010 return ret;
1011 }
1012
1013 static irqreturn_t nvme_irq_check(int irq, void *data)
1014 {
1015 struct nvme_queue *nvmeq = data;
1016 if (nvme_cqe_pending(nvmeq))
1017 return IRQ_WAKE_THREAD;
1018 return IRQ_NONE;
1019 }
1020
1021 /*
1022 * Poll for completions for any interrupt driven queue
1023 * Can be called from any context.
1024 */
1025 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1026 {
1027 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1028
1029 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1030
1031 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1032 nvme_process_cq(nvmeq);
1033 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1034 }
1035
1036 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1037 {
1038 struct nvme_queue *nvmeq = hctx->driver_data;
1039 bool found;
1040
1041 if (!nvme_cqe_pending(nvmeq))
1042 return 0;
1043
1044 spin_lock(&nvmeq->cq_poll_lock);
1045 found = nvme_process_cq(nvmeq);
1046 spin_unlock(&nvmeq->cq_poll_lock);
1047
1048 return found;
1049 }
1050
1051 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1052 {
1053 struct nvme_dev *dev = to_nvme_dev(ctrl);
1054 struct nvme_queue *nvmeq = &dev->queues[0];
1055 struct nvme_command c;
1056
1057 memset(&c, 0, sizeof(c));
1058 c.common.opcode = nvme_admin_async_event;
1059 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1060 nvme_submit_cmd(nvmeq, &c, true);
1061 }
1062
1063 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1064 {
1065 struct nvme_command c;
1066
1067 memset(&c, 0, sizeof(c));
1068 c.delete_queue.opcode = opcode;
1069 c.delete_queue.qid = cpu_to_le16(id);
1070
1071 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1072 }
1073
1074 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1075 struct nvme_queue *nvmeq, s16 vector)
1076 {
1077 struct nvme_command c;
1078 int flags = NVME_QUEUE_PHYS_CONTIG;
1079
1080 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1081 flags |= NVME_CQ_IRQ_ENABLED;
1082
1083 /*
1084 * Note: we (ab)use the fact that the prp fields survive if no data
1085 * is attached to the request.
1086 */
1087 memset(&c, 0, sizeof(c));
1088 c.create_cq.opcode = nvme_admin_create_cq;
1089 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1090 c.create_cq.cqid = cpu_to_le16(qid);
1091 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1092 c.create_cq.cq_flags = cpu_to_le16(flags);
1093 c.create_cq.irq_vector = cpu_to_le16(vector);
1094
1095 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1096 }
1097
1098 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1099 struct nvme_queue *nvmeq)
1100 {
1101 struct nvme_ctrl *ctrl = &dev->ctrl;
1102 struct nvme_command c;
1103 int flags = NVME_QUEUE_PHYS_CONTIG;
1104
1105 /*
1106 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1107 * set. Since URGENT priority is zeroes, it makes all queues
1108 * URGENT.
1109 */
1110 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1111 flags |= NVME_SQ_PRIO_MEDIUM;
1112
1113 /*
1114 * Note: we (ab)use the fact that the prp fields survive if no data
1115 * is attached to the request.
1116 */
1117 memset(&c, 0, sizeof(c));
1118 c.create_sq.opcode = nvme_admin_create_sq;
1119 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1120 c.create_sq.sqid = cpu_to_le16(qid);
1121 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1122 c.create_sq.sq_flags = cpu_to_le16(flags);
1123 c.create_sq.cqid = cpu_to_le16(qid);
1124
1125 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1126 }
1127
1128 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1129 {
1130 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1131 }
1132
1133 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1134 {
1135 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1136 }
1137
1138 static void abort_endio(struct request *req, blk_status_t error)
1139 {
1140 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1141 struct nvme_queue *nvmeq = iod->nvmeq;
1142
1143 dev_warn(nvmeq->dev->ctrl.device,
1144 "Abort status: 0x%x", nvme_req(req)->status);
1145 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1146 blk_mq_free_request(req);
1147 }
1148
1149 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1150 {
1151
1152 /* If true, indicates loss of adapter communication, possibly by a
1153 * NVMe Subsystem reset.
1154 */
1155 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1156
1157 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1158 switch (dev->ctrl.state) {
1159 case NVME_CTRL_RESETTING:
1160 case NVME_CTRL_CONNECTING:
1161 return false;
1162 default:
1163 break;
1164 }
1165
1166 /* We shouldn't reset unless the controller is on fatal error state
1167 * _or_ if we lost the communication with it.
1168 */
1169 if (!(csts & NVME_CSTS_CFS) && !nssro)
1170 return false;
1171
1172 return true;
1173 }
1174
1175 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1176 {
1177 /* Read a config register to help see what died. */
1178 u16 pci_status;
1179 int result;
1180
1181 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1182 &pci_status);
1183 if (result == PCIBIOS_SUCCESSFUL)
1184 dev_warn(dev->ctrl.device,
1185 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1186 csts, pci_status);
1187 else
1188 dev_warn(dev->ctrl.device,
1189 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1190 csts, result);
1191 }
1192
1193 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1194 {
1195 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1196 struct nvme_queue *nvmeq = iod->nvmeq;
1197 struct nvme_dev *dev = nvmeq->dev;
1198 struct request *abort_req;
1199 struct nvme_command cmd;
1200 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1201
1202 /* If PCI error recovery process is happening, we cannot reset or
1203 * the recovery mechanism will surely fail.
1204 */
1205 mb();
1206 if (pci_channel_offline(to_pci_dev(dev->dev)))
1207 return BLK_EH_RESET_TIMER;
1208
1209 /*
1210 * Reset immediately if the controller is failed
1211 */
1212 if (nvme_should_reset(dev, csts)) {
1213 nvme_warn_reset(dev, csts);
1214 nvme_dev_disable(dev, false);
1215 nvme_reset_ctrl(&dev->ctrl);
1216 return BLK_EH_DONE;
1217 }
1218
1219 /*
1220 * Did we miss an interrupt?
1221 */
1222 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1223 nvme_poll(req->mq_hctx);
1224 else
1225 nvme_poll_irqdisable(nvmeq);
1226
1227 if (blk_mq_request_completed(req)) {
1228 dev_warn(dev->ctrl.device,
1229 "I/O %d QID %d timeout, completion polled\n",
1230 req->tag, nvmeq->qid);
1231 return BLK_EH_DONE;
1232 }
1233
1234 /*
1235 * Shutdown immediately if controller times out while starting. The
1236 * reset work will see the pci device disabled when it gets the forced
1237 * cancellation error. All outstanding requests are completed on
1238 * shutdown, so we return BLK_EH_DONE.
1239 */
1240 switch (dev->ctrl.state) {
1241 case NVME_CTRL_CONNECTING:
1242 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1243 /* fall through */
1244 case NVME_CTRL_DELETING:
1245 dev_warn_ratelimited(dev->ctrl.device,
1246 "I/O %d QID %d timeout, disable controller\n",
1247 req->tag, nvmeq->qid);
1248 nvme_dev_disable(dev, true);
1249 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1250 return BLK_EH_DONE;
1251 case NVME_CTRL_RESETTING:
1252 return BLK_EH_RESET_TIMER;
1253 default:
1254 break;
1255 }
1256
1257 /*
1258 * Shutdown the controller immediately and schedule a reset if the
1259 * command was already aborted once before and still hasn't been
1260 * returned to the driver, or if this is the admin queue.
1261 */
1262 if (!nvmeq->qid || iod->aborted) {
1263 dev_warn(dev->ctrl.device,
1264 "I/O %d QID %d timeout, reset controller\n",
1265 req->tag, nvmeq->qid);
1266 nvme_dev_disable(dev, false);
1267 nvme_reset_ctrl(&dev->ctrl);
1268
1269 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1270 return BLK_EH_DONE;
1271 }
1272
1273 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1274 atomic_inc(&dev->ctrl.abort_limit);
1275 return BLK_EH_RESET_TIMER;
1276 }
1277 iod->aborted = 1;
1278
1279 memset(&cmd, 0, sizeof(cmd));
1280 cmd.abort.opcode = nvme_admin_abort_cmd;
1281 cmd.abort.cid = req->tag;
1282 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1283
1284 dev_warn(nvmeq->dev->ctrl.device,
1285 "I/O %d QID %d timeout, aborting\n",
1286 req->tag, nvmeq->qid);
1287
1288 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1289 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1290 if (IS_ERR(abort_req)) {
1291 atomic_inc(&dev->ctrl.abort_limit);
1292 return BLK_EH_RESET_TIMER;
1293 }
1294
1295 abort_req->timeout = ADMIN_TIMEOUT;
1296 abort_req->end_io_data = NULL;
1297 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1298
1299 /*
1300 * The aborted req will be completed on receiving the abort req.
1301 * We enable the timer again. If hit twice, it'll cause a device reset,
1302 * as the device then is in a faulty state.
1303 */
1304 return BLK_EH_RESET_TIMER;
1305 }
1306
1307 static void nvme_free_queue(struct nvme_queue *nvmeq)
1308 {
1309 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1310 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1311 if (!nvmeq->sq_cmds)
1312 return;
1313
1314 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1315 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1316 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1317 } else {
1318 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1319 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1320 }
1321 }
1322
1323 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1324 {
1325 int i;
1326
1327 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1328 dev->ctrl.queue_count--;
1329 nvme_free_queue(&dev->queues[i]);
1330 }
1331 }
1332
1333 /**
1334 * nvme_suspend_queue - put queue into suspended state
1335 * @nvmeq: queue to suspend
1336 */
1337 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1338 {
1339 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1340 return 1;
1341
1342 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1343 mb();
1344
1345 nvmeq->dev->online_queues--;
1346 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1347 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1348 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1349 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1350 return 0;
1351 }
1352
1353 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1354 {
1355 int i;
1356
1357 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1358 nvme_suspend_queue(&dev->queues[i]);
1359 }
1360
1361 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1362 {
1363 struct nvme_queue *nvmeq = &dev->queues[0];
1364
1365 if (shutdown)
1366 nvme_shutdown_ctrl(&dev->ctrl);
1367 else
1368 nvme_disable_ctrl(&dev->ctrl);
1369
1370 nvme_poll_irqdisable(nvmeq);
1371 }
1372
1373 /*
1374 * Called only on a device that has been disabled and after all other threads
1375 * that can check this device's completion queues have synced. This is the
1376 * last chance for the driver to see a natural completion before
1377 * nvme_cancel_request() terminates all incomplete requests.
1378 */
1379 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1380 {
1381 int i;
1382
1383 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1384 nvme_process_cq(&dev->queues[i]);
1385 }
1386
1387 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1388 int entry_size)
1389 {
1390 int q_depth = dev->q_depth;
1391 unsigned q_size_aligned = roundup(q_depth * entry_size,
1392 dev->ctrl.page_size);
1393
1394 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1395 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1396 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1397 q_depth = div_u64(mem_per_q, entry_size);
1398
1399 /*
1400 * Ensure the reduced q_depth is above some threshold where it
1401 * would be better to map queues in system memory with the
1402 * original depth
1403 */
1404 if (q_depth < 64)
1405 return -ENOMEM;
1406 }
1407
1408 return q_depth;
1409 }
1410
1411 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1412 int qid)
1413 {
1414 struct pci_dev *pdev = to_pci_dev(dev->dev);
1415
1416 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1417 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1418 if (nvmeq->sq_cmds) {
1419 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1420 nvmeq->sq_cmds);
1421 if (nvmeq->sq_dma_addr) {
1422 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1423 return 0;
1424 }
1425
1426 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1427 }
1428 }
1429
1430 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1431 &nvmeq->sq_dma_addr, GFP_KERNEL);
1432 if (!nvmeq->sq_cmds)
1433 return -ENOMEM;
1434 return 0;
1435 }
1436
1437 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1438 {
1439 struct nvme_queue *nvmeq = &dev->queues[qid];
1440
1441 if (dev->ctrl.queue_count > qid)
1442 return 0;
1443
1444 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1445 nvmeq->q_depth = depth;
1446 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1447 &nvmeq->cq_dma_addr, GFP_KERNEL);
1448 if (!nvmeq->cqes)
1449 goto free_nvmeq;
1450
1451 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1452 goto free_cqdma;
1453
1454 nvmeq->dev = dev;
1455 spin_lock_init(&nvmeq->sq_lock);
1456 spin_lock_init(&nvmeq->cq_poll_lock);
1457 nvmeq->cq_head = 0;
1458 nvmeq->cq_phase = 1;
1459 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1460 nvmeq->qid = qid;
1461 dev->ctrl.queue_count++;
1462
1463 return 0;
1464
1465 free_cqdma:
1466 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1467 nvmeq->cq_dma_addr);
1468 free_nvmeq:
1469 return -ENOMEM;
1470 }
1471
1472 static int queue_request_irq(struct nvme_queue *nvmeq)
1473 {
1474 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1475 int nr = nvmeq->dev->ctrl.instance;
1476
1477 if (use_threaded_interrupts) {
1478 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1479 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1480 } else {
1481 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1482 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1483 }
1484 }
1485
1486 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1487 {
1488 struct nvme_dev *dev = nvmeq->dev;
1489
1490 nvmeq->sq_tail = 0;
1491 nvmeq->cq_head = 0;
1492 nvmeq->cq_phase = 1;
1493 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1494 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1495 nvme_dbbuf_init(dev, nvmeq, qid);
1496 dev->online_queues++;
1497 wmb(); /* ensure the first interrupt sees the initialization */
1498 }
1499
1500 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1501 {
1502 struct nvme_dev *dev = nvmeq->dev;
1503 int result;
1504 u16 vector = 0;
1505
1506 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1507
1508 /*
1509 * A queue's vector matches the queue identifier unless the controller
1510 * has only one vector available.
1511 */
1512 if (!polled)
1513 vector = dev->num_vecs == 1 ? 0 : qid;
1514 else
1515 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1516
1517 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1518 if (result)
1519 return result;
1520
1521 result = adapter_alloc_sq(dev, qid, nvmeq);
1522 if (result < 0)
1523 return result;
1524 if (result)
1525 goto release_cq;
1526
1527 nvmeq->cq_vector = vector;
1528 nvme_init_queue(nvmeq, qid);
1529
1530 if (!polled) {
1531 result = queue_request_irq(nvmeq);
1532 if (result < 0)
1533 goto release_sq;
1534 }
1535
1536 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1537 return result;
1538
1539 release_sq:
1540 dev->online_queues--;
1541 adapter_delete_sq(dev, qid);
1542 release_cq:
1543 adapter_delete_cq(dev, qid);
1544 return result;
1545 }
1546
1547 static const struct blk_mq_ops nvme_mq_admin_ops = {
1548 .queue_rq = nvme_queue_rq,
1549 .complete = nvme_pci_complete_rq,
1550 .init_hctx = nvme_admin_init_hctx,
1551 .init_request = nvme_init_request,
1552 .timeout = nvme_timeout,
1553 };
1554
1555 static const struct blk_mq_ops nvme_mq_ops = {
1556 .queue_rq = nvme_queue_rq,
1557 .complete = nvme_pci_complete_rq,
1558 .commit_rqs = nvme_commit_rqs,
1559 .init_hctx = nvme_init_hctx,
1560 .init_request = nvme_init_request,
1561 .map_queues = nvme_pci_map_queues,
1562 .timeout = nvme_timeout,
1563 .poll = nvme_poll,
1564 };
1565
1566 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1567 {
1568 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1569 /*
1570 * If the controller was reset during removal, it's possible
1571 * user requests may be waiting on a stopped queue. Start the
1572 * queue to flush these to completion.
1573 */
1574 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1575 blk_cleanup_queue(dev->ctrl.admin_q);
1576 blk_mq_free_tag_set(&dev->admin_tagset);
1577 }
1578 }
1579
1580 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1581 {
1582 if (!dev->ctrl.admin_q) {
1583 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1584 dev->admin_tagset.nr_hw_queues = 1;
1585
1586 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1587 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1588 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1589 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1590 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1591 dev->admin_tagset.driver_data = dev;
1592
1593 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1594 return -ENOMEM;
1595 dev->ctrl.admin_tagset = &dev->admin_tagset;
1596
1597 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1598 if (IS_ERR(dev->ctrl.admin_q)) {
1599 blk_mq_free_tag_set(&dev->admin_tagset);
1600 return -ENOMEM;
1601 }
1602 if (!blk_get_queue(dev->ctrl.admin_q)) {
1603 nvme_dev_remove_admin(dev);
1604 dev->ctrl.admin_q = NULL;
1605 return -ENODEV;
1606 }
1607 } else
1608 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1609
1610 return 0;
1611 }
1612
1613 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1614 {
1615 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1616 }
1617
1618 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1619 {
1620 struct pci_dev *pdev = to_pci_dev(dev->dev);
1621
1622 if (size <= dev->bar_mapped_size)
1623 return 0;
1624 if (size > pci_resource_len(pdev, 0))
1625 return -ENOMEM;
1626 if (dev->bar)
1627 iounmap(dev->bar);
1628 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1629 if (!dev->bar) {
1630 dev->bar_mapped_size = 0;
1631 return -ENOMEM;
1632 }
1633 dev->bar_mapped_size = size;
1634 dev->dbs = dev->bar + NVME_REG_DBS;
1635
1636 return 0;
1637 }
1638
1639 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1640 {
1641 int result;
1642 u32 aqa;
1643 struct nvme_queue *nvmeq;
1644
1645 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1646 if (result < 0)
1647 return result;
1648
1649 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1650 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1651
1652 if (dev->subsystem &&
1653 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1654 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1655
1656 result = nvme_disable_ctrl(&dev->ctrl);
1657 if (result < 0)
1658 return result;
1659
1660 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1661 if (result)
1662 return result;
1663
1664 nvmeq = &dev->queues[0];
1665 aqa = nvmeq->q_depth - 1;
1666 aqa |= aqa << 16;
1667
1668 writel(aqa, dev->bar + NVME_REG_AQA);
1669 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1670 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1671
1672 result = nvme_enable_ctrl(&dev->ctrl);
1673 if (result)
1674 return result;
1675
1676 nvmeq->cq_vector = 0;
1677 nvme_init_queue(nvmeq, 0);
1678 result = queue_request_irq(nvmeq);
1679 if (result) {
1680 dev->online_queues--;
1681 return result;
1682 }
1683
1684 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1685 return result;
1686 }
1687
1688 static int nvme_create_io_queues(struct nvme_dev *dev)
1689 {
1690 unsigned i, max, rw_queues;
1691 int ret = 0;
1692
1693 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1694 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1695 ret = -ENOMEM;
1696 break;
1697 }
1698 }
1699
1700 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1701 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1702 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1703 dev->io_queues[HCTX_TYPE_READ];
1704 } else {
1705 rw_queues = max;
1706 }
1707
1708 for (i = dev->online_queues; i <= max; i++) {
1709 bool polled = i > rw_queues;
1710
1711 ret = nvme_create_queue(&dev->queues[i], i, polled);
1712 if (ret)
1713 break;
1714 }
1715
1716 /*
1717 * Ignore failing Create SQ/CQ commands, we can continue with less
1718 * than the desired amount of queues, and even a controller without
1719 * I/O queues can still be used to issue admin commands. This might
1720 * be useful to upgrade a buggy firmware for example.
1721 */
1722 return ret >= 0 ? 0 : ret;
1723 }
1724
1725 static ssize_t nvme_cmb_show(struct device *dev,
1726 struct device_attribute *attr,
1727 char *buf)
1728 {
1729 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1730
1731 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1732 ndev->cmbloc, ndev->cmbsz);
1733 }
1734 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1735
1736 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1737 {
1738 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1739
1740 return 1ULL << (12 + 4 * szu);
1741 }
1742
1743 static u32 nvme_cmb_size(struct nvme_dev *dev)
1744 {
1745 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1746 }
1747
1748 static void nvme_map_cmb(struct nvme_dev *dev)
1749 {
1750 u64 size, offset;
1751 resource_size_t bar_size;
1752 struct pci_dev *pdev = to_pci_dev(dev->dev);
1753 int bar;
1754
1755 if (dev->cmb_size)
1756 return;
1757
1758 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1759 if (!dev->cmbsz)
1760 return;
1761 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1762
1763 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1764 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1765 bar = NVME_CMB_BIR(dev->cmbloc);
1766 bar_size = pci_resource_len(pdev, bar);
1767
1768 if (offset > bar_size)
1769 return;
1770
1771 /*
1772 * Controllers may support a CMB size larger than their BAR,
1773 * for example, due to being behind a bridge. Reduce the CMB to
1774 * the reported size of the BAR
1775 */
1776 if (size > bar_size - offset)
1777 size = bar_size - offset;
1778
1779 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1780 dev_warn(dev->ctrl.device,
1781 "failed to register the CMB\n");
1782 return;
1783 }
1784
1785 dev->cmb_size = size;
1786 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1787
1788 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1789 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1790 pci_p2pmem_publish(pdev, true);
1791
1792 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1793 &dev_attr_cmb.attr, NULL))
1794 dev_warn(dev->ctrl.device,
1795 "failed to add sysfs attribute for CMB\n");
1796 }
1797
1798 static inline void nvme_release_cmb(struct nvme_dev *dev)
1799 {
1800 if (dev->cmb_size) {
1801 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1802 &dev_attr_cmb.attr, NULL);
1803 dev->cmb_size = 0;
1804 }
1805 }
1806
1807 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1808 {
1809 u64 dma_addr = dev->host_mem_descs_dma;
1810 struct nvme_command c;
1811 int ret;
1812
1813 memset(&c, 0, sizeof(c));
1814 c.features.opcode = nvme_admin_set_features;
1815 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1816 c.features.dword11 = cpu_to_le32(bits);
1817 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1818 ilog2(dev->ctrl.page_size));
1819 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1820 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1821 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1822
1823 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1824 if (ret) {
1825 dev_warn(dev->ctrl.device,
1826 "failed to set host mem (err %d, flags %#x).\n",
1827 ret, bits);
1828 }
1829 return ret;
1830 }
1831
1832 static void nvme_free_host_mem(struct nvme_dev *dev)
1833 {
1834 int i;
1835
1836 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1837 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1838 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1839
1840 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1841 le64_to_cpu(desc->addr),
1842 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1843 }
1844
1845 kfree(dev->host_mem_desc_bufs);
1846 dev->host_mem_desc_bufs = NULL;
1847 dma_free_coherent(dev->dev,
1848 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1849 dev->host_mem_descs, dev->host_mem_descs_dma);
1850 dev->host_mem_descs = NULL;
1851 dev->nr_host_mem_descs = 0;
1852 }
1853
1854 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1855 u32 chunk_size)
1856 {
1857 struct nvme_host_mem_buf_desc *descs;
1858 u32 max_entries, len;
1859 dma_addr_t descs_dma;
1860 int i = 0;
1861 void **bufs;
1862 u64 size, tmp;
1863
1864 tmp = (preferred + chunk_size - 1);
1865 do_div(tmp, chunk_size);
1866 max_entries = tmp;
1867
1868 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1869 max_entries = dev->ctrl.hmmaxd;
1870
1871 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1872 &descs_dma, GFP_KERNEL);
1873 if (!descs)
1874 goto out;
1875
1876 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1877 if (!bufs)
1878 goto out_free_descs;
1879
1880 for (size = 0; size < preferred && i < max_entries; size += len) {
1881 dma_addr_t dma_addr;
1882
1883 len = min_t(u64, chunk_size, preferred - size);
1884 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1885 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1886 if (!bufs[i])
1887 break;
1888
1889 descs[i].addr = cpu_to_le64(dma_addr);
1890 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1891 i++;
1892 }
1893
1894 if (!size)
1895 goto out_free_bufs;
1896
1897 dev->nr_host_mem_descs = i;
1898 dev->host_mem_size = size;
1899 dev->host_mem_descs = descs;
1900 dev->host_mem_descs_dma = descs_dma;
1901 dev->host_mem_desc_bufs = bufs;
1902 return 0;
1903
1904 out_free_bufs:
1905 while (--i >= 0) {
1906 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1907
1908 dma_free_attrs(dev->dev, size, bufs[i],
1909 le64_to_cpu(descs[i].addr),
1910 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1911 }
1912
1913 kfree(bufs);
1914 out_free_descs:
1915 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1916 descs_dma);
1917 out:
1918 dev->host_mem_descs = NULL;
1919 return -ENOMEM;
1920 }
1921
1922 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1923 {
1924 u32 chunk_size;
1925
1926 /* start big and work our way down */
1927 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1928 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1929 chunk_size /= 2) {
1930 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1931 if (!min || dev->host_mem_size >= min)
1932 return 0;
1933 nvme_free_host_mem(dev);
1934 }
1935 }
1936
1937 return -ENOMEM;
1938 }
1939
1940 static int nvme_setup_host_mem(struct nvme_dev *dev)
1941 {
1942 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1943 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1944 u64 min = (u64)dev->ctrl.hmmin * 4096;
1945 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1946 int ret;
1947
1948 preferred = min(preferred, max);
1949 if (min > max) {
1950 dev_warn(dev->ctrl.device,
1951 "min host memory (%lld MiB) above limit (%d MiB).\n",
1952 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1953 nvme_free_host_mem(dev);
1954 return 0;
1955 }
1956
1957 /*
1958 * If we already have a buffer allocated check if we can reuse it.
1959 */
1960 if (dev->host_mem_descs) {
1961 if (dev->host_mem_size >= min)
1962 enable_bits |= NVME_HOST_MEM_RETURN;
1963 else
1964 nvme_free_host_mem(dev);
1965 }
1966
1967 if (!dev->host_mem_descs) {
1968 if (nvme_alloc_host_mem(dev, min, preferred)) {
1969 dev_warn(dev->ctrl.device,
1970 "failed to allocate host memory buffer.\n");
1971 return 0; /* controller must work without HMB */
1972 }
1973
1974 dev_info(dev->ctrl.device,
1975 "allocated %lld MiB host memory buffer.\n",
1976 dev->host_mem_size >> ilog2(SZ_1M));
1977 }
1978
1979 ret = nvme_set_host_mem(dev, enable_bits);
1980 if (ret)
1981 nvme_free_host_mem(dev);
1982 return ret;
1983 }
1984
1985 /*
1986 * nirqs is the number of interrupts available for write and read
1987 * queues. The core already reserved an interrupt for the admin queue.
1988 */
1989 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
1990 {
1991 struct nvme_dev *dev = affd->priv;
1992 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
1993
1994 /*
1995 * If there is no interupt available for queues, ensure that
1996 * the default queue is set to 1. The affinity set size is
1997 * also set to one, but the irq core ignores it for this case.
1998 *
1999 * If only one interrupt is available or 'write_queue' == 0, combine
2000 * write and read queues.
2001 *
2002 * If 'write_queues' > 0, ensure it leaves room for at least one read
2003 * queue.
2004 */
2005 if (!nrirqs) {
2006 nrirqs = 1;
2007 nr_read_queues = 0;
2008 } else if (nrirqs == 1 || !nr_write_queues) {
2009 nr_read_queues = 0;
2010 } else if (nr_write_queues >= nrirqs) {
2011 nr_read_queues = 1;
2012 } else {
2013 nr_read_queues = nrirqs - nr_write_queues;
2014 }
2015
2016 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2017 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2018 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2019 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2020 affd->nr_sets = nr_read_queues ? 2 : 1;
2021 }
2022
2023 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2024 {
2025 struct pci_dev *pdev = to_pci_dev(dev->dev);
2026 struct irq_affinity affd = {
2027 .pre_vectors = 1,
2028 .calc_sets = nvme_calc_irq_sets,
2029 .priv = dev,
2030 };
2031 unsigned int irq_queues, this_p_queues;
2032
2033 /*
2034 * Poll queues don't need interrupts, but we need at least one IO
2035 * queue left over for non-polled IO.
2036 */
2037 this_p_queues = dev->nr_poll_queues;
2038 if (this_p_queues >= nr_io_queues) {
2039 this_p_queues = nr_io_queues - 1;
2040 irq_queues = 1;
2041 } else {
2042 irq_queues = nr_io_queues - this_p_queues + 1;
2043 }
2044 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2045
2046 /* Initialize for the single interrupt case */
2047 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2048 dev->io_queues[HCTX_TYPE_READ] = 0;
2049
2050 /*
2051 * Some Apple controllers require all queues to use the
2052 * first vector.
2053 */
2054 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2055 irq_queues = 1;
2056
2057 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2058 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2059 }
2060
2061 static void nvme_disable_io_queues(struct nvme_dev *dev)
2062 {
2063 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2064 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2065 }
2066
2067 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2068 {
2069 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2070 }
2071
2072 static int nvme_setup_io_queues(struct nvme_dev *dev)
2073 {
2074 struct nvme_queue *adminq = &dev->queues[0];
2075 struct pci_dev *pdev = to_pci_dev(dev->dev);
2076 unsigned int nr_io_queues;
2077 unsigned long size;
2078 int result;
2079
2080 /*
2081 * Sample the module parameters once at reset time so that we have
2082 * stable values to work with.
2083 */
2084 dev->nr_write_queues = write_queues;
2085 dev->nr_poll_queues = poll_queues;
2086
2087 /*
2088 * If tags are shared with admin queue (Apple bug), then
2089 * make sure we only use one IO queue.
2090 */
2091 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2092 nr_io_queues = 1;
2093 else
2094 nr_io_queues = min(nvme_max_io_queues(dev),
2095 dev->nr_allocated_queues - 1);
2096
2097 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2098 if (result < 0)
2099 return result;
2100
2101 if (nr_io_queues == 0)
2102 return 0;
2103
2104 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2105
2106 if (dev->cmb_use_sqes) {
2107 result = nvme_cmb_qdepth(dev, nr_io_queues,
2108 sizeof(struct nvme_command));
2109 if (result > 0)
2110 dev->q_depth = result;
2111 else
2112 dev->cmb_use_sqes = false;
2113 }
2114
2115 do {
2116 size = db_bar_size(dev, nr_io_queues);
2117 result = nvme_remap_bar(dev, size);
2118 if (!result)
2119 break;
2120 if (!--nr_io_queues)
2121 return -ENOMEM;
2122 } while (1);
2123 adminq->q_db = dev->dbs;
2124
2125 retry:
2126 /* Deregister the admin queue's interrupt */
2127 pci_free_irq(pdev, 0, adminq);
2128
2129 /*
2130 * If we enable msix early due to not intx, disable it again before
2131 * setting up the full range we need.
2132 */
2133 pci_free_irq_vectors(pdev);
2134
2135 result = nvme_setup_irqs(dev, nr_io_queues);
2136 if (result <= 0)
2137 return -EIO;
2138
2139 dev->num_vecs = result;
2140 result = max(result - 1, 1);
2141 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2142
2143 /*
2144 * Should investigate if there's a performance win from allocating
2145 * more queues than interrupt vectors; it might allow the submission
2146 * path to scale better, even if the receive path is limited by the
2147 * number of interrupts.
2148 */
2149 result = queue_request_irq(adminq);
2150 if (result)
2151 return result;
2152 set_bit(NVMEQ_ENABLED, &adminq->flags);
2153
2154 result = nvme_create_io_queues(dev);
2155 if (result || dev->online_queues < 2)
2156 return result;
2157
2158 if (dev->online_queues - 1 < dev->max_qid) {
2159 nr_io_queues = dev->online_queues - 1;
2160 nvme_disable_io_queues(dev);
2161 nvme_suspend_io_queues(dev);
2162 goto retry;
2163 }
2164 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2165 dev->io_queues[HCTX_TYPE_DEFAULT],
2166 dev->io_queues[HCTX_TYPE_READ],
2167 dev->io_queues[HCTX_TYPE_POLL]);
2168 return 0;
2169 }
2170
2171 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2172 {
2173 struct nvme_queue *nvmeq = req->end_io_data;
2174
2175 blk_mq_free_request(req);
2176 complete(&nvmeq->delete_done);
2177 }
2178
2179 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2180 {
2181 struct nvme_queue *nvmeq = req->end_io_data;
2182
2183 if (error)
2184 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2185
2186 nvme_del_queue_end(req, error);
2187 }
2188
2189 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2190 {
2191 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2192 struct request *req;
2193 struct nvme_command cmd;
2194
2195 memset(&cmd, 0, sizeof(cmd));
2196 cmd.delete_queue.opcode = opcode;
2197 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2198
2199 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2200 if (IS_ERR(req))
2201 return PTR_ERR(req);
2202
2203 req->timeout = ADMIN_TIMEOUT;
2204 req->end_io_data = nvmeq;
2205
2206 init_completion(&nvmeq->delete_done);
2207 blk_execute_rq_nowait(q, NULL, req, false,
2208 opcode == nvme_admin_delete_cq ?
2209 nvme_del_cq_end : nvme_del_queue_end);
2210 return 0;
2211 }
2212
2213 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2214 {
2215 int nr_queues = dev->online_queues - 1, sent = 0;
2216 unsigned long timeout;
2217
2218 retry:
2219 timeout = ADMIN_TIMEOUT;
2220 while (nr_queues > 0) {
2221 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2222 break;
2223 nr_queues--;
2224 sent++;
2225 }
2226 while (sent) {
2227 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2228
2229 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2230 timeout);
2231 if (timeout == 0)
2232 return false;
2233
2234 sent--;
2235 if (nr_queues)
2236 goto retry;
2237 }
2238 return true;
2239 }
2240
2241 static void nvme_dev_add(struct nvme_dev *dev)
2242 {
2243 int ret;
2244
2245 if (!dev->ctrl.tagset) {
2246 dev->tagset.ops = &nvme_mq_ops;
2247 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2248 dev->tagset.nr_maps = 2; /* default + read */
2249 if (dev->io_queues[HCTX_TYPE_POLL])
2250 dev->tagset.nr_maps++;
2251 dev->tagset.timeout = NVME_IO_TIMEOUT;
2252 dev->tagset.numa_node = dev_to_node(dev->dev);
2253 dev->tagset.queue_depth =
2254 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2255 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2256 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2257 dev->tagset.driver_data = dev;
2258
2259 /*
2260 * Some Apple controllers requires tags to be unique
2261 * across admin and IO queue, so reserve the first 32
2262 * tags of the IO queue.
2263 */
2264 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2265 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2266
2267 ret = blk_mq_alloc_tag_set(&dev->tagset);
2268 if (ret) {
2269 dev_warn(dev->ctrl.device,
2270 "IO queues tagset allocation failed %d\n", ret);
2271 return;
2272 }
2273 dev->ctrl.tagset = &dev->tagset;
2274 } else {
2275 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2276
2277 /* Free previously allocated queues that are no longer usable */
2278 nvme_free_queues(dev, dev->online_queues);
2279 }
2280
2281 nvme_dbbuf_set(dev);
2282 }
2283
2284 static int nvme_pci_enable(struct nvme_dev *dev)
2285 {
2286 int result = -ENOMEM;
2287 struct pci_dev *pdev = to_pci_dev(dev->dev);
2288
2289 if (pci_enable_device_mem(pdev))
2290 return result;
2291
2292 pci_set_master(pdev);
2293
2294 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2295 goto disable;
2296
2297 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2298 result = -ENODEV;
2299 goto disable;
2300 }
2301
2302 /*
2303 * Some devices and/or platforms don't advertise or work with INTx
2304 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2305 * adjust this later.
2306 */
2307 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2308 if (result < 0)
2309 return result;
2310
2311 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2312
2313 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2314 io_queue_depth);
2315 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2316 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2317 dev->dbs = dev->bar + 4096;
2318
2319 /*
2320 * Some Apple controllers require a non-standard SQE size.
2321 * Interestingly they also seem to ignore the CC:IOSQES register
2322 * so we don't bother updating it here.
2323 */
2324 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2325 dev->io_sqes = 7;
2326 else
2327 dev->io_sqes = NVME_NVM_IOSQES;
2328
2329 /*
2330 * Temporary fix for the Apple controller found in the MacBook8,1 and
2331 * some MacBook7,1 to avoid controller resets and data loss.
2332 */
2333 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2334 dev->q_depth = 2;
2335 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2336 "set queue depth=%u to work around controller resets\n",
2337 dev->q_depth);
2338 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2339 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2340 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2341 dev->q_depth = 64;
2342 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2343 "set queue depth=%u\n", dev->q_depth);
2344 }
2345
2346 /*
2347 * Controllers with the shared tags quirk need the IO queue to be
2348 * big enough so that we get 32 tags for the admin queue
2349 */
2350 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2351 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2352 dev->q_depth = NVME_AQ_DEPTH + 2;
2353 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2354 dev->q_depth);
2355 }
2356
2357
2358 nvme_map_cmb(dev);
2359
2360 pci_enable_pcie_error_reporting(pdev);
2361 pci_save_state(pdev);
2362 return 0;
2363
2364 disable:
2365 pci_disable_device(pdev);
2366 return result;
2367 }
2368
2369 static void nvme_dev_unmap(struct nvme_dev *dev)
2370 {
2371 if (dev->bar)
2372 iounmap(dev->bar);
2373 pci_release_mem_regions(to_pci_dev(dev->dev));
2374 }
2375
2376 static void nvme_pci_disable(struct nvme_dev *dev)
2377 {
2378 struct pci_dev *pdev = to_pci_dev(dev->dev);
2379
2380 pci_free_irq_vectors(pdev);
2381
2382 if (pci_is_enabled(pdev)) {
2383 pci_disable_pcie_error_reporting(pdev);
2384 pci_disable_device(pdev);
2385 }
2386 }
2387
2388 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2389 {
2390 bool dead = true, freeze = false;
2391 struct pci_dev *pdev = to_pci_dev(dev->dev);
2392
2393 mutex_lock(&dev->shutdown_lock);
2394 if (pci_is_enabled(pdev)) {
2395 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2396
2397 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2398 dev->ctrl.state == NVME_CTRL_RESETTING) {
2399 freeze = true;
2400 nvme_start_freeze(&dev->ctrl);
2401 }
2402 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2403 pdev->error_state != pci_channel_io_normal);
2404 }
2405
2406 /*
2407 * Give the controller a chance to complete all entered requests if
2408 * doing a safe shutdown.
2409 */
2410 if (!dead && shutdown && freeze)
2411 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2412
2413 nvme_stop_queues(&dev->ctrl);
2414
2415 if (!dead && dev->ctrl.queue_count > 0) {
2416 nvme_disable_io_queues(dev);
2417 nvme_disable_admin_queue(dev, shutdown);
2418 }
2419 nvme_suspend_io_queues(dev);
2420 nvme_suspend_queue(&dev->queues[0]);
2421 nvme_pci_disable(dev);
2422 nvme_reap_pending_cqes(dev);
2423
2424 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2425 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2426 blk_mq_tagset_wait_completed_request(&dev->tagset);
2427 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2428
2429 /*
2430 * The driver will not be starting up queues again if shutting down so
2431 * must flush all entered requests to their failed completion to avoid
2432 * deadlocking blk-mq hot-cpu notifier.
2433 */
2434 if (shutdown) {
2435 nvme_start_queues(&dev->ctrl);
2436 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2437 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2438 }
2439 mutex_unlock(&dev->shutdown_lock);
2440 }
2441
2442 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2443 {
2444 if (!nvme_wait_reset(&dev->ctrl))
2445 return -EBUSY;
2446 nvme_dev_disable(dev, shutdown);
2447 return 0;
2448 }
2449
2450 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2451 {
2452 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2453 PAGE_SIZE, PAGE_SIZE, 0);
2454 if (!dev->prp_page_pool)
2455 return -ENOMEM;
2456
2457 /* Optimisation for I/Os between 4k and 128k */
2458 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2459 256, 256, 0);
2460 if (!dev->prp_small_pool) {
2461 dma_pool_destroy(dev->prp_page_pool);
2462 return -ENOMEM;
2463 }
2464 return 0;
2465 }
2466
2467 static void nvme_release_prp_pools(struct nvme_dev *dev)
2468 {
2469 dma_pool_destroy(dev->prp_page_pool);
2470 dma_pool_destroy(dev->prp_small_pool);
2471 }
2472
2473 static void nvme_free_tagset(struct nvme_dev *dev)
2474 {
2475 if (dev->tagset.tags)
2476 blk_mq_free_tag_set(&dev->tagset);
2477 dev->ctrl.tagset = NULL;
2478 }
2479
2480 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2481 {
2482 struct nvme_dev *dev = to_nvme_dev(ctrl);
2483
2484 nvme_dbbuf_dma_free(dev);
2485 nvme_free_tagset(dev);
2486 if (dev->ctrl.admin_q)
2487 blk_put_queue(dev->ctrl.admin_q);
2488 free_opal_dev(dev->ctrl.opal_dev);
2489 mempool_destroy(dev->iod_mempool);
2490 put_device(dev->dev);
2491 kfree(dev->queues);
2492 kfree(dev);
2493 }
2494
2495 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2496 {
2497 /*
2498 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2499 * may be holding this pci_dev's device lock.
2500 */
2501 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2502 nvme_get_ctrl(&dev->ctrl);
2503 nvme_dev_disable(dev, false);
2504 nvme_kill_queues(&dev->ctrl);
2505 if (!queue_work(nvme_wq, &dev->remove_work))
2506 nvme_put_ctrl(&dev->ctrl);
2507 }
2508
2509 static void nvme_reset_work(struct work_struct *work)
2510 {
2511 struct nvme_dev *dev =
2512 container_of(work, struct nvme_dev, ctrl.reset_work);
2513 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2514 int result;
2515
2516 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2517 result = -ENODEV;
2518 goto out;
2519 }
2520
2521 /*
2522 * If we're called to reset a live controller first shut it down before
2523 * moving on.
2524 */
2525 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2526 nvme_dev_disable(dev, false);
2527 nvme_sync_queues(&dev->ctrl);
2528
2529 mutex_lock(&dev->shutdown_lock);
2530 result = nvme_pci_enable(dev);
2531 if (result)
2532 goto out_unlock;
2533
2534 result = nvme_pci_configure_admin_queue(dev);
2535 if (result)
2536 goto out_unlock;
2537
2538 result = nvme_alloc_admin_tags(dev);
2539 if (result)
2540 goto out_unlock;
2541
2542 /*
2543 * Limit the max command size to prevent iod->sg allocations going
2544 * over a single page.
2545 */
2546 dev->ctrl.max_hw_sectors = min_t(u32,
2547 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2548 dev->ctrl.max_segments = NVME_MAX_SEGS;
2549
2550 /*
2551 * Don't limit the IOMMU merged segment size.
2552 */
2553 dma_set_max_seg_size(dev->dev, 0xffffffff);
2554
2555 mutex_unlock(&dev->shutdown_lock);
2556
2557 /*
2558 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2559 * initializing procedure here.
2560 */
2561 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2562 dev_warn(dev->ctrl.device,
2563 "failed to mark controller CONNECTING\n");
2564 result = -EBUSY;
2565 goto out;
2566 }
2567
2568 /*
2569 * We do not support an SGL for metadata (yet), so we are limited to a
2570 * single integrity segment for the separate metadata pointer.
2571 */
2572 dev->ctrl.max_integrity_segments = 1;
2573
2574 result = nvme_init_identify(&dev->ctrl);
2575 if (result)
2576 goto out;
2577
2578 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2579 if (!dev->ctrl.opal_dev)
2580 dev->ctrl.opal_dev =
2581 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2582 else if (was_suspend)
2583 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2584 } else {
2585 free_opal_dev(dev->ctrl.opal_dev);
2586 dev->ctrl.opal_dev = NULL;
2587 }
2588
2589 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2590 result = nvme_dbbuf_dma_alloc(dev);
2591 if (result)
2592 dev_warn(dev->dev,
2593 "unable to allocate dma for dbbuf\n");
2594 }
2595
2596 if (dev->ctrl.hmpre) {
2597 result = nvme_setup_host_mem(dev);
2598 if (result < 0)
2599 goto out;
2600 }
2601
2602 result = nvme_setup_io_queues(dev);
2603 if (result)
2604 goto out;
2605
2606 /*
2607 * Keep the controller around but remove all namespaces if we don't have
2608 * any working I/O queue.
2609 */
2610 if (dev->online_queues < 2) {
2611 dev_warn(dev->ctrl.device, "IO queues not created\n");
2612 nvme_kill_queues(&dev->ctrl);
2613 nvme_remove_namespaces(&dev->ctrl);
2614 nvme_free_tagset(dev);
2615 } else {
2616 nvme_start_queues(&dev->ctrl);
2617 nvme_wait_freeze(&dev->ctrl);
2618 nvme_dev_add(dev);
2619 nvme_unfreeze(&dev->ctrl);
2620 }
2621
2622 /*
2623 * If only admin queue live, keep it to do further investigation or
2624 * recovery.
2625 */
2626 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2627 dev_warn(dev->ctrl.device,
2628 "failed to mark controller live state\n");
2629 result = -ENODEV;
2630 goto out;
2631 }
2632
2633 nvme_start_ctrl(&dev->ctrl);
2634 return;
2635
2636 out_unlock:
2637 mutex_unlock(&dev->shutdown_lock);
2638 out:
2639 if (result)
2640 dev_warn(dev->ctrl.device,
2641 "Removing after probe failure status: %d\n", result);
2642 nvme_remove_dead_ctrl(dev);
2643 }
2644
2645 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2646 {
2647 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2648 struct pci_dev *pdev = to_pci_dev(dev->dev);
2649
2650 if (pci_get_drvdata(pdev))
2651 device_release_driver(&pdev->dev);
2652 nvme_put_ctrl(&dev->ctrl);
2653 }
2654
2655 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2656 {
2657 *val = readl(to_nvme_dev(ctrl)->bar + off);
2658 return 0;
2659 }
2660
2661 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2662 {
2663 writel(val, to_nvme_dev(ctrl)->bar + off);
2664 return 0;
2665 }
2666
2667 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2668 {
2669 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2670 return 0;
2671 }
2672
2673 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2674 {
2675 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2676
2677 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2678 }
2679
2680 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2681 .name = "pcie",
2682 .module = THIS_MODULE,
2683 .flags = NVME_F_METADATA_SUPPORTED |
2684 NVME_F_PCI_P2PDMA,
2685 .reg_read32 = nvme_pci_reg_read32,
2686 .reg_write32 = nvme_pci_reg_write32,
2687 .reg_read64 = nvme_pci_reg_read64,
2688 .free_ctrl = nvme_pci_free_ctrl,
2689 .submit_async_event = nvme_pci_submit_async_event,
2690 .get_address = nvme_pci_get_address,
2691 };
2692
2693 static int nvme_dev_map(struct nvme_dev *dev)
2694 {
2695 struct pci_dev *pdev = to_pci_dev(dev->dev);
2696
2697 if (pci_request_mem_regions(pdev, "nvme"))
2698 return -ENODEV;
2699
2700 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2701 goto release;
2702
2703 return 0;
2704 release:
2705 pci_release_mem_regions(pdev);
2706 return -ENODEV;
2707 }
2708
2709 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2710 {
2711 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2712 /*
2713 * Several Samsung devices seem to drop off the PCIe bus
2714 * randomly when APST is on and uses the deepest sleep state.
2715 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2716 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2717 * 950 PRO 256GB", but it seems to be restricted to two Dell
2718 * laptops.
2719 */
2720 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2721 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2722 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2723 return NVME_QUIRK_NO_DEEPEST_PS;
2724 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2725 /*
2726 * Samsung SSD 960 EVO drops off the PCIe bus after system
2727 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2728 * within few minutes after bootup on a Coffee Lake board -
2729 * ASUS PRIME Z370-A
2730 */
2731 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2732 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2733 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2734 return NVME_QUIRK_NO_APST;
2735 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2736 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2737 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2738 /*
2739 * Forcing to use host managed nvme power settings for
2740 * lowest idle power with quick resume latency on
2741 * Samsung and Toshiba SSDs based on suspend behavior
2742 * on Coffee Lake board for LENOVO C640
2743 */
2744 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2745 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2746 return NVME_QUIRK_SIMPLE_SUSPEND;
2747 }
2748
2749 return 0;
2750 }
2751
2752 static void nvme_async_probe(void *data, async_cookie_t cookie)
2753 {
2754 struct nvme_dev *dev = data;
2755
2756 flush_work(&dev->ctrl.reset_work);
2757 flush_work(&dev->ctrl.scan_work);
2758 nvme_put_ctrl(&dev->ctrl);
2759 }
2760
2761 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2762 {
2763 int node, result = -ENOMEM;
2764 struct nvme_dev *dev;
2765 unsigned long quirks = id->driver_data;
2766 size_t alloc_size;
2767
2768 node = dev_to_node(&pdev->dev);
2769 if (node == NUMA_NO_NODE)
2770 set_dev_node(&pdev->dev, first_memory_node);
2771
2772 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2773 if (!dev)
2774 return -ENOMEM;
2775
2776 dev->nr_write_queues = write_queues;
2777 dev->nr_poll_queues = poll_queues;
2778 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2779 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2780 sizeof(struct nvme_queue), GFP_KERNEL, node);
2781 if (!dev->queues)
2782 goto free;
2783
2784 dev->dev = get_device(&pdev->dev);
2785 pci_set_drvdata(pdev, dev);
2786
2787 result = nvme_dev_map(dev);
2788 if (result)
2789 goto put_pci;
2790
2791 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2792 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2793 mutex_init(&dev->shutdown_lock);
2794
2795 result = nvme_setup_prp_pools(dev);
2796 if (result)
2797 goto unmap;
2798
2799 quirks |= check_vendor_combination_bug(pdev);
2800
2801 /*
2802 * Double check that our mempool alloc size will cover the biggest
2803 * command we support.
2804 */
2805 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2806 NVME_MAX_SEGS, true);
2807 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2808
2809 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2810 mempool_kfree,
2811 (void *) alloc_size,
2812 GFP_KERNEL, node);
2813 if (!dev->iod_mempool) {
2814 result = -ENOMEM;
2815 goto release_pools;
2816 }
2817
2818 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2819 quirks);
2820 if (result)
2821 goto release_mempool;
2822
2823 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2824
2825 nvme_reset_ctrl(&dev->ctrl);
2826 async_schedule(nvme_async_probe, dev);
2827
2828 return 0;
2829
2830 release_mempool:
2831 mempool_destroy(dev->iod_mempool);
2832 release_pools:
2833 nvme_release_prp_pools(dev);
2834 unmap:
2835 nvme_dev_unmap(dev);
2836 put_pci:
2837 put_device(dev->dev);
2838 free:
2839 kfree(dev->queues);
2840 kfree(dev);
2841 return result;
2842 }
2843
2844 static void nvme_reset_prepare(struct pci_dev *pdev)
2845 {
2846 struct nvme_dev *dev = pci_get_drvdata(pdev);
2847
2848 /*
2849 * We don't need to check the return value from waiting for the reset
2850 * state as pci_dev device lock is held, making it impossible to race
2851 * with ->remove().
2852 */
2853 nvme_disable_prepare_reset(dev, false);
2854 nvme_sync_queues(&dev->ctrl);
2855 }
2856
2857 static void nvme_reset_done(struct pci_dev *pdev)
2858 {
2859 struct nvme_dev *dev = pci_get_drvdata(pdev);
2860
2861 if (!nvme_try_sched_reset(&dev->ctrl))
2862 flush_work(&dev->ctrl.reset_work);
2863 }
2864
2865 static void nvme_shutdown(struct pci_dev *pdev)
2866 {
2867 struct nvme_dev *dev = pci_get_drvdata(pdev);
2868 nvme_disable_prepare_reset(dev, true);
2869 }
2870
2871 /*
2872 * The driver's remove may be called on a device in a partially initialized
2873 * state. This function must not have any dependencies on the device state in
2874 * order to proceed.
2875 */
2876 static void nvme_remove(struct pci_dev *pdev)
2877 {
2878 struct nvme_dev *dev = pci_get_drvdata(pdev);
2879
2880 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2881 pci_set_drvdata(pdev, NULL);
2882
2883 if (!pci_device_is_present(pdev)) {
2884 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2885 nvme_dev_disable(dev, true);
2886 nvme_dev_remove_admin(dev);
2887 }
2888
2889 flush_work(&dev->ctrl.reset_work);
2890 nvme_stop_ctrl(&dev->ctrl);
2891 nvme_remove_namespaces(&dev->ctrl);
2892 nvme_dev_disable(dev, true);
2893 nvme_release_cmb(dev);
2894 nvme_free_host_mem(dev);
2895 nvme_dev_remove_admin(dev);
2896 nvme_free_queues(dev, 0);
2897 nvme_release_prp_pools(dev);
2898 nvme_dev_unmap(dev);
2899 nvme_uninit_ctrl(&dev->ctrl);
2900 }
2901
2902 #ifdef CONFIG_PM_SLEEP
2903 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2904 {
2905 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2906 }
2907
2908 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2909 {
2910 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2911 }
2912
2913 static int nvme_resume(struct device *dev)
2914 {
2915 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2916 struct nvme_ctrl *ctrl = &ndev->ctrl;
2917
2918 if (ndev->last_ps == U32_MAX ||
2919 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2920 return nvme_try_sched_reset(&ndev->ctrl);
2921 return 0;
2922 }
2923
2924 static int nvme_suspend(struct device *dev)
2925 {
2926 struct pci_dev *pdev = to_pci_dev(dev);
2927 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2928 struct nvme_ctrl *ctrl = &ndev->ctrl;
2929 int ret = -EBUSY;
2930
2931 ndev->last_ps = U32_MAX;
2932
2933 /*
2934 * The platform does not remove power for a kernel managed suspend so
2935 * use host managed nvme power settings for lowest idle power if
2936 * possible. This should have quicker resume latency than a full device
2937 * shutdown. But if the firmware is involved after the suspend or the
2938 * device does not support any non-default power states, shut down the
2939 * device fully.
2940 *
2941 * If ASPM is not enabled for the device, shut down the device and allow
2942 * the PCI bus layer to put it into D3 in order to take the PCIe link
2943 * down, so as to allow the platform to achieve its minimum low-power
2944 * state (which may not be possible if the link is up).
2945 */
2946 if (pm_suspend_via_firmware() || !ctrl->npss ||
2947 !pcie_aspm_enabled(pdev) ||
2948 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2949 return nvme_disable_prepare_reset(ndev, true);
2950
2951 nvme_start_freeze(ctrl);
2952 nvme_wait_freeze(ctrl);
2953 nvme_sync_queues(ctrl);
2954
2955 if (ctrl->state != NVME_CTRL_LIVE)
2956 goto unfreeze;
2957
2958 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2959 if (ret < 0)
2960 goto unfreeze;
2961
2962 /*
2963 * A saved state prevents pci pm from generically controlling the
2964 * device's power. If we're using protocol specific settings, we don't
2965 * want pci interfering.
2966 */
2967 pci_save_state(pdev);
2968
2969 ret = nvme_set_power_state(ctrl, ctrl->npss);
2970 if (ret < 0)
2971 goto unfreeze;
2972
2973 if (ret) {
2974 /* discard the saved state */
2975 pci_load_saved_state(pdev, NULL);
2976
2977 /*
2978 * Clearing npss forces a controller reset on resume. The
2979 * correct value will be rediscovered then.
2980 */
2981 ret = nvme_disable_prepare_reset(ndev, true);
2982 ctrl->npss = 0;
2983 }
2984 unfreeze:
2985 nvme_unfreeze(ctrl);
2986 return ret;
2987 }
2988
2989 static int nvme_simple_suspend(struct device *dev)
2990 {
2991 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2992 return nvme_disable_prepare_reset(ndev, true);
2993 }
2994
2995 static int nvme_simple_resume(struct device *dev)
2996 {
2997 struct pci_dev *pdev = to_pci_dev(dev);
2998 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2999
3000 return nvme_try_sched_reset(&ndev->ctrl);
3001 }
3002
3003 static const struct dev_pm_ops nvme_dev_pm_ops = {
3004 .suspend = nvme_suspend,
3005 .resume = nvme_resume,
3006 .freeze = nvme_simple_suspend,
3007 .thaw = nvme_simple_resume,
3008 .poweroff = nvme_simple_suspend,
3009 .restore = nvme_simple_resume,
3010 };
3011 #endif /* CONFIG_PM_SLEEP */
3012
3013 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3014 pci_channel_state_t state)
3015 {
3016 struct nvme_dev *dev = pci_get_drvdata(pdev);
3017
3018 /*
3019 * A frozen channel requires a reset. When detected, this method will
3020 * shutdown the controller to quiesce. The controller will be restarted
3021 * after the slot reset through driver's slot_reset callback.
3022 */
3023 switch (state) {
3024 case pci_channel_io_normal:
3025 return PCI_ERS_RESULT_CAN_RECOVER;
3026 case pci_channel_io_frozen:
3027 dev_warn(dev->ctrl.device,
3028 "frozen state error detected, reset controller\n");
3029 nvme_dev_disable(dev, false);
3030 return PCI_ERS_RESULT_NEED_RESET;
3031 case pci_channel_io_perm_failure:
3032 dev_warn(dev->ctrl.device,
3033 "failure state error detected, request disconnect\n");
3034 return PCI_ERS_RESULT_DISCONNECT;
3035 }
3036 return PCI_ERS_RESULT_NEED_RESET;
3037 }
3038
3039 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3040 {
3041 struct nvme_dev *dev = pci_get_drvdata(pdev);
3042
3043 dev_info(dev->ctrl.device, "restart after slot reset\n");
3044 pci_restore_state(pdev);
3045 nvme_reset_ctrl(&dev->ctrl);
3046 return PCI_ERS_RESULT_RECOVERED;
3047 }
3048
3049 static void nvme_error_resume(struct pci_dev *pdev)
3050 {
3051 struct nvme_dev *dev = pci_get_drvdata(pdev);
3052
3053 flush_work(&dev->ctrl.reset_work);
3054 }
3055
3056 static const struct pci_error_handlers nvme_err_handler = {
3057 .error_detected = nvme_error_detected,
3058 .slot_reset = nvme_slot_reset,
3059 .resume = nvme_error_resume,
3060 .reset_prepare = nvme_reset_prepare,
3061 .reset_done = nvme_reset_done,
3062 };
3063
3064 static const struct pci_device_id nvme_id_table[] = {
3065 { PCI_VDEVICE(INTEL, 0x0953),
3066 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3067 NVME_QUIRK_DEALLOCATE_ZEROES, },
3068 { PCI_VDEVICE(INTEL, 0x0a53),
3069 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3070 NVME_QUIRK_DEALLOCATE_ZEROES, },
3071 { PCI_VDEVICE(INTEL, 0x0a54),
3072 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3073 NVME_QUIRK_DEALLOCATE_ZEROES, },
3074 { PCI_VDEVICE(INTEL, 0x0a55),
3075 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3076 NVME_QUIRK_DEALLOCATE_ZEROES, },
3077 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3078 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3079 NVME_QUIRK_MEDIUM_PRIO_SQ |
3080 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
3081 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3082 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3083 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3084 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3085 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3086 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3087 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3088 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3089 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3090 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3091 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3092 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3093 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3094 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3095 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3096 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3097 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3098 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3099 .driver_data = NVME_QUIRK_LIGHTNVM, },
3100 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3101 .driver_data = NVME_QUIRK_LIGHTNVM, },
3102 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3103 .driver_data = NVME_QUIRK_LIGHTNVM, },
3104 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3105 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3106 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3107 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3108 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3109 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3110 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3111 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3112 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3113 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3114 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3115 NVME_QUIRK_128_BYTES_SQES |
3116 NVME_QUIRK_SHARED_TAGS },
3117 { 0, }
3118 };
3119 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3120
3121 static struct pci_driver nvme_driver = {
3122 .name = "nvme",
3123 .id_table = nvme_id_table,
3124 .probe = nvme_probe,
3125 .remove = nvme_remove,
3126 .shutdown = nvme_shutdown,
3127 #ifdef CONFIG_PM_SLEEP
3128 .driver = {
3129 .pm = &nvme_dev_pm_ops,
3130 },
3131 #endif
3132 .sriov_configure = pci_sriov_configure_simple,
3133 .err_handler = &nvme_err_handler,
3134 };
3135
3136 static int __init nvme_init(void)
3137 {
3138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3141 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3142
3143 return pci_register_driver(&nvme_driver);
3144 }
3145
3146 static void __exit nvme_exit(void)
3147 {
3148 pci_unregister_driver(&nvme_driver);
3149 flush_workqueue(nvme_wq);
3150 }
3151
3152 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3153 MODULE_LICENSE("GPL");
3154 MODULE_VERSION("1.0");
3155 module_init(nvme_init);
3156 module_exit(nvme_exit);
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