2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/hdreg.h>
26 #include <linux/idr.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
30 #include <linux/kdev_t.h>
31 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/mutex.h>
36 #include <linux/pci.h>
37 #include <linux/poison.h>
38 #include <linux/ptrace.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/t10-pi.h>
42 #include <linux/timer.h>
43 #include <linux/types.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
46 #include <linux/sed-opal.h>
50 #define NVME_Q_DEPTH 1024
51 #define NVME_AQ_DEPTH 256
52 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
53 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
56 * We handle AEN commands ourselves and don't even let the
57 * block layer know about them.
59 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
61 static int use_threaded_interrupts
;
62 module_param(use_threaded_interrupts
, int, 0);
64 static bool use_cmb_sqes
= true;
65 module_param(use_cmb_sqes
, bool, 0644);
66 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
68 static struct workqueue_struct
*nvme_workq
;
73 static int nvme_reset(struct nvme_dev
*dev
);
74 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
75 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
78 * Represents an NVM Express device. Each nvme_dev is a PCI function.
81 struct nvme_queue
**queues
;
82 struct blk_mq_tag_set tagset
;
83 struct blk_mq_tag_set admin_tagset
;
86 struct dma_pool
*prp_page_pool
;
87 struct dma_pool
*prp_small_pool
;
89 unsigned online_queues
;
94 struct work_struct reset_work
;
95 struct work_struct remove_work
;
96 struct timer_list watchdog_timer
;
97 struct mutex shutdown_lock
;
100 dma_addr_t cmb_dma_addr
;
104 struct nvme_ctrl ctrl
;
105 struct completion ioq_wait
;
108 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
110 return container_of(ctrl
, struct nvme_dev
, ctrl
);
114 * An NVM Express queue. Each device has at least two (one for admin
115 * commands and one for I/O commands).
118 struct device
*q_dmadev
;
119 struct nvme_dev
*dev
;
120 char irqname
[24]; /* nvme4294967295-65535\0 */
122 struct nvme_command
*sq_cmds
;
123 struct nvme_command __iomem
*sq_cmds_io
;
124 volatile struct nvme_completion
*cqes
;
125 struct blk_mq_tags
**tags
;
126 dma_addr_t sq_dma_addr
;
127 dma_addr_t cq_dma_addr
;
139 * The nvme_iod describes the data in an I/O, including the list of PRP
140 * entries. You can't see it in this data structure because C doesn't let
141 * me express that. Use nvme_init_iod to ensure there's enough space
142 * allocated to store the PRP list.
145 struct nvme_request req
;
146 struct nvme_queue
*nvmeq
;
148 int npages
; /* In the PRP list. 0 means small pool in use */
149 int nents
; /* Used in scatterlist */
150 int length
; /* Of data, in bytes */
151 dma_addr_t first_dma
;
152 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
153 struct scatterlist
*sg
;
154 struct scatterlist inline_sg
[0];
158 * Check we didin't inadvertently grow the command struct
160 static inline void _nvme_check_size(void)
162 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
163 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
164 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
165 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
166 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
167 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
168 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
169 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
171 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
172 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
173 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
177 * Max size of iod being embedded in the request payload
179 #define NVME_INT_PAGES 2
180 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
183 * Will slightly overestimate the number of pages needed. This is OK
184 * as it only leads to a small amount of wasted memory for the lifetime of
187 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
189 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
190 dev
->ctrl
.page_size
);
191 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
194 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
195 unsigned int size
, unsigned int nseg
)
197 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
198 sizeof(struct scatterlist
) * nseg
;
201 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
203 return sizeof(struct nvme_iod
) +
204 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
207 static int nvmeq_irq(struct nvme_queue
*nvmeq
)
209 return pci_irq_vector(to_pci_dev(nvmeq
->dev
->dev
), nvmeq
->cq_vector
);
212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
213 unsigned int hctx_idx
)
215 struct nvme_dev
*dev
= data
;
216 struct nvme_queue
*nvmeq
= dev
->queues
[0];
218 WARN_ON(hctx_idx
!= 0);
219 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
220 WARN_ON(nvmeq
->tags
);
222 hctx
->driver_data
= nvmeq
;
223 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
229 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
234 static int nvme_admin_init_request(void *data
, struct request
*req
,
235 unsigned int hctx_idx
, unsigned int rq_idx
,
236 unsigned int numa_node
)
238 struct nvme_dev
*dev
= data
;
239 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
240 struct nvme_queue
*nvmeq
= dev
->queues
[0];
247 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
248 unsigned int hctx_idx
)
250 struct nvme_dev
*dev
= data
;
251 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
254 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
256 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
257 hctx
->driver_data
= nvmeq
;
261 static int nvme_init_request(void *data
, struct request
*req
,
262 unsigned int hctx_idx
, unsigned int rq_idx
,
263 unsigned int numa_node
)
265 struct nvme_dev
*dev
= data
;
266 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
267 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
274 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
276 struct nvme_dev
*dev
= set
->driver_data
;
278 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
282 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
283 * @nvmeq: The queue to use
284 * @cmd: The command to send
286 * Safe to use from interrupt context
288 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
289 struct nvme_command
*cmd
)
291 u16 tail
= nvmeq
->sq_tail
;
293 if (nvmeq
->sq_cmds_io
)
294 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
296 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
298 if (++tail
== nvmeq
->q_depth
)
300 writel(tail
, nvmeq
->q_db
);
301 nvmeq
->sq_tail
= tail
;
304 static __le64
**iod_list(struct request
*req
)
306 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
307 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
310 static int nvme_init_iod(struct request
*rq
, unsigned size
,
311 struct nvme_dev
*dev
)
313 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
314 int nseg
= blk_rq_nr_phys_segments(rq
);
316 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
317 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
319 return BLK_MQ_RQ_QUEUE_BUSY
;
321 iod
->sg
= iod
->inline_sg
;
329 if (!(rq
->rq_flags
& RQF_DONTPREP
)) {
331 rq
->rq_flags
|= RQF_DONTPREP
;
333 return BLK_MQ_RQ_QUEUE_OK
;
336 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
338 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
339 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
341 __le64
**list
= iod_list(req
);
342 dma_addr_t prp_dma
= iod
->first_dma
;
344 if (iod
->npages
== 0)
345 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
346 for (i
= 0; i
< iod
->npages
; i
++) {
347 __le64
*prp_list
= list
[i
];
348 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
349 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
350 prp_dma
= next_prp_dma
;
353 if (iod
->sg
!= iod
->inline_sg
)
357 #ifdef CONFIG_BLK_DEV_INTEGRITY
358 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
360 if (be32_to_cpu(pi
->ref_tag
) == v
)
361 pi
->ref_tag
= cpu_to_be32(p
);
364 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
366 if (be32_to_cpu(pi
->ref_tag
) == p
)
367 pi
->ref_tag
= cpu_to_be32(v
);
371 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
373 * The virtual start sector is the one that was originally submitted by the
374 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
375 * start sector may be different. Remap protection information to match the
376 * physical LBA on writes, and back to the original seed on reads.
378 * Type 0 and 3 do not have a ref tag, so no remapping required.
380 static void nvme_dif_remap(struct request
*req
,
381 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
383 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
384 struct bio_integrity_payload
*bip
;
385 struct t10_pi_tuple
*pi
;
387 u32 i
, nlb
, ts
, phys
, virt
;
389 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
392 bip
= bio_integrity(req
->bio
);
396 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
399 virt
= bip_get_seed(bip
);
400 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
401 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
402 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
404 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
405 pi
= (struct t10_pi_tuple
*)p
;
406 dif_swap(phys
, virt
, pi
);
411 #else /* CONFIG_BLK_DEV_INTEGRITY */
412 static void nvme_dif_remap(struct request
*req
,
413 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
416 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
419 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
424 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
,
427 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
428 struct dma_pool
*pool
;
429 int length
= total_len
;
430 struct scatterlist
*sg
= iod
->sg
;
431 int dma_len
= sg_dma_len(sg
);
432 u64 dma_addr
= sg_dma_address(sg
);
433 u32 page_size
= dev
->ctrl
.page_size
;
434 int offset
= dma_addr
& (page_size
- 1);
436 __le64
**list
= iod_list(req
);
440 length
-= (page_size
- offset
);
444 dma_len
-= (page_size
- offset
);
446 dma_addr
+= (page_size
- offset
);
449 dma_addr
= sg_dma_address(sg
);
450 dma_len
= sg_dma_len(sg
);
453 if (length
<= page_size
) {
454 iod
->first_dma
= dma_addr
;
458 nprps
= DIV_ROUND_UP(length
, page_size
);
459 if (nprps
<= (256 / 8)) {
460 pool
= dev
->prp_small_pool
;
463 pool
= dev
->prp_page_pool
;
467 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
469 iod
->first_dma
= dma_addr
;
474 iod
->first_dma
= prp_dma
;
477 if (i
== page_size
>> 3) {
478 __le64
*old_prp_list
= prp_list
;
479 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
482 list
[iod
->npages
++] = prp_list
;
483 prp_list
[0] = old_prp_list
[i
- 1];
484 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
487 prp_list
[i
++] = cpu_to_le64(dma_addr
);
488 dma_len
-= page_size
;
489 dma_addr
+= page_size
;
497 dma_addr
= sg_dma_address(sg
);
498 dma_len
= sg_dma_len(sg
);
504 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
505 unsigned size
, struct nvme_command
*cmnd
)
507 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
508 struct request_queue
*q
= req
->q
;
509 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
510 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
511 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
513 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
514 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
518 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
519 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
523 if (!nvme_setup_prps(dev
, req
, size
))
526 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
527 if (blk_integrity_rq(req
)) {
528 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
531 sg_init_table(&iod
->meta_sg
, 1);
532 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
535 if (rq_data_dir(req
))
536 nvme_dif_remap(req
, nvme_dif_prep
);
538 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
542 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
543 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
544 if (blk_integrity_rq(req
))
545 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
546 return BLK_MQ_RQ_QUEUE_OK
;
549 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
554 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
556 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
557 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
558 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
561 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
562 if (blk_integrity_rq(req
)) {
563 if (!rq_data_dir(req
))
564 nvme_dif_remap(req
, nvme_dif_complete
);
565 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
569 nvme_cleanup_cmd(req
);
570 nvme_free_iod(dev
, req
);
574 * NOTE: ns is NULL when called on the admin queue.
576 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
577 const struct blk_mq_queue_data
*bd
)
579 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
580 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
581 struct nvme_dev
*dev
= nvmeq
->dev
;
582 struct request
*req
= bd
->rq
;
583 struct nvme_command cmnd
;
585 int ret
= BLK_MQ_RQ_QUEUE_OK
;
588 * If formated with metadata, require the block layer provide a buffer
589 * unless this namespace is formated such that the metadata can be
590 * stripped/generated by the controller with PRACT=1.
592 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
593 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
594 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
595 blk_mq_end_request(req
, -EFAULT
);
596 return BLK_MQ_RQ_QUEUE_OK
;
600 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
601 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
604 map_len
= nvme_map_len(req
);
605 ret
= nvme_init_iod(req
, map_len
, dev
);
606 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
609 if (blk_rq_nr_phys_segments(req
))
610 ret
= nvme_map_data(dev
, req
, map_len
, &cmnd
);
612 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
613 goto out_cleanup_iod
;
615 blk_mq_start_request(req
);
617 spin_lock_irq(&nvmeq
->q_lock
);
618 if (unlikely(nvmeq
->cq_vector
< 0)) {
619 if (ns
&& !test_bit(NVME_NS_DEAD
, &ns
->flags
))
620 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
622 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
623 spin_unlock_irq(&nvmeq
->q_lock
);
624 goto out_cleanup_iod
;
626 __nvme_submit_cmd(nvmeq
, &cmnd
);
627 nvme_process_cq(nvmeq
);
628 spin_unlock_irq(&nvmeq
->q_lock
);
629 return BLK_MQ_RQ_QUEUE_OK
;
631 nvme_free_iod(dev
, req
);
633 nvme_cleanup_cmd(req
);
637 static void nvme_complete_rq(struct request
*req
)
639 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
640 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
643 nvme_unmap_data(dev
, req
);
645 if (unlikely(req
->errors
)) {
646 if (nvme_req_needs_retry(req
, req
->errors
)) {
648 nvme_requeue_req(req
);
652 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
655 error
= nvme_error_status(req
->errors
);
658 if (unlikely(iod
->aborted
)) {
659 dev_warn(dev
->ctrl
.device
,
660 "completing aborted command with status: %04x\n",
664 blk_mq_end_request(req
, error
);
667 /* We read the CQE phase first to check if the rest of the entry is valid */
668 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
671 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
674 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
678 head
= nvmeq
->cq_head
;
679 phase
= nvmeq
->cq_phase
;
681 while (nvme_cqe_valid(nvmeq
, head
, phase
)) {
682 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
685 if (++head
== nvmeq
->q_depth
) {
690 if (tag
&& *tag
== cqe
.command_id
)
693 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
694 dev_warn(nvmeq
->dev
->ctrl
.device
,
695 "invalid id %d completed on queue %d\n",
696 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
701 * AEN requests are special as they don't time out and can
702 * survive any kind of queue freeze and often don't respond to
703 * aborts. We don't even bother to allocate a struct request
704 * for them but rather special case them here.
706 if (unlikely(nvmeq
->qid
== 0 &&
707 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
708 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
709 cqe
.status
, &cqe
.result
);
713 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
714 nvme_req(req
)->result
= cqe
.result
;
715 blk_mq_complete_request(req
, le16_to_cpu(cqe
.status
) >> 1);
718 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
721 if (likely(nvmeq
->cq_vector
>= 0))
722 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
723 nvmeq
->cq_head
= head
;
724 nvmeq
->cq_phase
= phase
;
729 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
731 __nvme_process_cq(nvmeq
, NULL
);
734 static irqreturn_t
nvme_irq(int irq
, void *data
)
737 struct nvme_queue
*nvmeq
= data
;
738 spin_lock(&nvmeq
->q_lock
);
739 nvme_process_cq(nvmeq
);
740 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
742 spin_unlock(&nvmeq
->q_lock
);
746 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
748 struct nvme_queue
*nvmeq
= data
;
749 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
750 return IRQ_WAKE_THREAD
;
754 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
756 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
758 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
759 spin_lock_irq(&nvmeq
->q_lock
);
760 __nvme_process_cq(nvmeq
, &tag
);
761 spin_unlock_irq(&nvmeq
->q_lock
);
770 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
772 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
773 struct nvme_queue
*nvmeq
= dev
->queues
[0];
774 struct nvme_command c
;
776 memset(&c
, 0, sizeof(c
));
777 c
.common
.opcode
= nvme_admin_async_event
;
778 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
780 spin_lock_irq(&nvmeq
->q_lock
);
781 __nvme_submit_cmd(nvmeq
, &c
);
782 spin_unlock_irq(&nvmeq
->q_lock
);
785 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
787 struct nvme_command c
;
789 memset(&c
, 0, sizeof(c
));
790 c
.delete_queue
.opcode
= opcode
;
791 c
.delete_queue
.qid
= cpu_to_le16(id
);
793 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
796 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
797 struct nvme_queue
*nvmeq
)
799 struct nvme_command c
;
800 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
803 * Note: we (ab)use the fact the the prp fields survive if no data
804 * is attached to the request.
806 memset(&c
, 0, sizeof(c
));
807 c
.create_cq
.opcode
= nvme_admin_create_cq
;
808 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
809 c
.create_cq
.cqid
= cpu_to_le16(qid
);
810 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
811 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
812 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
814 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
817 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
818 struct nvme_queue
*nvmeq
)
820 struct nvme_command c
;
821 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
824 * Note: we (ab)use the fact the the prp fields survive if no data
825 * is attached to the request.
827 memset(&c
, 0, sizeof(c
));
828 c
.create_sq
.opcode
= nvme_admin_create_sq
;
829 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
830 c
.create_sq
.sqid
= cpu_to_le16(qid
);
831 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
832 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
833 c
.create_sq
.cqid
= cpu_to_le16(qid
);
835 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
838 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
840 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
843 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
845 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
848 static void abort_endio(struct request
*req
, int error
)
850 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
851 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
852 u16 status
= req
->errors
;
854 dev_warn(nvmeq
->dev
->ctrl
.device
, "Abort status: 0x%x", status
);
855 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
856 blk_mq_free_request(req
);
859 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
861 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
862 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
863 struct nvme_dev
*dev
= nvmeq
->dev
;
864 struct request
*abort_req
;
865 struct nvme_command cmd
;
868 * Shutdown immediately if controller times out while starting. The
869 * reset work will see the pci device disabled when it gets the forced
870 * cancellation error. All outstanding requests are completed on
871 * shutdown, so we return BLK_EH_HANDLED.
873 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
874 dev_warn(dev
->ctrl
.device
,
875 "I/O %d QID %d timeout, disable controller\n",
876 req
->tag
, nvmeq
->qid
);
877 nvme_dev_disable(dev
, false);
878 req
->errors
= NVME_SC_CANCELLED
;
879 return BLK_EH_HANDLED
;
883 * Shutdown the controller immediately and schedule a reset if the
884 * command was already aborted once before and still hasn't been
885 * returned to the driver, or if this is the admin queue.
887 if (!nvmeq
->qid
|| iod
->aborted
) {
888 dev_warn(dev
->ctrl
.device
,
889 "I/O %d QID %d timeout, reset controller\n",
890 req
->tag
, nvmeq
->qid
);
891 nvme_dev_disable(dev
, false);
895 * Mark the request as handled, since the inline shutdown
896 * forces all outstanding requests to complete.
898 req
->errors
= NVME_SC_CANCELLED
;
899 return BLK_EH_HANDLED
;
902 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
903 atomic_inc(&dev
->ctrl
.abort_limit
);
904 return BLK_EH_RESET_TIMER
;
908 memset(&cmd
, 0, sizeof(cmd
));
909 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
910 cmd
.abort
.cid
= req
->tag
;
911 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
913 dev_warn(nvmeq
->dev
->ctrl
.device
,
914 "I/O %d QID %d timeout, aborting\n",
915 req
->tag
, nvmeq
->qid
);
917 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
918 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
919 if (IS_ERR(abort_req
)) {
920 atomic_inc(&dev
->ctrl
.abort_limit
);
921 return BLK_EH_RESET_TIMER
;
924 abort_req
->timeout
= ADMIN_TIMEOUT
;
925 abort_req
->end_io_data
= NULL
;
926 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
929 * The aborted req will be completed on receiving the abort req.
930 * We enable the timer again. If hit twice, it'll cause a device reset,
931 * as the device then is in a faulty state.
933 return BLK_EH_RESET_TIMER
;
936 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
938 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
939 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
941 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
942 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
946 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
950 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
951 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
953 dev
->queues
[i
] = NULL
;
954 nvme_free_queue(nvmeq
);
959 * nvme_suspend_queue - put queue into suspended state
960 * @nvmeq - queue to suspend
962 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
966 spin_lock_irq(&nvmeq
->q_lock
);
967 if (nvmeq
->cq_vector
== -1) {
968 spin_unlock_irq(&nvmeq
->q_lock
);
971 vector
= nvmeq_irq(nvmeq
);
972 nvmeq
->dev
->online_queues
--;
973 nvmeq
->cq_vector
= -1;
974 spin_unlock_irq(&nvmeq
->q_lock
);
976 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
977 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
979 free_irq(vector
, nvmeq
);
984 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
986 struct nvme_queue
*nvmeq
= dev
->queues
[0];
990 if (nvme_suspend_queue(nvmeq
))
994 nvme_shutdown_ctrl(&dev
->ctrl
);
996 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
997 dev
->bar
+ NVME_REG_CAP
));
999 spin_lock_irq(&nvmeq
->q_lock
);
1000 nvme_process_cq(nvmeq
);
1001 spin_unlock_irq(&nvmeq
->q_lock
);
1004 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1007 int q_depth
= dev
->q_depth
;
1008 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1009 dev
->ctrl
.page_size
);
1011 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1012 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1013 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1014 q_depth
= div_u64(mem_per_q
, entry_size
);
1017 * Ensure the reduced q_depth is above some threshold where it
1018 * would be better to map queues in system memory with the
1028 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1031 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1032 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1033 dev
->ctrl
.page_size
);
1034 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1035 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1037 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1038 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1039 if (!nvmeq
->sq_cmds
)
1046 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1049 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1053 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1054 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1058 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1061 nvmeq
->q_dmadev
= dev
->dev
;
1063 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1064 dev
->ctrl
.instance
, qid
);
1065 spin_lock_init(&nvmeq
->q_lock
);
1067 nvmeq
->cq_phase
= 1;
1068 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1069 nvmeq
->q_depth
= depth
;
1071 nvmeq
->cq_vector
= -1;
1072 dev
->queues
[qid
] = nvmeq
;
1078 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1079 nvmeq
->cq_dma_addr
);
1085 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1087 if (use_threaded_interrupts
)
1088 return request_threaded_irq(nvmeq_irq(nvmeq
), nvme_irq_check
,
1089 nvme_irq
, IRQF_SHARED
, nvmeq
->irqname
, nvmeq
);
1091 return request_irq(nvmeq_irq(nvmeq
), nvme_irq
, IRQF_SHARED
,
1092 nvmeq
->irqname
, nvmeq
);
1095 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1097 struct nvme_dev
*dev
= nvmeq
->dev
;
1099 spin_lock_irq(&nvmeq
->q_lock
);
1102 nvmeq
->cq_phase
= 1;
1103 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1104 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1105 dev
->online_queues
++;
1106 spin_unlock_irq(&nvmeq
->q_lock
);
1109 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1111 struct nvme_dev
*dev
= nvmeq
->dev
;
1114 nvmeq
->cq_vector
= qid
- 1;
1115 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1119 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1123 result
= queue_request_irq(nvmeq
);
1127 nvme_init_queue(nvmeq
, qid
);
1131 adapter_delete_sq(dev
, qid
);
1133 adapter_delete_cq(dev
, qid
);
1137 static struct blk_mq_ops nvme_mq_admin_ops
= {
1138 .queue_rq
= nvme_queue_rq
,
1139 .complete
= nvme_complete_rq
,
1140 .init_hctx
= nvme_admin_init_hctx
,
1141 .exit_hctx
= nvme_admin_exit_hctx
,
1142 .init_request
= nvme_admin_init_request
,
1143 .timeout
= nvme_timeout
,
1146 static struct blk_mq_ops nvme_mq_ops
= {
1147 .queue_rq
= nvme_queue_rq
,
1148 .complete
= nvme_complete_rq
,
1149 .init_hctx
= nvme_init_hctx
,
1150 .init_request
= nvme_init_request
,
1151 .map_queues
= nvme_pci_map_queues
,
1152 .timeout
= nvme_timeout
,
1156 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1158 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1160 * If the controller was reset during removal, it's possible
1161 * user requests may be waiting on a stopped queue. Start the
1162 * queue to flush these to completion.
1164 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1165 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1166 blk_mq_free_tag_set(&dev
->admin_tagset
);
1170 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1172 if (!dev
->ctrl
.admin_q
) {
1173 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1174 dev
->admin_tagset
.nr_hw_queues
= 1;
1177 * Subtract one to leave an empty queue entry for 'Full Queue'
1178 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1180 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1181 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1182 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1183 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1184 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1185 dev
->admin_tagset
.driver_data
= dev
;
1187 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1190 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1191 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1192 blk_mq_free_tag_set(&dev
->admin_tagset
);
1195 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1196 nvme_dev_remove_admin(dev
);
1197 dev
->ctrl
.admin_q
= NULL
;
1201 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1206 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1210 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1211 struct nvme_queue
*nvmeq
;
1213 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1214 NVME_CAP_NSSRC(cap
) : 0;
1216 if (dev
->subsystem
&&
1217 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1218 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1220 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1224 nvmeq
= dev
->queues
[0];
1226 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1231 aqa
= nvmeq
->q_depth
- 1;
1234 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1235 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1236 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1238 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1242 nvmeq
->cq_vector
= 0;
1243 result
= queue_request_irq(nvmeq
);
1245 nvmeq
->cq_vector
= -1;
1252 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1255 /* If true, indicates loss of adapter communication, possibly by a
1256 * NVMe Subsystem reset.
1258 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1260 /* If there is a reset ongoing, we shouldn't reset again. */
1261 if (work_busy(&dev
->reset_work
))
1264 /* We shouldn't reset unless the controller is on fatal error state
1265 * _or_ if we lost the communication with it.
1267 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1270 /* If PCI error recovery process is happening, we cannot reset or
1271 * the recovery mechanism will surely fail.
1273 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1279 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1281 /* Read a config register to help see what died. */
1285 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1287 if (result
== PCIBIOS_SUCCESSFUL
)
1289 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1293 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1297 static void nvme_watchdog_timer(unsigned long data
)
1299 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1300 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1302 /* Skip controllers under certain specific conditions. */
1303 if (nvme_should_reset(dev
, csts
)) {
1304 if (!nvme_reset(dev
))
1305 nvme_warn_reset(dev
, csts
);
1309 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1312 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1317 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1318 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1324 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1325 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1326 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1332 * Ignore failing Create SQ/CQ commands, we can continue with less
1333 * than the desired aount of queues, and even a controller without
1334 * I/O queues an still be used to issue admin commands. This might
1335 * be useful to upgrade a buggy firmware for example.
1337 return ret
>= 0 ? 0 : ret
;
1340 static ssize_t
nvme_cmb_show(struct device
*dev
,
1341 struct device_attribute
*attr
,
1344 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1346 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1347 ndev
->cmbloc
, ndev
->cmbsz
);
1349 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1351 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1353 u64 szu
, size
, offset
;
1354 resource_size_t bar_size
;
1355 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1357 dma_addr_t dma_addr
;
1359 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1360 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1362 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1367 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1368 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1369 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1370 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1372 if (offset
> bar_size
)
1376 * Controllers may support a CMB size larger than their BAR,
1377 * for example, due to being behind a bridge. Reduce the CMB to
1378 * the reported size of the BAR
1380 if (size
> bar_size
- offset
)
1381 size
= bar_size
- offset
;
1383 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1384 cmb
= ioremap_wc(dma_addr
, size
);
1388 dev
->cmb_dma_addr
= dma_addr
;
1389 dev
->cmb_size
= size
;
1393 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1401 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1403 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1406 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1408 struct nvme_queue
*adminq
= dev
->queues
[0];
1409 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1410 int result
, nr_io_queues
, size
;
1412 nr_io_queues
= num_online_cpus();
1413 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1417 if (nr_io_queues
== 0)
1420 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1421 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1422 sizeof(struct nvme_command
));
1424 dev
->q_depth
= result
;
1426 nvme_release_cmb(dev
);
1429 size
= db_bar_size(dev
, nr_io_queues
);
1433 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1436 if (!--nr_io_queues
)
1438 size
= db_bar_size(dev
, nr_io_queues
);
1440 dev
->dbs
= dev
->bar
+ 4096;
1441 adminq
->q_db
= dev
->dbs
;
1444 /* Deregister the admin queue's interrupt */
1445 free_irq(pci_irq_vector(pdev
, 0), adminq
);
1448 * If we enable msix early due to not intx, disable it again before
1449 * setting up the full range we need.
1451 pci_free_irq_vectors(pdev
);
1452 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1453 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1454 if (nr_io_queues
<= 0)
1456 dev
->max_qid
= nr_io_queues
;
1459 * Should investigate if there's a performance win from allocating
1460 * more queues than interrupt vectors; it might allow the submission
1461 * path to scale better, even if the receive path is limited by the
1462 * number of interrupts.
1465 result
= queue_request_irq(adminq
);
1467 adminq
->cq_vector
= -1;
1470 return nvme_create_io_queues(dev
);
1473 static void nvme_del_queue_end(struct request
*req
, int error
)
1475 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1477 blk_mq_free_request(req
);
1478 complete(&nvmeq
->dev
->ioq_wait
);
1481 static void nvme_del_cq_end(struct request
*req
, int error
)
1483 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1486 unsigned long flags
;
1489 * We might be called with the AQ q_lock held
1490 * and the I/O queue q_lock should always
1491 * nest inside the AQ one.
1493 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1494 SINGLE_DEPTH_NESTING
);
1495 nvme_process_cq(nvmeq
);
1496 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1499 nvme_del_queue_end(req
, error
);
1502 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1504 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1505 struct request
*req
;
1506 struct nvme_command cmd
;
1508 memset(&cmd
, 0, sizeof(cmd
));
1509 cmd
.delete_queue
.opcode
= opcode
;
1510 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1512 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1514 return PTR_ERR(req
);
1516 req
->timeout
= ADMIN_TIMEOUT
;
1517 req
->end_io_data
= nvmeq
;
1519 blk_execute_rq_nowait(q
, NULL
, req
, false,
1520 opcode
== nvme_admin_delete_cq
?
1521 nvme_del_cq_end
: nvme_del_queue_end
);
1525 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1528 unsigned long timeout
;
1529 u8 opcode
= nvme_admin_delete_sq
;
1531 for (pass
= 0; pass
< 2; pass
++) {
1532 int sent
= 0, i
= queues
;
1534 reinit_completion(&dev
->ioq_wait
);
1536 timeout
= ADMIN_TIMEOUT
;
1537 for (; i
> 0; i
--, sent
++)
1538 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1542 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1548 opcode
= nvme_admin_delete_cq
;
1553 * Return: error value if an error occurred setting up the queues or calling
1554 * Identify Device. 0 if these succeeded, even if adding some of the
1555 * namespaces failed. At the moment, these failures are silent. TBD which
1556 * failures should be reported.
1558 static int nvme_dev_add(struct nvme_dev
*dev
)
1560 if (!dev
->ctrl
.tagset
) {
1561 dev
->tagset
.ops
= &nvme_mq_ops
;
1562 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1563 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1564 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1565 dev
->tagset
.queue_depth
=
1566 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1567 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1568 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1569 dev
->tagset
.driver_data
= dev
;
1571 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1573 dev
->ctrl
.tagset
= &dev
->tagset
;
1575 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1577 /* Free previously allocated queues that are no longer usable */
1578 nvme_free_queues(dev
, dev
->online_queues
);
1584 static int nvme_pci_enable(struct nvme_dev
*dev
)
1587 int result
= -ENOMEM
;
1588 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1590 if (pci_enable_device_mem(pdev
))
1593 pci_set_master(pdev
);
1595 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1596 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1599 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1605 * Some devices and/or platforms don't advertise or work with INTx
1606 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1607 * adjust this later.
1609 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1613 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1615 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1616 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1617 dev
->dbs
= dev
->bar
+ 4096;
1620 * Temporary fix for the Apple controller found in the MacBook8,1 and
1621 * some MacBook7,1 to avoid controller resets and data loss.
1623 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1625 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1626 "queue depth=%u to work around controller resets\n",
1631 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1632 * populate sysfs if a CMB is implemented. Note that we add the
1633 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1634 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1635 * NULL as final argument to sysfs_add_file_to_group.
1638 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1639 dev
->cmb
= nvme_map_cmb(dev
);
1642 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1643 &dev_attr_cmb
.attr
, NULL
))
1645 "failed to add sysfs attribute for CMB\n");
1649 pci_enable_pcie_error_reporting(pdev
);
1650 pci_save_state(pdev
);
1654 pci_disable_device(pdev
);
1658 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1662 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1665 static void nvme_pci_disable(struct nvme_dev
*dev
)
1667 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1669 pci_free_irq_vectors(pdev
);
1671 if (pci_is_enabled(pdev
)) {
1672 pci_disable_pcie_error_reporting(pdev
);
1673 pci_disable_device(pdev
);
1677 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1682 del_timer_sync(&dev
->watchdog_timer
);
1684 mutex_lock(&dev
->shutdown_lock
);
1685 if (pci_is_enabled(to_pci_dev(dev
->dev
))) {
1686 nvme_stop_queues(&dev
->ctrl
);
1687 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1690 queues
= dev
->online_queues
- 1;
1691 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1692 nvme_suspend_queue(dev
->queues
[i
]);
1694 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1695 /* A device might become IO incapable very soon during
1696 * probe, before the admin queue is configured. Thus,
1697 * queue_count can be 0 here.
1699 if (dev
->queue_count
)
1700 nvme_suspend_queue(dev
->queues
[0]);
1702 nvme_disable_io_queues(dev
, queues
);
1703 nvme_disable_admin_queue(dev
, shutdown
);
1705 nvme_pci_disable(dev
);
1707 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
1708 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
1709 mutex_unlock(&dev
->shutdown_lock
);
1712 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1714 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1715 PAGE_SIZE
, PAGE_SIZE
, 0);
1716 if (!dev
->prp_page_pool
)
1719 /* Optimisation for I/Os between 4k and 128k */
1720 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1722 if (!dev
->prp_small_pool
) {
1723 dma_pool_destroy(dev
->prp_page_pool
);
1729 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1731 dma_pool_destroy(dev
->prp_page_pool
);
1732 dma_pool_destroy(dev
->prp_small_pool
);
1735 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1737 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1739 put_device(dev
->dev
);
1740 if (dev
->tagset
.tags
)
1741 blk_mq_free_tag_set(&dev
->tagset
);
1742 if (dev
->ctrl
.admin_q
)
1743 blk_put_queue(dev
->ctrl
.admin_q
);
1745 kfree(dev
->ctrl
.opal_dev
);
1749 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
1751 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
1753 kref_get(&dev
->ctrl
.kref
);
1754 nvme_dev_disable(dev
, false);
1755 if (!schedule_work(&dev
->remove_work
))
1756 nvme_put_ctrl(&dev
->ctrl
);
1759 static void nvme_reset_work(struct work_struct
*work
)
1761 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1762 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
1763 int result
= -ENODEV
;
1765 if (WARN_ON(dev
->ctrl
.state
== NVME_CTRL_RESETTING
))
1769 * If we're called to reset a live controller first shut it down before
1772 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
1773 nvme_dev_disable(dev
, false);
1775 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
))
1778 result
= nvme_pci_enable(dev
);
1782 result
= nvme_configure_admin_queue(dev
);
1786 nvme_init_queue(dev
->queues
[0], 0);
1787 result
= nvme_alloc_admin_tags(dev
);
1791 result
= nvme_init_identify(&dev
->ctrl
);
1795 if (!dev
->ctrl
.opal_dev
) {
1796 dev
->ctrl
.opal_dev
=
1797 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
1801 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
1803 result
= nvme_setup_io_queues(dev
);
1808 * A controller that can not execute IO typically requires user
1809 * intervention to correct. For such degraded controllers, the driver
1810 * should not submit commands the user did not request, so skip
1811 * registering for asynchronous event notification on this condition.
1813 if (dev
->online_queues
> 1)
1814 nvme_queue_async_events(&dev
->ctrl
);
1816 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1819 * Keep the controller around but remove all namespaces if we don't have
1820 * any working I/O queue.
1822 if (dev
->online_queues
< 2) {
1823 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
1824 nvme_kill_queues(&dev
->ctrl
);
1825 nvme_remove_namespaces(&dev
->ctrl
);
1827 nvme_start_queues(&dev
->ctrl
);
1831 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
1832 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
1836 if (dev
->online_queues
> 1)
1837 nvme_queue_scan(&dev
->ctrl
);
1841 nvme_remove_dead_ctrl(dev
, result
);
1844 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1846 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1847 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1849 nvme_kill_queues(&dev
->ctrl
);
1850 if (pci_get_drvdata(pdev
))
1851 device_release_driver(&pdev
->dev
);
1852 nvme_put_ctrl(&dev
->ctrl
);
1855 static int nvme_reset(struct nvme_dev
*dev
)
1857 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1859 if (work_busy(&dev
->reset_work
))
1861 if (!queue_work(nvme_workq
, &dev
->reset_work
))
1866 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
1868 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
1872 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
1874 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
1878 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
1880 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
1884 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
1886 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1887 int ret
= nvme_reset(dev
);
1890 flush_work(&dev
->reset_work
);
1894 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
1896 .module
= THIS_MODULE
,
1897 .reg_read32
= nvme_pci_reg_read32
,
1898 .reg_write32
= nvme_pci_reg_write32
,
1899 .reg_read64
= nvme_pci_reg_read64
,
1900 .reset_ctrl
= nvme_pci_reset_ctrl
,
1901 .free_ctrl
= nvme_pci_free_ctrl
,
1902 .submit_async_event
= nvme_pci_submit_async_event
,
1905 static int nvme_dev_map(struct nvme_dev
*dev
)
1907 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1909 if (pci_request_mem_regions(pdev
, "nvme"))
1912 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1918 pci_release_mem_regions(pdev
);
1922 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1924 int node
, result
= -ENOMEM
;
1925 struct nvme_dev
*dev
;
1927 node
= dev_to_node(&pdev
->dev
);
1928 if (node
== NUMA_NO_NODE
)
1929 set_dev_node(&pdev
->dev
, first_memory_node
);
1931 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
1934 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1939 dev
->dev
= get_device(&pdev
->dev
);
1940 pci_set_drvdata(pdev
, dev
);
1942 result
= nvme_dev_map(dev
);
1946 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
1947 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
1948 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
1949 (unsigned long)dev
);
1950 mutex_init(&dev
->shutdown_lock
);
1951 init_completion(&dev
->ioq_wait
);
1953 result
= nvme_setup_prp_pools(dev
);
1957 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
1962 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
1964 queue_work(nvme_workq
, &dev
->reset_work
);
1968 nvme_release_prp_pools(dev
);
1970 put_device(dev
->dev
);
1971 nvme_dev_unmap(dev
);
1978 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
1980 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1983 nvme_dev_disable(dev
, false);
1988 static void nvme_shutdown(struct pci_dev
*pdev
)
1990 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1991 nvme_dev_disable(dev
, true);
1995 * The driver's remove may be called on a device in a partially initialized
1996 * state. This function must not have any dependencies on the device state in
1999 static void nvme_remove(struct pci_dev
*pdev
)
2001 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2003 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2005 pci_set_drvdata(pdev
, NULL
);
2007 if (!pci_device_is_present(pdev
))
2008 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2010 flush_work(&dev
->reset_work
);
2011 nvme_uninit_ctrl(&dev
->ctrl
);
2012 nvme_dev_disable(dev
, true);
2013 nvme_dev_remove_admin(dev
);
2014 nvme_free_queues(dev
, 0);
2015 nvme_release_cmb(dev
);
2016 nvme_release_prp_pools(dev
);
2017 nvme_dev_unmap(dev
);
2018 nvme_put_ctrl(&dev
->ctrl
);
2021 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2026 if (pci_vfs_assigned(pdev
)) {
2027 dev_warn(&pdev
->dev
,
2028 "Cannot disable SR-IOV VFs while assigned\n");
2031 pci_disable_sriov(pdev
);
2035 ret
= pci_enable_sriov(pdev
, numvfs
);
2036 return ret
? ret
: numvfs
;
2039 #ifdef CONFIG_PM_SLEEP
2040 static int nvme_suspend(struct device
*dev
)
2042 struct pci_dev
*pdev
= to_pci_dev(dev
);
2043 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2045 nvme_dev_disable(ndev
, true);
2049 static int nvme_resume(struct device
*dev
)
2051 struct pci_dev
*pdev
= to_pci_dev(dev
);
2052 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2059 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2061 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2062 pci_channel_state_t state
)
2064 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2067 * A frozen channel requires a reset. When detected, this method will
2068 * shutdown the controller to quiesce. The controller will be restarted
2069 * after the slot reset through driver's slot_reset callback.
2072 case pci_channel_io_normal
:
2073 return PCI_ERS_RESULT_CAN_RECOVER
;
2074 case pci_channel_io_frozen
:
2075 dev_warn(dev
->ctrl
.device
,
2076 "frozen state error detected, reset controller\n");
2077 nvme_dev_disable(dev
, false);
2078 return PCI_ERS_RESULT_NEED_RESET
;
2079 case pci_channel_io_perm_failure
:
2080 dev_warn(dev
->ctrl
.device
,
2081 "failure state error detected, request disconnect\n");
2082 return PCI_ERS_RESULT_DISCONNECT
;
2084 return PCI_ERS_RESULT_NEED_RESET
;
2087 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2089 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2091 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2092 pci_restore_state(pdev
);
2094 return PCI_ERS_RESULT_RECOVERED
;
2097 static void nvme_error_resume(struct pci_dev
*pdev
)
2099 pci_cleanup_aer_uncorrect_error_status(pdev
);
2102 static const struct pci_error_handlers nvme_err_handler
= {
2103 .error_detected
= nvme_error_detected
,
2104 .slot_reset
= nvme_slot_reset
,
2105 .resume
= nvme_error_resume
,
2106 .reset_notify
= nvme_reset_notify
,
2109 static const struct pci_device_id nvme_id_table
[] = {
2110 { PCI_VDEVICE(INTEL
, 0x0953),
2111 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2112 NVME_QUIRK_DISCARD_ZEROES
, },
2113 { PCI_VDEVICE(INTEL
, 0x0a53),
2114 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2115 NVME_QUIRK_DISCARD_ZEROES
, },
2116 { PCI_VDEVICE(INTEL
, 0x0a54),
2117 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2118 NVME_QUIRK_DISCARD_ZEROES
, },
2119 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2120 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2121 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2122 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2123 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2124 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2125 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2126 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2129 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2131 static struct pci_driver nvme_driver
= {
2133 .id_table
= nvme_id_table
,
2134 .probe
= nvme_probe
,
2135 .remove
= nvme_remove
,
2136 .shutdown
= nvme_shutdown
,
2138 .pm
= &nvme_dev_pm_ops
,
2140 .sriov_configure
= nvme_pci_sriov_configure
,
2141 .err_handler
= &nvme_err_handler
,
2144 static int __init
nvme_init(void)
2148 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2152 result
= pci_register_driver(&nvme_driver
);
2154 destroy_workqueue(nvme_workq
);
2158 static void __exit
nvme_exit(void)
2160 pci_unregister_driver(&nvme_driver
);
2161 destroy_workqueue(nvme_workq
);
2165 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2166 MODULE_LICENSE("GPL");
2167 MODULE_VERSION("1.0");
2168 module_init(nvme_init
);
2169 module_exit(nvme_exit
);