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[mirror_ubuntu-artful-kernel.git] / drivers / nvme / host / pci.c
1 /*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
31 #include <linux/list_sort.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
42 #include <linux/pr.h>
43 #include <scsi/sg.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
46
47 #include <uapi/linux/nvme_ioctl.h>
48 #include "nvme.h"
49
50 #define NVME_MINORS (1U << MINORBITS)
51 #define NVME_Q_DEPTH 1024
52 #define NVME_AQ_DEPTH 256
53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
55 #define ADMIN_TIMEOUT (admin_timeout * HZ)
56 #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
57
58 static unsigned char admin_timeout = 60;
59 module_param(admin_timeout, byte, 0644);
60 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
61
62 unsigned char nvme_io_timeout = 30;
63 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
64 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
65
66 static unsigned char shutdown_timeout = 5;
67 module_param(shutdown_timeout, byte, 0644);
68 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
70 static int nvme_major;
71 module_param(nvme_major, int, 0);
72
73 static int nvme_char_major;
74 module_param(nvme_char_major, int, 0);
75
76 static int use_threaded_interrupts;
77 module_param(use_threaded_interrupts, int, 0);
78
79 static bool use_cmb_sqes = true;
80 module_param(use_cmb_sqes, bool, 0644);
81 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82
83 static DEFINE_SPINLOCK(dev_list_lock);
84 static LIST_HEAD(dev_list);
85 static struct task_struct *nvme_thread;
86 static struct workqueue_struct *nvme_workq;
87 static wait_queue_head_t nvme_kthread_wait;
88
89 static struct class *nvme_class;
90
91 static int __nvme_reset(struct nvme_dev *dev);
92 static int nvme_reset(struct nvme_dev *dev);
93 static void nvme_process_cq(struct nvme_queue *nvmeq);
94 static void nvme_dead_ctrl(struct nvme_dev *dev);
95
96 struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
99 struct request *req;
100 u32 result;
101 int status;
102 void *ctx;
103 };
104
105 /*
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
108 */
109 struct nvme_queue {
110 struct device *q_dmadev;
111 struct nvme_dev *dev;
112 char irqname[24]; /* nvme4294967295-65535\0 */
113 spinlock_t q_lock;
114 struct nvme_command *sq_cmds;
115 struct nvme_command __iomem *sq_cmds_io;
116 volatile struct nvme_completion *cqes;
117 struct blk_mq_tags **tags;
118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
120 u32 __iomem *q_db;
121 u16 q_depth;
122 s16 cq_vector;
123 u16 sq_head;
124 u16 sq_tail;
125 u16 cq_head;
126 u16 qid;
127 u8 cq_phase;
128 u8 cqe_seen;
129 struct async_cmd_info cmdinfo;
130 };
131
132 /*
133 * Check we didin't inadvertently grow the command struct
134 */
135 static inline void _nvme_check_size(void)
136 {
137 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
142 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
143 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
144 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
145 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
146 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
147 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
148 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
149 }
150
151 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
152 struct nvme_completion *);
153
154 struct nvme_cmd_info {
155 nvme_completion_fn fn;
156 void *ctx;
157 int aborted;
158 struct nvme_queue *nvmeq;
159 struct nvme_iod iod[0];
160 };
161
162 /*
163 * Max size of iod being embedded in the request payload
164 */
165 #define NVME_INT_PAGES 2
166 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
167 #define NVME_INT_MASK 0x01
168
169 /*
170 * Will slightly overestimate the number of pages needed. This is OK
171 * as it only leads to a small amount of wasted memory for the lifetime of
172 * the I/O.
173 */
174 static int nvme_npages(unsigned size, struct nvme_dev *dev)
175 {
176 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
177 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
178 }
179
180 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
181 {
182 unsigned int ret = sizeof(struct nvme_cmd_info);
183
184 ret += sizeof(struct nvme_iod);
185 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
186 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
187
188 return ret;
189 }
190
191 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
192 unsigned int hctx_idx)
193 {
194 struct nvme_dev *dev = data;
195 struct nvme_queue *nvmeq = dev->queues[0];
196
197 WARN_ON(hctx_idx != 0);
198 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
199 WARN_ON(nvmeq->tags);
200
201 hctx->driver_data = nvmeq;
202 nvmeq->tags = &dev->admin_tagset.tags[0];
203 return 0;
204 }
205
206 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
207 {
208 struct nvme_queue *nvmeq = hctx->driver_data;
209
210 nvmeq->tags = NULL;
211 }
212
213 static int nvme_admin_init_request(void *data, struct request *req,
214 unsigned int hctx_idx, unsigned int rq_idx,
215 unsigned int numa_node)
216 {
217 struct nvme_dev *dev = data;
218 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
219 struct nvme_queue *nvmeq = dev->queues[0];
220
221 BUG_ON(!nvmeq);
222 cmd->nvmeq = nvmeq;
223 return 0;
224 }
225
226 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
227 unsigned int hctx_idx)
228 {
229 struct nvme_dev *dev = data;
230 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
231
232 if (!nvmeq->tags)
233 nvmeq->tags = &dev->tagset.tags[hctx_idx];
234
235 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
236 hctx->driver_data = nvmeq;
237 return 0;
238 }
239
240 static int nvme_init_request(void *data, struct request *req,
241 unsigned int hctx_idx, unsigned int rq_idx,
242 unsigned int numa_node)
243 {
244 struct nvme_dev *dev = data;
245 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
246 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
247
248 BUG_ON(!nvmeq);
249 cmd->nvmeq = nvmeq;
250 return 0;
251 }
252
253 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
254 nvme_completion_fn handler)
255 {
256 cmd->fn = handler;
257 cmd->ctx = ctx;
258 cmd->aborted = 0;
259 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
260 }
261
262 static void *iod_get_private(struct nvme_iod *iod)
263 {
264 return (void *) (iod->private & ~0x1UL);
265 }
266
267 /*
268 * If bit 0 is set, the iod is embedded in the request payload.
269 */
270 static bool iod_should_kfree(struct nvme_iod *iod)
271 {
272 return (iod->private & NVME_INT_MASK) == 0;
273 }
274
275 /* Special values must be less than 0x1000 */
276 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
277 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
278 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
279 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
280
281 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
282 struct nvme_completion *cqe)
283 {
284 if (ctx == CMD_CTX_CANCELLED)
285 return;
286 if (ctx == CMD_CTX_COMPLETED) {
287 dev_warn(nvmeq->q_dmadev,
288 "completed id %d twice on queue %d\n",
289 cqe->command_id, le16_to_cpup(&cqe->sq_id));
290 return;
291 }
292 if (ctx == CMD_CTX_INVALID) {
293 dev_warn(nvmeq->q_dmadev,
294 "invalid id %d completed on queue %d\n",
295 cqe->command_id, le16_to_cpup(&cqe->sq_id));
296 return;
297 }
298 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
299 }
300
301 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
302 {
303 void *ctx;
304
305 if (fn)
306 *fn = cmd->fn;
307 ctx = cmd->ctx;
308 cmd->fn = special_completion;
309 cmd->ctx = CMD_CTX_CANCELLED;
310 return ctx;
311 }
312
313 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
314 struct nvme_completion *cqe)
315 {
316 u32 result = le32_to_cpup(&cqe->result);
317 u16 status = le16_to_cpup(&cqe->status) >> 1;
318
319 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
320 ++nvmeq->dev->event_limit;
321 if (status != NVME_SC_SUCCESS)
322 return;
323
324 switch (result & 0xff07) {
325 case NVME_AER_NOTICE_NS_CHANGED:
326 dev_info(nvmeq->q_dmadev, "rescanning\n");
327 schedule_work(&nvmeq->dev->scan_work);
328 default:
329 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
330 }
331 }
332
333 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
334 struct nvme_completion *cqe)
335 {
336 struct request *req = ctx;
337
338 u16 status = le16_to_cpup(&cqe->status) >> 1;
339 u32 result = le32_to_cpup(&cqe->result);
340
341 blk_mq_free_request(req);
342
343 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
344 ++nvmeq->dev->abort_limit;
345 }
346
347 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
348 struct nvme_completion *cqe)
349 {
350 struct async_cmd_info *cmdinfo = ctx;
351 cmdinfo->result = le32_to_cpup(&cqe->result);
352 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
353 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
354 blk_mq_free_request(cmdinfo->req);
355 }
356
357 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
358 unsigned int tag)
359 {
360 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
361
362 return blk_mq_rq_to_pdu(req);
363 }
364
365 /*
366 * Called with local interrupts disabled and the q_lock held. May not sleep.
367 */
368 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
369 nvme_completion_fn *fn)
370 {
371 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
372 void *ctx;
373 if (tag >= nvmeq->q_depth) {
374 *fn = special_completion;
375 return CMD_CTX_INVALID;
376 }
377 if (fn)
378 *fn = cmd->fn;
379 ctx = cmd->ctx;
380 cmd->fn = special_completion;
381 cmd->ctx = CMD_CTX_COMPLETED;
382 return ctx;
383 }
384
385 /**
386 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
387 * @nvmeq: The queue to use
388 * @cmd: The command to send
389 *
390 * Safe to use from interrupt context
391 */
392 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
393 struct nvme_command *cmd)
394 {
395 u16 tail = nvmeq->sq_tail;
396
397 if (nvmeq->sq_cmds_io)
398 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
399 else
400 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
401
402 if (++tail == nvmeq->q_depth)
403 tail = 0;
404 writel(tail, nvmeq->q_db);
405 nvmeq->sq_tail = tail;
406 }
407
408 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
409 {
410 unsigned long flags;
411 spin_lock_irqsave(&nvmeq->q_lock, flags);
412 __nvme_submit_cmd(nvmeq, cmd);
413 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
414 }
415
416 static __le64 **iod_list(struct nvme_iod *iod)
417 {
418 return ((void *)iod) + iod->offset;
419 }
420
421 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
422 unsigned nseg, unsigned long private)
423 {
424 iod->private = private;
425 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
426 iod->npages = -1;
427 iod->length = nbytes;
428 iod->nents = 0;
429 }
430
431 static struct nvme_iod *
432 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
433 unsigned long priv, gfp_t gfp)
434 {
435 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
436 sizeof(__le64 *) * nvme_npages(bytes, dev) +
437 sizeof(struct scatterlist) * nseg, gfp);
438
439 if (iod)
440 iod_init(iod, bytes, nseg, priv);
441
442 return iod;
443 }
444
445 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
446 gfp_t gfp)
447 {
448 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
449 sizeof(struct nvme_dsm_range);
450 struct nvme_iod *iod;
451
452 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
453 size <= NVME_INT_BYTES(dev)) {
454 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
455
456 iod = cmd->iod;
457 iod_init(iod, size, rq->nr_phys_segments,
458 (unsigned long) rq | NVME_INT_MASK);
459 return iod;
460 }
461
462 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
463 (unsigned long) rq, gfp);
464 }
465
466 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
467 {
468 const int last_prp = dev->page_size / 8 - 1;
469 int i;
470 __le64 **list = iod_list(iod);
471 dma_addr_t prp_dma = iod->first_dma;
472
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
480 }
481
482 if (iod_should_kfree(iod))
483 kfree(iod);
484 }
485
486 static int nvme_error_status(u16 status)
487 {
488 switch (status & 0x7ff) {
489 case NVME_SC_SUCCESS:
490 return 0;
491 case NVME_SC_CAP_EXCEEDED:
492 return -ENOSPC;
493 default:
494 return -EIO;
495 }
496 }
497
498 #ifdef CONFIG_BLK_DEV_INTEGRITY
499 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
500 {
501 if (be32_to_cpu(pi->ref_tag) == v)
502 pi->ref_tag = cpu_to_be32(p);
503 }
504
505 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
506 {
507 if (be32_to_cpu(pi->ref_tag) == p)
508 pi->ref_tag = cpu_to_be32(v);
509 }
510
511 /**
512 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
513 *
514 * The virtual start sector is the one that was originally submitted by the
515 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
516 * start sector may be different. Remap protection information to match the
517 * physical LBA on writes, and back to the original seed on reads.
518 *
519 * Type 0 and 3 do not have a ref tag, so no remapping required.
520 */
521 static void nvme_dif_remap(struct request *req,
522 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
523 {
524 struct nvme_ns *ns = req->rq_disk->private_data;
525 struct bio_integrity_payload *bip;
526 struct t10_pi_tuple *pi;
527 void *p, *pmap;
528 u32 i, nlb, ts, phys, virt;
529
530 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
531 return;
532
533 bip = bio_integrity(req->bio);
534 if (!bip)
535 return;
536
537 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
538
539 p = pmap;
540 virt = bip_get_seed(bip);
541 phys = nvme_block_nr(ns, blk_rq_pos(req));
542 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
543 ts = ns->disk->queue->integrity.tuple_size;
544
545 for (i = 0; i < nlb; i++, virt++, phys++) {
546 pi = (struct t10_pi_tuple *)p;
547 dif_swap(phys, virt, pi);
548 p += ts;
549 }
550 kunmap_atomic(pmap);
551 }
552
553 static void nvme_init_integrity(struct nvme_ns *ns)
554 {
555 struct blk_integrity integrity;
556
557 switch (ns->pi_type) {
558 case NVME_NS_DPS_PI_TYPE3:
559 integrity.profile = &t10_pi_type3_crc;
560 break;
561 case NVME_NS_DPS_PI_TYPE1:
562 case NVME_NS_DPS_PI_TYPE2:
563 integrity.profile = &t10_pi_type1_crc;
564 break;
565 default:
566 integrity.profile = NULL;
567 break;
568 }
569 integrity.tuple_size = ns->ms;
570 blk_integrity_register(ns->disk, &integrity);
571 blk_queue_max_integrity_segments(ns->queue, 1);
572 }
573 #else /* CONFIG_BLK_DEV_INTEGRITY */
574 static void nvme_dif_remap(struct request *req,
575 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
576 {
577 }
578 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
579 {
580 }
581 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
582 {
583 }
584 static void nvme_init_integrity(struct nvme_ns *ns)
585 {
586 }
587 #endif
588
589 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
590 struct nvme_completion *cqe)
591 {
592 struct nvme_iod *iod = ctx;
593 struct request *req = iod_get_private(iod);
594 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
595 u16 status = le16_to_cpup(&cqe->status) >> 1;
596 bool requeue = false;
597 int error = 0;
598
599 if (unlikely(status)) {
600 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
601 && (jiffies - req->start_time) < req->timeout) {
602 unsigned long flags;
603
604 requeue = true;
605 blk_mq_requeue_request(req);
606 spin_lock_irqsave(req->q->queue_lock, flags);
607 if (!blk_queue_stopped(req->q))
608 blk_mq_kick_requeue_list(req->q);
609 spin_unlock_irqrestore(req->q->queue_lock, flags);
610 goto release_iod;
611 }
612
613 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
614 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
615 error = -EINTR;
616 else
617 error = status;
618 } else {
619 error = nvme_error_status(status);
620 }
621 }
622
623 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
624 u32 result = le32_to_cpup(&cqe->result);
625 req->special = (void *)(uintptr_t)result;
626 }
627
628 if (cmd_rq->aborted)
629 dev_warn(nvmeq->dev->dev,
630 "completing aborted command with status:%04x\n",
631 error);
632
633 release_iod:
634 if (iod->nents) {
635 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
636 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
637 if (blk_integrity_rq(req)) {
638 if (!rq_data_dir(req))
639 nvme_dif_remap(req, nvme_dif_complete);
640 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
641 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
642 }
643 }
644 nvme_free_iod(nvmeq->dev, iod);
645
646 if (likely(!requeue))
647 blk_mq_complete_request(req, error);
648 }
649
650 /* length is in bytes. gfp flags indicates whether we may sleep. */
651 static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
653 {
654 struct dma_pool *pool;
655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
661 __le64 *prp_list;
662 __le64 **list = iod_list(iod);
663 dma_addr_t prp_dma;
664 int nprps, i;
665
666 length -= (page_size - offset);
667 if (length <= 0)
668 return total_len;
669
670 dma_len -= (page_size - offset);
671 if (dma_len) {
672 dma_addr += (page_size - offset);
673 } else {
674 sg = sg_next(sg);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
677 }
678
679 if (length <= page_size) {
680 iod->first_dma = dma_addr;
681 return total_len;
682 }
683
684 nprps = DIV_ROUND_UP(length, page_size);
685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
687 iod->npages = 0;
688 } else {
689 pool = dev->prp_page_pool;
690 iod->npages = 1;
691 }
692
693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
694 if (!prp_list) {
695 iod->first_dma = dma_addr;
696 iod->npages = -1;
697 return (total_len - length) + page_size;
698 }
699 list[0] = prp_list;
700 iod->first_dma = prp_dma;
701 i = 0;
702 for (;;) {
703 if (i == page_size >> 3) {
704 __le64 *old_prp_list = prp_list;
705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
706 if (!prp_list)
707 return total_len - length;
708 list[iod->npages++] = prp_list;
709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
711 i = 1;
712 }
713 prp_list[i++] = cpu_to_le64(dma_addr);
714 dma_len -= page_size;
715 dma_addr += page_size;
716 length -= page_size;
717 if (length <= 0)
718 break;
719 if (dma_len > 0)
720 continue;
721 BUG_ON(dma_len < 0);
722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
725 }
726
727 return total_len;
728 }
729
730 static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
732 {
733 struct nvme_command cmnd;
734
735 memcpy(&cmnd, req->cmd, sizeof(cmnd));
736 cmnd.rw.command_id = req->tag;
737 if (req->nr_phys_segments) {
738 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
740 }
741
742 __nvme_submit_cmd(nvmeq, &cmnd);
743 }
744
745 /*
746 * We reuse the small pool to allocate the 16-byte range here as it is not
747 * worth having a special pool for these or additional cases to handle freeing
748 * the iod.
749 */
750 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
751 struct request *req, struct nvme_iod *iod)
752 {
753 struct nvme_dsm_range *range =
754 (struct nvme_dsm_range *)iod_list(iod)[0];
755 struct nvme_command cmnd;
756
757 range->cattr = cpu_to_le32(0);
758 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
759 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
760
761 memset(&cmnd, 0, sizeof(cmnd));
762 cmnd.dsm.opcode = nvme_cmd_dsm;
763 cmnd.dsm.command_id = req->tag;
764 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
765 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
766 cmnd.dsm.nr = 0;
767 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
768
769 __nvme_submit_cmd(nvmeq, &cmnd);
770 }
771
772 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
773 int cmdid)
774 {
775 struct nvme_command cmnd;
776
777 memset(&cmnd, 0, sizeof(cmnd));
778 cmnd.common.opcode = nvme_cmd_flush;
779 cmnd.common.command_id = cmdid;
780 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
781
782 __nvme_submit_cmd(nvmeq, &cmnd);
783 }
784
785 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
786 struct nvme_ns *ns)
787 {
788 struct request *req = iod_get_private(iod);
789 struct nvme_command cmnd;
790 u16 control = 0;
791 u32 dsmgmt = 0;
792
793 if (req->cmd_flags & REQ_FUA)
794 control |= NVME_RW_FUA;
795 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
796 control |= NVME_RW_LR;
797
798 if (req->cmd_flags & REQ_RAHEAD)
799 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
800
801 memset(&cmnd, 0, sizeof(cmnd));
802 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
803 cmnd.rw.command_id = req->tag;
804 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
805 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
806 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
807 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
808 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
809
810 if (ns->ms) {
811 switch (ns->pi_type) {
812 case NVME_NS_DPS_PI_TYPE3:
813 control |= NVME_RW_PRINFO_PRCHK_GUARD;
814 break;
815 case NVME_NS_DPS_PI_TYPE1:
816 case NVME_NS_DPS_PI_TYPE2:
817 control |= NVME_RW_PRINFO_PRCHK_GUARD |
818 NVME_RW_PRINFO_PRCHK_REF;
819 cmnd.rw.reftag = cpu_to_le32(
820 nvme_block_nr(ns, blk_rq_pos(req)));
821 break;
822 }
823 if (blk_integrity_rq(req))
824 cmnd.rw.metadata =
825 cpu_to_le64(sg_dma_address(iod->meta_sg));
826 else
827 control |= NVME_RW_PRINFO_PRACT;
828 }
829
830 cmnd.rw.control = cpu_to_le16(control);
831 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
832
833 __nvme_submit_cmd(nvmeq, &cmnd);
834
835 return 0;
836 }
837
838 /*
839 * NOTE: ns is NULL when called on the admin queue.
840 */
841 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
842 const struct blk_mq_queue_data *bd)
843 {
844 struct nvme_ns *ns = hctx->queue->queuedata;
845 struct nvme_queue *nvmeq = hctx->driver_data;
846 struct nvme_dev *dev = nvmeq->dev;
847 struct request *req = bd->rq;
848 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
849 struct nvme_iod *iod;
850 enum dma_data_direction dma_dir;
851
852 /*
853 * If formated with metadata, require the block layer provide a buffer
854 * unless this namespace is formated such that the metadata can be
855 * stripped/generated by the controller with PRACT=1.
856 */
857 if (ns && ns->ms && !blk_integrity_rq(req)) {
858 if (!(ns->pi_type && ns->ms == 8) &&
859 req->cmd_type != REQ_TYPE_DRV_PRIV) {
860 blk_mq_complete_request(req, -EFAULT);
861 return BLK_MQ_RQ_QUEUE_OK;
862 }
863 }
864
865 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
866 if (!iod)
867 return BLK_MQ_RQ_QUEUE_BUSY;
868
869 if (req->cmd_flags & REQ_DISCARD) {
870 void *range;
871 /*
872 * We reuse the small pool to allocate the 16-byte range here
873 * as it is not worth having a special pool for these or
874 * additional cases to handle freeing the iod.
875 */
876 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
877 &iod->first_dma);
878 if (!range)
879 goto retry_cmd;
880 iod_list(iod)[0] = (__le64 *)range;
881 iod->npages = 0;
882 } else if (req->nr_phys_segments) {
883 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
884
885 sg_init_table(iod->sg, req->nr_phys_segments);
886 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
887 if (!iod->nents)
888 goto error_cmd;
889
890 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
891 goto retry_cmd;
892
893 if (blk_rq_bytes(req) !=
894 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
895 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
896 goto retry_cmd;
897 }
898 if (blk_integrity_rq(req)) {
899 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
900 goto error_cmd;
901
902 sg_init_table(iod->meta_sg, 1);
903 if (blk_rq_map_integrity_sg(
904 req->q, req->bio, iod->meta_sg) != 1)
905 goto error_cmd;
906
907 if (rq_data_dir(req))
908 nvme_dif_remap(req, nvme_dif_prep);
909
910 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
911 goto error_cmd;
912 }
913 }
914
915 nvme_set_info(cmd, iod, req_completion);
916 spin_lock_irq(&nvmeq->q_lock);
917 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
918 nvme_submit_priv(nvmeq, req, iod);
919 else if (req->cmd_flags & REQ_DISCARD)
920 nvme_submit_discard(nvmeq, ns, req, iod);
921 else if (req->cmd_flags & REQ_FLUSH)
922 nvme_submit_flush(nvmeq, ns, req->tag);
923 else
924 nvme_submit_iod(nvmeq, iod, ns);
925
926 nvme_process_cq(nvmeq);
927 spin_unlock_irq(&nvmeq->q_lock);
928 return BLK_MQ_RQ_QUEUE_OK;
929
930 error_cmd:
931 nvme_free_iod(dev, iod);
932 return BLK_MQ_RQ_QUEUE_ERROR;
933 retry_cmd:
934 nvme_free_iod(dev, iod);
935 return BLK_MQ_RQ_QUEUE_BUSY;
936 }
937
938 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
939 {
940 u16 head, phase;
941
942 head = nvmeq->cq_head;
943 phase = nvmeq->cq_phase;
944
945 for (;;) {
946 void *ctx;
947 nvme_completion_fn fn;
948 struct nvme_completion cqe = nvmeq->cqes[head];
949 if ((le16_to_cpu(cqe.status) & 1) != phase)
950 break;
951 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
952 if (++head == nvmeq->q_depth) {
953 head = 0;
954 phase = !phase;
955 }
956 if (tag && *tag == cqe.command_id)
957 *tag = -1;
958 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
959 fn(nvmeq, ctx, &cqe);
960 }
961
962 /* If the controller ignores the cq head doorbell and continuously
963 * writes to the queue, it is theoretically possible to wrap around
964 * the queue twice and mistakenly return IRQ_NONE. Linux only
965 * requires that 0.1% of your interrupts are handled, so this isn't
966 * a big problem.
967 */
968 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
969 return;
970
971 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
972 nvmeq->cq_head = head;
973 nvmeq->cq_phase = phase;
974
975 nvmeq->cqe_seen = 1;
976 }
977
978 static void nvme_process_cq(struct nvme_queue *nvmeq)
979 {
980 __nvme_process_cq(nvmeq, NULL);
981 }
982
983 static irqreturn_t nvme_irq(int irq, void *data)
984 {
985 irqreturn_t result;
986 struct nvme_queue *nvmeq = data;
987 spin_lock(&nvmeq->q_lock);
988 nvme_process_cq(nvmeq);
989 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
990 nvmeq->cqe_seen = 0;
991 spin_unlock(&nvmeq->q_lock);
992 return result;
993 }
994
995 static irqreturn_t nvme_irq_check(int irq, void *data)
996 {
997 struct nvme_queue *nvmeq = data;
998 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
999 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1000 return IRQ_NONE;
1001 return IRQ_WAKE_THREAD;
1002 }
1003
1004 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1005 {
1006 struct nvme_queue *nvmeq = hctx->driver_data;
1007
1008 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
1009 nvmeq->cq_phase) {
1010 spin_lock_irq(&nvmeq->q_lock);
1011 __nvme_process_cq(nvmeq, &tag);
1012 spin_unlock_irq(&nvmeq->q_lock);
1013
1014 if (tag == -1)
1015 return 1;
1016 }
1017
1018 return 0;
1019 }
1020
1021 /*
1022 * Returns 0 on success. If the result is negative, it's a Linux error code;
1023 * if the result is positive, it's an NVM Express status code
1024 */
1025 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1026 void *buffer, void __user *ubuffer, unsigned bufflen,
1027 u32 *result, unsigned timeout)
1028 {
1029 bool write = cmd->common.opcode & 1;
1030 struct bio *bio = NULL;
1031 struct request *req;
1032 int ret;
1033
1034 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
1035 if (IS_ERR(req))
1036 return PTR_ERR(req);
1037
1038 req->cmd_type = REQ_TYPE_DRV_PRIV;
1039 req->cmd_flags |= REQ_FAILFAST_DRIVER;
1040 req->__data_len = 0;
1041 req->__sector = (sector_t) -1;
1042 req->bio = req->biotail = NULL;
1043
1044 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
1045
1046 req->cmd = (unsigned char *)cmd;
1047 req->cmd_len = sizeof(struct nvme_command);
1048 req->special = (void *)0;
1049
1050 if (buffer && bufflen) {
1051 ret = blk_rq_map_kern(q, req, buffer, bufflen,
1052 __GFP_DIRECT_RECLAIM);
1053 if (ret)
1054 goto out;
1055 } else if (ubuffer && bufflen) {
1056 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
1057 __GFP_DIRECT_RECLAIM);
1058 if (ret)
1059 goto out;
1060 bio = req->bio;
1061 }
1062
1063 blk_execute_rq(req->q, NULL, req, 0);
1064 if (bio)
1065 blk_rq_unmap_user(bio);
1066 if (result)
1067 *result = (u32)(uintptr_t)req->special;
1068 ret = req->errors;
1069 out:
1070 blk_mq_free_request(req);
1071 return ret;
1072 }
1073
1074 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1075 void *buffer, unsigned bufflen)
1076 {
1077 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
1078 }
1079
1080 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1081 {
1082 struct nvme_queue *nvmeq = dev->queues[0];
1083 struct nvme_command c;
1084 struct nvme_cmd_info *cmd_info;
1085 struct request *req;
1086
1087 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
1088 if (IS_ERR(req))
1089 return PTR_ERR(req);
1090
1091 req->cmd_flags |= REQ_NO_TIMEOUT;
1092 cmd_info = blk_mq_rq_to_pdu(req);
1093 nvme_set_info(cmd_info, NULL, async_req_completion);
1094
1095 memset(&c, 0, sizeof(c));
1096 c.common.opcode = nvme_admin_async_event;
1097 c.common.command_id = req->tag;
1098
1099 blk_mq_free_request(req);
1100 __nvme_submit_cmd(nvmeq, &c);
1101 return 0;
1102 }
1103
1104 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1105 struct nvme_command *cmd,
1106 struct async_cmd_info *cmdinfo, unsigned timeout)
1107 {
1108 struct nvme_queue *nvmeq = dev->queues[0];
1109 struct request *req;
1110 struct nvme_cmd_info *cmd_rq;
1111
1112 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1113 if (IS_ERR(req))
1114 return PTR_ERR(req);
1115
1116 req->timeout = timeout;
1117 cmd_rq = blk_mq_rq_to_pdu(req);
1118 cmdinfo->req = req;
1119 nvme_set_info(cmd_rq, cmdinfo, async_completion);
1120 cmdinfo->status = -EINTR;
1121
1122 cmd->common.command_id = req->tag;
1123
1124 nvme_submit_cmd(nvmeq, cmd);
1125 return 0;
1126 }
1127
1128 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1129 {
1130 struct nvme_command c;
1131
1132 memset(&c, 0, sizeof(c));
1133 c.delete_queue.opcode = opcode;
1134 c.delete_queue.qid = cpu_to_le16(id);
1135
1136 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1137 }
1138
1139 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1140 struct nvme_queue *nvmeq)
1141 {
1142 struct nvme_command c;
1143 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1144
1145 /*
1146 * Note: we (ab)use the fact the the prp fields survive if no data
1147 * is attached to the request.
1148 */
1149 memset(&c, 0, sizeof(c));
1150 c.create_cq.opcode = nvme_admin_create_cq;
1151 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1152 c.create_cq.cqid = cpu_to_le16(qid);
1153 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1154 c.create_cq.cq_flags = cpu_to_le16(flags);
1155 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1156
1157 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1158 }
1159
1160 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1161 struct nvme_queue *nvmeq)
1162 {
1163 struct nvme_command c;
1164 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1165
1166 /*
1167 * Note: we (ab)use the fact the the prp fields survive if no data
1168 * is attached to the request.
1169 */
1170 memset(&c, 0, sizeof(c));
1171 c.create_sq.opcode = nvme_admin_create_sq;
1172 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1173 c.create_sq.sqid = cpu_to_le16(qid);
1174 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1175 c.create_sq.sq_flags = cpu_to_le16(flags);
1176 c.create_sq.cqid = cpu_to_le16(qid);
1177
1178 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1179 }
1180
1181 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1182 {
1183 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1184 }
1185
1186 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1187 {
1188 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1189 }
1190
1191 int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
1192 {
1193 struct nvme_command c = { };
1194 int error;
1195
1196 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1197 c.identify.opcode = nvme_admin_identify;
1198 c.identify.cns = cpu_to_le32(1);
1199
1200 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1201 if (!*id)
1202 return -ENOMEM;
1203
1204 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1205 sizeof(struct nvme_id_ctrl));
1206 if (error)
1207 kfree(*id);
1208 return error;
1209 }
1210
1211 int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1212 struct nvme_id_ns **id)
1213 {
1214 struct nvme_command c = { };
1215 int error;
1216
1217 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1218 c.identify.opcode = nvme_admin_identify,
1219 c.identify.nsid = cpu_to_le32(nsid),
1220
1221 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1222 if (!*id)
1223 return -ENOMEM;
1224
1225 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1226 sizeof(struct nvme_id_ns));
1227 if (error)
1228 kfree(*id);
1229 return error;
1230 }
1231
1232 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1233 dma_addr_t dma_addr, u32 *result)
1234 {
1235 struct nvme_command c;
1236
1237 memset(&c, 0, sizeof(c));
1238 c.features.opcode = nvme_admin_get_features;
1239 c.features.nsid = cpu_to_le32(nsid);
1240 c.features.prp1 = cpu_to_le64(dma_addr);
1241 c.features.fid = cpu_to_le32(fid);
1242
1243 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1244 result, 0);
1245 }
1246
1247 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1248 dma_addr_t dma_addr, u32 *result)
1249 {
1250 struct nvme_command c;
1251
1252 memset(&c, 0, sizeof(c));
1253 c.features.opcode = nvme_admin_set_features;
1254 c.features.prp1 = cpu_to_le64(dma_addr);
1255 c.features.fid = cpu_to_le32(fid);
1256 c.features.dword11 = cpu_to_le32(dword11);
1257
1258 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1259 result, 0);
1260 }
1261
1262 int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1263 {
1264 struct nvme_command c = { };
1265 int error;
1266
1267 c.common.opcode = nvme_admin_get_log_page,
1268 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1269 c.common.cdw10[0] = cpu_to_le32(
1270 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1271 NVME_LOG_SMART),
1272
1273 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1274 if (!*log)
1275 return -ENOMEM;
1276
1277 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1278 sizeof(struct nvme_smart_log));
1279 if (error)
1280 kfree(*log);
1281 return error;
1282 }
1283
1284 /**
1285 * nvme_abort_req - Attempt aborting a request
1286 *
1287 * Schedule controller reset if the command was already aborted once before and
1288 * still hasn't been returned to the driver, or if this is the admin queue.
1289 */
1290 static void nvme_abort_req(struct request *req)
1291 {
1292 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1293 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1294 struct nvme_dev *dev = nvmeq->dev;
1295 struct request *abort_req;
1296 struct nvme_cmd_info *abort_cmd;
1297 struct nvme_command cmd;
1298
1299 if (!nvmeq->qid || cmd_rq->aborted) {
1300 spin_lock(&dev_list_lock);
1301 if (!__nvme_reset(dev)) {
1302 dev_warn(dev->dev,
1303 "I/O %d QID %d timeout, reset controller\n",
1304 req->tag, nvmeq->qid);
1305 }
1306 spin_unlock(&dev_list_lock);
1307 return;
1308 }
1309
1310 if (!dev->abort_limit)
1311 return;
1312
1313 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1314 false);
1315 if (IS_ERR(abort_req))
1316 return;
1317
1318 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1319 nvme_set_info(abort_cmd, abort_req, abort_completion);
1320
1321 memset(&cmd, 0, sizeof(cmd));
1322 cmd.abort.opcode = nvme_admin_abort_cmd;
1323 cmd.abort.cid = req->tag;
1324 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1325 cmd.abort.command_id = abort_req->tag;
1326
1327 --dev->abort_limit;
1328 cmd_rq->aborted = 1;
1329
1330 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1331 nvmeq->qid);
1332 nvme_submit_cmd(dev->queues[0], &cmd);
1333 }
1334
1335 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1336 {
1337 struct nvme_queue *nvmeq = data;
1338 void *ctx;
1339 nvme_completion_fn fn;
1340 struct nvme_cmd_info *cmd;
1341 struct nvme_completion cqe;
1342
1343 if (!blk_mq_request_started(req))
1344 return;
1345
1346 cmd = blk_mq_rq_to_pdu(req);
1347
1348 if (cmd->ctx == CMD_CTX_CANCELLED)
1349 return;
1350
1351 if (blk_queue_dying(req->q))
1352 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1353 else
1354 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1355
1356
1357 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1358 req->tag, nvmeq->qid);
1359 ctx = cancel_cmd_info(cmd, &fn);
1360 fn(nvmeq, ctx, &cqe);
1361 }
1362
1363 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1364 {
1365 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1366 struct nvme_queue *nvmeq = cmd->nvmeq;
1367
1368 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1369 nvmeq->qid);
1370 spin_lock_irq(&nvmeq->q_lock);
1371 nvme_abort_req(req);
1372 spin_unlock_irq(&nvmeq->q_lock);
1373
1374 /*
1375 * The aborted req will be completed on receiving the abort req.
1376 * We enable the timer again. If hit twice, it'll cause a device reset,
1377 * as the device then is in a faulty state.
1378 */
1379 return BLK_EH_RESET_TIMER;
1380 }
1381
1382 static void nvme_free_queue(struct nvme_queue *nvmeq)
1383 {
1384 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1385 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1386 if (nvmeq->sq_cmds)
1387 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1388 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1389 kfree(nvmeq);
1390 }
1391
1392 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1393 {
1394 int i;
1395
1396 for (i = dev->queue_count - 1; i >= lowest; i--) {
1397 struct nvme_queue *nvmeq = dev->queues[i];
1398 dev->queue_count--;
1399 dev->queues[i] = NULL;
1400 nvme_free_queue(nvmeq);
1401 }
1402 }
1403
1404 /**
1405 * nvme_suspend_queue - put queue into suspended state
1406 * @nvmeq - queue to suspend
1407 */
1408 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1409 {
1410 int vector;
1411
1412 spin_lock_irq(&nvmeq->q_lock);
1413 if (nvmeq->cq_vector == -1) {
1414 spin_unlock_irq(&nvmeq->q_lock);
1415 return 1;
1416 }
1417 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1418 nvmeq->dev->online_queues--;
1419 nvmeq->cq_vector = -1;
1420 spin_unlock_irq(&nvmeq->q_lock);
1421
1422 if (!nvmeq->qid && nvmeq->dev->admin_q)
1423 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1424
1425 irq_set_affinity_hint(vector, NULL);
1426 free_irq(vector, nvmeq);
1427
1428 return 0;
1429 }
1430
1431 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1432 {
1433 spin_lock_irq(&nvmeq->q_lock);
1434 if (nvmeq->tags && *nvmeq->tags)
1435 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1436 spin_unlock_irq(&nvmeq->q_lock);
1437 }
1438
1439 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1440 {
1441 struct nvme_queue *nvmeq = dev->queues[qid];
1442
1443 if (!nvmeq)
1444 return;
1445 if (nvme_suspend_queue(nvmeq))
1446 return;
1447
1448 /* Don't tell the adapter to delete the admin queue.
1449 * Don't tell a removed adapter to delete IO queues. */
1450 if (qid && readl(&dev->bar->csts) != -1) {
1451 adapter_delete_sq(dev, qid);
1452 adapter_delete_cq(dev, qid);
1453 }
1454
1455 spin_lock_irq(&nvmeq->q_lock);
1456 nvme_process_cq(nvmeq);
1457 spin_unlock_irq(&nvmeq->q_lock);
1458 }
1459
1460 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1461 int entry_size)
1462 {
1463 int q_depth = dev->q_depth;
1464 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1465
1466 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1467 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1468 mem_per_q = round_down(mem_per_q, dev->page_size);
1469 q_depth = div_u64(mem_per_q, entry_size);
1470
1471 /*
1472 * Ensure the reduced q_depth is above some threshold where it
1473 * would be better to map queues in system memory with the
1474 * original depth
1475 */
1476 if (q_depth < 64)
1477 return -ENOMEM;
1478 }
1479
1480 return q_depth;
1481 }
1482
1483 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1484 int qid, int depth)
1485 {
1486 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1487 unsigned offset = (qid - 1) *
1488 roundup(SQ_SIZE(depth), dev->page_size);
1489 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1490 nvmeq->sq_cmds_io = dev->cmb + offset;
1491 } else {
1492 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1493 &nvmeq->sq_dma_addr, GFP_KERNEL);
1494 if (!nvmeq->sq_cmds)
1495 return -ENOMEM;
1496 }
1497
1498 return 0;
1499 }
1500
1501 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1502 int depth)
1503 {
1504 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1505 if (!nvmeq)
1506 return NULL;
1507
1508 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1509 &nvmeq->cq_dma_addr, GFP_KERNEL);
1510 if (!nvmeq->cqes)
1511 goto free_nvmeq;
1512
1513 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1514 goto free_cqdma;
1515
1516 nvmeq->q_dmadev = dev->dev;
1517 nvmeq->dev = dev;
1518 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1519 dev->instance, qid);
1520 spin_lock_init(&nvmeq->q_lock);
1521 nvmeq->cq_head = 0;
1522 nvmeq->cq_phase = 1;
1523 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1524 nvmeq->q_depth = depth;
1525 nvmeq->qid = qid;
1526 nvmeq->cq_vector = -1;
1527 dev->queues[qid] = nvmeq;
1528
1529 /* make sure queue descriptor is set before queue count, for kthread */
1530 mb();
1531 dev->queue_count++;
1532
1533 return nvmeq;
1534
1535 free_cqdma:
1536 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1537 nvmeq->cq_dma_addr);
1538 free_nvmeq:
1539 kfree(nvmeq);
1540 return NULL;
1541 }
1542
1543 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1544 const char *name)
1545 {
1546 if (use_threaded_interrupts)
1547 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1548 nvme_irq_check, nvme_irq, IRQF_SHARED,
1549 name, nvmeq);
1550 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1551 IRQF_SHARED, name, nvmeq);
1552 }
1553
1554 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1555 {
1556 struct nvme_dev *dev = nvmeq->dev;
1557
1558 spin_lock_irq(&nvmeq->q_lock);
1559 nvmeq->sq_tail = 0;
1560 nvmeq->cq_head = 0;
1561 nvmeq->cq_phase = 1;
1562 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1563 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1564 dev->online_queues++;
1565 spin_unlock_irq(&nvmeq->q_lock);
1566 }
1567
1568 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1569 {
1570 struct nvme_dev *dev = nvmeq->dev;
1571 int result;
1572
1573 nvmeq->cq_vector = qid - 1;
1574 result = adapter_alloc_cq(dev, qid, nvmeq);
1575 if (result < 0)
1576 return result;
1577
1578 result = adapter_alloc_sq(dev, qid, nvmeq);
1579 if (result < 0)
1580 goto release_cq;
1581
1582 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1583 if (result < 0)
1584 goto release_sq;
1585
1586 nvme_init_queue(nvmeq, qid);
1587 return result;
1588
1589 release_sq:
1590 adapter_delete_sq(dev, qid);
1591 release_cq:
1592 adapter_delete_cq(dev, qid);
1593 return result;
1594 }
1595
1596 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1597 {
1598 unsigned long timeout;
1599 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1600
1601 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1602
1603 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1604 msleep(100);
1605 if (fatal_signal_pending(current))
1606 return -EINTR;
1607 if (time_after(jiffies, timeout)) {
1608 dev_err(dev->dev,
1609 "Device not ready; aborting %s\n", enabled ?
1610 "initialisation" : "reset");
1611 return -ENODEV;
1612 }
1613 }
1614
1615 return 0;
1616 }
1617
1618 /*
1619 * If the device has been passed off to us in an enabled state, just clear
1620 * the enabled bit. The spec says we should set the 'shutdown notification
1621 * bits', but doing so may cause the device to complete commands to the
1622 * admin queue ... and we don't know what memory that might be pointing at!
1623 */
1624 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1625 {
1626 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1627 dev->ctrl_config &= ~NVME_CC_ENABLE;
1628 writel(dev->ctrl_config, &dev->bar->cc);
1629
1630 return nvme_wait_ready(dev, cap, false);
1631 }
1632
1633 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1634 {
1635 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1636 dev->ctrl_config |= NVME_CC_ENABLE;
1637 writel(dev->ctrl_config, &dev->bar->cc);
1638
1639 return nvme_wait_ready(dev, cap, true);
1640 }
1641
1642 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1643 {
1644 unsigned long timeout;
1645
1646 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1647 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1648
1649 writel(dev->ctrl_config, &dev->bar->cc);
1650
1651 timeout = SHUTDOWN_TIMEOUT + jiffies;
1652 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1653 NVME_CSTS_SHST_CMPLT) {
1654 msleep(100);
1655 if (fatal_signal_pending(current))
1656 return -EINTR;
1657 if (time_after(jiffies, timeout)) {
1658 dev_err(dev->dev,
1659 "Device shutdown incomplete; abort shutdown\n");
1660 return -ENODEV;
1661 }
1662 }
1663
1664 return 0;
1665 }
1666
1667 static struct blk_mq_ops nvme_mq_admin_ops = {
1668 .queue_rq = nvme_queue_rq,
1669 .map_queue = blk_mq_map_queue,
1670 .init_hctx = nvme_admin_init_hctx,
1671 .exit_hctx = nvme_admin_exit_hctx,
1672 .init_request = nvme_admin_init_request,
1673 .timeout = nvme_timeout,
1674 };
1675
1676 static struct blk_mq_ops nvme_mq_ops = {
1677 .queue_rq = nvme_queue_rq,
1678 .map_queue = blk_mq_map_queue,
1679 .init_hctx = nvme_init_hctx,
1680 .init_request = nvme_init_request,
1681 .timeout = nvme_timeout,
1682 .poll = nvme_poll,
1683 };
1684
1685 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1686 {
1687 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1688 blk_cleanup_queue(dev->admin_q);
1689 blk_mq_free_tag_set(&dev->admin_tagset);
1690 }
1691 }
1692
1693 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1694 {
1695 if (!dev->admin_q) {
1696 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1697 dev->admin_tagset.nr_hw_queues = 1;
1698 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1699 dev->admin_tagset.reserved_tags = 1;
1700 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1701 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1702 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1703 dev->admin_tagset.driver_data = dev;
1704
1705 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1706 return -ENOMEM;
1707
1708 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1709 if (IS_ERR(dev->admin_q)) {
1710 blk_mq_free_tag_set(&dev->admin_tagset);
1711 return -ENOMEM;
1712 }
1713 if (!blk_get_queue(dev->admin_q)) {
1714 nvme_dev_remove_admin(dev);
1715 dev->admin_q = NULL;
1716 return -ENODEV;
1717 }
1718 } else
1719 blk_mq_unfreeze_queue(dev->admin_q);
1720
1721 return 0;
1722 }
1723
1724 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1725 {
1726 int result;
1727 u32 aqa;
1728 u64 cap = readq(&dev->bar->cap);
1729 struct nvme_queue *nvmeq;
1730 unsigned page_shift = PAGE_SHIFT;
1731 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1732 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1733
1734 if (page_shift < dev_page_min) {
1735 dev_err(dev->dev,
1736 "Minimum device page size (%u) too large for "
1737 "host (%u)\n", 1 << dev_page_min,
1738 1 << page_shift);
1739 return -ENODEV;
1740 }
1741 if (page_shift > dev_page_max) {
1742 dev_info(dev->dev,
1743 "Device maximum page size (%u) smaller than "
1744 "host (%u); enabling work-around\n",
1745 1 << dev_page_max, 1 << page_shift);
1746 page_shift = dev_page_max;
1747 }
1748
1749 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1750 NVME_CAP_NSSRC(cap) : 0;
1751
1752 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1753 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1754
1755 result = nvme_disable_ctrl(dev, cap);
1756 if (result < 0)
1757 return result;
1758
1759 nvmeq = dev->queues[0];
1760 if (!nvmeq) {
1761 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1762 if (!nvmeq)
1763 return -ENOMEM;
1764 }
1765
1766 aqa = nvmeq->q_depth - 1;
1767 aqa |= aqa << 16;
1768
1769 dev->page_size = 1 << page_shift;
1770
1771 dev->ctrl_config = NVME_CC_CSS_NVM;
1772 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1773 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1774 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1775
1776 writel(aqa, &dev->bar->aqa);
1777 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1778 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1779
1780 result = nvme_enable_ctrl(dev, cap);
1781 if (result)
1782 goto free_nvmeq;
1783
1784 nvmeq->cq_vector = 0;
1785 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1786 if (result) {
1787 nvmeq->cq_vector = -1;
1788 goto free_nvmeq;
1789 }
1790
1791 return result;
1792
1793 free_nvmeq:
1794 nvme_free_queues(dev, 0);
1795 return result;
1796 }
1797
1798 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1799 {
1800 struct nvme_dev *dev = ns->dev;
1801 struct nvme_user_io io;
1802 struct nvme_command c;
1803 unsigned length, meta_len;
1804 int status, write;
1805 dma_addr_t meta_dma = 0;
1806 void *meta = NULL;
1807 void __user *metadata;
1808
1809 if (copy_from_user(&io, uio, sizeof(io)))
1810 return -EFAULT;
1811
1812 switch (io.opcode) {
1813 case nvme_cmd_write:
1814 case nvme_cmd_read:
1815 case nvme_cmd_compare:
1816 break;
1817 default:
1818 return -EINVAL;
1819 }
1820
1821 length = (io.nblocks + 1) << ns->lba_shift;
1822 meta_len = (io.nblocks + 1) * ns->ms;
1823 metadata = (void __user *)(uintptr_t)io.metadata;
1824 write = io.opcode & 1;
1825
1826 if (ns->ext) {
1827 length += meta_len;
1828 meta_len = 0;
1829 }
1830 if (meta_len) {
1831 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1832 return -EINVAL;
1833
1834 meta = dma_alloc_coherent(dev->dev, meta_len,
1835 &meta_dma, GFP_KERNEL);
1836
1837 if (!meta) {
1838 status = -ENOMEM;
1839 goto unmap;
1840 }
1841 if (write) {
1842 if (copy_from_user(meta, metadata, meta_len)) {
1843 status = -EFAULT;
1844 goto unmap;
1845 }
1846 }
1847 }
1848
1849 memset(&c, 0, sizeof(c));
1850 c.rw.opcode = io.opcode;
1851 c.rw.flags = io.flags;
1852 c.rw.nsid = cpu_to_le32(ns->ns_id);
1853 c.rw.slba = cpu_to_le64(io.slba);
1854 c.rw.length = cpu_to_le16(io.nblocks);
1855 c.rw.control = cpu_to_le16(io.control);
1856 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1857 c.rw.reftag = cpu_to_le32(io.reftag);
1858 c.rw.apptag = cpu_to_le16(io.apptag);
1859 c.rw.appmask = cpu_to_le16(io.appmask);
1860 c.rw.metadata = cpu_to_le64(meta_dma);
1861
1862 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1863 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
1864 unmap:
1865 if (meta) {
1866 if (status == NVME_SC_SUCCESS && !write) {
1867 if (copy_to_user(metadata, meta, meta_len))
1868 status = -EFAULT;
1869 }
1870 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
1871 }
1872 return status;
1873 }
1874
1875 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1876 struct nvme_passthru_cmd __user *ucmd)
1877 {
1878 struct nvme_passthru_cmd cmd;
1879 struct nvme_command c;
1880 unsigned timeout = 0;
1881 int status;
1882
1883 if (!capable(CAP_SYS_ADMIN))
1884 return -EACCES;
1885 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1886 return -EFAULT;
1887
1888 memset(&c, 0, sizeof(c));
1889 c.common.opcode = cmd.opcode;
1890 c.common.flags = cmd.flags;
1891 c.common.nsid = cpu_to_le32(cmd.nsid);
1892 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1893 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1894 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1895 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1896 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1897 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1898 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1899 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1900
1901 if (cmd.timeout_ms)
1902 timeout = msecs_to_jiffies(cmd.timeout_ms);
1903
1904 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
1905 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1906 &cmd.result, timeout);
1907 if (status >= 0) {
1908 if (put_user(cmd.result, &ucmd->result))
1909 return -EFAULT;
1910 }
1911
1912 return status;
1913 }
1914
1915 static int nvme_subsys_reset(struct nvme_dev *dev)
1916 {
1917 if (!dev->subsystem)
1918 return -ENOTTY;
1919
1920 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1921 return 0;
1922 }
1923
1924 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1925 unsigned long arg)
1926 {
1927 struct nvme_ns *ns = bdev->bd_disk->private_data;
1928
1929 switch (cmd) {
1930 case NVME_IOCTL_ID:
1931 force_successful_syscall_return();
1932 return ns->ns_id;
1933 case NVME_IOCTL_ADMIN_CMD:
1934 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1935 case NVME_IOCTL_IO_CMD:
1936 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1937 case NVME_IOCTL_SUBMIT_IO:
1938 return nvme_submit_io(ns, (void __user *)arg);
1939 case SG_GET_VERSION_NUM:
1940 return nvme_sg_get_version_num((void __user *)arg);
1941 case SG_IO:
1942 return nvme_sg_io(ns, (void __user *)arg);
1943 default:
1944 return -ENOTTY;
1945 }
1946 }
1947
1948 #ifdef CONFIG_COMPAT
1949 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1950 unsigned int cmd, unsigned long arg)
1951 {
1952 switch (cmd) {
1953 case SG_IO:
1954 return -ENOIOCTLCMD;
1955 }
1956 return nvme_ioctl(bdev, mode, cmd, arg);
1957 }
1958 #else
1959 #define nvme_compat_ioctl NULL
1960 #endif
1961
1962 static void nvme_free_dev(struct kref *kref);
1963 static void nvme_free_ns(struct kref *kref)
1964 {
1965 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1966
1967 if (ns->type == NVME_NS_LIGHTNVM)
1968 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1969
1970 spin_lock(&dev_list_lock);
1971 ns->disk->private_data = NULL;
1972 spin_unlock(&dev_list_lock);
1973
1974 kref_put(&ns->dev->kref, nvme_free_dev);
1975 put_disk(ns->disk);
1976 kfree(ns);
1977 }
1978
1979 static int nvme_open(struct block_device *bdev, fmode_t mode)
1980 {
1981 int ret = 0;
1982 struct nvme_ns *ns;
1983
1984 spin_lock(&dev_list_lock);
1985 ns = bdev->bd_disk->private_data;
1986 if (!ns)
1987 ret = -ENXIO;
1988 else if (!kref_get_unless_zero(&ns->kref))
1989 ret = -ENXIO;
1990 spin_unlock(&dev_list_lock);
1991
1992 return ret;
1993 }
1994
1995 static void nvme_release(struct gendisk *disk, fmode_t mode)
1996 {
1997 struct nvme_ns *ns = disk->private_data;
1998 kref_put(&ns->kref, nvme_free_ns);
1999 }
2000
2001 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
2002 {
2003 /* some standard values */
2004 geo->heads = 1 << 6;
2005 geo->sectors = 1 << 5;
2006 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2007 return 0;
2008 }
2009
2010 static void nvme_config_discard(struct nvme_ns *ns)
2011 {
2012 u32 logical_block_size = queue_logical_block_size(ns->queue);
2013 ns->queue->limits.discard_zeroes_data = 0;
2014 ns->queue->limits.discard_alignment = logical_block_size;
2015 ns->queue->limits.discard_granularity = logical_block_size;
2016 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
2017 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2018 }
2019
2020 static int nvme_revalidate_disk(struct gendisk *disk)
2021 {
2022 struct nvme_ns *ns = disk->private_data;
2023 struct nvme_dev *dev = ns->dev;
2024 struct nvme_id_ns *id;
2025 u8 lbaf, pi_type;
2026 u16 old_ms;
2027 unsigned short bs;
2028
2029 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
2030 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2031 dev->instance, ns->ns_id);
2032 return -ENODEV;
2033 }
2034 if (id->ncap == 0) {
2035 kfree(id);
2036 return -ENODEV;
2037 }
2038
2039 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2040 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2041 dev_warn(dev->dev,
2042 "%s: LightNVM init failure\n", __func__);
2043 kfree(id);
2044 return -ENODEV;
2045 }
2046 ns->type = NVME_NS_LIGHTNVM;
2047 }
2048
2049 old_ms = ns->ms;
2050 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2051 ns->lba_shift = id->lbaf[lbaf].ds;
2052 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2053 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
2054
2055 /*
2056 * If identify namespace failed, use default 512 byte block size so
2057 * block layer can use before failing read/write for 0 capacity.
2058 */
2059 if (ns->lba_shift == 0)
2060 ns->lba_shift = 9;
2061 bs = 1 << ns->lba_shift;
2062
2063 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2064 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2065 id->dps & NVME_NS_DPS_PI_MASK : 0;
2066
2067 blk_mq_freeze_queue(disk->queue);
2068 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2069 ns->ms != old_ms ||
2070 bs != queue_logical_block_size(disk->queue) ||
2071 (ns->ms && ns->ext)))
2072 blk_integrity_unregister(disk);
2073
2074 ns->pi_type = pi_type;
2075 blk_queue_logical_block_size(ns->queue, bs);
2076
2077 if (ns->ms && !ns->ext)
2078 nvme_init_integrity(ns);
2079
2080 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2081 !blk_get_integrity(disk)) ||
2082 ns->type == NVME_NS_LIGHTNVM)
2083 set_capacity(disk, 0);
2084 else
2085 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2086
2087 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2088 nvme_config_discard(ns);
2089 blk_mq_unfreeze_queue(disk->queue);
2090
2091 kfree(id);
2092 return 0;
2093 }
2094
2095 static char nvme_pr_type(enum pr_type type)
2096 {
2097 switch (type) {
2098 case PR_WRITE_EXCLUSIVE:
2099 return 1;
2100 case PR_EXCLUSIVE_ACCESS:
2101 return 2;
2102 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2103 return 3;
2104 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2105 return 4;
2106 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2107 return 5;
2108 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2109 return 6;
2110 default:
2111 return 0;
2112 }
2113 };
2114
2115 static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2116 u64 key, u64 sa_key, u8 op)
2117 {
2118 struct nvme_ns *ns = bdev->bd_disk->private_data;
2119 struct nvme_command c;
2120 u8 data[16] = { 0, };
2121
2122 put_unaligned_le64(key, &data[0]);
2123 put_unaligned_le64(sa_key, &data[8]);
2124
2125 memset(&c, 0, sizeof(c));
2126 c.common.opcode = op;
2127 c.common.nsid = cpu_to_le32(ns->ns_id);
2128 c.common.cdw10[0] = cpu_to_le32(cdw10);
2129
2130 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2131 }
2132
2133 static int nvme_pr_register(struct block_device *bdev, u64 old,
2134 u64 new, unsigned flags)
2135 {
2136 u32 cdw10;
2137
2138 if (flags & ~PR_FL_IGNORE_KEY)
2139 return -EOPNOTSUPP;
2140
2141 cdw10 = old ? 2 : 0;
2142 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2143 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2144 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2145 }
2146
2147 static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2148 enum pr_type type, unsigned flags)
2149 {
2150 u32 cdw10;
2151
2152 if (flags & ~PR_FL_IGNORE_KEY)
2153 return -EOPNOTSUPP;
2154
2155 cdw10 = nvme_pr_type(type) << 8;
2156 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2157 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2158 }
2159
2160 static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2161 enum pr_type type, bool abort)
2162 {
2163 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2164 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2165 }
2166
2167 static int nvme_pr_clear(struct block_device *bdev, u64 key)
2168 {
2169 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
2170 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2171 }
2172
2173 static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2174 {
2175 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2176 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2177 }
2178
2179 static const struct pr_ops nvme_pr_ops = {
2180 .pr_register = nvme_pr_register,
2181 .pr_reserve = nvme_pr_reserve,
2182 .pr_release = nvme_pr_release,
2183 .pr_preempt = nvme_pr_preempt,
2184 .pr_clear = nvme_pr_clear,
2185 };
2186
2187 static const struct block_device_operations nvme_fops = {
2188 .owner = THIS_MODULE,
2189 .ioctl = nvme_ioctl,
2190 .compat_ioctl = nvme_compat_ioctl,
2191 .open = nvme_open,
2192 .release = nvme_release,
2193 .getgeo = nvme_getgeo,
2194 .revalidate_disk= nvme_revalidate_disk,
2195 .pr_ops = &nvme_pr_ops,
2196 };
2197
2198 static int nvme_kthread(void *data)
2199 {
2200 struct nvme_dev *dev, *next;
2201
2202 while (!kthread_should_stop()) {
2203 set_current_state(TASK_INTERRUPTIBLE);
2204 spin_lock(&dev_list_lock);
2205 list_for_each_entry_safe(dev, next, &dev_list, node) {
2206 int i;
2207 u32 csts = readl(&dev->bar->csts);
2208
2209 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2210 csts & NVME_CSTS_CFS) {
2211 if (!__nvme_reset(dev)) {
2212 dev_warn(dev->dev,
2213 "Failed status: %x, reset controller\n",
2214 readl(&dev->bar->csts));
2215 }
2216 continue;
2217 }
2218 for (i = 0; i < dev->queue_count; i++) {
2219 struct nvme_queue *nvmeq = dev->queues[i];
2220 if (!nvmeq)
2221 continue;
2222 spin_lock_irq(&nvmeq->q_lock);
2223 nvme_process_cq(nvmeq);
2224
2225 while ((i == 0) && (dev->event_limit > 0)) {
2226 if (nvme_submit_async_admin_req(dev))
2227 break;
2228 dev->event_limit--;
2229 }
2230 spin_unlock_irq(&nvmeq->q_lock);
2231 }
2232 }
2233 spin_unlock(&dev_list_lock);
2234 schedule_timeout(round_jiffies_relative(HZ));
2235 }
2236 return 0;
2237 }
2238
2239 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2240 {
2241 struct nvme_ns *ns;
2242 struct gendisk *disk;
2243 int node = dev_to_node(dev->dev);
2244
2245 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2246 if (!ns)
2247 return;
2248
2249 ns->queue = blk_mq_init_queue(&dev->tagset);
2250 if (IS_ERR(ns->queue))
2251 goto out_free_ns;
2252 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2253 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2254 ns->dev = dev;
2255 ns->queue->queuedata = ns;
2256
2257 disk = alloc_disk_node(0, node);
2258 if (!disk)
2259 goto out_free_queue;
2260
2261 kref_init(&ns->kref);
2262 ns->ns_id = nsid;
2263 ns->disk = disk;
2264 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2265 list_add_tail(&ns->list, &dev->namespaces);
2266
2267 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2268 if (dev->max_hw_sectors) {
2269 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2270 blk_queue_max_segments(ns->queue,
2271 ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
2272 }
2273 if (dev->stripe_size)
2274 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2275 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2276 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2277 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
2278
2279 disk->major = nvme_major;
2280 disk->first_minor = 0;
2281 disk->fops = &nvme_fops;
2282 disk->private_data = ns;
2283 disk->queue = ns->queue;
2284 disk->driverfs_dev = dev->device;
2285 disk->flags = GENHD_FL_EXT_DEVT;
2286 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2287
2288 /*
2289 * Initialize capacity to 0 until we establish the namespace format and
2290 * setup integrity extentions if necessary. The revalidate_disk after
2291 * add_disk allows the driver to register with integrity if the format
2292 * requires it.
2293 */
2294 set_capacity(disk, 0);
2295 if (nvme_revalidate_disk(ns->disk))
2296 goto out_free_disk;
2297
2298 kref_get(&dev->kref);
2299 if (ns->type != NVME_NS_LIGHTNVM) {
2300 add_disk(ns->disk);
2301 if (ns->ms) {
2302 struct block_device *bd = bdget_disk(ns->disk, 0);
2303 if (!bd)
2304 return;
2305 if (blkdev_get(bd, FMODE_READ, NULL)) {
2306 bdput(bd);
2307 return;
2308 }
2309 blkdev_reread_part(bd);
2310 blkdev_put(bd, FMODE_READ);
2311 }
2312 }
2313 return;
2314 out_free_disk:
2315 kfree(disk);
2316 list_del(&ns->list);
2317 out_free_queue:
2318 blk_cleanup_queue(ns->queue);
2319 out_free_ns:
2320 kfree(ns);
2321 }
2322
2323 /*
2324 * Create I/O queues. Failing to create an I/O queue is not an issue,
2325 * we can continue with less than the desired amount of queues, and
2326 * even a controller without I/O queues an still be used to issue
2327 * admin commands. This might be useful to upgrade a buggy firmware
2328 * for example.
2329 */
2330 static void nvme_create_io_queues(struct nvme_dev *dev)
2331 {
2332 unsigned i;
2333
2334 for (i = dev->queue_count; i <= dev->max_qid; i++)
2335 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2336 break;
2337
2338 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2339 if (nvme_create_queue(dev->queues[i], i)) {
2340 nvme_free_queues(dev, i);
2341 break;
2342 }
2343 }
2344
2345 static int set_queue_count(struct nvme_dev *dev, int count)
2346 {
2347 int status;
2348 u32 result;
2349 u32 q_count = (count - 1) | ((count - 1) << 16);
2350
2351 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2352 &result);
2353 if (status < 0)
2354 return status;
2355 if (status > 0) {
2356 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
2357 return 0;
2358 }
2359 return min(result & 0xffff, result >> 16) + 1;
2360 }
2361
2362 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2363 {
2364 u64 szu, size, offset;
2365 u32 cmbloc;
2366 resource_size_t bar_size;
2367 struct pci_dev *pdev = to_pci_dev(dev->dev);
2368 void __iomem *cmb;
2369 dma_addr_t dma_addr;
2370
2371 if (!use_cmb_sqes)
2372 return NULL;
2373
2374 dev->cmbsz = readl(&dev->bar->cmbsz);
2375 if (!(NVME_CMB_SZ(dev->cmbsz)))
2376 return NULL;
2377
2378 cmbloc = readl(&dev->bar->cmbloc);
2379
2380 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2381 size = szu * NVME_CMB_SZ(dev->cmbsz);
2382 offset = szu * NVME_CMB_OFST(cmbloc);
2383 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2384
2385 if (offset > bar_size)
2386 return NULL;
2387
2388 /*
2389 * Controllers may support a CMB size larger than their BAR,
2390 * for example, due to being behind a bridge. Reduce the CMB to
2391 * the reported size of the BAR
2392 */
2393 if (size > bar_size - offset)
2394 size = bar_size - offset;
2395
2396 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2397 cmb = ioremap_wc(dma_addr, size);
2398 if (!cmb)
2399 return NULL;
2400
2401 dev->cmb_dma_addr = dma_addr;
2402 dev->cmb_size = size;
2403 return cmb;
2404 }
2405
2406 static inline void nvme_release_cmb(struct nvme_dev *dev)
2407 {
2408 if (dev->cmb) {
2409 iounmap(dev->cmb);
2410 dev->cmb = NULL;
2411 }
2412 }
2413
2414 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2415 {
2416 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2417 }
2418
2419 static int nvme_setup_io_queues(struct nvme_dev *dev)
2420 {
2421 struct nvme_queue *adminq = dev->queues[0];
2422 struct pci_dev *pdev = to_pci_dev(dev->dev);
2423 int result, i, vecs, nr_io_queues, size;
2424
2425 nr_io_queues = num_possible_cpus();
2426 result = set_queue_count(dev, nr_io_queues);
2427 if (result <= 0)
2428 return result;
2429 if (result < nr_io_queues)
2430 nr_io_queues = result;
2431
2432 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2433 result = nvme_cmb_qdepth(dev, nr_io_queues,
2434 sizeof(struct nvme_command));
2435 if (result > 0)
2436 dev->q_depth = result;
2437 else
2438 nvme_release_cmb(dev);
2439 }
2440
2441 size = db_bar_size(dev, nr_io_queues);
2442 if (size > 8192) {
2443 iounmap(dev->bar);
2444 do {
2445 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2446 if (dev->bar)
2447 break;
2448 if (!--nr_io_queues)
2449 return -ENOMEM;
2450 size = db_bar_size(dev, nr_io_queues);
2451 } while (1);
2452 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2453 adminq->q_db = dev->dbs;
2454 }
2455
2456 /* Deregister the admin queue's interrupt */
2457 free_irq(dev->entry[0].vector, adminq);
2458
2459 /*
2460 * If we enable msix early due to not intx, disable it again before
2461 * setting up the full range we need.
2462 */
2463 if (!pdev->irq)
2464 pci_disable_msix(pdev);
2465
2466 for (i = 0; i < nr_io_queues; i++)
2467 dev->entry[i].entry = i;
2468 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2469 if (vecs < 0) {
2470 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2471 if (vecs < 0) {
2472 vecs = 1;
2473 } else {
2474 for (i = 0; i < vecs; i++)
2475 dev->entry[i].vector = i + pdev->irq;
2476 }
2477 }
2478
2479 /*
2480 * Should investigate if there's a performance win from allocating
2481 * more queues than interrupt vectors; it might allow the submission
2482 * path to scale better, even if the receive path is limited by the
2483 * number of interrupts.
2484 */
2485 nr_io_queues = vecs;
2486 dev->max_qid = nr_io_queues;
2487
2488 result = queue_request_irq(dev, adminq, adminq->irqname);
2489 if (result) {
2490 adminq->cq_vector = -1;
2491 goto free_queues;
2492 }
2493
2494 /* Free previously allocated queues that are no longer usable */
2495 nvme_free_queues(dev, nr_io_queues + 1);
2496 nvme_create_io_queues(dev);
2497
2498 return 0;
2499
2500 free_queues:
2501 nvme_free_queues(dev, 1);
2502 return result;
2503 }
2504
2505 static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2506 {
2507 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2508 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2509
2510 return nsa->ns_id - nsb->ns_id;
2511 }
2512
2513 static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2514 {
2515 struct nvme_ns *ns;
2516
2517 list_for_each_entry(ns, &dev->namespaces, list) {
2518 if (ns->ns_id == nsid)
2519 return ns;
2520 if (ns->ns_id > nsid)
2521 break;
2522 }
2523 return NULL;
2524 }
2525
2526 static inline bool nvme_io_incapable(struct nvme_dev *dev)
2527 {
2528 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2529 dev->online_queues < 2);
2530 }
2531
2532 static void nvme_ns_remove(struct nvme_ns *ns)
2533 {
2534 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2535
2536 if (kill)
2537 blk_set_queue_dying(ns->queue);
2538 if (ns->disk->flags & GENHD_FL_UP)
2539 del_gendisk(ns->disk);
2540 if (kill || !blk_queue_dying(ns->queue)) {
2541 blk_mq_abort_requeue_list(ns->queue);
2542 blk_cleanup_queue(ns->queue);
2543 }
2544 list_del_init(&ns->list);
2545 kref_put(&ns->kref, nvme_free_ns);
2546 }
2547
2548 static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2549 {
2550 struct nvme_ns *ns, *next;
2551 unsigned i;
2552
2553 for (i = 1; i <= nn; i++) {
2554 ns = nvme_find_ns(dev, i);
2555 if (ns) {
2556 if (revalidate_disk(ns->disk))
2557 nvme_ns_remove(ns);
2558 } else
2559 nvme_alloc_ns(dev, i);
2560 }
2561 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2562 if (ns->ns_id > nn)
2563 nvme_ns_remove(ns);
2564 }
2565 list_sort(NULL, &dev->namespaces, ns_cmp);
2566 }
2567
2568 static void nvme_set_irq_hints(struct nvme_dev *dev)
2569 {
2570 struct nvme_queue *nvmeq;
2571 int i;
2572
2573 for (i = 0; i < dev->online_queues; i++) {
2574 nvmeq = dev->queues[i];
2575
2576 if (!nvmeq->tags || !(*nvmeq->tags))
2577 continue;
2578
2579 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2580 blk_mq_tags_cpumask(*nvmeq->tags));
2581 }
2582 }
2583
2584 static void nvme_dev_scan(struct work_struct *work)
2585 {
2586 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2587 struct nvme_id_ctrl *ctrl;
2588
2589 if (!dev->tagset.tags)
2590 return;
2591 if (nvme_identify_ctrl(dev, &ctrl))
2592 return;
2593 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2594 kfree(ctrl);
2595 nvme_set_irq_hints(dev);
2596 }
2597
2598 /*
2599 * Return: error value if an error occurred setting up the queues or calling
2600 * Identify Device. 0 if these succeeded, even if adding some of the
2601 * namespaces failed. At the moment, these failures are silent. TBD which
2602 * failures should be reported.
2603 */
2604 static int nvme_dev_add(struct nvme_dev *dev)
2605 {
2606 struct pci_dev *pdev = to_pci_dev(dev->dev);
2607 int res;
2608 struct nvme_id_ctrl *ctrl;
2609 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2610
2611 res = nvme_identify_ctrl(dev, &ctrl);
2612 if (res) {
2613 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
2614 return -EIO;
2615 }
2616
2617 dev->oncs = le16_to_cpup(&ctrl->oncs);
2618 dev->abort_limit = ctrl->acl + 1;
2619 dev->vwc = ctrl->vwc;
2620 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2621 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2622 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2623 if (ctrl->mdts)
2624 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2625 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2626 (pdev->device == 0x0953) && ctrl->vs[3]) {
2627 unsigned int max_hw_sectors;
2628
2629 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2630 max_hw_sectors = dev->stripe_size >> (shift - 9);
2631 if (dev->max_hw_sectors) {
2632 dev->max_hw_sectors = min(max_hw_sectors,
2633 dev->max_hw_sectors);
2634 } else
2635 dev->max_hw_sectors = max_hw_sectors;
2636 }
2637 kfree(ctrl);
2638
2639 if (!dev->tagset.tags) {
2640 dev->tagset.ops = &nvme_mq_ops;
2641 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2642 dev->tagset.timeout = NVME_IO_TIMEOUT;
2643 dev->tagset.numa_node = dev_to_node(dev->dev);
2644 dev->tagset.queue_depth =
2645 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2646 dev->tagset.cmd_size = nvme_cmd_size(dev);
2647 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2648 dev->tagset.driver_data = dev;
2649
2650 if (blk_mq_alloc_tag_set(&dev->tagset))
2651 return 0;
2652 }
2653 schedule_work(&dev->scan_work);
2654 return 0;
2655 }
2656
2657 static int nvme_dev_map(struct nvme_dev *dev)
2658 {
2659 u64 cap;
2660 int bars, result = -ENOMEM;
2661 struct pci_dev *pdev = to_pci_dev(dev->dev);
2662
2663 if (pci_enable_device_mem(pdev))
2664 return result;
2665
2666 dev->entry[0].vector = pdev->irq;
2667 pci_set_master(pdev);
2668 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2669 if (!bars)
2670 goto disable_pci;
2671
2672 if (pci_request_selected_regions(pdev, bars, "nvme"))
2673 goto disable_pci;
2674
2675 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2676 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2677 goto disable;
2678
2679 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2680 if (!dev->bar)
2681 goto disable;
2682
2683 if (readl(&dev->bar->csts) == -1) {
2684 result = -ENODEV;
2685 goto unmap;
2686 }
2687
2688 /*
2689 * Some devices don't advertse INTx interrupts, pre-enable a single
2690 * MSIX vec for setup. We'll adjust this later.
2691 */
2692 if (!pdev->irq) {
2693 result = pci_enable_msix(pdev, dev->entry, 1);
2694 if (result < 0)
2695 goto unmap;
2696 }
2697
2698 cap = readq(&dev->bar->cap);
2699 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2700 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2701 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2702 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2703 dev->cmb = nvme_map_cmb(dev);
2704
2705 return 0;
2706
2707 unmap:
2708 iounmap(dev->bar);
2709 dev->bar = NULL;
2710 disable:
2711 pci_release_regions(pdev);
2712 disable_pci:
2713 pci_disable_device(pdev);
2714 return result;
2715 }
2716
2717 static void nvme_dev_unmap(struct nvme_dev *dev)
2718 {
2719 struct pci_dev *pdev = to_pci_dev(dev->dev);
2720
2721 if (pdev->msi_enabled)
2722 pci_disable_msi(pdev);
2723 else if (pdev->msix_enabled)
2724 pci_disable_msix(pdev);
2725
2726 if (dev->bar) {
2727 iounmap(dev->bar);
2728 dev->bar = NULL;
2729 pci_release_regions(pdev);
2730 }
2731
2732 if (pci_is_enabled(pdev))
2733 pci_disable_device(pdev);
2734 }
2735
2736 struct nvme_delq_ctx {
2737 struct task_struct *waiter;
2738 struct kthread_worker *worker;
2739 atomic_t refcount;
2740 };
2741
2742 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2743 {
2744 dq->waiter = current;
2745 mb();
2746
2747 for (;;) {
2748 set_current_state(TASK_KILLABLE);
2749 if (!atomic_read(&dq->refcount))
2750 break;
2751 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2752 fatal_signal_pending(current)) {
2753 /*
2754 * Disable the controller first since we can't trust it
2755 * at this point, but leave the admin queue enabled
2756 * until all queue deletion requests are flushed.
2757 * FIXME: This may take a while if there are more h/w
2758 * queues than admin tags.
2759 */
2760 set_current_state(TASK_RUNNING);
2761 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2762 nvme_clear_queue(dev->queues[0]);
2763 flush_kthread_worker(dq->worker);
2764 nvme_disable_queue(dev, 0);
2765 return;
2766 }
2767 }
2768 set_current_state(TASK_RUNNING);
2769 }
2770
2771 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2772 {
2773 atomic_dec(&dq->refcount);
2774 if (dq->waiter)
2775 wake_up_process(dq->waiter);
2776 }
2777
2778 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2779 {
2780 atomic_inc(&dq->refcount);
2781 return dq;
2782 }
2783
2784 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2785 {
2786 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2787 nvme_put_dq(dq);
2788 }
2789
2790 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2791 kthread_work_func_t fn)
2792 {
2793 struct nvme_command c;
2794
2795 memset(&c, 0, sizeof(c));
2796 c.delete_queue.opcode = opcode;
2797 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2798
2799 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2800 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2801 ADMIN_TIMEOUT);
2802 }
2803
2804 static void nvme_del_cq_work_handler(struct kthread_work *work)
2805 {
2806 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2807 cmdinfo.work);
2808 nvme_del_queue_end(nvmeq);
2809 }
2810
2811 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2812 {
2813 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2814 nvme_del_cq_work_handler);
2815 }
2816
2817 static void nvme_del_sq_work_handler(struct kthread_work *work)
2818 {
2819 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2820 cmdinfo.work);
2821 int status = nvmeq->cmdinfo.status;
2822
2823 if (!status)
2824 status = nvme_delete_cq(nvmeq);
2825 if (status)
2826 nvme_del_queue_end(nvmeq);
2827 }
2828
2829 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2830 {
2831 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2832 nvme_del_sq_work_handler);
2833 }
2834
2835 static void nvme_del_queue_start(struct kthread_work *work)
2836 {
2837 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2838 cmdinfo.work);
2839 if (nvme_delete_sq(nvmeq))
2840 nvme_del_queue_end(nvmeq);
2841 }
2842
2843 static void nvme_disable_io_queues(struct nvme_dev *dev)
2844 {
2845 int i;
2846 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2847 struct nvme_delq_ctx dq;
2848 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2849 &worker, "nvme%d", dev->instance);
2850
2851 if (IS_ERR(kworker_task)) {
2852 dev_err(dev->dev,
2853 "Failed to create queue del task\n");
2854 for (i = dev->queue_count - 1; i > 0; i--)
2855 nvme_disable_queue(dev, i);
2856 return;
2857 }
2858
2859 dq.waiter = NULL;
2860 atomic_set(&dq.refcount, 0);
2861 dq.worker = &worker;
2862 for (i = dev->queue_count - 1; i > 0; i--) {
2863 struct nvme_queue *nvmeq = dev->queues[i];
2864
2865 if (nvme_suspend_queue(nvmeq))
2866 continue;
2867 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2868 nvmeq->cmdinfo.worker = dq.worker;
2869 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2870 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2871 }
2872 nvme_wait_dq(&dq, dev);
2873 kthread_stop(kworker_task);
2874 }
2875
2876 /*
2877 * Remove the node from the device list and check
2878 * for whether or not we need to stop the nvme_thread.
2879 */
2880 static void nvme_dev_list_remove(struct nvme_dev *dev)
2881 {
2882 struct task_struct *tmp = NULL;
2883
2884 spin_lock(&dev_list_lock);
2885 list_del_init(&dev->node);
2886 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2887 tmp = nvme_thread;
2888 nvme_thread = NULL;
2889 }
2890 spin_unlock(&dev_list_lock);
2891
2892 if (tmp)
2893 kthread_stop(tmp);
2894 }
2895
2896 static void nvme_freeze_queues(struct nvme_dev *dev)
2897 {
2898 struct nvme_ns *ns;
2899
2900 list_for_each_entry(ns, &dev->namespaces, list) {
2901 blk_mq_freeze_queue_start(ns->queue);
2902
2903 spin_lock_irq(ns->queue->queue_lock);
2904 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2905 spin_unlock_irq(ns->queue->queue_lock);
2906
2907 blk_mq_cancel_requeue_work(ns->queue);
2908 blk_mq_stop_hw_queues(ns->queue);
2909 }
2910 }
2911
2912 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2913 {
2914 struct nvme_ns *ns;
2915
2916 list_for_each_entry(ns, &dev->namespaces, list) {
2917 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2918 blk_mq_unfreeze_queue(ns->queue);
2919 blk_mq_start_stopped_hw_queues(ns->queue, true);
2920 blk_mq_kick_requeue_list(ns->queue);
2921 }
2922 }
2923
2924 static void nvme_dev_shutdown(struct nvme_dev *dev)
2925 {
2926 int i;
2927 u32 csts = -1;
2928
2929 nvme_dev_list_remove(dev);
2930
2931 if (dev->bar) {
2932 nvme_freeze_queues(dev);
2933 csts = readl(&dev->bar->csts);
2934 }
2935 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2936 for (i = dev->queue_count - 1; i >= 0; i--) {
2937 struct nvme_queue *nvmeq = dev->queues[i];
2938 nvme_suspend_queue(nvmeq);
2939 }
2940 } else {
2941 nvme_disable_io_queues(dev);
2942 nvme_shutdown_ctrl(dev);
2943 nvme_disable_queue(dev, 0);
2944 }
2945 nvme_dev_unmap(dev);
2946
2947 for (i = dev->queue_count - 1; i >= 0; i--)
2948 nvme_clear_queue(dev->queues[i]);
2949 }
2950
2951 static void nvme_dev_remove(struct nvme_dev *dev)
2952 {
2953 struct nvme_ns *ns, *next;
2954
2955 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2956 nvme_ns_remove(ns);
2957 }
2958
2959 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2960 {
2961 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2962 PAGE_SIZE, PAGE_SIZE, 0);
2963 if (!dev->prp_page_pool)
2964 return -ENOMEM;
2965
2966 /* Optimisation for I/Os between 4k and 128k */
2967 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2968 256, 256, 0);
2969 if (!dev->prp_small_pool) {
2970 dma_pool_destroy(dev->prp_page_pool);
2971 return -ENOMEM;
2972 }
2973 return 0;
2974 }
2975
2976 static void nvme_release_prp_pools(struct nvme_dev *dev)
2977 {
2978 dma_pool_destroy(dev->prp_page_pool);
2979 dma_pool_destroy(dev->prp_small_pool);
2980 }
2981
2982 static DEFINE_IDA(nvme_instance_ida);
2983
2984 static int nvme_set_instance(struct nvme_dev *dev)
2985 {
2986 int instance, error;
2987
2988 do {
2989 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2990 return -ENODEV;
2991
2992 spin_lock(&dev_list_lock);
2993 error = ida_get_new(&nvme_instance_ida, &instance);
2994 spin_unlock(&dev_list_lock);
2995 } while (error == -EAGAIN);
2996
2997 if (error)
2998 return -ENODEV;
2999
3000 dev->instance = instance;
3001 return 0;
3002 }
3003
3004 static void nvme_release_instance(struct nvme_dev *dev)
3005 {
3006 spin_lock(&dev_list_lock);
3007 ida_remove(&nvme_instance_ida, dev->instance);
3008 spin_unlock(&dev_list_lock);
3009 }
3010
3011 static void nvme_free_dev(struct kref *kref)
3012 {
3013 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
3014
3015 put_device(dev->dev);
3016 put_device(dev->device);
3017 nvme_release_instance(dev);
3018 if (dev->tagset.tags)
3019 blk_mq_free_tag_set(&dev->tagset);
3020 if (dev->admin_q)
3021 blk_put_queue(dev->admin_q);
3022 kfree(dev->queues);
3023 kfree(dev->entry);
3024 kfree(dev);
3025 }
3026
3027 static int nvme_dev_open(struct inode *inode, struct file *f)
3028 {
3029 struct nvme_dev *dev;
3030 int instance = iminor(inode);
3031 int ret = -ENODEV;
3032
3033 spin_lock(&dev_list_lock);
3034 list_for_each_entry(dev, &dev_list, node) {
3035 if (dev->instance == instance) {
3036 if (!dev->admin_q) {
3037 ret = -EWOULDBLOCK;
3038 break;
3039 }
3040 if (!kref_get_unless_zero(&dev->kref))
3041 break;
3042 f->private_data = dev;
3043 ret = 0;
3044 break;
3045 }
3046 }
3047 spin_unlock(&dev_list_lock);
3048
3049 return ret;
3050 }
3051
3052 static int nvme_dev_release(struct inode *inode, struct file *f)
3053 {
3054 struct nvme_dev *dev = f->private_data;
3055 kref_put(&dev->kref, nvme_free_dev);
3056 return 0;
3057 }
3058
3059 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3060 {
3061 struct nvme_dev *dev = f->private_data;
3062 struct nvme_ns *ns;
3063
3064 switch (cmd) {
3065 case NVME_IOCTL_ADMIN_CMD:
3066 return nvme_user_cmd(dev, NULL, (void __user *)arg);
3067 case NVME_IOCTL_IO_CMD:
3068 if (list_empty(&dev->namespaces))
3069 return -ENOTTY;
3070 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3071 return nvme_user_cmd(dev, ns, (void __user *)arg);
3072 case NVME_IOCTL_RESET:
3073 dev_warn(dev->dev, "resetting controller\n");
3074 return nvme_reset(dev);
3075 case NVME_IOCTL_SUBSYS_RESET:
3076 return nvme_subsys_reset(dev);
3077 default:
3078 return -ENOTTY;
3079 }
3080 }
3081
3082 static const struct file_operations nvme_dev_fops = {
3083 .owner = THIS_MODULE,
3084 .open = nvme_dev_open,
3085 .release = nvme_dev_release,
3086 .unlocked_ioctl = nvme_dev_ioctl,
3087 .compat_ioctl = nvme_dev_ioctl,
3088 };
3089
3090 static void nvme_probe_work(struct work_struct *work)
3091 {
3092 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3093 bool start_thread = false;
3094 int result;
3095
3096 result = nvme_dev_map(dev);
3097 if (result)
3098 goto out;
3099
3100 result = nvme_configure_admin_queue(dev);
3101 if (result)
3102 goto unmap;
3103
3104 spin_lock(&dev_list_lock);
3105 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3106 start_thread = true;
3107 nvme_thread = NULL;
3108 }
3109 list_add(&dev->node, &dev_list);
3110 spin_unlock(&dev_list_lock);
3111
3112 if (start_thread) {
3113 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
3114 wake_up_all(&nvme_kthread_wait);
3115 } else
3116 wait_event_killable(nvme_kthread_wait, nvme_thread);
3117
3118 if (IS_ERR_OR_NULL(nvme_thread)) {
3119 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3120 goto disable;
3121 }
3122
3123 nvme_init_queue(dev->queues[0], 0);
3124 result = nvme_alloc_admin_tags(dev);
3125 if (result)
3126 goto disable;
3127
3128 result = nvme_setup_io_queues(dev);
3129 if (result)
3130 goto free_tags;
3131
3132 dev->event_limit = 1;
3133
3134 /*
3135 * Keep the controller around but remove all namespaces if we don't have
3136 * any working I/O queue.
3137 */
3138 if (dev->online_queues < 2) {
3139 dev_warn(dev->dev, "IO queues not created\n");
3140 nvme_dev_remove(dev);
3141 } else {
3142 nvme_unfreeze_queues(dev);
3143 nvme_dev_add(dev);
3144 }
3145
3146 return;
3147
3148 free_tags:
3149 nvme_dev_remove_admin(dev);
3150 blk_put_queue(dev->admin_q);
3151 dev->admin_q = NULL;
3152 dev->queues[0]->tags = NULL;
3153 disable:
3154 nvme_disable_queue(dev, 0);
3155 nvme_dev_list_remove(dev);
3156 unmap:
3157 nvme_dev_unmap(dev);
3158 out:
3159 if (!work_busy(&dev->reset_work))
3160 nvme_dead_ctrl(dev);
3161 }
3162
3163 static int nvme_remove_dead_ctrl(void *arg)
3164 {
3165 struct nvme_dev *dev = (struct nvme_dev *)arg;
3166 struct pci_dev *pdev = to_pci_dev(dev->dev);
3167
3168 if (pci_get_drvdata(pdev))
3169 pci_stop_and_remove_bus_device_locked(pdev);
3170 kref_put(&dev->kref, nvme_free_dev);
3171 return 0;
3172 }
3173
3174 static void nvme_dead_ctrl(struct nvme_dev *dev)
3175 {
3176 dev_warn(dev->dev, "Device failed to resume\n");
3177 kref_get(&dev->kref);
3178 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3179 dev->instance))) {
3180 dev_err(dev->dev,
3181 "Failed to start controller remove task\n");
3182 kref_put(&dev->kref, nvme_free_dev);
3183 }
3184 }
3185
3186 static void nvme_reset_work(struct work_struct *ws)
3187 {
3188 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
3189 bool in_probe = work_busy(&dev->probe_work);
3190
3191 nvme_dev_shutdown(dev);
3192
3193 /* Synchronize with device probe so that work will see failure status
3194 * and exit gracefully without trying to schedule another reset */
3195 flush_work(&dev->probe_work);
3196
3197 /* Fail this device if reset occured during probe to avoid
3198 * infinite initialization loops. */
3199 if (in_probe) {
3200 nvme_dead_ctrl(dev);
3201 return;
3202 }
3203 /* Schedule device resume asynchronously so the reset work is available
3204 * to cleanup errors that may occur during reinitialization */
3205 schedule_work(&dev->probe_work);
3206 }
3207
3208 static int __nvme_reset(struct nvme_dev *dev)
3209 {
3210 if (work_pending(&dev->reset_work))
3211 return -EBUSY;
3212 list_del_init(&dev->node);
3213 queue_work(nvme_workq, &dev->reset_work);
3214 return 0;
3215 }
3216
3217 static int nvme_reset(struct nvme_dev *dev)
3218 {
3219 int ret;
3220
3221 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3222 return -ENODEV;
3223
3224 spin_lock(&dev_list_lock);
3225 ret = __nvme_reset(dev);
3226 spin_unlock(&dev_list_lock);
3227
3228 if (!ret) {
3229 flush_work(&dev->reset_work);
3230 flush_work(&dev->probe_work);
3231 return 0;
3232 }
3233
3234 return ret;
3235 }
3236
3237 static ssize_t nvme_sysfs_reset(struct device *dev,
3238 struct device_attribute *attr, const char *buf,
3239 size_t count)
3240 {
3241 struct nvme_dev *ndev = dev_get_drvdata(dev);
3242 int ret;
3243
3244 ret = nvme_reset(ndev);
3245 if (ret < 0)
3246 return ret;
3247
3248 return count;
3249 }
3250 static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3251
3252 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3253 {
3254 int node, result = -ENOMEM;
3255 struct nvme_dev *dev;
3256
3257 node = dev_to_node(&pdev->dev);
3258 if (node == NUMA_NO_NODE)
3259 set_dev_node(&pdev->dev, 0);
3260
3261 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3262 if (!dev)
3263 return -ENOMEM;
3264 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3265 GFP_KERNEL, node);
3266 if (!dev->entry)
3267 goto free;
3268 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3269 GFP_KERNEL, node);
3270 if (!dev->queues)
3271 goto free;
3272
3273 INIT_LIST_HEAD(&dev->namespaces);
3274 INIT_WORK(&dev->reset_work, nvme_reset_work);
3275 dev->dev = get_device(&pdev->dev);
3276 pci_set_drvdata(pdev, dev);
3277 result = nvme_set_instance(dev);
3278 if (result)
3279 goto put_pci;
3280
3281 result = nvme_setup_prp_pools(dev);
3282 if (result)
3283 goto release;
3284
3285 kref_init(&dev->kref);
3286 dev->device = device_create(nvme_class, &pdev->dev,
3287 MKDEV(nvme_char_major, dev->instance),
3288 dev, "nvme%d", dev->instance);
3289 if (IS_ERR(dev->device)) {
3290 result = PTR_ERR(dev->device);
3291 goto release_pools;
3292 }
3293 get_device(dev->device);
3294 dev_set_drvdata(dev->device, dev);
3295
3296 result = device_create_file(dev->device, &dev_attr_reset_controller);
3297 if (result)
3298 goto put_dev;
3299
3300 INIT_LIST_HEAD(&dev->node);
3301 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3302 INIT_WORK(&dev->probe_work, nvme_probe_work);
3303 schedule_work(&dev->probe_work);
3304 return 0;
3305
3306 put_dev:
3307 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3308 put_device(dev->device);
3309 release_pools:
3310 nvme_release_prp_pools(dev);
3311 release:
3312 nvme_release_instance(dev);
3313 put_pci:
3314 put_device(dev->dev);
3315 free:
3316 kfree(dev->queues);
3317 kfree(dev->entry);
3318 kfree(dev);
3319 return result;
3320 }
3321
3322 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3323 {
3324 struct nvme_dev *dev = pci_get_drvdata(pdev);
3325
3326 if (prepare)
3327 nvme_dev_shutdown(dev);
3328 else
3329 schedule_work(&dev->probe_work);
3330 }
3331
3332 static void nvme_shutdown(struct pci_dev *pdev)
3333 {
3334 struct nvme_dev *dev = pci_get_drvdata(pdev);
3335 nvme_dev_shutdown(dev);
3336 }
3337
3338 static void nvme_remove(struct pci_dev *pdev)
3339 {
3340 struct nvme_dev *dev = pci_get_drvdata(pdev);
3341
3342 spin_lock(&dev_list_lock);
3343 list_del_init(&dev->node);
3344 spin_unlock(&dev_list_lock);
3345
3346 pci_set_drvdata(pdev, NULL);
3347 flush_work(&dev->probe_work);
3348 flush_work(&dev->reset_work);
3349 flush_work(&dev->scan_work);
3350 device_remove_file(dev->device, &dev_attr_reset_controller);
3351 nvme_dev_remove(dev);
3352 nvme_dev_shutdown(dev);
3353 nvme_dev_remove_admin(dev);
3354 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3355 nvme_free_queues(dev, 0);
3356 nvme_release_cmb(dev);
3357 nvme_release_prp_pools(dev);
3358 kref_put(&dev->kref, nvme_free_dev);
3359 }
3360
3361 /* These functions are yet to be implemented */
3362 #define nvme_error_detected NULL
3363 #define nvme_dump_registers NULL
3364 #define nvme_link_reset NULL
3365 #define nvme_slot_reset NULL
3366 #define nvme_error_resume NULL
3367
3368 #ifdef CONFIG_PM_SLEEP
3369 static int nvme_suspend(struct device *dev)
3370 {
3371 struct pci_dev *pdev = to_pci_dev(dev);
3372 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3373
3374 nvme_dev_shutdown(ndev);
3375 return 0;
3376 }
3377
3378 static int nvme_resume(struct device *dev)
3379 {
3380 struct pci_dev *pdev = to_pci_dev(dev);
3381 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3382
3383 schedule_work(&ndev->probe_work);
3384 return 0;
3385 }
3386 #endif
3387
3388 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3389
3390 static const struct pci_error_handlers nvme_err_handler = {
3391 .error_detected = nvme_error_detected,
3392 .mmio_enabled = nvme_dump_registers,
3393 .link_reset = nvme_link_reset,
3394 .slot_reset = nvme_slot_reset,
3395 .resume = nvme_error_resume,
3396 .reset_notify = nvme_reset_notify,
3397 };
3398
3399 /* Move to pci_ids.h later */
3400 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
3401
3402 static const struct pci_device_id nvme_id_table[] = {
3403 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3404 { 0, }
3405 };
3406 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3407
3408 static struct pci_driver nvme_driver = {
3409 .name = "nvme",
3410 .id_table = nvme_id_table,
3411 .probe = nvme_probe,
3412 .remove = nvme_remove,
3413 .shutdown = nvme_shutdown,
3414 .driver = {
3415 .pm = &nvme_dev_pm_ops,
3416 },
3417 .err_handler = &nvme_err_handler,
3418 };
3419
3420 static int __init nvme_init(void)
3421 {
3422 int result;
3423
3424 init_waitqueue_head(&nvme_kthread_wait);
3425
3426 nvme_workq = create_singlethread_workqueue("nvme");
3427 if (!nvme_workq)
3428 return -ENOMEM;
3429
3430 result = register_blkdev(nvme_major, "nvme");
3431 if (result < 0)
3432 goto kill_workq;
3433 else if (result > 0)
3434 nvme_major = result;
3435
3436 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3437 &nvme_dev_fops);
3438 if (result < 0)
3439 goto unregister_blkdev;
3440 else if (result > 0)
3441 nvme_char_major = result;
3442
3443 nvme_class = class_create(THIS_MODULE, "nvme");
3444 if (IS_ERR(nvme_class)) {
3445 result = PTR_ERR(nvme_class);
3446 goto unregister_chrdev;
3447 }
3448
3449 result = pci_register_driver(&nvme_driver);
3450 if (result)
3451 goto destroy_class;
3452 return 0;
3453
3454 destroy_class:
3455 class_destroy(nvme_class);
3456 unregister_chrdev:
3457 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3458 unregister_blkdev:
3459 unregister_blkdev(nvme_major, "nvme");
3460 kill_workq:
3461 destroy_workqueue(nvme_workq);
3462 return result;
3463 }
3464
3465 static void __exit nvme_exit(void)
3466 {
3467 pci_unregister_driver(&nvme_driver);
3468 unregister_blkdev(nvme_major, "nvme");
3469 destroy_workqueue(nvme_workq);
3470 class_destroy(nvme_class);
3471 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3472 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3473 _nvme_check_size();
3474 }
3475
3476 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3477 MODULE_LICENSE("GPL");
3478 MODULE_VERSION("1.0");
3479 module_init(nvme_init);
3480 module_exit(nvme_exit);