2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/pci.h>
28 #include <linux/poison.h>
29 #include <linux/t10-pi.h>
30 #include <linux/timer.h>
31 #include <linux/types.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #include <asm/unaligned.h>
34 #include <linux/sed-opal.h>
38 #define NVME_Q_DEPTH 1024
39 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
40 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43 * We handle AEN commands ourselves and don't even let the
44 * block layer know about them.
46 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
48 static int use_threaded_interrupts
;
49 module_param(use_threaded_interrupts
, int, 0);
51 static bool use_cmb_sqes
= true;
52 module_param(use_cmb_sqes
, bool, 0644);
53 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
55 static unsigned int max_host_mem_size_mb
= 128;
56 module_param(max_host_mem_size_mb
, uint
, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb
,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
63 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
64 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
67 * Represents an NVM Express device. Each nvme_dev is a PCI function.
70 struct nvme_queue
**queues
;
71 struct blk_mq_tag_set tagset
;
72 struct blk_mq_tag_set admin_tagset
;
75 struct dma_pool
*prp_page_pool
;
76 struct dma_pool
*prp_small_pool
;
78 unsigned online_queues
;
83 unsigned long bar_mapped_size
;
84 struct work_struct remove_work
;
85 struct mutex shutdown_lock
;
88 dma_addr_t cmb_dma_addr
;
92 struct nvme_ctrl ctrl
;
93 struct completion ioq_wait
;
95 /* shadow doorbell buffer support: */
97 dma_addr_t dbbuf_dbs_dma_addr
;
99 dma_addr_t dbbuf_eis_dma_addr
;
101 /* host memory buffer support: */
103 u32 nr_host_mem_descs
;
104 struct nvme_host_mem_buf_desc
*host_mem_descs
;
105 void **host_mem_desc_bufs
;
108 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
110 return qid
* 2 * stride
;
113 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
115 return (qid
* 2 + 1) * stride
;
118 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
120 return container_of(ctrl
, struct nvme_dev
, ctrl
);
124 * An NVM Express queue. Each device has at least two (one for admin
125 * commands and one for I/O commands).
128 struct device
*q_dmadev
;
129 struct nvme_dev
*dev
;
131 struct nvme_command
*sq_cmds
;
132 struct nvme_command __iomem
*sq_cmds_io
;
133 volatile struct nvme_completion
*cqes
;
134 struct blk_mq_tags
**tags
;
135 dma_addr_t sq_dma_addr
;
136 dma_addr_t cq_dma_addr
;
152 * The nvme_iod describes the data in an I/O, including the list of PRP
153 * entries. You can't see it in this data structure because C doesn't let
154 * me express that. Use nvme_init_iod to ensure there's enough space
155 * allocated to store the PRP list.
158 struct nvme_request req
;
159 struct nvme_queue
*nvmeq
;
161 int npages
; /* In the PRP list. 0 means small pool in use */
162 int nents
; /* Used in scatterlist */
163 int length
; /* Of data, in bytes */
164 dma_addr_t first_dma
;
165 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
166 struct scatterlist
*sg
;
167 struct scatterlist inline_sg
[0];
171 * Check we didin't inadvertently grow the command struct
173 static inline void _nvme_check_size(void)
175 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
176 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
177 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
178 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
179 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
180 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
181 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
184 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
185 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
187 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
190 static inline unsigned int nvme_dbbuf_size(u32 stride
)
192 return ((num_possible_cpus() + 1) * 8 * stride
);
195 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
197 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
202 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
203 &dev
->dbbuf_dbs_dma_addr
,
207 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
208 &dev
->dbbuf_eis_dma_addr
,
210 if (!dev
->dbbuf_eis
) {
211 dma_free_coherent(dev
->dev
, mem_size
,
212 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
213 dev
->dbbuf_dbs
= NULL
;
220 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
222 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
224 if (dev
->dbbuf_dbs
) {
225 dma_free_coherent(dev
->dev
, mem_size
,
226 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
227 dev
->dbbuf_dbs
= NULL
;
229 if (dev
->dbbuf_eis
) {
230 dma_free_coherent(dev
->dev
, mem_size
,
231 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
232 dev
->dbbuf_eis
= NULL
;
236 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
237 struct nvme_queue
*nvmeq
, int qid
)
239 if (!dev
->dbbuf_dbs
|| !qid
)
242 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
243 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
244 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
245 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
248 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
250 struct nvme_command c
;
255 memset(&c
, 0, sizeof(c
));
256 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
257 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
258 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
260 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
261 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
262 /* Free memory and continue on */
263 nvme_dbbuf_dma_free(dev
);
267 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
269 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
272 /* Update dbbuf and return true if an MMIO is required */
273 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
274 volatile u32
*dbbuf_ei
)
280 * Ensure that the queue is written before updating
281 * the doorbell in memory
285 old_value
= *dbbuf_db
;
288 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
296 * Max size of iod being embedded in the request payload
298 #define NVME_INT_PAGES 2
299 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
302 * Will slightly overestimate the number of pages needed. This is OK
303 * as it only leads to a small amount of wasted memory for the lifetime of
306 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
308 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
309 dev
->ctrl
.page_size
);
310 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
313 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
314 unsigned int size
, unsigned int nseg
)
316 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
317 sizeof(struct scatterlist
) * nseg
;
320 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
322 return sizeof(struct nvme_iod
) +
323 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
326 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
327 unsigned int hctx_idx
)
329 struct nvme_dev
*dev
= data
;
330 struct nvme_queue
*nvmeq
= dev
->queues
[0];
332 WARN_ON(hctx_idx
!= 0);
333 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
334 WARN_ON(nvmeq
->tags
);
336 hctx
->driver_data
= nvmeq
;
337 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
341 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
343 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
348 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
349 unsigned int hctx_idx
)
351 struct nvme_dev
*dev
= data
;
352 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
355 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
357 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
358 hctx
->driver_data
= nvmeq
;
362 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
363 unsigned int hctx_idx
, unsigned int numa_node
)
365 struct nvme_dev
*dev
= set
->driver_data
;
366 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
367 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
368 struct nvme_queue
*nvmeq
= dev
->queues
[queue_idx
];
375 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
377 struct nvme_dev
*dev
= set
->driver_data
;
379 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
383 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
384 * @nvmeq: The queue to use
385 * @cmd: The command to send
387 * Safe to use from interrupt context
389 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
390 struct nvme_command
*cmd
)
392 u16 tail
= nvmeq
->sq_tail
;
394 if (nvmeq
->sq_cmds_io
)
395 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
397 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
399 if (++tail
== nvmeq
->q_depth
)
401 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
403 writel(tail
, nvmeq
->q_db
);
404 nvmeq
->sq_tail
= tail
;
407 static __le64
**iod_list(struct request
*req
)
409 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
410 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
413 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
415 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
416 int nseg
= blk_rq_nr_phys_segments(rq
);
417 unsigned int size
= blk_rq_payload_bytes(rq
);
419 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
420 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
422 return BLK_STS_RESOURCE
;
424 iod
->sg
= iod
->inline_sg
;
435 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
437 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
438 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
440 __le64
**list
= iod_list(req
);
441 dma_addr_t prp_dma
= iod
->first_dma
;
443 if (iod
->npages
== 0)
444 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
445 for (i
= 0; i
< iod
->npages
; i
++) {
446 __le64
*prp_list
= list
[i
];
447 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
448 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
449 prp_dma
= next_prp_dma
;
452 if (iod
->sg
!= iod
->inline_sg
)
456 #ifdef CONFIG_BLK_DEV_INTEGRITY
457 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
459 if (be32_to_cpu(pi
->ref_tag
) == v
)
460 pi
->ref_tag
= cpu_to_be32(p
);
463 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
465 if (be32_to_cpu(pi
->ref_tag
) == p
)
466 pi
->ref_tag
= cpu_to_be32(v
);
470 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
472 * The virtual start sector is the one that was originally submitted by the
473 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
474 * start sector may be different. Remap protection information to match the
475 * physical LBA on writes, and back to the original seed on reads.
477 * Type 0 and 3 do not have a ref tag, so no remapping required.
479 static void nvme_dif_remap(struct request
*req
,
480 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
482 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
483 struct bio_integrity_payload
*bip
;
484 struct t10_pi_tuple
*pi
;
486 u32 i
, nlb
, ts
, phys
, virt
;
488 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
491 bip
= bio_integrity(req
->bio
);
495 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
498 virt
= bip_get_seed(bip
);
499 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
500 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
501 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
503 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
504 pi
= (struct t10_pi_tuple
*)p
;
505 dif_swap(phys
, virt
, pi
);
510 #else /* CONFIG_BLK_DEV_INTEGRITY */
511 static void nvme_dif_remap(struct request
*req
,
512 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
515 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
518 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
523 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
525 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
526 struct dma_pool
*pool
;
527 int length
= blk_rq_payload_bytes(req
);
528 struct scatterlist
*sg
= iod
->sg
;
529 int dma_len
= sg_dma_len(sg
);
530 u64 dma_addr
= sg_dma_address(sg
);
531 u32 page_size
= dev
->ctrl
.page_size
;
532 int offset
= dma_addr
& (page_size
- 1);
534 __le64
**list
= iod_list(req
);
538 length
-= (page_size
- offset
);
542 dma_len
-= (page_size
- offset
);
544 dma_addr
+= (page_size
- offset
);
547 dma_addr
= sg_dma_address(sg
);
548 dma_len
= sg_dma_len(sg
);
551 if (length
<= page_size
) {
552 iod
->first_dma
= dma_addr
;
556 nprps
= DIV_ROUND_UP(length
, page_size
);
557 if (nprps
<= (256 / 8)) {
558 pool
= dev
->prp_small_pool
;
561 pool
= dev
->prp_page_pool
;
565 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
567 iod
->first_dma
= dma_addr
;
572 iod
->first_dma
= prp_dma
;
575 if (i
== page_size
>> 3) {
576 __le64
*old_prp_list
= prp_list
;
577 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
580 list
[iod
->npages
++] = prp_list
;
581 prp_list
[0] = old_prp_list
[i
- 1];
582 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
585 prp_list
[i
++] = cpu_to_le64(dma_addr
);
586 dma_len
-= page_size
;
587 dma_addr
+= page_size
;
595 dma_addr
= sg_dma_address(sg
);
596 dma_len
= sg_dma_len(sg
);
602 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
603 struct nvme_command
*cmnd
)
605 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
606 struct request_queue
*q
= req
->q
;
607 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
608 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
609 blk_status_t ret
= BLK_STS_IOERR
;
611 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
612 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
616 ret
= BLK_STS_RESOURCE
;
617 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
621 if (!nvme_setup_prps(dev
, req
))
625 if (blk_integrity_rq(req
)) {
626 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
629 sg_init_table(&iod
->meta_sg
, 1);
630 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
633 if (rq_data_dir(req
))
634 nvme_dif_remap(req
, nvme_dif_prep
);
636 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
640 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
641 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
642 if (blk_integrity_rq(req
))
643 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
647 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
652 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
654 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
655 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
656 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
659 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
660 if (blk_integrity_rq(req
)) {
661 if (!rq_data_dir(req
))
662 nvme_dif_remap(req
, nvme_dif_complete
);
663 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
667 nvme_cleanup_cmd(req
);
668 nvme_free_iod(dev
, req
);
672 * NOTE: ns is NULL when called on the admin queue.
674 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
675 const struct blk_mq_queue_data
*bd
)
677 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
678 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
679 struct nvme_dev
*dev
= nvmeq
->dev
;
680 struct request
*req
= bd
->rq
;
681 struct nvme_command cmnd
;
684 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
688 ret
= nvme_init_iod(req
, dev
);
692 if (blk_rq_nr_phys_segments(req
)) {
693 ret
= nvme_map_data(dev
, req
, &cmnd
);
695 goto out_cleanup_iod
;
698 blk_mq_start_request(req
);
700 spin_lock_irq(&nvmeq
->q_lock
);
701 if (unlikely(nvmeq
->cq_vector
< 0)) {
703 spin_unlock_irq(&nvmeq
->q_lock
);
704 goto out_cleanup_iod
;
706 __nvme_submit_cmd(nvmeq
, &cmnd
);
707 nvme_process_cq(nvmeq
);
708 spin_unlock_irq(&nvmeq
->q_lock
);
711 nvme_free_iod(dev
, req
);
713 nvme_cleanup_cmd(req
);
717 static void nvme_pci_complete_rq(struct request
*req
)
719 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
721 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
722 nvme_complete_rq(req
);
725 /* We read the CQE phase first to check if the rest of the entry is valid */
726 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
729 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
732 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
734 u16 head
= nvmeq
->cq_head
;
736 if (likely(nvmeq
->cq_vector
>= 0)) {
737 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
739 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
743 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
,
744 struct nvme_completion
*cqe
)
748 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
749 dev_warn(nvmeq
->dev
->ctrl
.device
,
750 "invalid id %d completed on queue %d\n",
751 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
756 * AEN requests are special as they don't time out and can
757 * survive any kind of queue freeze and often don't respond to
758 * aborts. We don't even bother to allocate a struct request
759 * for them but rather special case them here.
761 if (unlikely(nvmeq
->qid
== 0 &&
762 cqe
->command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
763 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
764 cqe
->status
, &cqe
->result
);
768 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
769 nvme_end_request(req
, cqe
->status
, cqe
->result
);
772 static inline bool nvme_read_cqe(struct nvme_queue
*nvmeq
,
773 struct nvme_completion
*cqe
)
775 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
776 *cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
778 if (++nvmeq
->cq_head
== nvmeq
->q_depth
) {
780 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
787 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
789 struct nvme_completion cqe
;
792 while (nvme_read_cqe(nvmeq
, &cqe
)) {
793 nvme_handle_cqe(nvmeq
, &cqe
);
798 nvme_ring_cq_doorbell(nvmeq
);
803 static irqreturn_t
nvme_irq(int irq
, void *data
)
806 struct nvme_queue
*nvmeq
= data
;
807 spin_lock(&nvmeq
->q_lock
);
808 nvme_process_cq(nvmeq
);
809 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
811 spin_unlock(&nvmeq
->q_lock
);
815 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
817 struct nvme_queue
*nvmeq
= data
;
818 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
819 return IRQ_WAKE_THREAD
;
823 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
825 struct nvme_completion cqe
;
826 int found
= 0, consumed
= 0;
828 if (!nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
831 spin_lock_irq(&nvmeq
->q_lock
);
832 while (nvme_read_cqe(nvmeq
, &cqe
)) {
833 nvme_handle_cqe(nvmeq
, &cqe
);
836 if (tag
== cqe
.command_id
) {
843 nvme_ring_cq_doorbell(nvmeq
);
844 spin_unlock_irq(&nvmeq
->q_lock
);
849 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
851 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
853 return __nvme_poll(nvmeq
, tag
);
856 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
858 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
859 struct nvme_queue
*nvmeq
= dev
->queues
[0];
860 struct nvme_command c
;
862 memset(&c
, 0, sizeof(c
));
863 c
.common
.opcode
= nvme_admin_async_event
;
864 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
866 spin_lock_irq(&nvmeq
->q_lock
);
867 __nvme_submit_cmd(nvmeq
, &c
);
868 spin_unlock_irq(&nvmeq
->q_lock
);
871 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
873 struct nvme_command c
;
875 memset(&c
, 0, sizeof(c
));
876 c
.delete_queue
.opcode
= opcode
;
877 c
.delete_queue
.qid
= cpu_to_le16(id
);
879 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
882 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
883 struct nvme_queue
*nvmeq
)
885 struct nvme_command c
;
886 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
889 * Note: we (ab)use the fact the the prp fields survive if no data
890 * is attached to the request.
892 memset(&c
, 0, sizeof(c
));
893 c
.create_cq
.opcode
= nvme_admin_create_cq
;
894 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
895 c
.create_cq
.cqid
= cpu_to_le16(qid
);
896 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
897 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
898 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
900 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
903 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
904 struct nvme_queue
*nvmeq
)
906 struct nvme_command c
;
907 int flags
= NVME_QUEUE_PHYS_CONTIG
;
910 * Note: we (ab)use the fact the the prp fields survive if no data
911 * is attached to the request.
913 memset(&c
, 0, sizeof(c
));
914 c
.create_sq
.opcode
= nvme_admin_create_sq
;
915 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
916 c
.create_sq
.sqid
= cpu_to_le16(qid
);
917 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
918 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
919 c
.create_sq
.cqid
= cpu_to_le16(qid
);
921 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
924 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
926 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
929 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
931 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
934 static void abort_endio(struct request
*req
, blk_status_t error
)
936 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
937 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
939 dev_warn(nvmeq
->dev
->ctrl
.device
,
940 "Abort status: 0x%x", nvme_req(req
)->status
);
941 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
942 blk_mq_free_request(req
);
945 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
948 /* If true, indicates loss of adapter communication, possibly by a
949 * NVMe Subsystem reset.
951 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
953 /* If there is a reset ongoing, we shouldn't reset again. */
954 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
957 /* We shouldn't reset unless the controller is on fatal error state
958 * _or_ if we lost the communication with it.
960 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
963 /* If PCI error recovery process is happening, we cannot reset or
964 * the recovery mechanism will surely fail.
966 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
972 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
974 /* Read a config register to help see what died. */
978 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
980 if (result
== PCIBIOS_SUCCESSFUL
)
981 dev_warn(dev
->ctrl
.device
,
982 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
985 dev_warn(dev
->ctrl
.device
,
986 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
990 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
992 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
993 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
994 struct nvme_dev
*dev
= nvmeq
->dev
;
995 struct request
*abort_req
;
996 struct nvme_command cmd
;
997 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1000 * Reset immediately if the controller is failed
1002 if (nvme_should_reset(dev
, csts
)) {
1003 nvme_warn_reset(dev
, csts
);
1004 nvme_dev_disable(dev
, false);
1005 nvme_reset_ctrl(&dev
->ctrl
);
1006 return BLK_EH_HANDLED
;
1010 * Did we miss an interrupt?
1012 if (__nvme_poll(nvmeq
, req
->tag
)) {
1013 dev_warn(dev
->ctrl
.device
,
1014 "I/O %d QID %d timeout, completion polled\n",
1015 req
->tag
, nvmeq
->qid
);
1016 return BLK_EH_HANDLED
;
1020 * Shutdown immediately if controller times out while starting. The
1021 * reset work will see the pci device disabled when it gets the forced
1022 * cancellation error. All outstanding requests are completed on
1023 * shutdown, so we return BLK_EH_HANDLED.
1025 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
1026 dev_warn(dev
->ctrl
.device
,
1027 "I/O %d QID %d timeout, disable controller\n",
1028 req
->tag
, nvmeq
->qid
);
1029 nvme_dev_disable(dev
, false);
1030 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1031 return BLK_EH_HANDLED
;
1035 * Shutdown the controller immediately and schedule a reset if the
1036 * command was already aborted once before and still hasn't been
1037 * returned to the driver, or if this is the admin queue.
1039 if (!nvmeq
->qid
|| iod
->aborted
) {
1040 dev_warn(dev
->ctrl
.device
,
1041 "I/O %d QID %d timeout, reset controller\n",
1042 req
->tag
, nvmeq
->qid
);
1043 nvme_dev_disable(dev
, false);
1044 nvme_reset_ctrl(&dev
->ctrl
);
1047 * Mark the request as handled, since the inline shutdown
1048 * forces all outstanding requests to complete.
1050 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1051 return BLK_EH_HANDLED
;
1054 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1055 atomic_inc(&dev
->ctrl
.abort_limit
);
1056 return BLK_EH_RESET_TIMER
;
1060 memset(&cmd
, 0, sizeof(cmd
));
1061 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1062 cmd
.abort
.cid
= req
->tag
;
1063 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1065 dev_warn(nvmeq
->dev
->ctrl
.device
,
1066 "I/O %d QID %d timeout, aborting\n",
1067 req
->tag
, nvmeq
->qid
);
1069 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1070 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1071 if (IS_ERR(abort_req
)) {
1072 atomic_inc(&dev
->ctrl
.abort_limit
);
1073 return BLK_EH_RESET_TIMER
;
1076 abort_req
->timeout
= ADMIN_TIMEOUT
;
1077 abort_req
->end_io_data
= NULL
;
1078 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1081 * The aborted req will be completed on receiving the abort req.
1082 * We enable the timer again. If hit twice, it'll cause a device reset,
1083 * as the device then is in a faulty state.
1085 return BLK_EH_RESET_TIMER
;
1088 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1090 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1091 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1093 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1094 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1098 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1102 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1103 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1105 dev
->queues
[i
] = NULL
;
1106 nvme_free_queue(nvmeq
);
1111 * nvme_suspend_queue - put queue into suspended state
1112 * @nvmeq - queue to suspend
1114 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1118 spin_lock_irq(&nvmeq
->q_lock
);
1119 if (nvmeq
->cq_vector
== -1) {
1120 spin_unlock_irq(&nvmeq
->q_lock
);
1123 vector
= nvmeq
->cq_vector
;
1124 nvmeq
->dev
->online_queues
--;
1125 nvmeq
->cq_vector
= -1;
1126 spin_unlock_irq(&nvmeq
->q_lock
);
1128 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1129 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1131 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1136 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1138 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1142 if (nvme_suspend_queue(nvmeq
))
1146 nvme_shutdown_ctrl(&dev
->ctrl
);
1148 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1149 dev
->bar
+ NVME_REG_CAP
));
1151 spin_lock_irq(&nvmeq
->q_lock
);
1152 nvme_process_cq(nvmeq
);
1153 spin_unlock_irq(&nvmeq
->q_lock
);
1156 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1159 int q_depth
= dev
->q_depth
;
1160 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1161 dev
->ctrl
.page_size
);
1163 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1164 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1165 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1166 q_depth
= div_u64(mem_per_q
, entry_size
);
1169 * Ensure the reduced q_depth is above some threshold where it
1170 * would be better to map queues in system memory with the
1180 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1183 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1184 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1185 dev
->ctrl
.page_size
);
1186 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1187 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1189 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1190 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1191 if (!nvmeq
->sq_cmds
)
1198 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1199 int depth
, int node
)
1201 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1206 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1207 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1211 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1214 nvmeq
->q_dmadev
= dev
->dev
;
1216 spin_lock_init(&nvmeq
->q_lock
);
1218 nvmeq
->cq_phase
= 1;
1219 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1220 nvmeq
->q_depth
= depth
;
1222 nvmeq
->cq_vector
= -1;
1223 dev
->queues
[qid
] = nvmeq
;
1229 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1230 nvmeq
->cq_dma_addr
);
1236 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1238 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1239 int nr
= nvmeq
->dev
->ctrl
.instance
;
1241 if (use_threaded_interrupts
) {
1242 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1243 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1245 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1246 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1250 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1252 struct nvme_dev
*dev
= nvmeq
->dev
;
1254 spin_lock_irq(&nvmeq
->q_lock
);
1257 nvmeq
->cq_phase
= 1;
1258 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1259 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1260 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1261 dev
->online_queues
++;
1262 spin_unlock_irq(&nvmeq
->q_lock
);
1265 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1267 struct nvme_dev
*dev
= nvmeq
->dev
;
1270 nvmeq
->cq_vector
= qid
- 1;
1271 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1275 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1279 result
= queue_request_irq(nvmeq
);
1283 nvme_init_queue(nvmeq
, qid
);
1287 adapter_delete_sq(dev
, qid
);
1289 adapter_delete_cq(dev
, qid
);
1293 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1294 .queue_rq
= nvme_queue_rq
,
1295 .complete
= nvme_pci_complete_rq
,
1296 .init_hctx
= nvme_admin_init_hctx
,
1297 .exit_hctx
= nvme_admin_exit_hctx
,
1298 .init_request
= nvme_init_request
,
1299 .timeout
= nvme_timeout
,
1302 static const struct blk_mq_ops nvme_mq_ops
= {
1303 .queue_rq
= nvme_queue_rq
,
1304 .complete
= nvme_pci_complete_rq
,
1305 .init_hctx
= nvme_init_hctx
,
1306 .init_request
= nvme_init_request
,
1307 .map_queues
= nvme_pci_map_queues
,
1308 .timeout
= nvme_timeout
,
1312 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1314 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1316 * If the controller was reset during removal, it's possible
1317 * user requests may be waiting on a stopped queue. Start the
1318 * queue to flush these to completion.
1320 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1321 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1322 blk_mq_free_tag_set(&dev
->admin_tagset
);
1326 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1328 if (!dev
->ctrl
.admin_q
) {
1329 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1330 dev
->admin_tagset
.nr_hw_queues
= 1;
1333 * Subtract one to leave an empty queue entry for 'Full Queue'
1334 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1336 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1337 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1338 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1339 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1340 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1341 dev
->admin_tagset
.driver_data
= dev
;
1343 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1346 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1347 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1348 blk_mq_free_tag_set(&dev
->admin_tagset
);
1351 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1352 nvme_dev_remove_admin(dev
);
1353 dev
->ctrl
.admin_q
= NULL
;
1357 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1362 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1364 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1367 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1369 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1371 if (size
<= dev
->bar_mapped_size
)
1373 if (size
> pci_resource_len(pdev
, 0))
1377 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1379 dev
->bar_mapped_size
= 0;
1382 dev
->bar_mapped_size
= size
;
1383 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1388 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1392 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1393 struct nvme_queue
*nvmeq
;
1395 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1399 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1400 NVME_CAP_NSSRC(cap
) : 0;
1402 if (dev
->subsystem
&&
1403 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1404 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1406 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1410 nvmeq
= dev
->queues
[0];
1412 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1413 dev_to_node(dev
->dev
));
1418 aqa
= nvmeq
->q_depth
- 1;
1421 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1422 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1423 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1425 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1429 nvmeq
->cq_vector
= 0;
1430 result
= queue_request_irq(nvmeq
);
1432 nvmeq
->cq_vector
= -1;
1439 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1444 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1445 /* vector == qid - 1, match nvme_create_queue */
1446 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1447 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1453 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1454 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1455 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1461 * Ignore failing Create SQ/CQ commands, we can continue with less
1462 * than the desired aount of queues, and even a controller without
1463 * I/O queues an still be used to issue admin commands. This might
1464 * be useful to upgrade a buggy firmware for example.
1466 return ret
>= 0 ? 0 : ret
;
1469 static ssize_t
nvme_cmb_show(struct device
*dev
,
1470 struct device_attribute
*attr
,
1473 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1475 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1476 ndev
->cmbloc
, ndev
->cmbsz
);
1478 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1480 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1482 u64 szu
, size
, offset
;
1483 resource_size_t bar_size
;
1484 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1486 dma_addr_t dma_addr
;
1488 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1489 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1491 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1496 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1497 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1498 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1499 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1501 if (offset
> bar_size
)
1505 * Controllers may support a CMB size larger than their BAR,
1506 * for example, due to being behind a bridge. Reduce the CMB to
1507 * the reported size of the BAR
1509 if (size
> bar_size
- offset
)
1510 size
= bar_size
- offset
;
1512 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1513 cmb
= ioremap_wc(dma_addr
, size
);
1517 dev
->cmb_dma_addr
= dma_addr
;
1518 dev
->cmb_size
= size
;
1522 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1528 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1529 &dev_attr_cmb
.attr
, NULL
);
1535 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1537 size_t len
= dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
);
1538 struct nvme_command c
;
1542 dma_addr
= dma_map_single(dev
->dev
, dev
->host_mem_descs
, len
,
1544 if (dma_mapping_error(dev
->dev
, dma_addr
))
1547 memset(&c
, 0, sizeof(c
));
1548 c
.features
.opcode
= nvme_admin_set_features
;
1549 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1550 c
.features
.dword11
= cpu_to_le32(bits
);
1551 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1552 ilog2(dev
->ctrl
.page_size
));
1553 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1554 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1555 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1557 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1559 dev_warn(dev
->ctrl
.device
,
1560 "failed to set host mem (err %d, flags %#x).\n",
1563 dma_unmap_single(dev
->dev
, dma_addr
, len
, DMA_TO_DEVICE
);
1567 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1571 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1572 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1573 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1575 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1576 le64_to_cpu(desc
->addr
));
1579 kfree(dev
->host_mem_desc_bufs
);
1580 dev
->host_mem_desc_bufs
= NULL
;
1581 kfree(dev
->host_mem_descs
);
1582 dev
->host_mem_descs
= NULL
;
1585 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1587 struct nvme_host_mem_buf_desc
*descs
;
1588 u32 chunk_size
, max_entries
, i
= 0;
1592 /* start big and work our way down */
1593 chunk_size
= min(preferred
, (u64
)PAGE_SIZE
<< MAX_ORDER
);
1595 tmp
= (preferred
+ chunk_size
- 1);
1596 do_div(tmp
, chunk_size
);
1598 descs
= kcalloc(max_entries
, sizeof(*descs
), GFP_KERNEL
);
1602 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1604 goto out_free_descs
;
1606 for (size
= 0; size
< preferred
; size
+= chunk_size
) {
1607 u32 len
= min_t(u64
, chunk_size
, preferred
- size
);
1608 dma_addr_t dma_addr
;
1610 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1611 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1615 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1616 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1620 if (!size
|| (min
&& size
< min
)) {
1621 dev_warn(dev
->ctrl
.device
,
1622 "failed to allocate host memory buffer.\n");
1626 dev_info(dev
->ctrl
.device
,
1627 "allocated %lld MiB host memory buffer.\n",
1628 size
>> ilog2(SZ_1M
));
1629 dev
->nr_host_mem_descs
= i
;
1630 dev
->host_mem_size
= size
;
1631 dev
->host_mem_descs
= descs
;
1632 dev
->host_mem_desc_bufs
= bufs
;
1637 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1639 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1640 le64_to_cpu(descs
[i
].addr
));
1647 /* try a smaller chunk size if we failed early */
1648 if (chunk_size
>= PAGE_SIZE
* 2 && (i
== 0 || size
< min
)) {
1652 dev
->host_mem_descs
= NULL
;
1656 static void nvme_setup_host_mem(struct nvme_dev
*dev
)
1658 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1659 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1660 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1661 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1663 preferred
= min(preferred
, max
);
1665 dev_warn(dev
->ctrl
.device
,
1666 "min host memory (%lld MiB) above limit (%d MiB).\n",
1667 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1668 nvme_free_host_mem(dev
);
1673 * If we already have a buffer allocated check if we can reuse it.
1675 if (dev
->host_mem_descs
) {
1676 if (dev
->host_mem_size
>= min
)
1677 enable_bits
|= NVME_HOST_MEM_RETURN
;
1679 nvme_free_host_mem(dev
);
1682 if (!dev
->host_mem_descs
) {
1683 if (nvme_alloc_host_mem(dev
, min
, preferred
))
1687 if (nvme_set_host_mem(dev
, enable_bits
))
1688 nvme_free_host_mem(dev
);
1691 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1693 struct nvme_queue
*adminq
= dev
->queues
[0];
1694 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1695 int result
, nr_io_queues
;
1698 nr_io_queues
= num_present_cpus();
1699 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1703 if (nr_io_queues
== 0)
1706 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1707 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1708 sizeof(struct nvme_command
));
1710 dev
->q_depth
= result
;
1712 nvme_release_cmb(dev
);
1716 size
= db_bar_size(dev
, nr_io_queues
);
1717 result
= nvme_remap_bar(dev
, size
);
1720 if (!--nr_io_queues
)
1723 adminq
->q_db
= dev
->dbs
;
1725 /* Deregister the admin queue's interrupt */
1726 pci_free_irq(pdev
, 0, adminq
);
1729 * If we enable msix early due to not intx, disable it again before
1730 * setting up the full range we need.
1732 pci_free_irq_vectors(pdev
);
1733 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1734 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1735 if (nr_io_queues
<= 0)
1737 dev
->max_qid
= nr_io_queues
;
1740 * Should investigate if there's a performance win from allocating
1741 * more queues than interrupt vectors; it might allow the submission
1742 * path to scale better, even if the receive path is limited by the
1743 * number of interrupts.
1746 result
= queue_request_irq(adminq
);
1748 adminq
->cq_vector
= -1;
1751 return nvme_create_io_queues(dev
);
1754 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1756 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1758 blk_mq_free_request(req
);
1759 complete(&nvmeq
->dev
->ioq_wait
);
1762 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1764 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1767 unsigned long flags
;
1770 * We might be called with the AQ q_lock held
1771 * and the I/O queue q_lock should always
1772 * nest inside the AQ one.
1774 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1775 SINGLE_DEPTH_NESTING
);
1776 nvme_process_cq(nvmeq
);
1777 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1780 nvme_del_queue_end(req
, error
);
1783 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1785 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1786 struct request
*req
;
1787 struct nvme_command cmd
;
1789 memset(&cmd
, 0, sizeof(cmd
));
1790 cmd
.delete_queue
.opcode
= opcode
;
1791 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1793 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1795 return PTR_ERR(req
);
1797 req
->timeout
= ADMIN_TIMEOUT
;
1798 req
->end_io_data
= nvmeq
;
1800 blk_execute_rq_nowait(q
, NULL
, req
, false,
1801 opcode
== nvme_admin_delete_cq
?
1802 nvme_del_cq_end
: nvme_del_queue_end
);
1806 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1809 unsigned long timeout
;
1810 u8 opcode
= nvme_admin_delete_sq
;
1812 for (pass
= 0; pass
< 2; pass
++) {
1813 int sent
= 0, i
= queues
;
1815 reinit_completion(&dev
->ioq_wait
);
1817 timeout
= ADMIN_TIMEOUT
;
1818 for (; i
> 0; i
--, sent
++)
1819 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1823 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1829 opcode
= nvme_admin_delete_cq
;
1834 * Return: error value if an error occurred setting up the queues or calling
1835 * Identify Device. 0 if these succeeded, even if adding some of the
1836 * namespaces failed. At the moment, these failures are silent. TBD which
1837 * failures should be reported.
1839 static int nvme_dev_add(struct nvme_dev
*dev
)
1841 if (!dev
->ctrl
.tagset
) {
1842 dev
->tagset
.ops
= &nvme_mq_ops
;
1843 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1844 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1845 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1846 dev
->tagset
.queue_depth
=
1847 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1848 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1849 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1850 dev
->tagset
.driver_data
= dev
;
1852 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1854 dev
->ctrl
.tagset
= &dev
->tagset
;
1856 nvme_dbbuf_set(dev
);
1858 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1860 /* Free previously allocated queues that are no longer usable */
1861 nvme_free_queues(dev
, dev
->online_queues
);
1867 static int nvme_pci_enable(struct nvme_dev
*dev
)
1870 int result
= -ENOMEM
;
1871 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1873 if (pci_enable_device_mem(pdev
))
1876 pci_set_master(pdev
);
1878 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1879 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1882 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1888 * Some devices and/or platforms don't advertise or work with INTx
1889 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1890 * adjust this later.
1892 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1896 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1898 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1899 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1900 dev
->dbs
= dev
->bar
+ 4096;
1903 * Temporary fix for the Apple controller found in the MacBook8,1 and
1904 * some MacBook7,1 to avoid controller resets and data loss.
1906 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1908 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
1909 "set queue depth=%u to work around controller resets\n",
1914 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1915 * populate sysfs if a CMB is implemented. Note that we add the
1916 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1917 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1918 * NULL as final argument to sysfs_add_file_to_group.
1921 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1922 dev
->cmb
= nvme_map_cmb(dev
);
1925 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1926 &dev_attr_cmb
.attr
, NULL
))
1927 dev_warn(dev
->ctrl
.device
,
1928 "failed to add sysfs attribute for CMB\n");
1932 pci_enable_pcie_error_reporting(pdev
);
1933 pci_save_state(pdev
);
1937 pci_disable_device(pdev
);
1941 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1945 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1948 static void nvme_pci_disable(struct nvme_dev
*dev
)
1950 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1952 nvme_release_cmb(dev
);
1953 pci_free_irq_vectors(pdev
);
1955 if (pci_is_enabled(pdev
)) {
1956 pci_disable_pcie_error_reporting(pdev
);
1957 pci_disable_device(pdev
);
1961 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1965 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1967 mutex_lock(&dev
->shutdown_lock
);
1968 if (pci_is_enabled(pdev
)) {
1969 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1971 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
1972 dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
1973 nvme_start_freeze(&dev
->ctrl
);
1974 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
1975 pdev
->error_state
!= pci_channel_io_normal
);
1979 * Give the controller a chance to complete all entered requests if
1980 * doing a safe shutdown.
1984 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
1987 * If the controller is still alive tell it to stop using the
1988 * host memory buffer. In theory the shutdown / reset should
1989 * make sure that it doesn't access the host memoery anymore,
1990 * but I'd rather be safe than sorry..
1992 if (dev
->host_mem_descs
)
1993 nvme_set_host_mem(dev
, 0);
1996 nvme_stop_queues(&dev
->ctrl
);
1998 queues
= dev
->online_queues
- 1;
1999 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
2000 nvme_suspend_queue(dev
->queues
[i
]);
2003 /* A device might become IO incapable very soon during
2004 * probe, before the admin queue is configured. Thus,
2005 * queue_count can be 0 here.
2007 if (dev
->queue_count
)
2008 nvme_suspend_queue(dev
->queues
[0]);
2010 nvme_disable_io_queues(dev
, queues
);
2011 nvme_disable_admin_queue(dev
, shutdown
);
2013 nvme_pci_disable(dev
);
2015 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2016 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2019 * The driver will not be starting up queues again if shutting down so
2020 * must flush all entered requests to their failed completion to avoid
2021 * deadlocking blk-mq hot-cpu notifier.
2024 nvme_start_queues(&dev
->ctrl
);
2025 mutex_unlock(&dev
->shutdown_lock
);
2028 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2030 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2031 PAGE_SIZE
, PAGE_SIZE
, 0);
2032 if (!dev
->prp_page_pool
)
2035 /* Optimisation for I/Os between 4k and 128k */
2036 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2038 if (!dev
->prp_small_pool
) {
2039 dma_pool_destroy(dev
->prp_page_pool
);
2045 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2047 dma_pool_destroy(dev
->prp_page_pool
);
2048 dma_pool_destroy(dev
->prp_small_pool
);
2051 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2053 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2055 nvme_dbbuf_dma_free(dev
);
2056 put_device(dev
->dev
);
2057 if (dev
->tagset
.tags
)
2058 blk_mq_free_tag_set(&dev
->tagset
);
2059 if (dev
->ctrl
.admin_q
)
2060 blk_put_queue(dev
->ctrl
.admin_q
);
2062 free_opal_dev(dev
->ctrl
.opal_dev
);
2066 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2068 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2070 kref_get(&dev
->ctrl
.kref
);
2071 nvme_dev_disable(dev
, false);
2072 if (!schedule_work(&dev
->remove_work
))
2073 nvme_put_ctrl(&dev
->ctrl
);
2076 static void nvme_reset_work(struct work_struct
*work
)
2078 struct nvme_dev
*dev
=
2079 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2080 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2081 int result
= -ENODEV
;
2083 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2087 * If we're called to reset a live controller first shut it down before
2090 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2091 nvme_dev_disable(dev
, false);
2093 result
= nvme_pci_enable(dev
);
2097 result
= nvme_configure_admin_queue(dev
);
2101 nvme_init_queue(dev
->queues
[0], 0);
2102 result
= nvme_alloc_admin_tags(dev
);
2106 result
= nvme_init_identify(&dev
->ctrl
);
2110 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2111 if (!dev
->ctrl
.opal_dev
)
2112 dev
->ctrl
.opal_dev
=
2113 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2114 else if (was_suspend
)
2115 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2117 free_opal_dev(dev
->ctrl
.opal_dev
);
2118 dev
->ctrl
.opal_dev
= NULL
;
2121 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2122 result
= nvme_dbbuf_dma_alloc(dev
);
2125 "unable to allocate dma for dbbuf\n");
2128 if (dev
->ctrl
.hmpre
)
2129 nvme_setup_host_mem(dev
);
2131 result
= nvme_setup_io_queues(dev
);
2136 * A controller that can not execute IO typically requires user
2137 * intervention to correct. For such degraded controllers, the driver
2138 * should not submit commands the user did not request, so skip
2139 * registering for asynchronous event notification on this condition.
2141 if (dev
->online_queues
> 1)
2142 nvme_queue_async_events(&dev
->ctrl
);
2145 * Keep the controller around but remove all namespaces if we don't have
2146 * any working I/O queue.
2148 if (dev
->online_queues
< 2) {
2149 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2150 nvme_kill_queues(&dev
->ctrl
);
2151 nvme_remove_namespaces(&dev
->ctrl
);
2153 nvme_start_queues(&dev
->ctrl
);
2154 nvme_wait_freeze(&dev
->ctrl
);
2156 nvme_unfreeze(&dev
->ctrl
);
2159 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2160 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2164 if (dev
->online_queues
> 1)
2165 nvme_queue_scan(&dev
->ctrl
);
2169 nvme_remove_dead_ctrl(dev
, result
);
2172 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2174 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2175 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2177 nvme_kill_queues(&dev
->ctrl
);
2178 if (pci_get_drvdata(pdev
))
2179 device_release_driver(&pdev
->dev
);
2180 nvme_put_ctrl(&dev
->ctrl
);
2183 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2185 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2189 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2191 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2195 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2197 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2201 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2203 .module
= THIS_MODULE
,
2204 .flags
= NVME_F_METADATA_SUPPORTED
,
2205 .reg_read32
= nvme_pci_reg_read32
,
2206 .reg_write32
= nvme_pci_reg_write32
,
2207 .reg_read64
= nvme_pci_reg_read64
,
2208 .free_ctrl
= nvme_pci_free_ctrl
,
2209 .submit_async_event
= nvme_pci_submit_async_event
,
2212 static int nvme_dev_map(struct nvme_dev
*dev
)
2214 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2216 if (pci_request_mem_regions(pdev
, "nvme"))
2219 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2224 pci_release_mem_regions(pdev
);
2228 static unsigned long check_dell_samsung_bug(struct pci_dev
*pdev
)
2230 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2232 * Several Samsung devices seem to drop off the PCIe bus
2233 * randomly when APST is on and uses the deepest sleep state.
2234 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2235 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2236 * 950 PRO 256GB", but it seems to be restricted to two Dell
2239 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2240 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2241 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2242 return NVME_QUIRK_NO_DEEPEST_PS
;
2248 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2250 int node
, result
= -ENOMEM
;
2251 struct nvme_dev
*dev
;
2252 unsigned long quirks
= id
->driver_data
;
2254 node
= dev_to_node(&pdev
->dev
);
2255 if (node
== NUMA_NO_NODE
)
2256 set_dev_node(&pdev
->dev
, first_memory_node
);
2258 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2261 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2266 dev
->dev
= get_device(&pdev
->dev
);
2267 pci_set_drvdata(pdev
, dev
);
2269 result
= nvme_dev_map(dev
);
2273 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2274 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2275 mutex_init(&dev
->shutdown_lock
);
2276 init_completion(&dev
->ioq_wait
);
2278 result
= nvme_setup_prp_pools(dev
);
2282 quirks
|= check_dell_samsung_bug(pdev
);
2284 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2289 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2290 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2292 queue_work(nvme_wq
, &dev
->ctrl
.reset_work
);
2296 nvme_release_prp_pools(dev
);
2298 put_device(dev
->dev
);
2299 nvme_dev_unmap(dev
);
2306 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2308 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2309 nvme_dev_disable(dev
, false);
2312 static void nvme_reset_done(struct pci_dev
*pdev
)
2314 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2315 nvme_reset_ctrl(&dev
->ctrl
);
2318 static void nvme_shutdown(struct pci_dev
*pdev
)
2320 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2321 nvme_dev_disable(dev
, true);
2325 * The driver's remove may be called on a device in a partially initialized
2326 * state. This function must not have any dependencies on the device state in
2329 static void nvme_remove(struct pci_dev
*pdev
)
2331 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2333 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2335 cancel_work_sync(&dev
->ctrl
.reset_work
);
2336 pci_set_drvdata(pdev
, NULL
);
2338 if (!pci_device_is_present(pdev
)) {
2339 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2340 nvme_dev_disable(dev
, false);
2343 flush_work(&dev
->ctrl
.reset_work
);
2344 nvme_uninit_ctrl(&dev
->ctrl
);
2345 nvme_dev_disable(dev
, true);
2346 nvme_free_host_mem(dev
);
2347 nvme_dev_remove_admin(dev
);
2348 nvme_free_queues(dev
, 0);
2349 nvme_release_prp_pools(dev
);
2350 nvme_dev_unmap(dev
);
2351 nvme_put_ctrl(&dev
->ctrl
);
2354 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2359 if (pci_vfs_assigned(pdev
)) {
2360 dev_warn(&pdev
->dev
,
2361 "Cannot disable SR-IOV VFs while assigned\n");
2364 pci_disable_sriov(pdev
);
2368 ret
= pci_enable_sriov(pdev
, numvfs
);
2369 return ret
? ret
: numvfs
;
2372 #ifdef CONFIG_PM_SLEEP
2373 static int nvme_suspend(struct device
*dev
)
2375 struct pci_dev
*pdev
= to_pci_dev(dev
);
2376 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2378 nvme_dev_disable(ndev
, true);
2382 static int nvme_resume(struct device
*dev
)
2384 struct pci_dev
*pdev
= to_pci_dev(dev
);
2385 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2387 nvme_reset_ctrl(&ndev
->ctrl
);
2392 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2394 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2395 pci_channel_state_t state
)
2397 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2400 * A frozen channel requires a reset. When detected, this method will
2401 * shutdown the controller to quiesce. The controller will be restarted
2402 * after the slot reset through driver's slot_reset callback.
2405 case pci_channel_io_normal
:
2406 return PCI_ERS_RESULT_CAN_RECOVER
;
2407 case pci_channel_io_frozen
:
2408 dev_warn(dev
->ctrl
.device
,
2409 "frozen state error detected, reset controller\n");
2410 nvme_dev_disable(dev
, false);
2411 return PCI_ERS_RESULT_NEED_RESET
;
2412 case pci_channel_io_perm_failure
:
2413 dev_warn(dev
->ctrl
.device
,
2414 "failure state error detected, request disconnect\n");
2415 return PCI_ERS_RESULT_DISCONNECT
;
2417 return PCI_ERS_RESULT_NEED_RESET
;
2420 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2422 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2424 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2425 pci_restore_state(pdev
);
2426 nvme_reset_ctrl(&dev
->ctrl
);
2427 return PCI_ERS_RESULT_RECOVERED
;
2430 static void nvme_error_resume(struct pci_dev
*pdev
)
2432 pci_cleanup_aer_uncorrect_error_status(pdev
);
2435 static const struct pci_error_handlers nvme_err_handler
= {
2436 .error_detected
= nvme_error_detected
,
2437 .slot_reset
= nvme_slot_reset
,
2438 .resume
= nvme_error_resume
,
2439 .reset_prepare
= nvme_reset_prepare
,
2440 .reset_done
= nvme_reset_done
,
2443 static const struct pci_device_id nvme_id_table
[] = {
2444 { PCI_VDEVICE(INTEL
, 0x0953),
2445 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2446 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2447 { PCI_VDEVICE(INTEL
, 0x0a53),
2448 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2449 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2450 { PCI_VDEVICE(INTEL
, 0x0a54),
2451 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2452 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2453 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2454 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
},
2455 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2456 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2457 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2458 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2459 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2460 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2461 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2462 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2463 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2466 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2468 static struct pci_driver nvme_driver
= {
2470 .id_table
= nvme_id_table
,
2471 .probe
= nvme_probe
,
2472 .remove
= nvme_remove
,
2473 .shutdown
= nvme_shutdown
,
2475 .pm
= &nvme_dev_pm_ops
,
2477 .sriov_configure
= nvme_pci_sriov_configure
,
2478 .err_handler
= &nvme_err_handler
,
2481 static int __init
nvme_init(void)
2483 return pci_register_driver(&nvme_driver
);
2486 static void __exit
nvme_exit(void)
2488 pci_unregister_driver(&nvme_driver
);
2492 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2493 MODULE_LICENSE("GPL");
2494 MODULE_VERSION("1.0");
2495 module_init(nvme_init
);
2496 module_exit(nvme_exit
);