1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
43 static int use_threaded_interrupts
;
44 module_param(use_threaded_interrupts
, int, 0);
46 static bool use_cmb_sqes
= true;
47 module_param(use_cmb_sqes
, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
50 static unsigned int max_host_mem_size_mb
= 128;
51 module_param(max_host_mem_size_mb
, uint
, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb
,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
55 static unsigned int sgl_threshold
= SZ_32K
;
56 module_param(sgl_threshold
, uint
, 0644);
57 MODULE_PARM_DESC(sgl_threshold
,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
61 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
62 static const struct kernel_param_ops io_queue_depth_ops
= {
63 .set
= io_queue_depth_set
,
67 static int io_queue_depth
= 1024;
68 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
69 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
71 static int write_queues
;
72 module_param(write_queues
, int, 0644);
73 MODULE_PARM_DESC(write_queues
,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
77 static int poll_queues
;
78 module_param(poll_queues
, int, 0644);
79 MODULE_PARM_DESC(poll_queues
, "Number of queues to use for polled IO.");
84 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
85 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
);
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
91 struct nvme_queue
*queues
;
92 struct blk_mq_tag_set tagset
;
93 struct blk_mq_tag_set admin_tagset
;
96 struct dma_pool
*prp_page_pool
;
97 struct dma_pool
*prp_small_pool
;
98 unsigned online_queues
;
100 unsigned io_queues
[HCTX_MAX_TYPES
];
101 unsigned int num_vecs
;
106 unsigned long bar_mapped_size
;
107 struct work_struct remove_work
;
108 struct mutex shutdown_lock
;
114 struct nvme_ctrl ctrl
;
117 mempool_t
*iod_mempool
;
119 /* shadow doorbell buffer support: */
121 dma_addr_t dbbuf_dbs_dma_addr
;
123 dma_addr_t dbbuf_eis_dma_addr
;
125 /* host memory buffer support: */
127 u32 nr_host_mem_descs
;
128 dma_addr_t host_mem_descs_dma
;
129 struct nvme_host_mem_buf_desc
*host_mem_descs
;
130 void **host_mem_desc_bufs
;
133 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
137 ret
= kstrtoint(val
, 10, &n
);
138 if (ret
!= 0 || n
< 2)
141 return param_set_int(val
, kp
);
144 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
146 return qid
* 2 * stride
;
149 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
151 return (qid
* 2 + 1) * stride
;
154 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
156 return container_of(ctrl
, struct nvme_dev
, ctrl
);
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
164 struct nvme_dev
*dev
;
167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp
;
169 volatile struct nvme_completion
*cqes
;
170 struct blk_mq_tags
**tags
;
171 dma_addr_t sq_dma_addr
;
172 dma_addr_t cq_dma_addr
;
184 #define NVMEQ_ENABLED 0
185 #define NVMEQ_SQ_CMB 1
186 #define NVMEQ_DELETE_ERROR 2
187 #define NVMEQ_POLLED 3
192 struct completion delete_done
;
196 * The nvme_iod describes the data in an I/O.
198 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
199 * to the actual struct scatterlist.
202 struct nvme_request req
;
203 struct nvme_queue
*nvmeq
;
206 int npages
; /* In the PRP list. 0 means small pool in use */
207 int nents
; /* Used in scatterlist */
208 dma_addr_t first_dma
;
209 unsigned int dma_len
; /* length of single DMA segment mapping */
211 struct scatterlist
*sg
;
214 static unsigned int max_io_queues(void)
216 return num_possible_cpus() + write_queues
+ poll_queues
;
219 static unsigned int max_queue_count(void)
221 /* IO queues + admin queue */
222 return 1 + max_io_queues();
225 static inline unsigned int nvme_dbbuf_size(u32 stride
)
227 return (max_queue_count() * 8 * stride
);
230 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
232 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
237 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
238 &dev
->dbbuf_dbs_dma_addr
,
242 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
243 &dev
->dbbuf_eis_dma_addr
,
245 if (!dev
->dbbuf_eis
) {
246 dma_free_coherent(dev
->dev
, mem_size
,
247 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
248 dev
->dbbuf_dbs
= NULL
;
255 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
257 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
259 if (dev
->dbbuf_dbs
) {
260 dma_free_coherent(dev
->dev
, mem_size
,
261 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
262 dev
->dbbuf_dbs
= NULL
;
264 if (dev
->dbbuf_eis
) {
265 dma_free_coherent(dev
->dev
, mem_size
,
266 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
267 dev
->dbbuf_eis
= NULL
;
271 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
272 struct nvme_queue
*nvmeq
, int qid
)
274 if (!dev
->dbbuf_dbs
|| !qid
)
277 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
278 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
279 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
280 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
283 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
285 struct nvme_command c
;
290 memset(&c
, 0, sizeof(c
));
291 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
292 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
293 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
295 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
296 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
297 /* Free memory and continue on */
298 nvme_dbbuf_dma_free(dev
);
302 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
304 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
307 /* Update dbbuf and return true if an MMIO is required */
308 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
309 volatile u32
*dbbuf_ei
)
315 * Ensure that the queue is written before updating
316 * the doorbell in memory
320 old_value
= *dbbuf_db
;
324 * Ensure that the doorbell is updated before reading the event
325 * index from memory. The controller needs to provide similar
326 * ordering to ensure the envent index is updated before reading
331 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
339 * Will slightly overestimate the number of pages needed. This is OK
340 * as it only leads to a small amount of wasted memory for the lifetime of
343 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
345 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
346 dev
->ctrl
.page_size
);
347 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
351 * Calculates the number of pages needed for the SGL segments. For example a 4k
352 * page can accommodate 256 SGL descriptors.
354 static int nvme_pci_npages_sgl(unsigned int num_seg
)
356 return DIV_ROUND_UP(num_seg
* sizeof(struct nvme_sgl_desc
), PAGE_SIZE
);
359 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev
*dev
,
360 unsigned int size
, unsigned int nseg
, bool use_sgl
)
365 alloc_size
= sizeof(__le64
*) * nvme_pci_npages_sgl(nseg
);
367 alloc_size
= sizeof(__le64
*) * nvme_npages(size
, dev
);
369 return alloc_size
+ sizeof(struct scatterlist
) * nseg
;
372 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
373 unsigned int hctx_idx
)
375 struct nvme_dev
*dev
= data
;
376 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
378 WARN_ON(hctx_idx
!= 0);
379 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
380 WARN_ON(nvmeq
->tags
);
382 hctx
->driver_data
= nvmeq
;
383 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
387 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
389 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
394 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
395 unsigned int hctx_idx
)
397 struct nvme_dev
*dev
= data
;
398 struct nvme_queue
*nvmeq
= &dev
->queues
[hctx_idx
+ 1];
401 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
403 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
404 hctx
->driver_data
= nvmeq
;
408 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
409 unsigned int hctx_idx
, unsigned int numa_node
)
411 struct nvme_dev
*dev
= set
->driver_data
;
412 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
413 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
414 struct nvme_queue
*nvmeq
= &dev
->queues
[queue_idx
];
419 nvme_req(req
)->ctrl
= &dev
->ctrl
;
423 static int queue_irq_offset(struct nvme_dev
*dev
)
425 /* if we have more than 1 vec, admin queue offsets us by 1 */
426 if (dev
->num_vecs
> 1)
432 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
434 struct nvme_dev
*dev
= set
->driver_data
;
437 offset
= queue_irq_offset(dev
);
438 for (i
= 0, qoff
= 0; i
< set
->nr_maps
; i
++) {
439 struct blk_mq_queue_map
*map
= &set
->map
[i
];
441 map
->nr_queues
= dev
->io_queues
[i
];
442 if (!map
->nr_queues
) {
443 BUG_ON(i
== HCTX_TYPE_DEFAULT
);
448 * The poll queue(s) doesn't have an IRQ (and hence IRQ
449 * affinity), so use the regular blk-mq cpu mapping
451 map
->queue_offset
= qoff
;
452 if (i
!= HCTX_TYPE_POLL
&& offset
)
453 blk_mq_pci_map_queues(map
, to_pci_dev(dev
->dev
), offset
);
455 blk_mq_map_queues(map
);
456 qoff
+= map
->nr_queues
;
457 offset
+= map
->nr_queues
;
464 * Write sq tail if we are asked to, or if the next command would wrap.
466 static inline void nvme_write_sq_db(struct nvme_queue
*nvmeq
, bool write_sq
)
469 u16 next_tail
= nvmeq
->sq_tail
+ 1;
471 if (next_tail
== nvmeq
->q_depth
)
473 if (next_tail
!= nvmeq
->last_sq_tail
)
477 if (nvme_dbbuf_update_and_check_event(nvmeq
->sq_tail
,
478 nvmeq
->dbbuf_sq_db
, nvmeq
->dbbuf_sq_ei
))
479 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
480 nvmeq
->last_sq_tail
= nvmeq
->sq_tail
;
484 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
485 * @nvmeq: The queue to use
486 * @cmd: The command to send
487 * @write_sq: whether to write to the SQ doorbell
489 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
,
492 spin_lock(&nvmeq
->sq_lock
);
493 memcpy(nvmeq
->sq_cmds
+ (nvmeq
->sq_tail
<< nvmeq
->sqes
),
495 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
497 nvme_write_sq_db(nvmeq
, write_sq
);
498 spin_unlock(&nvmeq
->sq_lock
);
501 static void nvme_commit_rqs(struct blk_mq_hw_ctx
*hctx
)
503 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
505 spin_lock(&nvmeq
->sq_lock
);
506 if (nvmeq
->sq_tail
!= nvmeq
->last_sq_tail
)
507 nvme_write_sq_db(nvmeq
, true);
508 spin_unlock(&nvmeq
->sq_lock
);
511 static void **nvme_pci_iod_list(struct request
*req
)
513 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
514 return (void **)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
517 static inline bool nvme_pci_use_sgls(struct nvme_dev
*dev
, struct request
*req
)
519 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
520 int nseg
= blk_rq_nr_phys_segments(req
);
521 unsigned int avg_seg_size
;
526 avg_seg_size
= DIV_ROUND_UP(blk_rq_payload_bytes(req
), nseg
);
528 if (!(dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))))
530 if (!iod
->nvmeq
->qid
)
532 if (!sgl_threshold
|| avg_seg_size
< sgl_threshold
)
537 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
539 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
540 const int last_prp
= dev
->ctrl
.page_size
/ sizeof(__le64
) - 1;
541 dma_addr_t dma_addr
= iod
->first_dma
, next_dma_addr
;
545 dma_unmap_page(dev
->dev
, dma_addr
, iod
->dma_len
,
550 WARN_ON_ONCE(!iod
->nents
);
552 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
553 pci_p2pdma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
,
556 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, rq_dma_dir(req
));
559 if (iod
->npages
== 0)
560 dma_pool_free(dev
->prp_small_pool
, nvme_pci_iod_list(req
)[0],
563 for (i
= 0; i
< iod
->npages
; i
++) {
564 void *addr
= nvme_pci_iod_list(req
)[i
];
567 struct nvme_sgl_desc
*sg_list
= addr
;
570 le64_to_cpu((sg_list
[SGES_PER_PAGE
- 1]).addr
);
572 __le64
*prp_list
= addr
;
574 next_dma_addr
= le64_to_cpu(prp_list
[last_prp
]);
577 dma_pool_free(dev
->prp_page_pool
, addr
, dma_addr
);
578 dma_addr
= next_dma_addr
;
581 mempool_free(iod
->sg
, dev
->iod_mempool
);
584 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
587 struct scatterlist
*sg
;
589 for_each_sg(sgl
, sg
, nents
, i
) {
590 dma_addr_t phys
= sg_phys(sg
);
591 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
592 "dma_address:%pad dma_length:%d\n",
593 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
598 static blk_status_t
nvme_pci_setup_prps(struct nvme_dev
*dev
,
599 struct request
*req
, struct nvme_rw_command
*cmnd
)
601 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
602 struct dma_pool
*pool
;
603 int length
= blk_rq_payload_bytes(req
);
604 struct scatterlist
*sg
= iod
->sg
;
605 int dma_len
= sg_dma_len(sg
);
606 u64 dma_addr
= sg_dma_address(sg
);
607 u32 page_size
= dev
->ctrl
.page_size
;
608 int offset
= dma_addr
& (page_size
- 1);
610 void **list
= nvme_pci_iod_list(req
);
614 length
-= (page_size
- offset
);
620 dma_len
-= (page_size
- offset
);
622 dma_addr
+= (page_size
- offset
);
625 dma_addr
= sg_dma_address(sg
);
626 dma_len
= sg_dma_len(sg
);
629 if (length
<= page_size
) {
630 iod
->first_dma
= dma_addr
;
634 nprps
= DIV_ROUND_UP(length
, page_size
);
635 if (nprps
<= (256 / 8)) {
636 pool
= dev
->prp_small_pool
;
639 pool
= dev
->prp_page_pool
;
643 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
645 iod
->first_dma
= dma_addr
;
647 return BLK_STS_RESOURCE
;
650 iod
->first_dma
= prp_dma
;
653 if (i
== page_size
>> 3) {
654 __le64
*old_prp_list
= prp_list
;
655 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
657 return BLK_STS_RESOURCE
;
658 list
[iod
->npages
++] = prp_list
;
659 prp_list
[0] = old_prp_list
[i
- 1];
660 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
663 prp_list
[i
++] = cpu_to_le64(dma_addr
);
664 dma_len
-= page_size
;
665 dma_addr
+= page_size
;
671 if (unlikely(dma_len
< 0))
674 dma_addr
= sg_dma_address(sg
);
675 dma_len
= sg_dma_len(sg
);
679 cmnd
->dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
680 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
685 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
686 "Invalid SGL for payload:%d nents:%d\n",
687 blk_rq_payload_bytes(req
), iod
->nents
);
688 return BLK_STS_IOERR
;
691 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc
*sge
,
692 struct scatterlist
*sg
)
694 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
695 sge
->length
= cpu_to_le32(sg_dma_len(sg
));
696 sge
->type
= NVME_SGL_FMT_DATA_DESC
<< 4;
699 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc
*sge
,
700 dma_addr_t dma_addr
, int entries
)
702 sge
->addr
= cpu_to_le64(dma_addr
);
703 if (entries
< SGES_PER_PAGE
) {
704 sge
->length
= cpu_to_le32(entries
* sizeof(*sge
));
705 sge
->type
= NVME_SGL_FMT_LAST_SEG_DESC
<< 4;
707 sge
->length
= cpu_to_le32(PAGE_SIZE
);
708 sge
->type
= NVME_SGL_FMT_SEG_DESC
<< 4;
712 static blk_status_t
nvme_pci_setup_sgls(struct nvme_dev
*dev
,
713 struct request
*req
, struct nvme_rw_command
*cmd
, int entries
)
715 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
716 struct dma_pool
*pool
;
717 struct nvme_sgl_desc
*sg_list
;
718 struct scatterlist
*sg
= iod
->sg
;
722 /* setting the transfer type as SGL */
723 cmd
->flags
= NVME_CMD_SGL_METABUF
;
726 nvme_pci_sgl_set_data(&cmd
->dptr
.sgl
, sg
);
730 if (entries
<= (256 / sizeof(struct nvme_sgl_desc
))) {
731 pool
= dev
->prp_small_pool
;
734 pool
= dev
->prp_page_pool
;
738 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
741 return BLK_STS_RESOURCE
;
744 nvme_pci_iod_list(req
)[0] = sg_list
;
745 iod
->first_dma
= sgl_dma
;
747 nvme_pci_sgl_set_seg(&cmd
->dptr
.sgl
, sgl_dma
, entries
);
750 if (i
== SGES_PER_PAGE
) {
751 struct nvme_sgl_desc
*old_sg_desc
= sg_list
;
752 struct nvme_sgl_desc
*link
= &old_sg_desc
[i
- 1];
754 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
756 return BLK_STS_RESOURCE
;
759 nvme_pci_iod_list(req
)[iod
->npages
++] = sg_list
;
760 sg_list
[i
++] = *link
;
761 nvme_pci_sgl_set_seg(link
, sgl_dma
, entries
);
764 nvme_pci_sgl_set_data(&sg_list
[i
++], sg
);
766 } while (--entries
> 0);
771 static blk_status_t
nvme_setup_prp_simple(struct nvme_dev
*dev
,
772 struct request
*req
, struct nvme_rw_command
*cmnd
,
775 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
776 unsigned int offset
= bv
->bv_offset
& (dev
->ctrl
.page_size
- 1);
777 unsigned int first_prp_len
= dev
->ctrl
.page_size
- offset
;
779 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
780 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
781 return BLK_STS_RESOURCE
;
782 iod
->dma_len
= bv
->bv_len
;
784 cmnd
->dptr
.prp1
= cpu_to_le64(iod
->first_dma
);
785 if (bv
->bv_len
> first_prp_len
)
786 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
+ first_prp_len
);
790 static blk_status_t
nvme_setup_sgl_simple(struct nvme_dev
*dev
,
791 struct request
*req
, struct nvme_rw_command
*cmnd
,
794 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
796 iod
->first_dma
= dma_map_bvec(dev
->dev
, bv
, rq_dma_dir(req
), 0);
797 if (dma_mapping_error(dev
->dev
, iod
->first_dma
))
798 return BLK_STS_RESOURCE
;
799 iod
->dma_len
= bv
->bv_len
;
801 cmnd
->flags
= NVME_CMD_SGL_METABUF
;
802 cmnd
->dptr
.sgl
.addr
= cpu_to_le64(iod
->first_dma
);
803 cmnd
->dptr
.sgl
.length
= cpu_to_le32(iod
->dma_len
);
804 cmnd
->dptr
.sgl
.type
= NVME_SGL_FMT_DATA_DESC
<< 4;
808 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
809 struct nvme_command
*cmnd
)
811 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
812 blk_status_t ret
= BLK_STS_RESOURCE
;
815 if (blk_rq_nr_phys_segments(req
) == 1) {
816 struct bio_vec bv
= req_bvec(req
);
818 if (!is_pci_p2pdma_page(bv
.bv_page
)) {
819 if (bv
.bv_offset
+ bv
.bv_len
<= dev
->ctrl
.page_size
* 2)
820 return nvme_setup_prp_simple(dev
, req
,
823 if (iod
->nvmeq
->qid
&&
824 dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1)))
825 return nvme_setup_sgl_simple(dev
, req
,
831 iod
->sg
= mempool_alloc(dev
->iod_mempool
, GFP_ATOMIC
);
833 return BLK_STS_RESOURCE
;
834 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
835 iod
->nents
= blk_rq_map_sg(req
->q
, req
, iod
->sg
);
839 if (is_pci_p2pdma_page(sg_page(iod
->sg
)))
840 nr_mapped
= pci_p2pdma_map_sg_attrs(dev
->dev
, iod
->sg
,
841 iod
->nents
, rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
843 nr_mapped
= dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
,
844 rq_dma_dir(req
), DMA_ATTR_NO_WARN
);
848 iod
->use_sgl
= nvme_pci_use_sgls(dev
, req
);
850 ret
= nvme_pci_setup_sgls(dev
, req
, &cmnd
->rw
, nr_mapped
);
852 ret
= nvme_pci_setup_prps(dev
, req
, &cmnd
->rw
);
854 if (ret
!= BLK_STS_OK
)
855 nvme_unmap_data(dev
, req
);
859 static blk_status_t
nvme_map_metadata(struct nvme_dev
*dev
, struct request
*req
,
860 struct nvme_command
*cmnd
)
862 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
864 iod
->meta_dma
= dma_map_bvec(dev
->dev
, rq_integrity_vec(req
),
866 if (dma_mapping_error(dev
->dev
, iod
->meta_dma
))
867 return BLK_STS_IOERR
;
868 cmnd
->rw
.metadata
= cpu_to_le64(iod
->meta_dma
);
873 * NOTE: ns is NULL when called on the admin queue.
875 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
876 const struct blk_mq_queue_data
*bd
)
878 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
879 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
880 struct nvme_dev
*dev
= nvmeq
->dev
;
881 struct request
*req
= bd
->rq
;
882 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
883 struct nvme_command cmnd
;
891 * We should not need to do this, but we're still using this to
892 * ensure we can drain requests on a dying queue.
894 if (unlikely(!test_bit(NVMEQ_ENABLED
, &nvmeq
->flags
)))
895 return BLK_STS_IOERR
;
897 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
901 if (blk_rq_nr_phys_segments(req
)) {
902 ret
= nvme_map_data(dev
, req
, &cmnd
);
907 if (blk_integrity_rq(req
)) {
908 ret
= nvme_map_metadata(dev
, req
, &cmnd
);
913 blk_mq_start_request(req
);
914 nvme_submit_cmd(nvmeq
, &cmnd
, bd
->last
);
917 nvme_unmap_data(dev
, req
);
919 nvme_cleanup_cmd(req
);
923 static void nvme_pci_complete_rq(struct request
*req
)
925 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
926 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
928 if (blk_integrity_rq(req
))
929 dma_unmap_page(dev
->dev
, iod
->meta_dma
,
930 rq_integrity_vec(req
)->bv_len
, rq_data_dir(req
));
931 if (blk_rq_nr_phys_segments(req
))
932 nvme_unmap_data(dev
, req
);
933 nvme_complete_rq(req
);
936 /* We read the CQE phase first to check if the rest of the entry is valid */
937 static inline bool nvme_cqe_pending(struct nvme_queue
*nvmeq
)
939 return (le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
943 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
945 u16 head
= nvmeq
->cq_head
;
947 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
949 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
952 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
, u16 idx
)
954 volatile struct nvme_completion
*cqe
= &nvmeq
->cqes
[idx
];
957 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
958 dev_warn(nvmeq
->dev
->ctrl
.device
,
959 "invalid id %d completed on queue %d\n",
960 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
965 * AEN requests are special as they don't time out and can
966 * survive any kind of queue freeze and often don't respond to
967 * aborts. We don't even bother to allocate a struct request
968 * for them but rather special case them here.
970 if (unlikely(nvme_is_aen_req(nvmeq
->qid
, cqe
->command_id
))) {
971 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
972 cqe
->status
, &cqe
->result
);
976 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
977 trace_nvme_sq(req
, cqe
->sq_head
, nvmeq
->sq_tail
);
978 nvme_end_request(req
, cqe
->status
, cqe
->result
);
981 static void nvme_complete_cqes(struct nvme_queue
*nvmeq
, u16 start
, u16 end
)
983 while (start
!= end
) {
984 nvme_handle_cqe(nvmeq
, start
);
985 if (++start
== nvmeq
->q_depth
)
990 static inline void nvme_update_cq_head(struct nvme_queue
*nvmeq
)
992 if (nvmeq
->cq_head
== nvmeq
->q_depth
- 1) {
994 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
1000 static inline int nvme_process_cq(struct nvme_queue
*nvmeq
, u16
*start
,
1001 u16
*end
, unsigned int tag
)
1005 *start
= nvmeq
->cq_head
;
1006 while (nvme_cqe_pending(nvmeq
)) {
1007 if (tag
== -1U || nvmeq
->cqes
[nvmeq
->cq_head
].command_id
== tag
)
1009 nvme_update_cq_head(nvmeq
);
1011 *end
= nvmeq
->cq_head
;
1014 nvme_ring_cq_doorbell(nvmeq
);
1018 static irqreturn_t
nvme_irq(int irq
, void *data
)
1020 struct nvme_queue
*nvmeq
= data
;
1021 irqreturn_t ret
= IRQ_NONE
;
1025 * The rmb/wmb pair ensures we see all updates from a previous run of
1026 * the irq handler, even if that was on another CPU.
1029 if (nvmeq
->cq_head
!= nvmeq
->last_cq_head
)
1031 nvme_process_cq(nvmeq
, &start
, &end
, -1);
1032 nvmeq
->last_cq_head
= nvmeq
->cq_head
;
1036 nvme_complete_cqes(nvmeq
, start
, end
);
1043 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
1045 struct nvme_queue
*nvmeq
= data
;
1046 if (nvme_cqe_pending(nvmeq
))
1047 return IRQ_WAKE_THREAD
;
1052 * Poll for completions any queue, including those not dedicated to polling.
1053 * Can be called from any context.
1055 static int nvme_poll_irqdisable(struct nvme_queue
*nvmeq
, unsigned int tag
)
1057 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1062 * For a poll queue we need to protect against the polling thread
1063 * using the CQ lock. For normal interrupt driven threads we have
1064 * to disable the interrupt to avoid racing with it.
1066 if (test_bit(NVMEQ_POLLED
, &nvmeq
->flags
)) {
1067 spin_lock(&nvmeq
->cq_poll_lock
);
1068 found
= nvme_process_cq(nvmeq
, &start
, &end
, tag
);
1069 spin_unlock(&nvmeq
->cq_poll_lock
);
1071 disable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1072 found
= nvme_process_cq(nvmeq
, &start
, &end
, tag
);
1073 enable_irq(pci_irq_vector(pdev
, nvmeq
->cq_vector
));
1076 nvme_complete_cqes(nvmeq
, start
, end
);
1080 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
)
1082 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
1086 if (!nvme_cqe_pending(nvmeq
))
1089 spin_lock(&nvmeq
->cq_poll_lock
);
1090 found
= nvme_process_cq(nvmeq
, &start
, &end
, -1);
1091 spin_unlock(&nvmeq
->cq_poll_lock
);
1093 nvme_complete_cqes(nvmeq
, start
, end
);
1097 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
)
1099 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1100 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1101 struct nvme_command c
;
1103 memset(&c
, 0, sizeof(c
));
1104 c
.common
.opcode
= nvme_admin_async_event
;
1105 c
.common
.command_id
= NVME_AQ_BLK_MQ_DEPTH
;
1106 nvme_submit_cmd(nvmeq
, &c
, true);
1109 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1111 struct nvme_command c
;
1113 memset(&c
, 0, sizeof(c
));
1114 c
.delete_queue
.opcode
= opcode
;
1115 c
.delete_queue
.qid
= cpu_to_le16(id
);
1117 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1120 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1121 struct nvme_queue
*nvmeq
, s16 vector
)
1123 struct nvme_command c
;
1124 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1126 if (!test_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1127 flags
|= NVME_CQ_IRQ_ENABLED
;
1130 * Note: we (ab)use the fact that the prp fields survive if no data
1131 * is attached to the request.
1133 memset(&c
, 0, sizeof(c
));
1134 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1135 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1136 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1137 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1138 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1139 c
.create_cq
.irq_vector
= cpu_to_le16(vector
);
1141 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1144 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1145 struct nvme_queue
*nvmeq
)
1147 struct nvme_ctrl
*ctrl
= &dev
->ctrl
;
1148 struct nvme_command c
;
1149 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1152 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1153 * set. Since URGENT priority is zeroes, it makes all queues
1156 if (ctrl
->quirks
& NVME_QUIRK_MEDIUM_PRIO_SQ
)
1157 flags
|= NVME_SQ_PRIO_MEDIUM
;
1160 * Note: we (ab)use the fact that the prp fields survive if no data
1161 * is attached to the request.
1163 memset(&c
, 0, sizeof(c
));
1164 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1165 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1166 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1167 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1168 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1169 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1171 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1174 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1176 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1179 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1181 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1184 static void abort_endio(struct request
*req
, blk_status_t error
)
1186 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1187 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1189 dev_warn(nvmeq
->dev
->ctrl
.device
,
1190 "Abort status: 0x%x", nvme_req(req
)->status
);
1191 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
1192 blk_mq_free_request(req
);
1195 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1198 /* If true, indicates loss of adapter communication, possibly by a
1199 * NVMe Subsystem reset.
1201 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1203 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1204 switch (dev
->ctrl
.state
) {
1205 case NVME_CTRL_RESETTING
:
1206 case NVME_CTRL_CONNECTING
:
1212 /* We shouldn't reset unless the controller is on fatal error state
1213 * _or_ if we lost the communication with it.
1215 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1221 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1223 /* Read a config register to help see what died. */
1227 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1229 if (result
== PCIBIOS_SUCCESSFUL
)
1230 dev_warn(dev
->ctrl
.device
,
1231 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1234 dev_warn(dev
->ctrl
.device
,
1235 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1239 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1241 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1242 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1243 struct nvme_dev
*dev
= nvmeq
->dev
;
1244 struct request
*abort_req
;
1245 struct nvme_command cmd
;
1246 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1248 /* If PCI error recovery process is happening, we cannot reset or
1249 * the recovery mechanism will surely fail.
1252 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1253 return BLK_EH_RESET_TIMER
;
1256 * Reset immediately if the controller is failed
1258 if (nvme_should_reset(dev
, csts
)) {
1259 nvme_warn_reset(dev
, csts
);
1260 nvme_dev_disable(dev
, false);
1261 nvme_reset_ctrl(&dev
->ctrl
);
1266 * Did we miss an interrupt?
1268 if (nvme_poll_irqdisable(nvmeq
, req
->tag
)) {
1269 dev_warn(dev
->ctrl
.device
,
1270 "I/O %d QID %d timeout, completion polled\n",
1271 req
->tag
, nvmeq
->qid
);
1276 * Shutdown immediately if controller times out while starting. The
1277 * reset work will see the pci device disabled when it gets the forced
1278 * cancellation error. All outstanding requests are completed on
1279 * shutdown, so we return BLK_EH_DONE.
1281 switch (dev
->ctrl
.state
) {
1282 case NVME_CTRL_CONNECTING
:
1283 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
1285 case NVME_CTRL_DELETING
:
1286 dev_warn_ratelimited(dev
->ctrl
.device
,
1287 "I/O %d QID %d timeout, disable controller\n",
1288 req
->tag
, nvmeq
->qid
);
1289 nvme_dev_disable(dev
, true);
1290 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1292 case NVME_CTRL_RESETTING
:
1293 return BLK_EH_RESET_TIMER
;
1299 * Shutdown the controller immediately and schedule a reset if the
1300 * command was already aborted once before and still hasn't been
1301 * returned to the driver, or if this is the admin queue.
1303 if (!nvmeq
->qid
|| iod
->aborted
) {
1304 dev_warn(dev
->ctrl
.device
,
1305 "I/O %d QID %d timeout, reset controller\n",
1306 req
->tag
, nvmeq
->qid
);
1307 nvme_dev_disable(dev
, false);
1308 nvme_reset_ctrl(&dev
->ctrl
);
1310 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1314 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1315 atomic_inc(&dev
->ctrl
.abort_limit
);
1316 return BLK_EH_RESET_TIMER
;
1320 memset(&cmd
, 0, sizeof(cmd
));
1321 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1322 cmd
.abort
.cid
= req
->tag
;
1323 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1325 dev_warn(nvmeq
->dev
->ctrl
.device
,
1326 "I/O %d QID %d timeout, aborting\n",
1327 req
->tag
, nvmeq
->qid
);
1329 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1330 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1331 if (IS_ERR(abort_req
)) {
1332 atomic_inc(&dev
->ctrl
.abort_limit
);
1333 return BLK_EH_RESET_TIMER
;
1336 abort_req
->timeout
= ADMIN_TIMEOUT
;
1337 abort_req
->end_io_data
= NULL
;
1338 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1341 * The aborted req will be completed on receiving the abort req.
1342 * We enable the timer again. If hit twice, it'll cause a device reset,
1343 * as the device then is in a faulty state.
1345 return BLK_EH_RESET_TIMER
;
1348 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1350 dma_free_coherent(nvmeq
->dev
->dev
, CQ_SIZE(nvmeq
),
1351 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1352 if (!nvmeq
->sq_cmds
)
1355 if (test_and_clear_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
)) {
1356 pci_free_p2pmem(to_pci_dev(nvmeq
->dev
->dev
),
1357 nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1359 dma_free_coherent(nvmeq
->dev
->dev
, SQ_SIZE(nvmeq
),
1360 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1364 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1368 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1369 dev
->ctrl
.queue_count
--;
1370 nvme_free_queue(&dev
->queues
[i
]);
1375 * nvme_suspend_queue - put queue into suspended state
1376 * @nvmeq: queue to suspend
1378 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1380 if (!test_and_clear_bit(NVMEQ_ENABLED
, &nvmeq
->flags
))
1383 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1386 nvmeq
->dev
->online_queues
--;
1387 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1388 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1389 if (!test_and_clear_bit(NVMEQ_POLLED
, &nvmeq
->flags
))
1390 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), nvmeq
->cq_vector
, nvmeq
);
1394 static void nvme_suspend_io_queues(struct nvme_dev
*dev
)
1398 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
1399 nvme_suspend_queue(&dev
->queues
[i
]);
1402 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1404 struct nvme_queue
*nvmeq
= &dev
->queues
[0];
1407 nvme_shutdown_ctrl(&dev
->ctrl
);
1409 nvme_disable_ctrl(&dev
->ctrl
);
1411 nvme_poll_irqdisable(nvmeq
, -1);
1414 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1417 int q_depth
= dev
->q_depth
;
1418 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1419 dev
->ctrl
.page_size
);
1421 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1422 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1423 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1424 q_depth
= div_u64(mem_per_q
, entry_size
);
1427 * Ensure the reduced q_depth is above some threshold where it
1428 * would be better to map queues in system memory with the
1438 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1441 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1443 if (qid
&& dev
->cmb_use_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
)) {
1444 nvmeq
->sq_cmds
= pci_alloc_p2pmem(pdev
, SQ_SIZE(nvmeq
));
1445 if (nvmeq
->sq_cmds
) {
1446 nvmeq
->sq_dma_addr
= pci_p2pmem_virt_to_bus(pdev
,
1448 if (nvmeq
->sq_dma_addr
) {
1449 set_bit(NVMEQ_SQ_CMB
, &nvmeq
->flags
);
1453 pci_free_p2pmem(pdev
, nvmeq
->sq_cmds
, SQ_SIZE(nvmeq
));
1457 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(nvmeq
),
1458 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1459 if (!nvmeq
->sq_cmds
)
1464 static int nvme_alloc_queue(struct nvme_dev
*dev
, int qid
, int depth
)
1466 struct nvme_queue
*nvmeq
= &dev
->queues
[qid
];
1468 if (dev
->ctrl
.queue_count
> qid
)
1471 nvmeq
->sqes
= qid
? dev
->io_sqes
: NVME_ADM_SQES
;
1472 nvmeq
->q_depth
= depth
;
1473 nvmeq
->cqes
= dma_alloc_coherent(dev
->dev
, CQ_SIZE(nvmeq
),
1474 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1478 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
))
1482 spin_lock_init(&nvmeq
->sq_lock
);
1483 spin_lock_init(&nvmeq
->cq_poll_lock
);
1485 nvmeq
->cq_phase
= 1;
1486 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1488 dev
->ctrl
.queue_count
++;
1493 dma_free_coherent(dev
->dev
, CQ_SIZE(nvmeq
), (void *)nvmeq
->cqes
,
1494 nvmeq
->cq_dma_addr
);
1499 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1501 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1502 int nr
= nvmeq
->dev
->ctrl
.instance
;
1504 if (use_threaded_interrupts
) {
1505 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1506 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1508 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1509 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1513 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1515 struct nvme_dev
*dev
= nvmeq
->dev
;
1518 nvmeq
->last_sq_tail
= 0;
1520 nvmeq
->cq_phase
= 1;
1521 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1522 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
));
1523 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1524 dev
->online_queues
++;
1525 wmb(); /* ensure the first interrupt sees the initialization */
1528 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
, bool polled
)
1530 struct nvme_dev
*dev
= nvmeq
->dev
;
1534 clear_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
1537 * A queue's vector matches the queue identifier unless the controller
1538 * has only one vector available.
1541 vector
= dev
->num_vecs
== 1 ? 0 : qid
;
1543 set_bit(NVMEQ_POLLED
, &nvmeq
->flags
);
1545 result
= adapter_alloc_cq(dev
, qid
, nvmeq
, vector
);
1549 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1555 nvmeq
->cq_vector
= vector
;
1556 nvme_init_queue(nvmeq
, qid
);
1559 result
= queue_request_irq(nvmeq
);
1564 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1568 dev
->online_queues
--;
1569 adapter_delete_sq(dev
, qid
);
1571 adapter_delete_cq(dev
, qid
);
1575 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1576 .queue_rq
= nvme_queue_rq
,
1577 .complete
= nvme_pci_complete_rq
,
1578 .init_hctx
= nvme_admin_init_hctx
,
1579 .exit_hctx
= nvme_admin_exit_hctx
,
1580 .init_request
= nvme_init_request
,
1581 .timeout
= nvme_timeout
,
1584 static const struct blk_mq_ops nvme_mq_ops
= {
1585 .queue_rq
= nvme_queue_rq
,
1586 .complete
= nvme_pci_complete_rq
,
1587 .commit_rqs
= nvme_commit_rqs
,
1588 .init_hctx
= nvme_init_hctx
,
1589 .init_request
= nvme_init_request
,
1590 .map_queues
= nvme_pci_map_queues
,
1591 .timeout
= nvme_timeout
,
1595 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1597 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1599 * If the controller was reset during removal, it's possible
1600 * user requests may be waiting on a stopped queue. Start the
1601 * queue to flush these to completion.
1603 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1604 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1605 blk_mq_free_tag_set(&dev
->admin_tagset
);
1609 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1611 if (!dev
->ctrl
.admin_q
) {
1612 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1613 dev
->admin_tagset
.nr_hw_queues
= 1;
1615 dev
->admin_tagset
.queue_depth
= NVME_AQ_MQ_TAG_DEPTH
;
1616 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1617 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1618 dev
->admin_tagset
.cmd_size
= sizeof(struct nvme_iod
);
1619 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1620 dev
->admin_tagset
.driver_data
= dev
;
1622 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1624 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1626 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1627 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1628 blk_mq_free_tag_set(&dev
->admin_tagset
);
1631 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1632 nvme_dev_remove_admin(dev
);
1633 dev
->ctrl
.admin_q
= NULL
;
1637 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1642 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1644 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1647 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1649 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1651 if (size
<= dev
->bar_mapped_size
)
1653 if (size
> pci_resource_len(pdev
, 0))
1657 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1659 dev
->bar_mapped_size
= 0;
1662 dev
->bar_mapped_size
= size
;
1663 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1668 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1672 struct nvme_queue
*nvmeq
;
1674 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1678 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1679 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1681 if (dev
->subsystem
&&
1682 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1683 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1685 result
= nvme_disable_ctrl(&dev
->ctrl
);
1689 result
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1693 nvmeq
= &dev
->queues
[0];
1694 aqa
= nvmeq
->q_depth
- 1;
1697 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1698 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1699 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1701 result
= nvme_enable_ctrl(&dev
->ctrl
);
1705 nvmeq
->cq_vector
= 0;
1706 nvme_init_queue(nvmeq
, 0);
1707 result
= queue_request_irq(nvmeq
);
1709 dev
->online_queues
--;
1713 set_bit(NVMEQ_ENABLED
, &nvmeq
->flags
);
1717 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1719 unsigned i
, max
, rw_queues
;
1722 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1723 if (nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1729 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1730 if (max
!= 1 && dev
->io_queues
[HCTX_TYPE_POLL
]) {
1731 rw_queues
= dev
->io_queues
[HCTX_TYPE_DEFAULT
] +
1732 dev
->io_queues
[HCTX_TYPE_READ
];
1737 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1738 bool polled
= i
> rw_queues
;
1740 ret
= nvme_create_queue(&dev
->queues
[i
], i
, polled
);
1746 * Ignore failing Create SQ/CQ commands, we can continue with less
1747 * than the desired amount of queues, and even a controller without
1748 * I/O queues can still be used to issue admin commands. This might
1749 * be useful to upgrade a buggy firmware for example.
1751 return ret
>= 0 ? 0 : ret
;
1754 static ssize_t
nvme_cmb_show(struct device
*dev
,
1755 struct device_attribute
*attr
,
1758 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1760 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1761 ndev
->cmbloc
, ndev
->cmbsz
);
1763 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1765 static u64
nvme_cmb_size_unit(struct nvme_dev
*dev
)
1767 u8 szu
= (dev
->cmbsz
>> NVME_CMBSZ_SZU_SHIFT
) & NVME_CMBSZ_SZU_MASK
;
1769 return 1ULL << (12 + 4 * szu
);
1772 static u32
nvme_cmb_size(struct nvme_dev
*dev
)
1774 return (dev
->cmbsz
>> NVME_CMBSZ_SZ_SHIFT
) & NVME_CMBSZ_SZ_MASK
;
1777 static void nvme_map_cmb(struct nvme_dev
*dev
)
1780 resource_size_t bar_size
;
1781 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1787 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1790 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1792 size
= nvme_cmb_size_unit(dev
) * nvme_cmb_size(dev
);
1793 offset
= nvme_cmb_size_unit(dev
) * NVME_CMB_OFST(dev
->cmbloc
);
1794 bar
= NVME_CMB_BIR(dev
->cmbloc
);
1795 bar_size
= pci_resource_len(pdev
, bar
);
1797 if (offset
> bar_size
)
1801 * Controllers may support a CMB size larger than their BAR,
1802 * for example, due to being behind a bridge. Reduce the CMB to
1803 * the reported size of the BAR
1805 if (size
> bar_size
- offset
)
1806 size
= bar_size
- offset
;
1808 if (pci_p2pdma_add_resource(pdev
, bar
, size
, offset
)) {
1809 dev_warn(dev
->ctrl
.device
,
1810 "failed to register the CMB\n");
1814 dev
->cmb_size
= size
;
1815 dev
->cmb_use_sqes
= use_cmb_sqes
&& (dev
->cmbsz
& NVME_CMBSZ_SQS
);
1817 if ((dev
->cmbsz
& (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
)) ==
1818 (NVME_CMBSZ_WDS
| NVME_CMBSZ_RDS
))
1819 pci_p2pmem_publish(pdev
, true);
1821 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1822 &dev_attr_cmb
.attr
, NULL
))
1823 dev_warn(dev
->ctrl
.device
,
1824 "failed to add sysfs attribute for CMB\n");
1827 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1829 if (dev
->cmb_size
) {
1830 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1831 &dev_attr_cmb
.attr
, NULL
);
1836 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1838 u64 dma_addr
= dev
->host_mem_descs_dma
;
1839 struct nvme_command c
;
1842 memset(&c
, 0, sizeof(c
));
1843 c
.features
.opcode
= nvme_admin_set_features
;
1844 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1845 c
.features
.dword11
= cpu_to_le32(bits
);
1846 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1847 ilog2(dev
->ctrl
.page_size
));
1848 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1849 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1850 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1852 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1854 dev_warn(dev
->ctrl
.device
,
1855 "failed to set host mem (err %d, flags %#x).\n",
1861 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1865 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1866 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1867 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1869 dma_free_attrs(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1870 le64_to_cpu(desc
->addr
),
1871 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1874 kfree(dev
->host_mem_desc_bufs
);
1875 dev
->host_mem_desc_bufs
= NULL
;
1876 dma_free_coherent(dev
->dev
,
1877 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1878 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1879 dev
->host_mem_descs
= NULL
;
1880 dev
->nr_host_mem_descs
= 0;
1883 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1886 struct nvme_host_mem_buf_desc
*descs
;
1887 u32 max_entries
, len
;
1888 dma_addr_t descs_dma
;
1893 tmp
= (preferred
+ chunk_size
- 1);
1894 do_div(tmp
, chunk_size
);
1897 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1898 max_entries
= dev
->ctrl
.hmmaxd
;
1900 descs
= dma_alloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1901 &descs_dma
, GFP_KERNEL
);
1905 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1907 goto out_free_descs
;
1909 for (size
= 0; size
< preferred
&& i
< max_entries
; size
+= len
) {
1910 dma_addr_t dma_addr
;
1912 len
= min_t(u64
, chunk_size
, preferred
- size
);
1913 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1914 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1918 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1919 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1926 dev
->nr_host_mem_descs
= i
;
1927 dev
->host_mem_size
= size
;
1928 dev
->host_mem_descs
= descs
;
1929 dev
->host_mem_descs_dma
= descs_dma
;
1930 dev
->host_mem_desc_bufs
= bufs
;
1935 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1937 dma_free_attrs(dev
->dev
, size
, bufs
[i
],
1938 le64_to_cpu(descs
[i
].addr
),
1939 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1944 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1947 dev
->host_mem_descs
= NULL
;
1951 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1955 /* start big and work our way down */
1956 for (chunk_size
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
1957 chunk_size
>= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
1959 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
1960 if (!min
|| dev
->host_mem_size
>= min
)
1962 nvme_free_host_mem(dev
);
1969 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
1971 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1972 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1973 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1974 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1977 preferred
= min(preferred
, max
);
1979 dev_warn(dev
->ctrl
.device
,
1980 "min host memory (%lld MiB) above limit (%d MiB).\n",
1981 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1982 nvme_free_host_mem(dev
);
1987 * If we already have a buffer allocated check if we can reuse it.
1989 if (dev
->host_mem_descs
) {
1990 if (dev
->host_mem_size
>= min
)
1991 enable_bits
|= NVME_HOST_MEM_RETURN
;
1993 nvme_free_host_mem(dev
);
1996 if (!dev
->host_mem_descs
) {
1997 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
1998 dev_warn(dev
->ctrl
.device
,
1999 "failed to allocate host memory buffer.\n");
2000 return 0; /* controller must work without HMB */
2003 dev_info(dev
->ctrl
.device
,
2004 "allocated %lld MiB host memory buffer.\n",
2005 dev
->host_mem_size
>> ilog2(SZ_1M
));
2008 ret
= nvme_set_host_mem(dev
, enable_bits
);
2010 nvme_free_host_mem(dev
);
2015 * nirqs is the number of interrupts available for write and read
2016 * queues. The core already reserved an interrupt for the admin queue.
2018 static void nvme_calc_irq_sets(struct irq_affinity
*affd
, unsigned int nrirqs
)
2020 struct nvme_dev
*dev
= affd
->priv
;
2021 unsigned int nr_read_queues
;
2024 * If there is no interupt available for queues, ensure that
2025 * the default queue is set to 1. The affinity set size is
2026 * also set to one, but the irq core ignores it for this case.
2028 * If only one interrupt is available or 'write_queue' == 0, combine
2029 * write and read queues.
2031 * If 'write_queues' > 0, ensure it leaves room for at least one read
2037 } else if (nrirqs
== 1 || !write_queues
) {
2039 } else if (write_queues
>= nrirqs
) {
2042 nr_read_queues
= nrirqs
- write_queues
;
2045 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2046 affd
->set_size
[HCTX_TYPE_DEFAULT
] = nrirqs
- nr_read_queues
;
2047 dev
->io_queues
[HCTX_TYPE_READ
] = nr_read_queues
;
2048 affd
->set_size
[HCTX_TYPE_READ
] = nr_read_queues
;
2049 affd
->nr_sets
= nr_read_queues
? 2 : 1;
2052 static int nvme_setup_irqs(struct nvme_dev
*dev
, unsigned int nr_io_queues
)
2054 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2055 struct irq_affinity affd
= {
2057 .calc_sets
= nvme_calc_irq_sets
,
2060 unsigned int irq_queues
, this_p_queues
;
2061 unsigned int nr_cpus
= num_possible_cpus();
2064 * Poll queues don't need interrupts, but we need at least one IO
2065 * queue left over for non-polled IO.
2067 this_p_queues
= poll_queues
;
2068 if (this_p_queues
>= nr_io_queues
) {
2069 this_p_queues
= nr_io_queues
- 1;
2072 if (nr_cpus
< nr_io_queues
- this_p_queues
)
2073 irq_queues
= nr_cpus
+ 1;
2075 irq_queues
= nr_io_queues
- this_p_queues
+ 1;
2077 dev
->io_queues
[HCTX_TYPE_POLL
] = this_p_queues
;
2079 /* Initialize for the single interrupt case */
2080 dev
->io_queues
[HCTX_TYPE_DEFAULT
] = 1;
2081 dev
->io_queues
[HCTX_TYPE_READ
] = 0;
2084 * Some Apple controllers require all queues to use the
2087 if (dev
->ctrl
.quirks
& NVME_QUIRK_SINGLE_VECTOR
)
2090 return pci_alloc_irq_vectors_affinity(pdev
, 1, irq_queues
,
2091 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
, &affd
);
2094 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
2096 if (__nvme_disable_io_queues(dev
, nvme_admin_delete_sq
))
2097 __nvme_disable_io_queues(dev
, nvme_admin_delete_cq
);
2100 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
2102 struct nvme_queue
*adminq
= &dev
->queues
[0];
2103 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2104 int result
, nr_io_queues
;
2107 nr_io_queues
= max_io_queues();
2110 * If tags are shared with admin queue (Apple bug), then
2111 * make sure we only use one IO queue.
2113 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2116 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
2120 if (nr_io_queues
== 0)
2123 clear_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2125 if (dev
->cmb_use_sqes
) {
2126 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
2127 sizeof(struct nvme_command
));
2129 dev
->q_depth
= result
;
2131 dev
->cmb_use_sqes
= false;
2135 size
= db_bar_size(dev
, nr_io_queues
);
2136 result
= nvme_remap_bar(dev
, size
);
2139 if (!--nr_io_queues
)
2142 adminq
->q_db
= dev
->dbs
;
2145 /* Deregister the admin queue's interrupt */
2146 pci_free_irq(pdev
, 0, adminq
);
2149 * If we enable msix early due to not intx, disable it again before
2150 * setting up the full range we need.
2152 pci_free_irq_vectors(pdev
);
2154 result
= nvme_setup_irqs(dev
, nr_io_queues
);
2158 dev
->num_vecs
= result
;
2159 result
= max(result
- 1, 1);
2160 dev
->max_qid
= result
+ dev
->io_queues
[HCTX_TYPE_POLL
];
2163 * Should investigate if there's a performance win from allocating
2164 * more queues than interrupt vectors; it might allow the submission
2165 * path to scale better, even if the receive path is limited by the
2166 * number of interrupts.
2168 result
= queue_request_irq(adminq
);
2171 set_bit(NVMEQ_ENABLED
, &adminq
->flags
);
2173 result
= nvme_create_io_queues(dev
);
2174 if (result
|| dev
->online_queues
< 2)
2177 if (dev
->online_queues
- 1 < dev
->max_qid
) {
2178 nr_io_queues
= dev
->online_queues
- 1;
2179 nvme_disable_io_queues(dev
);
2180 nvme_suspend_io_queues(dev
);
2183 dev_info(dev
->ctrl
.device
, "%d/%d/%d default/read/poll queues\n",
2184 dev
->io_queues
[HCTX_TYPE_DEFAULT
],
2185 dev
->io_queues
[HCTX_TYPE_READ
],
2186 dev
->io_queues
[HCTX_TYPE_POLL
]);
2190 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
2192 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2194 blk_mq_free_request(req
);
2195 complete(&nvmeq
->delete_done
);
2198 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
2200 struct nvme_queue
*nvmeq
= req
->end_io_data
;
2203 set_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
);
2205 nvme_del_queue_end(req
, error
);
2208 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
2210 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
2211 struct request
*req
;
2212 struct nvme_command cmd
;
2214 memset(&cmd
, 0, sizeof(cmd
));
2215 cmd
.delete_queue
.opcode
= opcode
;
2216 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
2218 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
2220 return PTR_ERR(req
);
2222 req
->timeout
= ADMIN_TIMEOUT
;
2223 req
->end_io_data
= nvmeq
;
2225 init_completion(&nvmeq
->delete_done
);
2226 blk_execute_rq_nowait(q
, NULL
, req
, false,
2227 opcode
== nvme_admin_delete_cq
?
2228 nvme_del_cq_end
: nvme_del_queue_end
);
2232 static bool __nvme_disable_io_queues(struct nvme_dev
*dev
, u8 opcode
)
2234 int nr_queues
= dev
->online_queues
- 1, sent
= 0;
2235 unsigned long timeout
;
2238 timeout
= ADMIN_TIMEOUT
;
2239 while (nr_queues
> 0) {
2240 if (nvme_delete_queue(&dev
->queues
[nr_queues
], opcode
))
2246 struct nvme_queue
*nvmeq
= &dev
->queues
[nr_queues
+ sent
];
2248 timeout
= wait_for_completion_io_timeout(&nvmeq
->delete_done
,
2253 /* handle any remaining CQEs */
2254 if (opcode
== nvme_admin_delete_cq
&&
2255 !test_bit(NVMEQ_DELETE_ERROR
, &nvmeq
->flags
))
2256 nvme_poll_irqdisable(nvmeq
, -1);
2265 static void nvme_dev_add(struct nvme_dev
*dev
)
2269 if (!dev
->ctrl
.tagset
) {
2270 dev
->tagset
.ops
= &nvme_mq_ops
;
2271 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
2272 dev
->tagset
.nr_maps
= 2; /* default + read */
2273 if (dev
->io_queues
[HCTX_TYPE_POLL
])
2274 dev
->tagset
.nr_maps
++;
2275 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
2276 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
2277 dev
->tagset
.queue_depth
=
2278 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
2279 dev
->tagset
.cmd_size
= sizeof(struct nvme_iod
);
2280 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
2281 dev
->tagset
.driver_data
= dev
;
2284 * Some Apple controllers requires tags to be unique
2285 * across admin and IO queue, so reserve the first 32
2286 * tags of the IO queue.
2288 if (dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
)
2289 dev
->tagset
.reserved_tags
= NVME_AQ_DEPTH
;
2291 ret
= blk_mq_alloc_tag_set(&dev
->tagset
);
2293 dev_warn(dev
->ctrl
.device
,
2294 "IO queues tagset allocation failed %d\n", ret
);
2297 dev
->ctrl
.tagset
= &dev
->tagset
;
2299 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
2301 /* Free previously allocated queues that are no longer usable */
2302 nvme_free_queues(dev
, dev
->online_queues
);
2305 nvme_dbbuf_set(dev
);
2308 static int nvme_pci_enable(struct nvme_dev
*dev
)
2310 int result
= -ENOMEM
;
2311 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2313 if (pci_enable_device_mem(pdev
))
2316 pci_set_master(pdev
);
2318 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)))
2321 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
2327 * Some devices and/or platforms don't advertise or work with INTx
2328 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2329 * adjust this later.
2331 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
2335 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
2337 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
2339 dev
->ctrl
.sqsize
= dev
->q_depth
- 1; /* 0's based queue depth */
2340 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
2341 dev
->dbs
= dev
->bar
+ 4096;
2344 * Some Apple controllers require a non-standard SQE size.
2345 * Interestingly they also seem to ignore the CC:IOSQES register
2346 * so we don't bother updating it here.
2348 if (dev
->ctrl
.quirks
& NVME_QUIRK_128_BYTES_SQES
)
2351 dev
->io_sqes
= NVME_NVM_IOSQES
;
2354 * Temporary fix for the Apple controller found in the MacBook8,1 and
2355 * some MacBook7,1 to avoid controller resets and data loss.
2357 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
2359 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
2360 "set queue depth=%u to work around controller resets\n",
2362 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
2363 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
2364 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
2366 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
2367 "set queue depth=%u\n", dev
->q_depth
);
2371 * Controllers with the shared tags quirk need the IO queue to be
2372 * big enough so that we get 32 tags for the admin queue
2374 if ((dev
->ctrl
.quirks
& NVME_QUIRK_SHARED_TAGS
) &&
2375 (dev
->q_depth
< (NVME_AQ_DEPTH
+ 2))) {
2376 dev
->q_depth
= NVME_AQ_DEPTH
+ 2;
2377 dev_warn(dev
->ctrl
.device
, "IO queue depth clamped to %d\n",
2384 pci_enable_pcie_error_reporting(pdev
);
2385 pci_save_state(pdev
);
2389 pci_disable_device(pdev
);
2393 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2397 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2400 static void nvme_pci_disable(struct nvme_dev
*dev
)
2402 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2404 pci_free_irq_vectors(pdev
);
2406 if (pci_is_enabled(pdev
)) {
2407 pci_disable_pcie_error_reporting(pdev
);
2408 pci_disable_device(pdev
);
2412 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2414 bool dead
= true, freeze
= false;
2415 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2417 mutex_lock(&dev
->shutdown_lock
);
2418 if (pci_is_enabled(pdev
)) {
2419 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2421 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2422 dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
2424 nvme_start_freeze(&dev
->ctrl
);
2426 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2427 pdev
->error_state
!= pci_channel_io_normal
);
2431 * Give the controller a chance to complete all entered requests if
2432 * doing a safe shutdown.
2434 if (!dead
&& shutdown
&& freeze
)
2435 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2437 nvme_stop_queues(&dev
->ctrl
);
2439 if (!dead
&& dev
->ctrl
.queue_count
> 0) {
2440 nvme_disable_io_queues(dev
);
2441 nvme_disable_admin_queue(dev
, shutdown
);
2443 nvme_suspend_io_queues(dev
);
2444 nvme_suspend_queue(&dev
->queues
[0]);
2445 nvme_pci_disable(dev
);
2447 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2448 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2449 blk_mq_tagset_wait_completed_request(&dev
->tagset
);
2450 blk_mq_tagset_wait_completed_request(&dev
->admin_tagset
);
2453 * The driver will not be starting up queues again if shutting down so
2454 * must flush all entered requests to their failed completion to avoid
2455 * deadlocking blk-mq hot-cpu notifier.
2458 nvme_start_queues(&dev
->ctrl
);
2459 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
))
2460 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
2462 mutex_unlock(&dev
->shutdown_lock
);
2465 static int nvme_disable_prepare_reset(struct nvme_dev
*dev
, bool shutdown
)
2467 if (!nvme_wait_reset(&dev
->ctrl
))
2469 nvme_dev_disable(dev
, shutdown
);
2473 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2475 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2476 PAGE_SIZE
, PAGE_SIZE
, 0);
2477 if (!dev
->prp_page_pool
)
2480 /* Optimisation for I/Os between 4k and 128k */
2481 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2483 if (!dev
->prp_small_pool
) {
2484 dma_pool_destroy(dev
->prp_page_pool
);
2490 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2492 dma_pool_destroy(dev
->prp_page_pool
);
2493 dma_pool_destroy(dev
->prp_small_pool
);
2496 static void nvme_free_tagset(struct nvme_dev
*dev
)
2498 if (dev
->tagset
.tags
)
2499 blk_mq_free_tag_set(&dev
->tagset
);
2500 dev
->ctrl
.tagset
= NULL
;
2503 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2505 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2507 nvme_dbbuf_dma_free(dev
);
2508 put_device(dev
->dev
);
2509 nvme_free_tagset(dev
);
2510 if (dev
->ctrl
.admin_q
)
2511 blk_put_queue(dev
->ctrl
.admin_q
);
2513 free_opal_dev(dev
->ctrl
.opal_dev
);
2514 mempool_destroy(dev
->iod_mempool
);
2518 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
)
2521 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2522 * may be holding this pci_dev's device lock.
2524 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2525 nvme_get_ctrl(&dev
->ctrl
);
2526 nvme_dev_disable(dev
, false);
2527 nvme_kill_queues(&dev
->ctrl
);
2528 if (!queue_work(nvme_wq
, &dev
->remove_work
))
2529 nvme_put_ctrl(&dev
->ctrl
);
2532 static void nvme_reset_work(struct work_struct
*work
)
2534 struct nvme_dev
*dev
=
2535 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2536 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2539 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
)) {
2545 * If we're called to reset a live controller first shut it down before
2548 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2549 nvme_dev_disable(dev
, false);
2550 nvme_sync_queues(&dev
->ctrl
);
2552 mutex_lock(&dev
->shutdown_lock
);
2553 result
= nvme_pci_enable(dev
);
2557 result
= nvme_pci_configure_admin_queue(dev
);
2561 result
= nvme_alloc_admin_tags(dev
);
2566 * Limit the max command size to prevent iod->sg allocations going
2567 * over a single page.
2569 dev
->ctrl
.max_hw_sectors
= min_t(u32
,
2570 NVME_MAX_KB_SZ
<< 1, dma_max_mapping_size(dev
->dev
) >> 9);
2571 dev
->ctrl
.max_segments
= NVME_MAX_SEGS
;
2574 * Don't limit the IOMMU merged segment size.
2576 dma_set_max_seg_size(dev
->dev
, 0xffffffff);
2578 mutex_unlock(&dev
->shutdown_lock
);
2581 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2582 * initializing procedure here.
2584 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_CONNECTING
)) {
2585 dev_warn(dev
->ctrl
.device
,
2586 "failed to mark controller CONNECTING\n");
2591 result
= nvme_init_identify(&dev
->ctrl
);
2595 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2596 if (!dev
->ctrl
.opal_dev
)
2597 dev
->ctrl
.opal_dev
=
2598 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2599 else if (was_suspend
)
2600 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2602 free_opal_dev(dev
->ctrl
.opal_dev
);
2603 dev
->ctrl
.opal_dev
= NULL
;
2606 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2607 result
= nvme_dbbuf_dma_alloc(dev
);
2610 "unable to allocate dma for dbbuf\n");
2613 if (dev
->ctrl
.hmpre
) {
2614 result
= nvme_setup_host_mem(dev
);
2619 result
= nvme_setup_io_queues(dev
);
2624 * Keep the controller around but remove all namespaces if we don't have
2625 * any working I/O queue.
2627 if (dev
->online_queues
< 2) {
2628 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2629 nvme_kill_queues(&dev
->ctrl
);
2630 nvme_remove_namespaces(&dev
->ctrl
);
2631 nvme_free_tagset(dev
);
2633 nvme_start_queues(&dev
->ctrl
);
2634 nvme_wait_freeze(&dev
->ctrl
);
2636 nvme_unfreeze(&dev
->ctrl
);
2640 * If only admin queue live, keep it to do further investigation or
2643 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2644 dev_warn(dev
->ctrl
.device
,
2645 "failed to mark controller live state\n");
2650 nvme_start_ctrl(&dev
->ctrl
);
2654 mutex_unlock(&dev
->shutdown_lock
);
2657 dev_warn(dev
->ctrl
.device
,
2658 "Removing after probe failure status: %d\n", result
);
2659 nvme_remove_dead_ctrl(dev
);
2662 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2664 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2665 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2667 if (pci_get_drvdata(pdev
))
2668 device_release_driver(&pdev
->dev
);
2669 nvme_put_ctrl(&dev
->ctrl
);
2672 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2674 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2678 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2680 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2684 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2686 *val
= lo_hi_readq(to_nvme_dev(ctrl
)->bar
+ off
);
2690 static int nvme_pci_get_address(struct nvme_ctrl
*ctrl
, char *buf
, int size
)
2692 struct pci_dev
*pdev
= to_pci_dev(to_nvme_dev(ctrl
)->dev
);
2694 return snprintf(buf
, size
, "%s", dev_name(&pdev
->dev
));
2697 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2699 .module
= THIS_MODULE
,
2700 .flags
= NVME_F_METADATA_SUPPORTED
|
2702 .reg_read32
= nvme_pci_reg_read32
,
2703 .reg_write32
= nvme_pci_reg_write32
,
2704 .reg_read64
= nvme_pci_reg_read64
,
2705 .free_ctrl
= nvme_pci_free_ctrl
,
2706 .submit_async_event
= nvme_pci_submit_async_event
,
2707 .get_address
= nvme_pci_get_address
,
2710 static int nvme_dev_map(struct nvme_dev
*dev
)
2712 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2714 if (pci_request_mem_regions(pdev
, "nvme"))
2717 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2722 pci_release_mem_regions(pdev
);
2726 static unsigned long check_vendor_combination_bug(struct pci_dev
*pdev
)
2728 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2730 * Several Samsung devices seem to drop off the PCIe bus
2731 * randomly when APST is on and uses the deepest sleep state.
2732 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2733 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2734 * 950 PRO 256GB", but it seems to be restricted to two Dell
2737 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2738 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2739 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2740 return NVME_QUIRK_NO_DEEPEST_PS
;
2741 } else if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa804) {
2743 * Samsung SSD 960 EVO drops off the PCIe bus after system
2744 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2745 * within few minutes after bootup on a Coffee Lake board -
2748 if (dmi_match(DMI_BOARD_VENDOR
, "ASUSTeK COMPUTER INC.") &&
2749 (dmi_match(DMI_BOARD_NAME
, "PRIME B350M-A") ||
2750 dmi_match(DMI_BOARD_NAME
, "PRIME Z370-A")))
2751 return NVME_QUIRK_NO_APST
;
2757 static void nvme_async_probe(void *data
, async_cookie_t cookie
)
2759 struct nvme_dev
*dev
= data
;
2761 flush_work(&dev
->ctrl
.reset_work
);
2762 flush_work(&dev
->ctrl
.scan_work
);
2763 nvme_put_ctrl(&dev
->ctrl
);
2766 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2768 int node
, result
= -ENOMEM
;
2769 struct nvme_dev
*dev
;
2770 unsigned long quirks
= id
->driver_data
;
2773 node
= dev_to_node(&pdev
->dev
);
2774 if (node
== NUMA_NO_NODE
)
2775 set_dev_node(&pdev
->dev
, first_memory_node
);
2777 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2781 dev
->queues
= kcalloc_node(max_queue_count(), sizeof(struct nvme_queue
),
2786 dev
->dev
= get_device(&pdev
->dev
);
2787 pci_set_drvdata(pdev
, dev
);
2789 result
= nvme_dev_map(dev
);
2793 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2794 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2795 mutex_init(&dev
->shutdown_lock
);
2797 result
= nvme_setup_prp_pools(dev
);
2801 quirks
|= check_vendor_combination_bug(pdev
);
2804 * Double check that our mempool alloc size will cover the biggest
2805 * command we support.
2807 alloc_size
= nvme_pci_iod_alloc_size(dev
, NVME_MAX_KB_SZ
,
2808 NVME_MAX_SEGS
, true);
2809 WARN_ON_ONCE(alloc_size
> PAGE_SIZE
);
2811 dev
->iod_mempool
= mempool_create_node(1, mempool_kmalloc
,
2813 (void *) alloc_size
,
2815 if (!dev
->iod_mempool
) {
2820 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2823 goto release_mempool
;
2825 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2827 nvme_reset_ctrl(&dev
->ctrl
);
2828 nvme_get_ctrl(&dev
->ctrl
);
2829 async_schedule(nvme_async_probe
, dev
);
2834 mempool_destroy(dev
->iod_mempool
);
2836 nvme_release_prp_pools(dev
);
2838 nvme_dev_unmap(dev
);
2840 put_device(dev
->dev
);
2847 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2849 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2852 * We don't need to check the return value from waiting for the reset
2853 * state as pci_dev device lock is held, making it impossible to race
2856 nvme_disable_prepare_reset(dev
, false);
2857 nvme_sync_queues(&dev
->ctrl
);
2860 static void nvme_reset_done(struct pci_dev
*pdev
)
2862 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2864 if (!nvme_try_sched_reset(&dev
->ctrl
))
2865 flush_work(&dev
->ctrl
.reset_work
);
2868 static void nvme_shutdown(struct pci_dev
*pdev
)
2870 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2871 nvme_disable_prepare_reset(dev
, true);
2875 * The driver's remove may be called on a device in a partially initialized
2876 * state. This function must not have any dependencies on the device state in
2879 static void nvme_remove(struct pci_dev
*pdev
)
2881 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2883 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2884 pci_set_drvdata(pdev
, NULL
);
2886 if (!pci_device_is_present(pdev
)) {
2887 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2888 nvme_dev_disable(dev
, true);
2889 nvme_dev_remove_admin(dev
);
2892 flush_work(&dev
->ctrl
.reset_work
);
2893 nvme_stop_ctrl(&dev
->ctrl
);
2894 nvme_remove_namespaces(&dev
->ctrl
);
2895 nvme_dev_disable(dev
, true);
2896 nvme_release_cmb(dev
);
2897 nvme_free_host_mem(dev
);
2898 nvme_dev_remove_admin(dev
);
2899 nvme_free_queues(dev
, 0);
2900 nvme_uninit_ctrl(&dev
->ctrl
);
2901 nvme_release_prp_pools(dev
);
2902 nvme_dev_unmap(dev
);
2903 nvme_put_ctrl(&dev
->ctrl
);
2906 #ifdef CONFIG_PM_SLEEP
2907 static int nvme_get_power_state(struct nvme_ctrl
*ctrl
, u32
*ps
)
2909 return nvme_get_features(ctrl
, NVME_FEAT_POWER_MGMT
, 0, NULL
, 0, ps
);
2912 static int nvme_set_power_state(struct nvme_ctrl
*ctrl
, u32 ps
)
2914 return nvme_set_features(ctrl
, NVME_FEAT_POWER_MGMT
, ps
, NULL
, 0, NULL
);
2917 static int nvme_resume(struct device
*dev
)
2919 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
2920 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2922 if (ndev
->last_ps
== U32_MAX
||
2923 nvme_set_power_state(ctrl
, ndev
->last_ps
) != 0)
2924 return nvme_try_sched_reset(&ndev
->ctrl
);
2928 static int nvme_suspend(struct device
*dev
)
2930 struct pci_dev
*pdev
= to_pci_dev(dev
);
2931 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2932 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2935 ndev
->last_ps
= U32_MAX
;
2938 * The platform does not remove power for a kernel managed suspend so
2939 * use host managed nvme power settings for lowest idle power if
2940 * possible. This should have quicker resume latency than a full device
2941 * shutdown. But if the firmware is involved after the suspend or the
2942 * device does not support any non-default power states, shut down the
2945 * If ASPM is not enabled for the device, shut down the device and allow
2946 * the PCI bus layer to put it into D3 in order to take the PCIe link
2947 * down, so as to allow the platform to achieve its minimum low-power
2948 * state (which may not be possible if the link is up).
2950 if (pm_suspend_via_firmware() || !ctrl
->npss
||
2951 !pcie_aspm_enabled(pdev
) ||
2952 (ndev
->ctrl
.quirks
& NVME_QUIRK_SIMPLE_SUSPEND
))
2953 return nvme_disable_prepare_reset(ndev
, true);
2955 nvme_start_freeze(ctrl
);
2956 nvme_wait_freeze(ctrl
);
2957 nvme_sync_queues(ctrl
);
2959 if (ctrl
->state
!= NVME_CTRL_LIVE
)
2962 ret
= nvme_get_power_state(ctrl
, &ndev
->last_ps
);
2967 * A saved state prevents pci pm from generically controlling the
2968 * device's power. If we're using protocol specific settings, we don't
2969 * want pci interfering.
2971 pci_save_state(pdev
);
2973 ret
= nvme_set_power_state(ctrl
, ctrl
->npss
);
2978 /* discard the saved state */
2979 pci_load_saved_state(pdev
, NULL
);
2982 * Clearing npss forces a controller reset on resume. The
2983 * correct value will be rediscovered then.
2985 ret
= nvme_disable_prepare_reset(ndev
, true);
2989 nvme_unfreeze(ctrl
);
2993 static int nvme_simple_suspend(struct device
*dev
)
2995 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
2996 return nvme_disable_prepare_reset(ndev
, true);
2999 static int nvme_simple_resume(struct device
*dev
)
3001 struct pci_dev
*pdev
= to_pci_dev(dev
);
3002 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
3004 return nvme_try_sched_reset(&ndev
->ctrl
);
3007 static const struct dev_pm_ops nvme_dev_pm_ops
= {
3008 .suspend
= nvme_suspend
,
3009 .resume
= nvme_resume
,
3010 .freeze
= nvme_simple_suspend
,
3011 .thaw
= nvme_simple_resume
,
3012 .poweroff
= nvme_simple_suspend
,
3013 .restore
= nvme_simple_resume
,
3015 #endif /* CONFIG_PM_SLEEP */
3017 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
3018 pci_channel_state_t state
)
3020 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3023 * A frozen channel requires a reset. When detected, this method will
3024 * shutdown the controller to quiesce. The controller will be restarted
3025 * after the slot reset through driver's slot_reset callback.
3028 case pci_channel_io_normal
:
3029 return PCI_ERS_RESULT_CAN_RECOVER
;
3030 case pci_channel_io_frozen
:
3031 dev_warn(dev
->ctrl
.device
,
3032 "frozen state error detected, reset controller\n");
3033 nvme_dev_disable(dev
, false);
3034 return PCI_ERS_RESULT_NEED_RESET
;
3035 case pci_channel_io_perm_failure
:
3036 dev_warn(dev
->ctrl
.device
,
3037 "failure state error detected, request disconnect\n");
3038 return PCI_ERS_RESULT_DISCONNECT
;
3040 return PCI_ERS_RESULT_NEED_RESET
;
3043 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
3045 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3047 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
3048 pci_restore_state(pdev
);
3049 nvme_reset_ctrl(&dev
->ctrl
);
3050 return PCI_ERS_RESULT_RECOVERED
;
3053 static void nvme_error_resume(struct pci_dev
*pdev
)
3055 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
3057 flush_work(&dev
->ctrl
.reset_work
);
3060 static const struct pci_error_handlers nvme_err_handler
= {
3061 .error_detected
= nvme_error_detected
,
3062 .slot_reset
= nvme_slot_reset
,
3063 .resume
= nvme_error_resume
,
3064 .reset_prepare
= nvme_reset_prepare
,
3065 .reset_done
= nvme_reset_done
,
3068 static const struct pci_device_id nvme_id_table
[] = {
3069 { PCI_VDEVICE(INTEL
, 0x0953),
3070 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3071 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3072 { PCI_VDEVICE(INTEL
, 0x0a53),
3073 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3074 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3075 { PCI_VDEVICE(INTEL
, 0x0a54),
3076 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3077 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3078 { PCI_VDEVICE(INTEL
, 0x0a55),
3079 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
3080 NVME_QUIRK_DEALLOCATE_ZEROES
, },
3081 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
3082 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3083 NVME_QUIRK_MEDIUM_PRIO_SQ
|
3084 NVME_QUIRK_NO_TEMP_THRESH_CHANGE
},
3085 { PCI_VDEVICE(INTEL
, 0xf1a6), /* Intel 760p/Pro 7600p */
3086 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3087 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
3088 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
|
3089 NVME_QUIRK_DISABLE_WRITE_ZEROES
, },
3090 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3091 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3092 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3093 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3094 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3095 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3096 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3097 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3098 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3099 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3100 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3101 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
3102 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3103 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3104 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3105 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3106 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3107 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
3108 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3109 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3110 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3111 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
3112 NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
3113 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
3114 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
3115 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
3116 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2005),
3117 .driver_data
= NVME_QUIRK_SINGLE_VECTOR
|
3118 NVME_QUIRK_128_BYTES_SQES
|
3119 NVME_QUIRK_SHARED_TAGS
},
3122 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
3124 static struct pci_driver nvme_driver
= {
3126 .id_table
= nvme_id_table
,
3127 .probe
= nvme_probe
,
3128 .remove
= nvme_remove
,
3129 .shutdown
= nvme_shutdown
,
3130 #ifdef CONFIG_PM_SLEEP
3132 .pm
= &nvme_dev_pm_ops
,
3135 .sriov_configure
= pci_sriov_configure_simple
,
3136 .err_handler
= &nvme_err_handler
,
3139 static int __init
nvme_init(void)
3141 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
3142 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
3143 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
3144 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS
< 2);
3145 return pci_register_driver(&nvme_driver
);
3148 static void __exit
nvme_exit(void)
3150 pci_unregister_driver(&nvme_driver
);
3151 flush_workqueue(nvme_wq
);
3154 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3155 MODULE_LICENSE("GPL");
3156 MODULE_VERSION("1.0");
3157 module_init(nvme_init
);
3158 module_exit(nvme_exit
);