2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/hdreg.h>
26 #include <linux/idr.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
30 #include <linux/kdev_t.h>
31 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/mutex.h>
36 #include <linux/pci.h>
37 #include <linux/poison.h>
38 #include <linux/ptrace.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/t10-pi.h>
42 #include <linux/timer.h>
43 #include <linux/types.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
46 #include <linux/sed-opal.h>
50 #define NVME_Q_DEPTH 1024
51 #define NVME_AQ_DEPTH 256
52 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
53 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
56 * We handle AEN commands ourselves and don't even let the
57 * block layer know about them.
59 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
61 static int use_threaded_interrupts
;
62 module_param(use_threaded_interrupts
, int, 0);
64 static bool use_cmb_sqes
= true;
65 module_param(use_cmb_sqes
, bool, 0644);
66 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
68 static struct workqueue_struct
*nvme_workq
;
73 static int nvme_reset(struct nvme_dev
*dev
);
74 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
75 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
78 * Represents an NVM Express device. Each nvme_dev is a PCI function.
81 struct nvme_queue
**queues
;
82 struct blk_mq_tag_set tagset
;
83 struct blk_mq_tag_set admin_tagset
;
86 struct dma_pool
*prp_page_pool
;
87 struct dma_pool
*prp_small_pool
;
89 unsigned online_queues
;
94 struct work_struct reset_work
;
95 struct work_struct remove_work
;
96 struct timer_list watchdog_timer
;
97 struct mutex shutdown_lock
;
100 dma_addr_t cmb_dma_addr
;
104 struct nvme_ctrl ctrl
;
105 struct completion ioq_wait
;
108 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
110 return container_of(ctrl
, struct nvme_dev
, ctrl
);
114 * An NVM Express queue. Each device has at least two (one for admin
115 * commands and one for I/O commands).
118 struct device
*q_dmadev
;
119 struct nvme_dev
*dev
;
120 char irqname
[24]; /* nvme4294967295-65535\0 */
122 struct nvme_command
*sq_cmds
;
123 struct nvme_command __iomem
*sq_cmds_io
;
124 volatile struct nvme_completion
*cqes
;
125 struct blk_mq_tags
**tags
;
126 dma_addr_t sq_dma_addr
;
127 dma_addr_t cq_dma_addr
;
139 * The nvme_iod describes the data in an I/O, including the list of PRP
140 * entries. You can't see it in this data structure because C doesn't let
141 * me express that. Use nvme_init_iod to ensure there's enough space
142 * allocated to store the PRP list.
145 struct nvme_request req
;
146 struct nvme_queue
*nvmeq
;
148 int npages
; /* In the PRP list. 0 means small pool in use */
149 int nents
; /* Used in scatterlist */
150 int length
; /* Of data, in bytes */
151 dma_addr_t first_dma
;
152 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
153 struct scatterlist
*sg
;
154 struct scatterlist inline_sg
[0];
158 * Check we didin't inadvertently grow the command struct
160 static inline void _nvme_check_size(void)
162 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
163 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
164 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
165 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
166 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
167 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
168 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
169 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
171 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
172 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
173 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
177 * Max size of iod being embedded in the request payload
179 #define NVME_INT_PAGES 2
180 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
183 * Will slightly overestimate the number of pages needed. This is OK
184 * as it only leads to a small amount of wasted memory for the lifetime of
187 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
189 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
190 dev
->ctrl
.page_size
);
191 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
194 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
195 unsigned int size
, unsigned int nseg
)
197 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
198 sizeof(struct scatterlist
) * nseg
;
201 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
203 return sizeof(struct nvme_iod
) +
204 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
207 static int nvmeq_irq(struct nvme_queue
*nvmeq
)
209 return pci_irq_vector(to_pci_dev(nvmeq
->dev
->dev
), nvmeq
->cq_vector
);
212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
213 unsigned int hctx_idx
)
215 struct nvme_dev
*dev
= data
;
216 struct nvme_queue
*nvmeq
= dev
->queues
[0];
218 WARN_ON(hctx_idx
!= 0);
219 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
220 WARN_ON(nvmeq
->tags
);
222 hctx
->driver_data
= nvmeq
;
223 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
229 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
234 static int nvme_admin_init_request(void *data
, struct request
*req
,
235 unsigned int hctx_idx
, unsigned int rq_idx
,
236 unsigned int numa_node
)
238 struct nvme_dev
*dev
= data
;
239 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
240 struct nvme_queue
*nvmeq
= dev
->queues
[0];
247 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
248 unsigned int hctx_idx
)
250 struct nvme_dev
*dev
= data
;
251 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
254 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
256 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
257 hctx
->driver_data
= nvmeq
;
261 static int nvme_init_request(void *data
, struct request
*req
,
262 unsigned int hctx_idx
, unsigned int rq_idx
,
263 unsigned int numa_node
)
265 struct nvme_dev
*dev
= data
;
266 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
267 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
274 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
276 struct nvme_dev
*dev
= set
->driver_data
;
278 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
282 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
283 * @nvmeq: The queue to use
284 * @cmd: The command to send
286 * Safe to use from interrupt context
288 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
289 struct nvme_command
*cmd
)
291 u16 tail
= nvmeq
->sq_tail
;
293 if (nvmeq
->sq_cmds_io
)
294 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
296 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
298 if (++tail
== nvmeq
->q_depth
)
300 writel(tail
, nvmeq
->q_db
);
301 nvmeq
->sq_tail
= tail
;
304 static __le64
**iod_list(struct request
*req
)
306 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
307 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
310 static int nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
312 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
313 int nseg
= blk_rq_nr_phys_segments(rq
);
314 unsigned int size
= blk_rq_payload_bytes(rq
);
316 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
317 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
319 return BLK_MQ_RQ_QUEUE_BUSY
;
321 iod
->sg
= iod
->inline_sg
;
329 if (!(rq
->rq_flags
& RQF_DONTPREP
)) {
331 rq
->rq_flags
|= RQF_DONTPREP
;
333 return BLK_MQ_RQ_QUEUE_OK
;
336 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
338 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
339 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
341 __le64
**list
= iod_list(req
);
342 dma_addr_t prp_dma
= iod
->first_dma
;
344 if (iod
->npages
== 0)
345 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
346 for (i
= 0; i
< iod
->npages
; i
++) {
347 __le64
*prp_list
= list
[i
];
348 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
349 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
350 prp_dma
= next_prp_dma
;
353 if (iod
->sg
!= iod
->inline_sg
)
357 #ifdef CONFIG_BLK_DEV_INTEGRITY
358 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
360 if (be32_to_cpu(pi
->ref_tag
) == v
)
361 pi
->ref_tag
= cpu_to_be32(p
);
364 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
366 if (be32_to_cpu(pi
->ref_tag
) == p
)
367 pi
->ref_tag
= cpu_to_be32(v
);
371 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
373 * The virtual start sector is the one that was originally submitted by the
374 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
375 * start sector may be different. Remap protection information to match the
376 * physical LBA on writes, and back to the original seed on reads.
378 * Type 0 and 3 do not have a ref tag, so no remapping required.
380 static void nvme_dif_remap(struct request
*req
,
381 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
383 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
384 struct bio_integrity_payload
*bip
;
385 struct t10_pi_tuple
*pi
;
387 u32 i
, nlb
, ts
, phys
, virt
;
389 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
392 bip
= bio_integrity(req
->bio
);
396 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
399 virt
= bip_get_seed(bip
);
400 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
401 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
402 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
404 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
405 pi
= (struct t10_pi_tuple
*)p
;
406 dif_swap(phys
, virt
, pi
);
411 #else /* CONFIG_BLK_DEV_INTEGRITY */
412 static void nvme_dif_remap(struct request
*req
,
413 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
416 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
419 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
424 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
426 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
427 struct dma_pool
*pool
;
428 int length
= blk_rq_payload_bytes(req
);
429 struct scatterlist
*sg
= iod
->sg
;
430 int dma_len
= sg_dma_len(sg
);
431 u64 dma_addr
= sg_dma_address(sg
);
432 u32 page_size
= dev
->ctrl
.page_size
;
433 int offset
= dma_addr
& (page_size
- 1);
435 __le64
**list
= iod_list(req
);
439 length
-= (page_size
- offset
);
443 dma_len
-= (page_size
- offset
);
445 dma_addr
+= (page_size
- offset
);
448 dma_addr
= sg_dma_address(sg
);
449 dma_len
= sg_dma_len(sg
);
452 if (length
<= page_size
) {
453 iod
->first_dma
= dma_addr
;
457 nprps
= DIV_ROUND_UP(length
, page_size
);
458 if (nprps
<= (256 / 8)) {
459 pool
= dev
->prp_small_pool
;
462 pool
= dev
->prp_page_pool
;
466 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
468 iod
->first_dma
= dma_addr
;
473 iod
->first_dma
= prp_dma
;
476 if (i
== page_size
>> 3) {
477 __le64
*old_prp_list
= prp_list
;
478 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
481 list
[iod
->npages
++] = prp_list
;
482 prp_list
[0] = old_prp_list
[i
- 1];
483 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
486 prp_list
[i
++] = cpu_to_le64(dma_addr
);
487 dma_len
-= page_size
;
488 dma_addr
+= page_size
;
496 dma_addr
= sg_dma_address(sg
);
497 dma_len
= sg_dma_len(sg
);
503 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
504 struct nvme_command
*cmnd
)
506 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
507 struct request_queue
*q
= req
->q
;
508 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
509 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
510 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
512 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
513 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
517 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
518 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
522 if (!nvme_setup_prps(dev
, req
))
525 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
526 if (blk_integrity_rq(req
)) {
527 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
530 sg_init_table(&iod
->meta_sg
, 1);
531 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
534 if (rq_data_dir(req
))
535 nvme_dif_remap(req
, nvme_dif_prep
);
537 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
541 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
542 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
543 if (blk_integrity_rq(req
))
544 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
545 return BLK_MQ_RQ_QUEUE_OK
;
548 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
553 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
555 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
556 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
557 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
560 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
561 if (blk_integrity_rq(req
)) {
562 if (!rq_data_dir(req
))
563 nvme_dif_remap(req
, nvme_dif_complete
);
564 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
568 nvme_cleanup_cmd(req
);
569 nvme_free_iod(dev
, req
);
573 * NOTE: ns is NULL when called on the admin queue.
575 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
576 const struct blk_mq_queue_data
*bd
)
578 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
579 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
580 struct nvme_dev
*dev
= nvmeq
->dev
;
581 struct request
*req
= bd
->rq
;
582 struct nvme_command cmnd
;
583 int ret
= BLK_MQ_RQ_QUEUE_OK
;
586 * If formated with metadata, require the block layer provide a buffer
587 * unless this namespace is formated such that the metadata can be
588 * stripped/generated by the controller with PRACT=1.
590 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
591 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
592 !blk_rq_is_passthrough(req
)) {
593 blk_mq_end_request(req
, -EFAULT
);
594 return BLK_MQ_RQ_QUEUE_OK
;
598 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
599 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
602 ret
= nvme_init_iod(req
, dev
);
603 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
606 if (blk_rq_nr_phys_segments(req
))
607 ret
= nvme_map_data(dev
, req
, &cmnd
);
609 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
610 goto out_cleanup_iod
;
612 blk_mq_start_request(req
);
614 spin_lock_irq(&nvmeq
->q_lock
);
615 if (unlikely(nvmeq
->cq_vector
< 0)) {
616 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
617 spin_unlock_irq(&nvmeq
->q_lock
);
618 goto out_cleanup_iod
;
620 __nvme_submit_cmd(nvmeq
, &cmnd
);
621 nvme_process_cq(nvmeq
);
622 spin_unlock_irq(&nvmeq
->q_lock
);
623 return BLK_MQ_RQ_QUEUE_OK
;
625 nvme_free_iod(dev
, req
);
627 nvme_cleanup_cmd(req
);
631 static void nvme_complete_rq(struct request
*req
)
633 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
634 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
637 nvme_unmap_data(dev
, req
);
639 if (unlikely(req
->errors
)) {
640 if (nvme_req_needs_retry(req
, req
->errors
)) {
642 nvme_requeue_req(req
);
646 if (blk_rq_is_passthrough(req
))
649 error
= nvme_error_status(req
->errors
);
652 if (unlikely(iod
->aborted
)) {
653 dev_warn(dev
->ctrl
.device
,
654 "completing aborted command with status: %04x\n",
658 blk_mq_end_request(req
, error
);
661 /* We read the CQE phase first to check if the rest of the entry is valid */
662 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
665 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
668 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
672 head
= nvmeq
->cq_head
;
673 phase
= nvmeq
->cq_phase
;
675 while (nvme_cqe_valid(nvmeq
, head
, phase
)) {
676 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
679 if (++head
== nvmeq
->q_depth
) {
684 if (tag
&& *tag
== cqe
.command_id
)
687 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
688 dev_warn(nvmeq
->dev
->ctrl
.device
,
689 "invalid id %d completed on queue %d\n",
690 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
695 * AEN requests are special as they don't time out and can
696 * survive any kind of queue freeze and often don't respond to
697 * aborts. We don't even bother to allocate a struct request
698 * for them but rather special case them here.
700 if (unlikely(nvmeq
->qid
== 0 &&
701 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
702 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
703 cqe
.status
, &cqe
.result
);
707 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
708 nvme_req(req
)->result
= cqe
.result
;
709 blk_mq_complete_request(req
, le16_to_cpu(cqe
.status
) >> 1);
712 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
715 if (likely(nvmeq
->cq_vector
>= 0))
716 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
717 nvmeq
->cq_head
= head
;
718 nvmeq
->cq_phase
= phase
;
723 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
725 __nvme_process_cq(nvmeq
, NULL
);
728 static irqreturn_t
nvme_irq(int irq
, void *data
)
731 struct nvme_queue
*nvmeq
= data
;
732 spin_lock(&nvmeq
->q_lock
);
733 nvme_process_cq(nvmeq
);
734 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
736 spin_unlock(&nvmeq
->q_lock
);
740 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
742 struct nvme_queue
*nvmeq
= data
;
743 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
744 return IRQ_WAKE_THREAD
;
748 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
750 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
752 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
753 spin_lock_irq(&nvmeq
->q_lock
);
754 __nvme_process_cq(nvmeq
, &tag
);
755 spin_unlock_irq(&nvmeq
->q_lock
);
764 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
766 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
767 struct nvme_queue
*nvmeq
= dev
->queues
[0];
768 struct nvme_command c
;
770 memset(&c
, 0, sizeof(c
));
771 c
.common
.opcode
= nvme_admin_async_event
;
772 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
774 spin_lock_irq(&nvmeq
->q_lock
);
775 __nvme_submit_cmd(nvmeq
, &c
);
776 spin_unlock_irq(&nvmeq
->q_lock
);
779 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
781 struct nvme_command c
;
783 memset(&c
, 0, sizeof(c
));
784 c
.delete_queue
.opcode
= opcode
;
785 c
.delete_queue
.qid
= cpu_to_le16(id
);
787 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
790 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
791 struct nvme_queue
*nvmeq
)
793 struct nvme_command c
;
794 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
797 * Note: we (ab)use the fact the the prp fields survive if no data
798 * is attached to the request.
800 memset(&c
, 0, sizeof(c
));
801 c
.create_cq
.opcode
= nvme_admin_create_cq
;
802 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
803 c
.create_cq
.cqid
= cpu_to_le16(qid
);
804 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
805 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
806 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
808 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
811 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
812 struct nvme_queue
*nvmeq
)
814 struct nvme_command c
;
815 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
818 * Note: we (ab)use the fact the the prp fields survive if no data
819 * is attached to the request.
821 memset(&c
, 0, sizeof(c
));
822 c
.create_sq
.opcode
= nvme_admin_create_sq
;
823 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
824 c
.create_sq
.sqid
= cpu_to_le16(qid
);
825 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
826 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
827 c
.create_sq
.cqid
= cpu_to_le16(qid
);
829 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
832 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
834 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
837 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
839 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
842 static void abort_endio(struct request
*req
, int error
)
844 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
845 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
846 u16 status
= req
->errors
;
848 dev_warn(nvmeq
->dev
->ctrl
.device
, "Abort status: 0x%x", status
);
849 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
850 blk_mq_free_request(req
);
853 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
855 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
856 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
857 struct nvme_dev
*dev
= nvmeq
->dev
;
858 struct request
*abort_req
;
859 struct nvme_command cmd
;
862 * Shutdown immediately if controller times out while starting. The
863 * reset work will see the pci device disabled when it gets the forced
864 * cancellation error. All outstanding requests are completed on
865 * shutdown, so we return BLK_EH_HANDLED.
867 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
868 dev_warn(dev
->ctrl
.device
,
869 "I/O %d QID %d timeout, disable controller\n",
870 req
->tag
, nvmeq
->qid
);
871 nvme_dev_disable(dev
, false);
872 req
->errors
= NVME_SC_CANCELLED
;
873 return BLK_EH_HANDLED
;
877 * Shutdown the controller immediately and schedule a reset if the
878 * command was already aborted once before and still hasn't been
879 * returned to the driver, or if this is the admin queue.
881 if (!nvmeq
->qid
|| iod
->aborted
) {
882 dev_warn(dev
->ctrl
.device
,
883 "I/O %d QID %d timeout, reset controller\n",
884 req
->tag
, nvmeq
->qid
);
885 nvme_dev_disable(dev
, false);
889 * Mark the request as handled, since the inline shutdown
890 * forces all outstanding requests to complete.
892 req
->errors
= NVME_SC_CANCELLED
;
893 return BLK_EH_HANDLED
;
896 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
897 atomic_inc(&dev
->ctrl
.abort_limit
);
898 return BLK_EH_RESET_TIMER
;
902 memset(&cmd
, 0, sizeof(cmd
));
903 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
904 cmd
.abort
.cid
= req
->tag
;
905 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
907 dev_warn(nvmeq
->dev
->ctrl
.device
,
908 "I/O %d QID %d timeout, aborting\n",
909 req
->tag
, nvmeq
->qid
);
911 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
912 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
913 if (IS_ERR(abort_req
)) {
914 atomic_inc(&dev
->ctrl
.abort_limit
);
915 return BLK_EH_RESET_TIMER
;
918 abort_req
->timeout
= ADMIN_TIMEOUT
;
919 abort_req
->end_io_data
= NULL
;
920 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
923 * The aborted req will be completed on receiving the abort req.
924 * We enable the timer again. If hit twice, it'll cause a device reset,
925 * as the device then is in a faulty state.
927 return BLK_EH_RESET_TIMER
;
930 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
932 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
933 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
935 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
936 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
940 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
944 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
945 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
947 dev
->queues
[i
] = NULL
;
948 nvme_free_queue(nvmeq
);
953 * nvme_suspend_queue - put queue into suspended state
954 * @nvmeq - queue to suspend
956 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
960 spin_lock_irq(&nvmeq
->q_lock
);
961 if (nvmeq
->cq_vector
== -1) {
962 spin_unlock_irq(&nvmeq
->q_lock
);
965 vector
= nvmeq_irq(nvmeq
);
966 nvmeq
->dev
->online_queues
--;
967 nvmeq
->cq_vector
= -1;
968 spin_unlock_irq(&nvmeq
->q_lock
);
970 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
971 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
973 free_irq(vector
, nvmeq
);
978 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
980 struct nvme_queue
*nvmeq
= dev
->queues
[0];
984 if (nvme_suspend_queue(nvmeq
))
988 nvme_shutdown_ctrl(&dev
->ctrl
);
990 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
991 dev
->bar
+ NVME_REG_CAP
));
993 spin_lock_irq(&nvmeq
->q_lock
);
994 nvme_process_cq(nvmeq
);
995 spin_unlock_irq(&nvmeq
->q_lock
);
998 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1001 int q_depth
= dev
->q_depth
;
1002 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1003 dev
->ctrl
.page_size
);
1005 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1006 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1007 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1008 q_depth
= div_u64(mem_per_q
, entry_size
);
1011 * Ensure the reduced q_depth is above some threshold where it
1012 * would be better to map queues in system memory with the
1022 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1025 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1026 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1027 dev
->ctrl
.page_size
);
1028 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1029 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1031 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1032 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1033 if (!nvmeq
->sq_cmds
)
1040 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1043 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1047 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1048 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1052 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1055 nvmeq
->q_dmadev
= dev
->dev
;
1057 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1058 dev
->ctrl
.instance
, qid
);
1059 spin_lock_init(&nvmeq
->q_lock
);
1061 nvmeq
->cq_phase
= 1;
1062 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1063 nvmeq
->q_depth
= depth
;
1065 nvmeq
->cq_vector
= -1;
1066 dev
->queues
[qid
] = nvmeq
;
1072 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1073 nvmeq
->cq_dma_addr
);
1079 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1081 if (use_threaded_interrupts
)
1082 return request_threaded_irq(nvmeq_irq(nvmeq
), nvme_irq_check
,
1083 nvme_irq
, IRQF_SHARED
, nvmeq
->irqname
, nvmeq
);
1085 return request_irq(nvmeq_irq(nvmeq
), nvme_irq
, IRQF_SHARED
,
1086 nvmeq
->irqname
, nvmeq
);
1089 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1091 struct nvme_dev
*dev
= nvmeq
->dev
;
1093 spin_lock_irq(&nvmeq
->q_lock
);
1096 nvmeq
->cq_phase
= 1;
1097 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1098 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1099 dev
->online_queues
++;
1100 spin_unlock_irq(&nvmeq
->q_lock
);
1103 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1105 struct nvme_dev
*dev
= nvmeq
->dev
;
1108 nvmeq
->cq_vector
= qid
- 1;
1109 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1113 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1117 result
= queue_request_irq(nvmeq
);
1121 nvme_init_queue(nvmeq
, qid
);
1125 adapter_delete_sq(dev
, qid
);
1127 adapter_delete_cq(dev
, qid
);
1131 static struct blk_mq_ops nvme_mq_admin_ops
= {
1132 .queue_rq
= nvme_queue_rq
,
1133 .complete
= nvme_complete_rq
,
1134 .init_hctx
= nvme_admin_init_hctx
,
1135 .exit_hctx
= nvme_admin_exit_hctx
,
1136 .init_request
= nvme_admin_init_request
,
1137 .timeout
= nvme_timeout
,
1140 static struct blk_mq_ops nvme_mq_ops
= {
1141 .queue_rq
= nvme_queue_rq
,
1142 .complete
= nvme_complete_rq
,
1143 .init_hctx
= nvme_init_hctx
,
1144 .init_request
= nvme_init_request
,
1145 .map_queues
= nvme_pci_map_queues
,
1146 .timeout
= nvme_timeout
,
1150 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1152 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1154 * If the controller was reset during removal, it's possible
1155 * user requests may be waiting on a stopped queue. Start the
1156 * queue to flush these to completion.
1158 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1159 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1160 blk_mq_free_tag_set(&dev
->admin_tagset
);
1164 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1166 if (!dev
->ctrl
.admin_q
) {
1167 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1168 dev
->admin_tagset
.nr_hw_queues
= 1;
1171 * Subtract one to leave an empty queue entry for 'Full Queue'
1172 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1174 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1175 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1176 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1177 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1178 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1179 dev
->admin_tagset
.driver_data
= dev
;
1181 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1184 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1185 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1186 blk_mq_free_tag_set(&dev
->admin_tagset
);
1189 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1190 nvme_dev_remove_admin(dev
);
1191 dev
->ctrl
.admin_q
= NULL
;
1195 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1200 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1204 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1205 struct nvme_queue
*nvmeq
;
1207 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1208 NVME_CAP_NSSRC(cap
) : 0;
1210 if (dev
->subsystem
&&
1211 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1212 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1214 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1218 nvmeq
= dev
->queues
[0];
1220 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1225 aqa
= nvmeq
->q_depth
- 1;
1228 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1229 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1230 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1232 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1236 nvmeq
->cq_vector
= 0;
1237 result
= queue_request_irq(nvmeq
);
1239 nvmeq
->cq_vector
= -1;
1246 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1249 /* If true, indicates loss of adapter communication, possibly by a
1250 * NVMe Subsystem reset.
1252 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1254 /* If there is a reset ongoing, we shouldn't reset again. */
1255 if (work_busy(&dev
->reset_work
))
1258 /* We shouldn't reset unless the controller is on fatal error state
1259 * _or_ if we lost the communication with it.
1261 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1264 /* If PCI error recovery process is happening, we cannot reset or
1265 * the recovery mechanism will surely fail.
1267 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1273 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1275 /* Read a config register to help see what died. */
1279 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1281 if (result
== PCIBIOS_SUCCESSFUL
)
1283 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1287 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1291 static void nvme_watchdog_timer(unsigned long data
)
1293 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1294 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1296 /* Skip controllers under certain specific conditions. */
1297 if (nvme_should_reset(dev
, csts
)) {
1298 if (!nvme_reset(dev
))
1299 nvme_warn_reset(dev
, csts
);
1303 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1306 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1311 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1312 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1318 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1319 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1320 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1326 * Ignore failing Create SQ/CQ commands, we can continue with less
1327 * than the desired aount of queues, and even a controller without
1328 * I/O queues an still be used to issue admin commands. This might
1329 * be useful to upgrade a buggy firmware for example.
1331 return ret
>= 0 ? 0 : ret
;
1334 static ssize_t
nvme_cmb_show(struct device
*dev
,
1335 struct device_attribute
*attr
,
1338 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1340 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1341 ndev
->cmbloc
, ndev
->cmbsz
);
1343 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1345 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1347 u64 szu
, size
, offset
;
1348 resource_size_t bar_size
;
1349 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1351 dma_addr_t dma_addr
;
1353 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1354 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1356 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1361 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1362 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1363 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1364 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1366 if (offset
> bar_size
)
1370 * Controllers may support a CMB size larger than their BAR,
1371 * for example, due to being behind a bridge. Reduce the CMB to
1372 * the reported size of the BAR
1374 if (size
> bar_size
- offset
)
1375 size
= bar_size
- offset
;
1377 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1378 cmb
= ioremap_wc(dma_addr
, size
);
1382 dev
->cmb_dma_addr
= dma_addr
;
1383 dev
->cmb_size
= size
;
1387 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1395 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1397 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1400 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1402 struct nvme_queue
*adminq
= dev
->queues
[0];
1403 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1404 int result
, nr_io_queues
, size
;
1406 nr_io_queues
= num_online_cpus();
1407 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1411 if (nr_io_queues
== 0)
1414 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1415 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1416 sizeof(struct nvme_command
));
1418 dev
->q_depth
= result
;
1420 nvme_release_cmb(dev
);
1423 size
= db_bar_size(dev
, nr_io_queues
);
1427 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1430 if (!--nr_io_queues
)
1432 size
= db_bar_size(dev
, nr_io_queues
);
1434 dev
->dbs
= dev
->bar
+ 4096;
1435 adminq
->q_db
= dev
->dbs
;
1438 /* Deregister the admin queue's interrupt */
1439 free_irq(pci_irq_vector(pdev
, 0), adminq
);
1442 * If we enable msix early due to not intx, disable it again before
1443 * setting up the full range we need.
1445 pci_free_irq_vectors(pdev
);
1446 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1447 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1448 if (nr_io_queues
<= 0)
1450 dev
->max_qid
= nr_io_queues
;
1453 * Should investigate if there's a performance win from allocating
1454 * more queues than interrupt vectors; it might allow the submission
1455 * path to scale better, even if the receive path is limited by the
1456 * number of interrupts.
1459 result
= queue_request_irq(adminq
);
1461 adminq
->cq_vector
= -1;
1464 return nvme_create_io_queues(dev
);
1467 static void nvme_del_queue_end(struct request
*req
, int error
)
1469 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1471 blk_mq_free_request(req
);
1472 complete(&nvmeq
->dev
->ioq_wait
);
1475 static void nvme_del_cq_end(struct request
*req
, int error
)
1477 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1480 unsigned long flags
;
1483 * We might be called with the AQ q_lock held
1484 * and the I/O queue q_lock should always
1485 * nest inside the AQ one.
1487 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1488 SINGLE_DEPTH_NESTING
);
1489 nvme_process_cq(nvmeq
);
1490 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1493 nvme_del_queue_end(req
, error
);
1496 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1498 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1499 struct request
*req
;
1500 struct nvme_command cmd
;
1502 memset(&cmd
, 0, sizeof(cmd
));
1503 cmd
.delete_queue
.opcode
= opcode
;
1504 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1506 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1508 return PTR_ERR(req
);
1510 req
->timeout
= ADMIN_TIMEOUT
;
1511 req
->end_io_data
= nvmeq
;
1513 blk_execute_rq_nowait(q
, NULL
, req
, false,
1514 opcode
== nvme_admin_delete_cq
?
1515 nvme_del_cq_end
: nvme_del_queue_end
);
1519 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1522 unsigned long timeout
;
1523 u8 opcode
= nvme_admin_delete_sq
;
1525 for (pass
= 0; pass
< 2; pass
++) {
1526 int sent
= 0, i
= queues
;
1528 reinit_completion(&dev
->ioq_wait
);
1530 timeout
= ADMIN_TIMEOUT
;
1531 for (; i
> 0; i
--, sent
++)
1532 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1536 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1542 opcode
= nvme_admin_delete_cq
;
1547 * Return: error value if an error occurred setting up the queues or calling
1548 * Identify Device. 0 if these succeeded, even if adding some of the
1549 * namespaces failed. At the moment, these failures are silent. TBD which
1550 * failures should be reported.
1552 static int nvme_dev_add(struct nvme_dev
*dev
)
1554 if (!dev
->ctrl
.tagset
) {
1555 dev
->tagset
.ops
= &nvme_mq_ops
;
1556 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1557 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1558 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1559 dev
->tagset
.queue_depth
=
1560 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1561 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1562 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1563 dev
->tagset
.driver_data
= dev
;
1565 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1567 dev
->ctrl
.tagset
= &dev
->tagset
;
1569 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1571 /* Free previously allocated queues that are no longer usable */
1572 nvme_free_queues(dev
, dev
->online_queues
);
1578 static int nvme_pci_enable(struct nvme_dev
*dev
)
1581 int result
= -ENOMEM
;
1582 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1584 if (pci_enable_device_mem(pdev
))
1587 pci_set_master(pdev
);
1589 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1590 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1593 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1599 * Some devices and/or platforms don't advertise or work with INTx
1600 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1601 * adjust this later.
1603 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1607 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1609 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1610 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1611 dev
->dbs
= dev
->bar
+ 4096;
1614 * Temporary fix for the Apple controller found in the MacBook8,1 and
1615 * some MacBook7,1 to avoid controller resets and data loss.
1617 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1619 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1620 "queue depth=%u to work around controller resets\n",
1625 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1626 * populate sysfs if a CMB is implemented. Note that we add the
1627 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1628 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1629 * NULL as final argument to sysfs_add_file_to_group.
1632 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1633 dev
->cmb
= nvme_map_cmb(dev
);
1636 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1637 &dev_attr_cmb
.attr
, NULL
))
1639 "failed to add sysfs attribute for CMB\n");
1643 pci_enable_pcie_error_reporting(pdev
);
1644 pci_save_state(pdev
);
1648 pci_disable_device(pdev
);
1652 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1656 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1659 static void nvme_pci_disable(struct nvme_dev
*dev
)
1661 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1663 pci_free_irq_vectors(pdev
);
1665 if (pci_is_enabled(pdev
)) {
1666 pci_disable_pcie_error_reporting(pdev
);
1667 pci_disable_device(pdev
);
1671 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1676 del_timer_sync(&dev
->watchdog_timer
);
1678 mutex_lock(&dev
->shutdown_lock
);
1679 if (pci_is_enabled(to_pci_dev(dev
->dev
))) {
1680 nvme_stop_queues(&dev
->ctrl
);
1681 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1684 queues
= dev
->online_queues
- 1;
1685 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1686 nvme_suspend_queue(dev
->queues
[i
]);
1688 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1689 /* A device might become IO incapable very soon during
1690 * probe, before the admin queue is configured. Thus,
1691 * queue_count can be 0 here.
1693 if (dev
->queue_count
)
1694 nvme_suspend_queue(dev
->queues
[0]);
1696 nvme_disable_io_queues(dev
, queues
);
1697 nvme_disable_admin_queue(dev
, shutdown
);
1699 nvme_pci_disable(dev
);
1701 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
1702 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
1703 mutex_unlock(&dev
->shutdown_lock
);
1706 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1708 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1709 PAGE_SIZE
, PAGE_SIZE
, 0);
1710 if (!dev
->prp_page_pool
)
1713 /* Optimisation for I/Os between 4k and 128k */
1714 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1716 if (!dev
->prp_small_pool
) {
1717 dma_pool_destroy(dev
->prp_page_pool
);
1723 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1725 dma_pool_destroy(dev
->prp_page_pool
);
1726 dma_pool_destroy(dev
->prp_small_pool
);
1729 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1731 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1733 put_device(dev
->dev
);
1734 if (dev
->tagset
.tags
)
1735 blk_mq_free_tag_set(&dev
->tagset
);
1736 if (dev
->ctrl
.admin_q
)
1737 blk_put_queue(dev
->ctrl
.admin_q
);
1739 free_opal_dev(dev
->ctrl
.opal_dev
);
1743 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
1745 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
1747 kref_get(&dev
->ctrl
.kref
);
1748 nvme_dev_disable(dev
, false);
1749 if (!schedule_work(&dev
->remove_work
))
1750 nvme_put_ctrl(&dev
->ctrl
);
1753 static void nvme_reset_work(struct work_struct
*work
)
1755 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1756 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
1757 int result
= -ENODEV
;
1759 if (WARN_ON(dev
->ctrl
.state
== NVME_CTRL_RESETTING
))
1763 * If we're called to reset a live controller first shut it down before
1766 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
1767 nvme_dev_disable(dev
, false);
1769 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
))
1772 result
= nvme_pci_enable(dev
);
1776 result
= nvme_configure_admin_queue(dev
);
1780 nvme_init_queue(dev
->queues
[0], 0);
1781 result
= nvme_alloc_admin_tags(dev
);
1785 result
= nvme_init_identify(&dev
->ctrl
);
1789 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
1790 if (!dev
->ctrl
.opal_dev
)
1791 dev
->ctrl
.opal_dev
=
1792 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
1793 else if (was_suspend
)
1794 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
1796 free_opal_dev(dev
->ctrl
.opal_dev
);
1797 dev
->ctrl
.opal_dev
= NULL
;
1800 result
= nvme_setup_io_queues(dev
);
1805 * A controller that can not execute IO typically requires user
1806 * intervention to correct. For such degraded controllers, the driver
1807 * should not submit commands the user did not request, so skip
1808 * registering for asynchronous event notification on this condition.
1810 if (dev
->online_queues
> 1)
1811 nvme_queue_async_events(&dev
->ctrl
);
1813 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1816 * Keep the controller around but remove all namespaces if we don't have
1817 * any working I/O queue.
1819 if (dev
->online_queues
< 2) {
1820 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
1821 nvme_kill_queues(&dev
->ctrl
);
1822 nvme_remove_namespaces(&dev
->ctrl
);
1824 nvme_start_queues(&dev
->ctrl
);
1828 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
1829 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
1833 if (dev
->online_queues
> 1)
1834 nvme_queue_scan(&dev
->ctrl
);
1838 nvme_remove_dead_ctrl(dev
, result
);
1841 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1843 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1844 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1846 nvme_kill_queues(&dev
->ctrl
);
1847 if (pci_get_drvdata(pdev
))
1848 device_release_driver(&pdev
->dev
);
1849 nvme_put_ctrl(&dev
->ctrl
);
1852 static int nvme_reset(struct nvme_dev
*dev
)
1854 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1856 if (work_busy(&dev
->reset_work
))
1858 if (!queue_work(nvme_workq
, &dev
->reset_work
))
1863 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
1865 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
1869 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
1871 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
1875 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
1877 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
1881 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
1883 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1884 int ret
= nvme_reset(dev
);
1887 flush_work(&dev
->reset_work
);
1891 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
1893 .module
= THIS_MODULE
,
1894 .reg_read32
= nvme_pci_reg_read32
,
1895 .reg_write32
= nvme_pci_reg_write32
,
1896 .reg_read64
= nvme_pci_reg_read64
,
1897 .reset_ctrl
= nvme_pci_reset_ctrl
,
1898 .free_ctrl
= nvme_pci_free_ctrl
,
1899 .submit_async_event
= nvme_pci_submit_async_event
,
1902 static int nvme_dev_map(struct nvme_dev
*dev
)
1904 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1906 if (pci_request_mem_regions(pdev
, "nvme"))
1909 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1915 pci_release_mem_regions(pdev
);
1919 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1921 int node
, result
= -ENOMEM
;
1922 struct nvme_dev
*dev
;
1924 node
= dev_to_node(&pdev
->dev
);
1925 if (node
== NUMA_NO_NODE
)
1926 set_dev_node(&pdev
->dev
, first_memory_node
);
1928 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
1931 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1936 dev
->dev
= get_device(&pdev
->dev
);
1937 pci_set_drvdata(pdev
, dev
);
1939 result
= nvme_dev_map(dev
);
1943 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
1944 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
1945 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
1946 (unsigned long)dev
);
1947 mutex_init(&dev
->shutdown_lock
);
1948 init_completion(&dev
->ioq_wait
);
1950 result
= nvme_setup_prp_pools(dev
);
1954 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
1959 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
1961 queue_work(nvme_workq
, &dev
->reset_work
);
1965 nvme_release_prp_pools(dev
);
1967 put_device(dev
->dev
);
1968 nvme_dev_unmap(dev
);
1975 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
1977 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1980 nvme_dev_disable(dev
, false);
1985 static void nvme_shutdown(struct pci_dev
*pdev
)
1987 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1988 nvme_dev_disable(dev
, true);
1992 * The driver's remove may be called on a device in a partially initialized
1993 * state. This function must not have any dependencies on the device state in
1996 static void nvme_remove(struct pci_dev
*pdev
)
1998 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2000 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2002 pci_set_drvdata(pdev
, NULL
);
2004 if (!pci_device_is_present(pdev
)) {
2005 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2006 nvme_dev_disable(dev
, false);
2009 flush_work(&dev
->reset_work
);
2010 nvme_uninit_ctrl(&dev
->ctrl
);
2011 nvme_dev_disable(dev
, true);
2012 nvme_dev_remove_admin(dev
);
2013 nvme_free_queues(dev
, 0);
2014 nvme_release_cmb(dev
);
2015 nvme_release_prp_pools(dev
);
2016 nvme_dev_unmap(dev
);
2017 nvme_put_ctrl(&dev
->ctrl
);
2020 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2025 if (pci_vfs_assigned(pdev
)) {
2026 dev_warn(&pdev
->dev
,
2027 "Cannot disable SR-IOV VFs while assigned\n");
2030 pci_disable_sriov(pdev
);
2034 ret
= pci_enable_sriov(pdev
, numvfs
);
2035 return ret
? ret
: numvfs
;
2038 #ifdef CONFIG_PM_SLEEP
2039 static int nvme_suspend(struct device
*dev
)
2041 struct pci_dev
*pdev
= to_pci_dev(dev
);
2042 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2044 nvme_dev_disable(ndev
, true);
2048 static int nvme_resume(struct device
*dev
)
2050 struct pci_dev
*pdev
= to_pci_dev(dev
);
2051 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2058 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2060 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2061 pci_channel_state_t state
)
2063 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2066 * A frozen channel requires a reset. When detected, this method will
2067 * shutdown the controller to quiesce. The controller will be restarted
2068 * after the slot reset through driver's slot_reset callback.
2071 case pci_channel_io_normal
:
2072 return PCI_ERS_RESULT_CAN_RECOVER
;
2073 case pci_channel_io_frozen
:
2074 dev_warn(dev
->ctrl
.device
,
2075 "frozen state error detected, reset controller\n");
2076 nvme_dev_disable(dev
, false);
2077 return PCI_ERS_RESULT_NEED_RESET
;
2078 case pci_channel_io_perm_failure
:
2079 dev_warn(dev
->ctrl
.device
,
2080 "failure state error detected, request disconnect\n");
2081 return PCI_ERS_RESULT_DISCONNECT
;
2083 return PCI_ERS_RESULT_NEED_RESET
;
2086 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2088 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2090 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2091 pci_restore_state(pdev
);
2093 return PCI_ERS_RESULT_RECOVERED
;
2096 static void nvme_error_resume(struct pci_dev
*pdev
)
2098 pci_cleanup_aer_uncorrect_error_status(pdev
);
2101 static const struct pci_error_handlers nvme_err_handler
= {
2102 .error_detected
= nvme_error_detected
,
2103 .slot_reset
= nvme_slot_reset
,
2104 .resume
= nvme_error_resume
,
2105 .reset_notify
= nvme_reset_notify
,
2108 static const struct pci_device_id nvme_id_table
[] = {
2109 { PCI_VDEVICE(INTEL
, 0x0953),
2110 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2111 NVME_QUIRK_DISCARD_ZEROES
, },
2112 { PCI_VDEVICE(INTEL
, 0x0a53),
2113 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2114 NVME_QUIRK_DISCARD_ZEROES
, },
2115 { PCI_VDEVICE(INTEL
, 0x0a54),
2116 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2117 NVME_QUIRK_DISCARD_ZEROES
, },
2118 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2119 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2120 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2121 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2122 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2123 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2124 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2125 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2126 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2129 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2131 static struct pci_driver nvme_driver
= {
2133 .id_table
= nvme_id_table
,
2134 .probe
= nvme_probe
,
2135 .remove
= nvme_remove
,
2136 .shutdown
= nvme_shutdown
,
2138 .pm
= &nvme_dev_pm_ops
,
2140 .sriov_configure
= nvme_pci_sriov_configure
,
2141 .err_handler
= &nvme_err_handler
,
2144 static int __init
nvme_init(void)
2148 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2152 result
= pci_register_driver(&nvme_driver
);
2154 destroy_workqueue(nvme_workq
);
2158 static void __exit
nvme_exit(void)
2160 pci_unregister_driver(&nvme_driver
);
2161 destroy_workqueue(nvme_workq
);
2165 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2166 MODULE_LICENSE("GPL");
2167 MODULE_VERSION("1.0");
2168 module_init(nvme_init
);
2169 module_exit(nvme_exit
);