2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
42 #include <linux/io-64-nonatomic-lo-hi.h>
43 #include <asm/unaligned.h>
47 #define NVME_Q_DEPTH 1024
48 #define NVME_AQ_DEPTH 256
49 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
50 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
52 unsigned char admin_timeout
= 60;
53 module_param(admin_timeout
, byte
, 0644);
54 MODULE_PARM_DESC(admin_timeout
, "timeout in seconds for admin commands");
56 unsigned char nvme_io_timeout
= 30;
57 module_param_named(io_timeout
, nvme_io_timeout
, byte
, 0644);
58 MODULE_PARM_DESC(io_timeout
, "timeout in seconds for I/O");
60 unsigned char shutdown_timeout
= 5;
61 module_param(shutdown_timeout
, byte
, 0644);
62 MODULE_PARM_DESC(shutdown_timeout
, "timeout in seconds for controller shutdown");
64 static int use_threaded_interrupts
;
65 module_param(use_threaded_interrupts
, int, 0);
67 static bool use_cmb_sqes
= true;
68 module_param(use_cmb_sqes
, bool, 0644);
69 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
71 static LIST_HEAD(dev_list
);
72 static struct task_struct
*nvme_thread
;
73 static struct workqueue_struct
*nvme_workq
;
74 static wait_queue_head_t nvme_kthread_wait
;
80 static int nvme_reset(struct nvme_dev
*dev
);
81 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
82 static void nvme_unmap_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
);
83 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
);
84 static void nvme_dev_shutdown(struct nvme_dev
*dev
);
86 struct async_cmd_info
{
87 struct kthread_work work
;
88 struct kthread_worker
*worker
;
94 * Represents an NVM Express device. Each nvme_dev is a PCI function.
97 struct list_head node
;
98 struct nvme_queue
**queues
;
99 struct blk_mq_tag_set tagset
;
100 struct blk_mq_tag_set admin_tagset
;
103 struct dma_pool
*prp_page_pool
;
104 struct dma_pool
*prp_small_pool
;
105 unsigned queue_count
;
106 unsigned online_queues
;
110 struct msix_entry
*entry
;
112 struct work_struct reset_work
;
113 struct work_struct scan_work
;
114 struct work_struct remove_work
;
115 struct mutex shutdown_lock
;
118 dma_addr_t cmb_dma_addr
;
122 #define NVME_CTRL_RESETTING 0
124 struct nvme_ctrl ctrl
;
127 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
129 return container_of(ctrl
, struct nvme_dev
, ctrl
);
133 * An NVM Express queue. Each device has at least two (one for admin
134 * commands and one for I/O commands).
137 struct device
*q_dmadev
;
138 struct nvme_dev
*dev
;
139 char irqname
[24]; /* nvme4294967295-65535\0 */
141 struct nvme_command
*sq_cmds
;
142 struct nvme_command __iomem
*sq_cmds_io
;
143 volatile struct nvme_completion
*cqes
;
144 struct blk_mq_tags
**tags
;
145 dma_addr_t sq_dma_addr
;
146 dma_addr_t cq_dma_addr
;
156 struct async_cmd_info cmdinfo
;
160 * The nvme_iod describes the data in an I/O, including the list of PRP
161 * entries. You can't see it in this data structure because C doesn't let
162 * me express that. Use nvme_alloc_iod to ensure there's enough space
163 * allocated to store the PRP list.
166 unsigned long private; /* For the use of the submitter of the I/O */
167 int npages
; /* In the PRP list. 0 means small pool in use */
168 int offset
; /* Of PRP list */
169 int nents
; /* Used in scatterlist */
170 int length
; /* Of data, in bytes */
171 dma_addr_t first_dma
;
172 struct scatterlist meta_sg
[1]; /* metadata requires single contiguous buffer */
173 struct scatterlist sg
[0];
177 * Check we didin't inadvertently grow the command struct
179 static inline void _nvme_check_size(void)
181 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
188 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
190 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
191 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
192 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
195 typedef void (*nvme_completion_fn
)(struct nvme_queue
*, void *,
196 struct nvme_completion
*);
198 struct nvme_cmd_info
{
199 nvme_completion_fn fn
;
202 struct nvme_queue
*nvmeq
;
203 struct nvme_iod iod
[0];
207 * Max size of iod being embedded in the request payload
209 #define NVME_INT_PAGES 2
210 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
211 #define NVME_INT_MASK 0x01
214 * Will slightly overestimate the number of pages needed. This is OK
215 * as it only leads to a small amount of wasted memory for the lifetime of
218 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
220 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
221 dev
->ctrl
.page_size
);
222 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
225 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
227 unsigned int ret
= sizeof(struct nvme_cmd_info
);
229 ret
+= sizeof(struct nvme_iod
);
230 ret
+= sizeof(__le64
*) * nvme_npages(NVME_INT_BYTES(dev
), dev
);
231 ret
+= sizeof(struct scatterlist
) * NVME_INT_PAGES
;
236 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
237 unsigned int hctx_idx
)
239 struct nvme_dev
*dev
= data
;
240 struct nvme_queue
*nvmeq
= dev
->queues
[0];
242 WARN_ON(hctx_idx
!= 0);
243 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
244 WARN_ON(nvmeq
->tags
);
246 hctx
->driver_data
= nvmeq
;
247 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
251 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
253 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
258 static int nvme_admin_init_request(void *data
, struct request
*req
,
259 unsigned int hctx_idx
, unsigned int rq_idx
,
260 unsigned int numa_node
)
262 struct nvme_dev
*dev
= data
;
263 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
264 struct nvme_queue
*nvmeq
= dev
->queues
[0];
271 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
272 unsigned int hctx_idx
)
274 struct nvme_dev
*dev
= data
;
275 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
278 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
280 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
281 hctx
->driver_data
= nvmeq
;
285 static int nvme_init_request(void *data
, struct request
*req
,
286 unsigned int hctx_idx
, unsigned int rq_idx
,
287 unsigned int numa_node
)
289 struct nvme_dev
*dev
= data
;
290 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
291 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
298 static void nvme_set_info(struct nvme_cmd_info
*cmd
, void *ctx
,
299 nvme_completion_fn handler
)
304 blk_mq_start_request(blk_mq_rq_from_pdu(cmd
));
307 static void *iod_get_private(struct nvme_iod
*iod
)
309 return (void *) (iod
->private & ~0x1UL
);
313 * If bit 0 is set, the iod is embedded in the request payload.
315 static bool iod_should_kfree(struct nvme_iod
*iod
)
317 return (iod
->private & NVME_INT_MASK
) == 0;
320 /* Special values must be less than 0x1000 */
321 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
322 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
323 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
324 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
326 static void special_completion(struct nvme_queue
*nvmeq
, void *ctx
,
327 struct nvme_completion
*cqe
)
329 if (ctx
== CMD_CTX_CANCELLED
)
331 if (ctx
== CMD_CTX_COMPLETED
) {
332 dev_warn(nvmeq
->q_dmadev
,
333 "completed id %d twice on queue %d\n",
334 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
337 if (ctx
== CMD_CTX_INVALID
) {
338 dev_warn(nvmeq
->q_dmadev
,
339 "invalid id %d completed on queue %d\n",
340 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
343 dev_warn(nvmeq
->q_dmadev
, "Unknown special completion %p\n", ctx
);
346 static void *cancel_cmd_info(struct nvme_cmd_info
*cmd
, nvme_completion_fn
*fn
)
353 cmd
->fn
= special_completion
;
354 cmd
->ctx
= CMD_CTX_CANCELLED
;
358 static void async_req_completion(struct nvme_queue
*nvmeq
, void *ctx
,
359 struct nvme_completion
*cqe
)
361 u32 result
= le32_to_cpup(&cqe
->result
);
362 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
364 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
)
365 ++nvmeq
->dev
->ctrl
.event_limit
;
366 if (status
!= NVME_SC_SUCCESS
)
369 switch (result
& 0xff07) {
370 case NVME_AER_NOTICE_NS_CHANGED
:
371 dev_info(nvmeq
->q_dmadev
, "rescanning\n");
372 queue_work(nvme_workq
, &nvmeq
->dev
->scan_work
);
374 dev_warn(nvmeq
->q_dmadev
, "async event result %08x\n", result
);
378 static void abort_completion(struct nvme_queue
*nvmeq
, void *ctx
,
379 struct nvme_completion
*cqe
)
381 struct request
*req
= ctx
;
383 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
384 u32 result
= le32_to_cpup(&cqe
->result
);
386 blk_mq_free_request(req
);
388 dev_warn(nvmeq
->q_dmadev
, "Abort status:%x result:%x", status
, result
);
389 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
392 static inline struct nvme_cmd_info
*get_cmd_from_tag(struct nvme_queue
*nvmeq
,
395 struct request
*req
= blk_mq_tag_to_rq(*nvmeq
->tags
, tag
);
397 return blk_mq_rq_to_pdu(req
);
401 * Called with local interrupts disabled and the q_lock held. May not sleep.
403 static void *nvme_finish_cmd(struct nvme_queue
*nvmeq
, int tag
,
404 nvme_completion_fn
*fn
)
406 struct nvme_cmd_info
*cmd
= get_cmd_from_tag(nvmeq
, tag
);
408 if (tag
>= nvmeq
->q_depth
) {
409 *fn
= special_completion
;
410 return CMD_CTX_INVALID
;
415 cmd
->fn
= special_completion
;
416 cmd
->ctx
= CMD_CTX_COMPLETED
;
421 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
422 * @nvmeq: The queue to use
423 * @cmd: The command to send
425 * Safe to use from interrupt context
427 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
428 struct nvme_command
*cmd
)
430 u16 tail
= nvmeq
->sq_tail
;
432 if (nvmeq
->sq_cmds_io
)
433 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
435 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
437 if (++tail
== nvmeq
->q_depth
)
439 writel(tail
, nvmeq
->q_db
);
440 nvmeq
->sq_tail
= tail
;
443 static void nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
446 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
447 __nvme_submit_cmd(nvmeq
, cmd
);
448 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
451 static __le64
**iod_list(struct nvme_iod
*iod
)
453 return ((void *)iod
) + iod
->offset
;
456 static inline void iod_init(struct nvme_iod
*iod
, unsigned nbytes
,
457 unsigned nseg
, unsigned long private)
459 iod
->private = private;
460 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
462 iod
->length
= nbytes
;
466 static struct nvme_iod
*
467 __nvme_alloc_iod(unsigned nseg
, unsigned bytes
, struct nvme_dev
*dev
,
468 unsigned long priv
, gfp_t gfp
)
470 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
471 sizeof(__le64
*) * nvme_npages(bytes
, dev
) +
472 sizeof(struct scatterlist
) * nseg
, gfp
);
475 iod_init(iod
, bytes
, nseg
, priv
);
480 static struct nvme_iod
*nvme_alloc_iod(struct request
*rq
, struct nvme_dev
*dev
,
483 unsigned size
= !(rq
->cmd_flags
& REQ_DISCARD
) ? blk_rq_bytes(rq
) :
484 sizeof(struct nvme_dsm_range
);
485 struct nvme_iod
*iod
;
487 if (rq
->nr_phys_segments
<= NVME_INT_PAGES
&&
488 size
<= NVME_INT_BYTES(dev
)) {
489 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(rq
);
492 iod_init(iod
, size
, rq
->nr_phys_segments
,
493 (unsigned long) rq
| NVME_INT_MASK
);
497 return __nvme_alloc_iod(rq
->nr_phys_segments
, size
, dev
,
498 (unsigned long) rq
, gfp
);
501 static void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
503 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
505 __le64
**list
= iod_list(iod
);
506 dma_addr_t prp_dma
= iod
->first_dma
;
508 if (iod
->npages
== 0)
509 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
510 for (i
= 0; i
< iod
->npages
; i
++) {
511 __le64
*prp_list
= list
[i
];
512 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
513 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
514 prp_dma
= next_prp_dma
;
517 if (iod_should_kfree(iod
))
521 #ifdef CONFIG_BLK_DEV_INTEGRITY
522 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
524 if (be32_to_cpu(pi
->ref_tag
) == v
)
525 pi
->ref_tag
= cpu_to_be32(p
);
528 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
530 if (be32_to_cpu(pi
->ref_tag
) == p
)
531 pi
->ref_tag
= cpu_to_be32(v
);
535 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
537 * The virtual start sector is the one that was originally submitted by the
538 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
539 * start sector may be different. Remap protection information to match the
540 * physical LBA on writes, and back to the original seed on reads.
542 * Type 0 and 3 do not have a ref tag, so no remapping required.
544 static void nvme_dif_remap(struct request
*req
,
545 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
547 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
548 struct bio_integrity_payload
*bip
;
549 struct t10_pi_tuple
*pi
;
551 u32 i
, nlb
, ts
, phys
, virt
;
553 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
556 bip
= bio_integrity(req
->bio
);
560 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
563 virt
= bip_get_seed(bip
);
564 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
565 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
566 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
568 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
569 pi
= (struct t10_pi_tuple
*)p
;
570 dif_swap(phys
, virt
, pi
);
575 #else /* CONFIG_BLK_DEV_INTEGRITY */
576 static void nvme_dif_remap(struct request
*req
,
577 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
580 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
583 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
588 static void req_completion(struct nvme_queue
*nvmeq
, void *ctx
,
589 struct nvme_completion
*cqe
)
591 struct nvme_iod
*iod
= ctx
;
592 struct request
*req
= iod_get_private(iod
);
593 struct nvme_cmd_info
*cmd_rq
= blk_mq_rq_to_pdu(req
);
594 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
597 if (unlikely(status
)) {
598 if (nvme_req_needs_retry(req
, status
)) {
599 nvme_unmap_data(nvmeq
->dev
, iod
);
600 nvme_requeue_req(req
);
604 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
605 if (cmd_rq
->ctx
== CMD_CTX_CANCELLED
)
606 error
= NVME_SC_CANCELLED
;
610 error
= nvme_error_status(status
);
614 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
615 u32 result
= le32_to_cpup(&cqe
->result
);
616 req
->special
= (void *)(uintptr_t)result
;
620 dev_warn(nvmeq
->dev
->dev
,
621 "completing aborted command with status:%04x\n",
624 nvme_unmap_data(nvmeq
->dev
, iod
);
625 blk_mq_complete_request(req
, error
);
628 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct nvme_iod
*iod
,
631 struct dma_pool
*pool
;
632 int length
= total_len
;
633 struct scatterlist
*sg
= iod
->sg
;
634 int dma_len
= sg_dma_len(sg
);
635 u64 dma_addr
= sg_dma_address(sg
);
636 u32 page_size
= dev
->ctrl
.page_size
;
637 int offset
= dma_addr
& (page_size
- 1);
639 __le64
**list
= iod_list(iod
);
643 length
-= (page_size
- offset
);
647 dma_len
-= (page_size
- offset
);
649 dma_addr
+= (page_size
- offset
);
652 dma_addr
= sg_dma_address(sg
);
653 dma_len
= sg_dma_len(sg
);
656 if (length
<= page_size
) {
657 iod
->first_dma
= dma_addr
;
661 nprps
= DIV_ROUND_UP(length
, page_size
);
662 if (nprps
<= (256 / 8)) {
663 pool
= dev
->prp_small_pool
;
666 pool
= dev
->prp_page_pool
;
670 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
672 iod
->first_dma
= dma_addr
;
677 iod
->first_dma
= prp_dma
;
680 if (i
== page_size
>> 3) {
681 __le64
*old_prp_list
= prp_list
;
682 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
685 list
[iod
->npages
++] = prp_list
;
686 prp_list
[0] = old_prp_list
[i
- 1];
687 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
690 prp_list
[i
++] = cpu_to_le64(dma_addr
);
691 dma_len
-= page_size
;
692 dma_addr
+= page_size
;
700 dma_addr
= sg_dma_address(sg
);
701 dma_len
= sg_dma_len(sg
);
707 static int nvme_map_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
,
708 struct nvme_command
*cmnd
)
710 struct request
*req
= iod_get_private(iod
);
711 struct request_queue
*q
= req
->q
;
712 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
713 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
714 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
716 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
717 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
721 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
722 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
725 if (!nvme_setup_prps(dev
, iod
, blk_rq_bytes(req
)))
728 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
729 if (blk_integrity_rq(req
)) {
730 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
733 sg_init_table(iod
->meta_sg
, 1);
734 if (blk_rq_map_integrity_sg(q
, req
->bio
, iod
->meta_sg
) != 1)
737 if (rq_data_dir(req
))
738 nvme_dif_remap(req
, nvme_dif_prep
);
740 if (!dma_map_sg(dev
->dev
, iod
->meta_sg
, 1, dma_dir
))
744 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
745 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
746 if (blk_integrity_rq(req
))
747 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(iod
->meta_sg
));
748 return BLK_MQ_RQ_QUEUE_OK
;
751 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
756 static void nvme_unmap_data(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
758 struct request
*req
= iod_get_private(iod
);
759 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
760 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
763 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
764 if (blk_integrity_rq(req
)) {
765 if (!rq_data_dir(req
))
766 nvme_dif_remap(req
, nvme_dif_complete
);
767 dma_unmap_sg(dev
->dev
, iod
->meta_sg
, 1, dma_dir
);
771 nvme_free_iod(dev
, iod
);
775 * We reuse the small pool to allocate the 16-byte range here as it is not
776 * worth having a special pool for these or additional cases to handle freeing
779 static int nvme_setup_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
780 struct nvme_iod
*iod
, struct nvme_command
*cmnd
)
782 struct request
*req
= iod_get_private(iod
);
783 struct nvme_dsm_range
*range
;
785 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
788 return BLK_MQ_RQ_QUEUE_BUSY
;
789 iod_list(iod
)[0] = (__le64
*)range
;
792 range
->cattr
= cpu_to_le32(0);
793 range
->nlb
= cpu_to_le32(blk_rq_bytes(req
) >> ns
->lba_shift
);
794 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, blk_rq_pos(req
)));
796 memset(cmnd
, 0, sizeof(*cmnd
));
797 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
798 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
799 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
801 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
802 return BLK_MQ_RQ_QUEUE_OK
;
806 * NOTE: ns is NULL when called on the admin queue.
808 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
809 const struct blk_mq_queue_data
*bd
)
811 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
812 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
813 struct nvme_dev
*dev
= nvmeq
->dev
;
814 struct request
*req
= bd
->rq
;
815 struct nvme_cmd_info
*cmd
= blk_mq_rq_to_pdu(req
);
816 struct nvme_iod
*iod
;
817 struct nvme_command cmnd
;
818 int ret
= BLK_MQ_RQ_QUEUE_OK
;
821 * If formated with metadata, require the block layer provide a buffer
822 * unless this namespace is formated such that the metadata can be
823 * stripped/generated by the controller with PRACT=1.
825 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
826 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
827 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
828 blk_mq_complete_request(req
, -EFAULT
);
829 return BLK_MQ_RQ_QUEUE_OK
;
833 iod
= nvme_alloc_iod(req
, dev
, GFP_ATOMIC
);
835 return BLK_MQ_RQ_QUEUE_BUSY
;
837 if (req
->cmd_flags
& REQ_DISCARD
) {
838 ret
= nvme_setup_discard(nvmeq
, ns
, iod
, &cmnd
);
840 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
841 memcpy(&cmnd
, req
->cmd
, sizeof(cmnd
));
842 else if (req
->cmd_flags
& REQ_FLUSH
)
843 nvme_setup_flush(ns
, &cmnd
);
845 nvme_setup_rw(ns
, req
, &cmnd
);
847 if (req
->nr_phys_segments
)
848 ret
= nvme_map_data(dev
, iod
, &cmnd
);
854 cmnd
.common
.command_id
= req
->tag
;
855 nvme_set_info(cmd
, iod
, req_completion
);
857 spin_lock_irq(&nvmeq
->q_lock
);
858 __nvme_submit_cmd(nvmeq
, &cmnd
);
859 nvme_process_cq(nvmeq
);
860 spin_unlock_irq(&nvmeq
->q_lock
);
861 return BLK_MQ_RQ_QUEUE_OK
;
863 nvme_free_iod(dev
, iod
);
867 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
871 head
= nvmeq
->cq_head
;
872 phase
= nvmeq
->cq_phase
;
876 nvme_completion_fn fn
;
877 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
878 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
880 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
881 if (++head
== nvmeq
->q_depth
) {
885 if (tag
&& *tag
== cqe
.command_id
)
887 ctx
= nvme_finish_cmd(nvmeq
, cqe
.command_id
, &fn
);
888 fn(nvmeq
, ctx
, &cqe
);
891 /* If the controller ignores the cq head doorbell and continuously
892 * writes to the queue, it is theoretically possible to wrap around
893 * the queue twice and mistakenly return IRQ_NONE. Linux only
894 * requires that 0.1% of your interrupts are handled, so this isn't
897 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
900 if (likely(nvmeq
->cq_vector
>= 0))
901 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
902 nvmeq
->cq_head
= head
;
903 nvmeq
->cq_phase
= phase
;
908 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
910 __nvme_process_cq(nvmeq
, NULL
);
913 static irqreturn_t
nvme_irq(int irq
, void *data
)
916 struct nvme_queue
*nvmeq
= data
;
917 spin_lock(&nvmeq
->q_lock
);
918 nvme_process_cq(nvmeq
);
919 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
921 spin_unlock(&nvmeq
->q_lock
);
925 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
927 struct nvme_queue
*nvmeq
= data
;
928 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
929 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
931 return IRQ_WAKE_THREAD
;
934 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
936 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
938 if ((le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
940 spin_lock_irq(&nvmeq
->q_lock
);
941 __nvme_process_cq(nvmeq
, &tag
);
942 spin_unlock_irq(&nvmeq
->q_lock
);
951 static int nvme_submit_async_admin_req(struct nvme_dev
*dev
)
953 struct nvme_queue
*nvmeq
= dev
->queues
[0];
954 struct nvme_command c
;
955 struct nvme_cmd_info
*cmd_info
;
958 req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
,
959 BLK_MQ_REQ_NOWAIT
| BLK_MQ_REQ_RESERVED
);
963 req
->cmd_flags
|= REQ_NO_TIMEOUT
;
964 cmd_info
= blk_mq_rq_to_pdu(req
);
965 nvme_set_info(cmd_info
, NULL
, async_req_completion
);
967 memset(&c
, 0, sizeof(c
));
968 c
.common
.opcode
= nvme_admin_async_event
;
969 c
.common
.command_id
= req
->tag
;
971 blk_mq_free_request(req
);
972 __nvme_submit_cmd(nvmeq
, &c
);
976 static void async_cmd_info_endio(struct request
*req
, int error
)
978 struct async_cmd_info
*cmdinfo
= req
->end_io_data
;
980 cmdinfo
->status
= req
->errors
;
981 queue_kthread_work(cmdinfo
->worker
, &cmdinfo
->work
);
982 blk_mq_free_request(req
);
985 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
987 struct nvme_command c
;
989 memset(&c
, 0, sizeof(c
));
990 c
.delete_queue
.opcode
= opcode
;
991 c
.delete_queue
.qid
= cpu_to_le16(id
);
993 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
996 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
997 struct nvme_queue
*nvmeq
)
999 struct nvme_command c
;
1000 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
1003 * Note: we (ab)use the fact the the prp fields survive if no data
1004 * is attached to the request.
1006 memset(&c
, 0, sizeof(c
));
1007 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1008 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1009 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1010 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1011 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1012 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
1014 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1017 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1018 struct nvme_queue
*nvmeq
)
1020 struct nvme_command c
;
1021 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
1024 * Note: we (ab)use the fact the the prp fields survive if no data
1025 * is attached to the request.
1027 memset(&c
, 0, sizeof(c
));
1028 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1029 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1030 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1031 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1032 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1033 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1035 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1038 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1040 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1043 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1045 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1048 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1050 struct nvme_cmd_info
*cmd_rq
= blk_mq_rq_to_pdu(req
);
1051 struct nvme_queue
*nvmeq
= cmd_rq
->nvmeq
;
1052 struct nvme_dev
*dev
= nvmeq
->dev
;
1053 struct request
*abort_req
;
1054 struct nvme_cmd_info
*abort_cmd
;
1055 struct nvme_command cmd
;
1058 * Shutdown immediately if controller times out while starting. The
1059 * reset work will see the pci device disabled when it gets the forced
1060 * cancellation error. All outstanding requests are completed on
1061 * shutdown, so we return BLK_EH_HANDLED.
1063 if (test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)) {
1065 "I/O %d QID %d timeout, disable controller\n",
1066 req
->tag
, nvmeq
->qid
);
1067 nvme_dev_shutdown(dev
);
1068 req
->errors
= NVME_SC_CANCELLED
;
1069 return BLK_EH_HANDLED
;
1073 * Shutdown the controller immediately and schedule a reset if the
1074 * command was already aborted once before and still hasn't been
1075 * returned to the driver, or if this is the admin queue.
1077 if (!nvmeq
->qid
|| cmd_rq
->aborted
) {
1079 "I/O %d QID %d timeout, reset controller\n",
1080 req
->tag
, nvmeq
->qid
);
1081 nvme_dev_shutdown(dev
);
1082 queue_work(nvme_workq
, &dev
->reset_work
);
1085 * Mark the request as handled, since the inline shutdown
1086 * forces all outstanding requests to complete.
1088 req
->errors
= NVME_SC_CANCELLED
;
1089 return BLK_EH_HANDLED
;
1092 if (atomic_dec_and_test(&dev
->ctrl
.abort_limit
))
1093 return BLK_EH_RESET_TIMER
;
1095 abort_req
= blk_mq_alloc_request(dev
->ctrl
.admin_q
, WRITE
,
1097 if (IS_ERR(abort_req
)) {
1098 atomic_inc(&dev
->ctrl
.abort_limit
);
1099 return BLK_EH_RESET_TIMER
;
1102 abort_cmd
= blk_mq_rq_to_pdu(abort_req
);
1103 nvme_set_info(abort_cmd
, abort_req
, abort_completion
);
1105 memset(&cmd
, 0, sizeof(cmd
));
1106 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1107 cmd
.abort
.cid
= req
->tag
;
1108 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1109 cmd
.abort
.command_id
= abort_req
->tag
;
1111 cmd_rq
->aborted
= 1;
1113 dev_warn(nvmeq
->q_dmadev
, "I/O %d QID %d timeout, aborting\n",
1114 req
->tag
, nvmeq
->qid
);
1115 nvme_submit_cmd(dev
->queues
[0], &cmd
);
1118 * The aborted req will be completed on receiving the abort req.
1119 * We enable the timer again. If hit twice, it'll cause a device reset,
1120 * as the device then is in a faulty state.
1122 return BLK_EH_RESET_TIMER
;
1125 static void nvme_cancel_queue_ios(struct request
*req
, void *data
, bool reserved
)
1127 struct nvme_queue
*nvmeq
= data
;
1129 nvme_completion_fn fn
;
1130 struct nvme_cmd_info
*cmd
;
1131 struct nvme_completion cqe
;
1133 if (!blk_mq_request_started(req
))
1136 cmd
= blk_mq_rq_to_pdu(req
);
1138 if (cmd
->ctx
== CMD_CTX_CANCELLED
)
1141 if (blk_queue_dying(req
->q
))
1142 cqe
.status
= cpu_to_le16((NVME_SC_ABORT_REQ
| NVME_SC_DNR
) << 1);
1144 cqe
.status
= cpu_to_le16(NVME_SC_ABORT_REQ
<< 1);
1147 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d QID %d\n",
1148 req
->tag
, nvmeq
->qid
);
1149 ctx
= cancel_cmd_info(cmd
, &fn
);
1150 fn(nvmeq
, ctx
, &cqe
);
1153 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1155 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1156 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1158 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1159 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1163 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1167 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1168 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1170 dev
->queues
[i
] = NULL
;
1171 nvme_free_queue(nvmeq
);
1176 * nvme_suspend_queue - put queue into suspended state
1177 * @nvmeq - queue to suspend
1179 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1183 spin_lock_irq(&nvmeq
->q_lock
);
1184 if (nvmeq
->cq_vector
== -1) {
1185 spin_unlock_irq(&nvmeq
->q_lock
);
1188 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1189 nvmeq
->dev
->online_queues
--;
1190 nvmeq
->cq_vector
= -1;
1191 spin_unlock_irq(&nvmeq
->q_lock
);
1193 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1194 blk_mq_freeze_queue_start(nvmeq
->dev
->ctrl
.admin_q
);
1196 irq_set_affinity_hint(vector
, NULL
);
1197 free_irq(vector
, nvmeq
);
1202 static void nvme_clear_queue(struct nvme_queue
*nvmeq
)
1204 spin_lock_irq(&nvmeq
->q_lock
);
1205 if (nvmeq
->tags
&& *nvmeq
->tags
)
1206 blk_mq_all_tag_busy_iter(*nvmeq
->tags
, nvme_cancel_queue_ios
, nvmeq
);
1207 spin_unlock_irq(&nvmeq
->q_lock
);
1210 static void nvme_disable_queue(struct nvme_dev
*dev
, int qid
)
1212 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
1216 if (nvme_suspend_queue(nvmeq
))
1219 /* Don't tell the adapter to delete the admin queue.
1220 * Don't tell a removed adapter to delete IO queues. */
1221 if (qid
&& readl(dev
->bar
+ NVME_REG_CSTS
) != -1) {
1222 adapter_delete_sq(dev
, qid
);
1223 adapter_delete_cq(dev
, qid
);
1226 spin_lock_irq(&nvmeq
->q_lock
);
1227 nvme_process_cq(nvmeq
);
1228 spin_unlock_irq(&nvmeq
->q_lock
);
1231 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1234 int q_depth
= dev
->q_depth
;
1235 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1236 dev
->ctrl
.page_size
);
1238 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1239 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1240 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1241 q_depth
= div_u64(mem_per_q
, entry_size
);
1244 * Ensure the reduced q_depth is above some threshold where it
1245 * would be better to map queues in system memory with the
1255 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1258 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1259 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1260 dev
->ctrl
.page_size
);
1261 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1262 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1264 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1265 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1266 if (!nvmeq
->sq_cmds
)
1273 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1276 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1280 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1281 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1285 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1288 nvmeq
->q_dmadev
= dev
->dev
;
1290 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1291 dev
->ctrl
.instance
, qid
);
1292 spin_lock_init(&nvmeq
->q_lock
);
1294 nvmeq
->cq_phase
= 1;
1295 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1296 nvmeq
->q_depth
= depth
;
1298 nvmeq
->cq_vector
= -1;
1299 dev
->queues
[qid
] = nvmeq
;
1301 /* make sure queue descriptor is set before queue count, for kthread */
1308 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1309 nvmeq
->cq_dma_addr
);
1315 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1318 if (use_threaded_interrupts
)
1319 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1320 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1322 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1323 IRQF_SHARED
, name
, nvmeq
);
1326 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1328 struct nvme_dev
*dev
= nvmeq
->dev
;
1330 spin_lock_irq(&nvmeq
->q_lock
);
1333 nvmeq
->cq_phase
= 1;
1334 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1335 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1336 dev
->online_queues
++;
1337 spin_unlock_irq(&nvmeq
->q_lock
);
1340 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1342 struct nvme_dev
*dev
= nvmeq
->dev
;
1345 nvmeq
->cq_vector
= qid
- 1;
1346 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1350 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1354 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1358 nvme_init_queue(nvmeq
, qid
);
1362 adapter_delete_sq(dev
, qid
);
1364 adapter_delete_cq(dev
, qid
);
1368 static struct blk_mq_ops nvme_mq_admin_ops
= {
1369 .queue_rq
= nvme_queue_rq
,
1370 .map_queue
= blk_mq_map_queue
,
1371 .init_hctx
= nvme_admin_init_hctx
,
1372 .exit_hctx
= nvme_admin_exit_hctx
,
1373 .init_request
= nvme_admin_init_request
,
1374 .timeout
= nvme_timeout
,
1377 static struct blk_mq_ops nvme_mq_ops
= {
1378 .queue_rq
= nvme_queue_rq
,
1379 .map_queue
= blk_mq_map_queue
,
1380 .init_hctx
= nvme_init_hctx
,
1381 .init_request
= nvme_init_request
,
1382 .timeout
= nvme_timeout
,
1386 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1388 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1389 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1390 blk_mq_free_tag_set(&dev
->admin_tagset
);
1394 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1396 if (!dev
->ctrl
.admin_q
) {
1397 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1398 dev
->admin_tagset
.nr_hw_queues
= 1;
1399 dev
->admin_tagset
.queue_depth
= NVME_AQ_DEPTH
;
1400 dev
->admin_tagset
.reserved_tags
= 1;
1401 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1402 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1403 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1404 dev
->admin_tagset
.driver_data
= dev
;
1406 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1409 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1410 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1411 blk_mq_free_tag_set(&dev
->admin_tagset
);
1414 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1415 nvme_dev_remove_admin(dev
);
1416 dev
->ctrl
.admin_q
= NULL
;
1420 blk_mq_unfreeze_queue(dev
->ctrl
.admin_q
);
1425 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1429 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1430 struct nvme_queue
*nvmeq
;
1432 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1433 NVME_CAP_NSSRC(cap
) : 0;
1435 if (dev
->subsystem
&&
1436 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1437 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1439 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1443 nvmeq
= dev
->queues
[0];
1445 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1450 aqa
= nvmeq
->q_depth
- 1;
1453 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1454 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1455 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1457 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1461 nvmeq
->cq_vector
= 0;
1462 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1464 nvmeq
->cq_vector
= -1;
1471 nvme_free_queues(dev
, 0);
1475 static int nvme_kthread(void *data
)
1477 struct nvme_dev
*dev
, *next
;
1479 while (!kthread_should_stop()) {
1480 set_current_state(TASK_INTERRUPTIBLE
);
1481 spin_lock(&dev_list_lock
);
1482 list_for_each_entry_safe(dev
, next
, &dev_list
, node
) {
1484 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1487 * Skip controllers currently under reset.
1489 if (work_pending(&dev
->reset_work
) || work_busy(&dev
->reset_work
))
1492 if ((dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
)) ||
1493 csts
& NVME_CSTS_CFS
) {
1494 if (queue_work(nvme_workq
, &dev
->reset_work
)) {
1496 "Failed status: %x, reset controller\n",
1497 readl(dev
->bar
+ NVME_REG_CSTS
));
1501 for (i
= 0; i
< dev
->queue_count
; i
++) {
1502 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1505 spin_lock_irq(&nvmeq
->q_lock
);
1506 nvme_process_cq(nvmeq
);
1508 while (i
== 0 && dev
->ctrl
.event_limit
> 0) {
1509 if (nvme_submit_async_admin_req(dev
))
1511 dev
->ctrl
.event_limit
--;
1513 spin_unlock_irq(&nvmeq
->q_lock
);
1516 spin_unlock(&dev_list_lock
);
1517 schedule_timeout(round_jiffies_relative(HZ
));
1522 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1527 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1528 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1534 for (i
= dev
->online_queues
; i
<= dev
->queue_count
- 1; i
++) {
1535 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1537 nvme_free_queues(dev
, i
);
1543 * Ignore failing Create SQ/CQ commands, we can continue with less
1544 * than the desired aount of queues, and even a controller without
1545 * I/O queues an still be used to issue admin commands. This might
1546 * be useful to upgrade a buggy firmware for example.
1548 return ret
>= 0 ? 0 : ret
;
1551 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1553 u64 szu
, size
, offset
;
1555 resource_size_t bar_size
;
1556 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1558 dma_addr_t dma_addr
;
1563 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1564 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1567 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1569 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1570 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1571 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1572 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1574 if (offset
> bar_size
)
1578 * Controllers may support a CMB size larger than their BAR,
1579 * for example, due to being behind a bridge. Reduce the CMB to
1580 * the reported size of the BAR
1582 if (size
> bar_size
- offset
)
1583 size
= bar_size
- offset
;
1585 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1586 cmb
= ioremap_wc(dma_addr
, size
);
1590 dev
->cmb_dma_addr
= dma_addr
;
1591 dev
->cmb_size
= size
;
1595 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1603 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1605 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1608 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1610 struct nvme_queue
*adminq
= dev
->queues
[0];
1611 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1612 int result
, i
, vecs
, nr_io_queues
, size
;
1614 nr_io_queues
= num_possible_cpus();
1615 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1620 * Degraded controllers might return an error when setting the queue
1621 * count. We still want to be able to bring them online and offer
1622 * access to the admin queue, as that might be only way to fix them up.
1625 dev_err(dev
->dev
, "Could not set queue count (%d)\n", result
);
1630 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1631 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1632 sizeof(struct nvme_command
));
1634 dev
->q_depth
= result
;
1636 nvme_release_cmb(dev
);
1639 size
= db_bar_size(dev
, nr_io_queues
);
1643 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1646 if (!--nr_io_queues
)
1648 size
= db_bar_size(dev
, nr_io_queues
);
1650 dev
->dbs
= dev
->bar
+ 4096;
1651 adminq
->q_db
= dev
->dbs
;
1654 /* Deregister the admin queue's interrupt */
1655 free_irq(dev
->entry
[0].vector
, adminq
);
1658 * If we enable msix early due to not intx, disable it again before
1659 * setting up the full range we need.
1662 pci_disable_msix(pdev
);
1664 for (i
= 0; i
< nr_io_queues
; i
++)
1665 dev
->entry
[i
].entry
= i
;
1666 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1668 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1672 for (i
= 0; i
< vecs
; i
++)
1673 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1678 * Should investigate if there's a performance win from allocating
1679 * more queues than interrupt vectors; it might allow the submission
1680 * path to scale better, even if the receive path is limited by the
1681 * number of interrupts.
1683 nr_io_queues
= vecs
;
1684 dev
->max_qid
= nr_io_queues
;
1686 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1688 adminq
->cq_vector
= -1;
1692 /* Free previously allocated queues that are no longer usable */
1693 nvme_free_queues(dev
, nr_io_queues
+ 1);
1694 return nvme_create_io_queues(dev
);
1697 nvme_free_queues(dev
, 1);
1701 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1703 struct nvme_queue
*nvmeq
;
1706 for (i
= 0; i
< dev
->online_queues
; i
++) {
1707 nvmeq
= dev
->queues
[i
];
1709 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1712 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1713 blk_mq_tags_cpumask(*nvmeq
->tags
));
1717 static void nvme_dev_scan(struct work_struct
*work
)
1719 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1721 if (!dev
->tagset
.tags
)
1723 nvme_scan_namespaces(&dev
->ctrl
);
1724 nvme_set_irq_hints(dev
);
1728 * Return: error value if an error occurred setting up the queues or calling
1729 * Identify Device. 0 if these succeeded, even if adding some of the
1730 * namespaces failed. At the moment, these failures are silent. TBD which
1731 * failures should be reported.
1733 static int nvme_dev_add(struct nvme_dev
*dev
)
1735 if (!dev
->ctrl
.tagset
) {
1736 dev
->tagset
.ops
= &nvme_mq_ops
;
1737 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1738 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1739 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1740 dev
->tagset
.queue_depth
=
1741 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1742 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1743 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1744 dev
->tagset
.driver_data
= dev
;
1746 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1748 dev
->ctrl
.tagset
= &dev
->tagset
;
1750 queue_work(nvme_workq
, &dev
->scan_work
);
1754 static int nvme_dev_map(struct nvme_dev
*dev
)
1757 int bars
, result
= -ENOMEM
;
1758 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1760 if (pci_enable_device_mem(pdev
))
1763 dev
->entry
[0].vector
= pdev
->irq
;
1764 pci_set_master(pdev
);
1765 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1769 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1772 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1773 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1776 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1780 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1786 * Some devices don't advertse INTx interrupts, pre-enable a single
1787 * MSIX vec for setup. We'll adjust this later.
1790 result
= pci_enable_msix(pdev
, dev
->entry
, 1);
1795 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1797 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1798 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1799 dev
->dbs
= dev
->bar
+ 4096;
1800 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1801 dev
->cmb
= nvme_map_cmb(dev
);
1809 pci_release_regions(pdev
);
1811 pci_disable_device(pdev
);
1815 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1817 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1819 if (pdev
->msi_enabled
)
1820 pci_disable_msi(pdev
);
1821 else if (pdev
->msix_enabled
)
1822 pci_disable_msix(pdev
);
1827 pci_release_regions(pdev
);
1830 if (pci_is_enabled(pdev
))
1831 pci_disable_device(pdev
);
1834 struct nvme_delq_ctx
{
1835 struct task_struct
*waiter
;
1836 struct kthread_worker
*worker
;
1840 static void nvme_wait_dq(struct nvme_delq_ctx
*dq
, struct nvme_dev
*dev
)
1842 dq
->waiter
= current
;
1846 set_current_state(TASK_KILLABLE
);
1847 if (!atomic_read(&dq
->refcount
))
1849 if (!schedule_timeout(ADMIN_TIMEOUT
) ||
1850 fatal_signal_pending(current
)) {
1852 * Disable the controller first since we can't trust it
1853 * at this point, but leave the admin queue enabled
1854 * until all queue deletion requests are flushed.
1855 * FIXME: This may take a while if there are more h/w
1856 * queues than admin tags.
1858 set_current_state(TASK_RUNNING
);
1859 nvme_disable_ctrl(&dev
->ctrl
,
1860 lo_hi_readq(dev
->bar
+ NVME_REG_CAP
));
1861 nvme_clear_queue(dev
->queues
[0]);
1862 flush_kthread_worker(dq
->worker
);
1863 nvme_disable_queue(dev
, 0);
1867 set_current_state(TASK_RUNNING
);
1870 static void nvme_put_dq(struct nvme_delq_ctx
*dq
)
1872 atomic_dec(&dq
->refcount
);
1874 wake_up_process(dq
->waiter
);
1877 static struct nvme_delq_ctx
*nvme_get_dq(struct nvme_delq_ctx
*dq
)
1879 atomic_inc(&dq
->refcount
);
1883 static void nvme_del_queue_end(struct nvme_queue
*nvmeq
)
1885 struct nvme_delq_ctx
*dq
= nvmeq
->cmdinfo
.ctx
;
1888 spin_lock_irq(&nvmeq
->q_lock
);
1889 nvme_process_cq(nvmeq
);
1890 spin_unlock_irq(&nvmeq
->q_lock
);
1893 static int adapter_async_del_queue(struct nvme_queue
*nvmeq
, u8 opcode
,
1894 kthread_work_func_t fn
)
1896 struct request
*req
;
1897 struct nvme_command c
;
1899 memset(&c
, 0, sizeof(c
));
1900 c
.delete_queue
.opcode
= opcode
;
1901 c
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1903 init_kthread_work(&nvmeq
->cmdinfo
.work
, fn
);
1905 req
= nvme_alloc_request(nvmeq
->dev
->ctrl
.admin_q
, &c
, 0);
1907 return PTR_ERR(req
);
1909 req
->timeout
= ADMIN_TIMEOUT
;
1910 req
->end_io_data
= &nvmeq
->cmdinfo
;
1911 blk_execute_rq_nowait(req
->q
, NULL
, req
, 0, async_cmd_info_endio
);
1915 static void nvme_del_cq_work_handler(struct kthread_work
*work
)
1917 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1919 nvme_del_queue_end(nvmeq
);
1922 static int nvme_delete_cq(struct nvme_queue
*nvmeq
)
1924 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_cq
,
1925 nvme_del_cq_work_handler
);
1928 static void nvme_del_sq_work_handler(struct kthread_work
*work
)
1930 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1932 int status
= nvmeq
->cmdinfo
.status
;
1935 status
= nvme_delete_cq(nvmeq
);
1937 nvme_del_queue_end(nvmeq
);
1940 static int nvme_delete_sq(struct nvme_queue
*nvmeq
)
1942 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_sq
,
1943 nvme_del_sq_work_handler
);
1946 static void nvme_del_queue_start(struct kthread_work
*work
)
1948 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1950 if (nvme_delete_sq(nvmeq
))
1951 nvme_del_queue_end(nvmeq
);
1954 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1957 DEFINE_KTHREAD_WORKER_ONSTACK(worker
);
1958 struct nvme_delq_ctx dq
;
1959 struct task_struct
*kworker_task
= kthread_run(kthread_worker_fn
,
1960 &worker
, "nvme%d", dev
->ctrl
.instance
);
1962 if (IS_ERR(kworker_task
)) {
1964 "Failed to create queue del task\n");
1965 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1966 nvme_disable_queue(dev
, i
);
1971 atomic_set(&dq
.refcount
, 0);
1972 dq
.worker
= &worker
;
1973 for (i
= dev
->queue_count
- 1; i
> 0; i
--) {
1974 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1976 if (nvme_suspend_queue(nvmeq
))
1978 nvmeq
->cmdinfo
.ctx
= nvme_get_dq(&dq
);
1979 nvmeq
->cmdinfo
.worker
= dq
.worker
;
1980 init_kthread_work(&nvmeq
->cmdinfo
.work
, nvme_del_queue_start
);
1981 queue_kthread_work(dq
.worker
, &nvmeq
->cmdinfo
.work
);
1983 nvme_wait_dq(&dq
, dev
);
1984 kthread_stop(kworker_task
);
1987 static int nvme_dev_list_add(struct nvme_dev
*dev
)
1989 bool start_thread
= false;
1991 spin_lock(&dev_list_lock
);
1992 if (list_empty(&dev_list
) && IS_ERR_OR_NULL(nvme_thread
)) {
1993 start_thread
= true;
1996 list_add(&dev
->node
, &dev_list
);
1997 spin_unlock(&dev_list_lock
);
2000 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
2001 wake_up_all(&nvme_kthread_wait
);
2003 wait_event_killable(nvme_kthread_wait
, nvme_thread
);
2005 if (IS_ERR_OR_NULL(nvme_thread
))
2006 return nvme_thread
? PTR_ERR(nvme_thread
) : -EINTR
;
2012 * Remove the node from the device list and check
2013 * for whether or not we need to stop the nvme_thread.
2015 static void nvme_dev_list_remove(struct nvme_dev
*dev
)
2017 struct task_struct
*tmp
= NULL
;
2019 spin_lock(&dev_list_lock
);
2020 list_del_init(&dev
->node
);
2021 if (list_empty(&dev_list
) && !IS_ERR_OR_NULL(nvme_thread
)) {
2025 spin_unlock(&dev_list_lock
);
2031 static void nvme_freeze_queues(struct nvme_dev
*dev
)
2035 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
2036 blk_mq_freeze_queue_start(ns
->queue
);
2038 spin_lock_irq(ns
->queue
->queue_lock
);
2039 queue_flag_set(QUEUE_FLAG_STOPPED
, ns
->queue
);
2040 spin_unlock_irq(ns
->queue
->queue_lock
);
2042 blk_mq_cancel_requeue_work(ns
->queue
);
2043 blk_mq_stop_hw_queues(ns
->queue
);
2047 static void nvme_unfreeze_queues(struct nvme_dev
*dev
)
2051 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
2052 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED
, ns
->queue
);
2053 blk_mq_unfreeze_queue(ns
->queue
);
2054 blk_mq_start_stopped_hw_queues(ns
->queue
, true);
2055 blk_mq_kick_requeue_list(ns
->queue
);
2059 static void nvme_dev_shutdown(struct nvme_dev
*dev
)
2064 nvme_dev_list_remove(dev
);
2066 mutex_lock(&dev
->shutdown_lock
);
2068 nvme_freeze_queues(dev
);
2069 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2071 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
2072 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
2073 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
2074 nvme_suspend_queue(nvmeq
);
2077 nvme_disable_io_queues(dev
);
2078 nvme_shutdown_ctrl(&dev
->ctrl
);
2079 nvme_disable_queue(dev
, 0);
2081 nvme_dev_unmap(dev
);
2083 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
2084 nvme_clear_queue(dev
->queues
[i
]);
2085 mutex_unlock(&dev
->shutdown_lock
);
2088 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2090 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2091 PAGE_SIZE
, PAGE_SIZE
, 0);
2092 if (!dev
->prp_page_pool
)
2095 /* Optimisation for I/Os between 4k and 128k */
2096 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2098 if (!dev
->prp_small_pool
) {
2099 dma_pool_destroy(dev
->prp_page_pool
);
2105 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2107 dma_pool_destroy(dev
->prp_page_pool
);
2108 dma_pool_destroy(dev
->prp_small_pool
);
2111 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2113 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2115 put_device(dev
->dev
);
2116 if (dev
->tagset
.tags
)
2117 blk_mq_free_tag_set(&dev
->tagset
);
2118 if (dev
->ctrl
.admin_q
)
2119 blk_put_queue(dev
->ctrl
.admin_q
);
2125 static void nvme_reset_work(struct work_struct
*work
)
2127 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
2130 if (WARN_ON(test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)))
2134 * If we're called to reset a live controller first shut it down before
2138 nvme_dev_shutdown(dev
);
2140 set_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
2142 result
= nvme_dev_map(dev
);
2146 result
= nvme_configure_admin_queue(dev
);
2150 nvme_init_queue(dev
->queues
[0], 0);
2151 result
= nvme_alloc_admin_tags(dev
);
2155 result
= nvme_init_identify(&dev
->ctrl
);
2159 result
= nvme_setup_io_queues(dev
);
2163 dev
->ctrl
.event_limit
= 1;
2165 result
= nvme_dev_list_add(dev
);
2170 * Keep the controller around but remove all namespaces if we don't have
2171 * any working I/O queue.
2173 if (dev
->online_queues
< 2) {
2174 dev_warn(dev
->dev
, "IO queues not created\n");
2175 nvme_remove_namespaces(&dev
->ctrl
);
2177 nvme_unfreeze_queues(dev
);
2181 clear_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
2185 nvme_dev_list_remove(dev
);
2187 nvme_dev_remove_admin(dev
);
2188 blk_put_queue(dev
->ctrl
.admin_q
);
2189 dev
->ctrl
.admin_q
= NULL
;
2190 dev
->queues
[0]->tags
= NULL
;
2192 nvme_disable_queue(dev
, 0);
2194 nvme_dev_unmap(dev
);
2196 nvme_remove_dead_ctrl(dev
);
2199 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2201 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2202 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2204 if (pci_get_drvdata(pdev
))
2205 pci_stop_and_remove_bus_device_locked(pdev
);
2206 nvme_put_ctrl(&dev
->ctrl
);
2209 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
)
2211 dev_warn(dev
->dev
, "Removing after probe failure\n");
2212 kref_get(&dev
->ctrl
.kref
);
2213 if (!schedule_work(&dev
->remove_work
))
2214 nvme_put_ctrl(&dev
->ctrl
);
2217 static int nvme_reset(struct nvme_dev
*dev
)
2219 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
2222 if (!queue_work(nvme_workq
, &dev
->reset_work
))
2225 flush_work(&dev
->reset_work
);
2229 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2231 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2235 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2237 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2241 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2243 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2247 static bool nvme_pci_io_incapable(struct nvme_ctrl
*ctrl
)
2249 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2251 return !dev
->bar
|| dev
->online_queues
< 2;
2254 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
2256 return nvme_reset(to_nvme_dev(ctrl
));
2259 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2260 .reg_read32
= nvme_pci_reg_read32
,
2261 .reg_write32
= nvme_pci_reg_write32
,
2262 .reg_read64
= nvme_pci_reg_read64
,
2263 .io_incapable
= nvme_pci_io_incapable
,
2264 .reset_ctrl
= nvme_pci_reset_ctrl
,
2265 .free_ctrl
= nvme_pci_free_ctrl
,
2268 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2270 int node
, result
= -ENOMEM
;
2271 struct nvme_dev
*dev
;
2273 node
= dev_to_node(&pdev
->dev
);
2274 if (node
== NUMA_NO_NODE
)
2275 set_dev_node(&pdev
->dev
, 0);
2277 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2280 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
2284 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2289 dev
->dev
= get_device(&pdev
->dev
);
2290 pci_set_drvdata(pdev
, dev
);
2292 INIT_LIST_HEAD(&dev
->node
);
2293 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
2294 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2295 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2296 mutex_init(&dev
->shutdown_lock
);
2298 result
= nvme_setup_prp_pools(dev
);
2302 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2307 queue_work(nvme_workq
, &dev
->reset_work
);
2311 nvme_release_prp_pools(dev
);
2313 put_device(dev
->dev
);
2321 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2323 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2326 nvme_dev_shutdown(dev
);
2328 queue_work(nvme_workq
, &dev
->reset_work
);
2331 static void nvme_shutdown(struct pci_dev
*pdev
)
2333 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2334 nvme_dev_shutdown(dev
);
2337 static void nvme_remove(struct pci_dev
*pdev
)
2339 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2341 spin_lock(&dev_list_lock
);
2342 list_del_init(&dev
->node
);
2343 spin_unlock(&dev_list_lock
);
2345 pci_set_drvdata(pdev
, NULL
);
2346 flush_work(&dev
->reset_work
);
2347 flush_work(&dev
->scan_work
);
2348 nvme_remove_namespaces(&dev
->ctrl
);
2349 nvme_uninit_ctrl(&dev
->ctrl
);
2350 nvme_dev_shutdown(dev
);
2351 nvme_dev_remove_admin(dev
);
2352 nvme_free_queues(dev
, 0);
2353 nvme_release_cmb(dev
);
2354 nvme_release_prp_pools(dev
);
2355 nvme_put_ctrl(&dev
->ctrl
);
2358 /* These functions are yet to be implemented */
2359 #define nvme_error_detected NULL
2360 #define nvme_dump_registers NULL
2361 #define nvme_link_reset NULL
2362 #define nvme_slot_reset NULL
2363 #define nvme_error_resume NULL
2365 #ifdef CONFIG_PM_SLEEP
2366 static int nvme_suspend(struct device
*dev
)
2368 struct pci_dev
*pdev
= to_pci_dev(dev
);
2369 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2371 nvme_dev_shutdown(ndev
);
2375 static int nvme_resume(struct device
*dev
)
2377 struct pci_dev
*pdev
= to_pci_dev(dev
);
2378 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2380 queue_work(nvme_workq
, &ndev
->reset_work
);
2385 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2387 static const struct pci_error_handlers nvme_err_handler
= {
2388 .error_detected
= nvme_error_detected
,
2389 .mmio_enabled
= nvme_dump_registers
,
2390 .link_reset
= nvme_link_reset
,
2391 .slot_reset
= nvme_slot_reset
,
2392 .resume
= nvme_error_resume
,
2393 .reset_notify
= nvme_reset_notify
,
2396 /* Move to pci_ids.h later */
2397 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2399 static const struct pci_device_id nvme_id_table
[] = {
2400 { PCI_VDEVICE(INTEL
, 0x0953),
2401 .driver_data
= NVME_QUIRK_STRIPE_SIZE
, },
2402 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2403 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2404 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2405 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2408 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2410 static struct pci_driver nvme_driver
= {
2412 .id_table
= nvme_id_table
,
2413 .probe
= nvme_probe
,
2414 .remove
= nvme_remove
,
2415 .shutdown
= nvme_shutdown
,
2417 .pm
= &nvme_dev_pm_ops
,
2419 .err_handler
= &nvme_err_handler
,
2422 static int __init
nvme_init(void)
2426 init_waitqueue_head(&nvme_kthread_wait
);
2428 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2432 result
= nvme_core_init();
2436 result
= pci_register_driver(&nvme_driver
);
2444 destroy_workqueue(nvme_workq
);
2448 static void __exit
nvme_exit(void)
2450 pci_unregister_driver(&nvme_driver
);
2452 destroy_workqueue(nvme_workq
);
2453 BUG_ON(nvme_thread
&& !IS_ERR(nvme_thread
));
2457 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2458 MODULE_LICENSE("GPL");
2459 MODULE_VERSION("1.0");
2460 module_init(nvme_init
);
2461 module_exit(nvme_exit
);