drivers/nvmem/imx-ocotp.c

   1 /*
   2  * i.MX6 OCOTP fusebox driver
   3  *
   4  * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
   5  *
   6  * Based on the barebox ocotp driver,
   7  * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
   8  *      Orex Computed Radiography
   9  *
  10  * Write support based on the fsl_otp driver,
  11  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2
  15  * as published by the Free Software Foundation.
  16  *
  17  * http://www.opensource.org/licenses/gpl-license.html
  18  * http://www.gnu.org/copyleft/gpl.html
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/device.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/nvmem-provider.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31
  32 #define IMX_OCOTP_OFFSET_B0W0           0x400 /* Offset from base address of the
  33                                                * OTP Bank0 Word0
  34                                                */
  35 #define IMX_OCOTP_OFFSET_PER_WORD       0x10  /* Offset between the start addr
  36                                                * of two consecutive OTP words.
  37                                                */
  38
  39 #define IMX_OCOTP_ADDR_CTRL             0x0000
  40 #define IMX_OCOTP_ADDR_CTRL_SET         0x0004
  41 #define IMX_OCOTP_ADDR_CTRL_CLR         0x0008
  42 #define IMX_OCOTP_ADDR_TIMING           0x0010
  43 #define IMX_OCOTP_ADDR_DATA             0x0020
  44
  45 #define IMX_OCOTP_BM_CTRL_ADDR          0x0000007F
  46 #define IMX_OCOTP_BM_CTRL_BUSY          0x00000100
  47 #define IMX_OCOTP_BM_CTRL_ERROR         0x00000200
  48 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS   0x00000400
  49
  50 #define DEF_RELAX                       20 /* > 16.5ns */
  51 #define IMX_OCOTP_WR_UNLOCK             0x3E770000
  52 #define IMX_OCOTP_READ_LOCKED_VAL       0xBADABADA
  53
  54 static DEFINE_MUTEX(ocotp_mutex);
  55
  56 struct ocotp_priv {
  57         struct device *dev;
  58         struct clk *clk;
  59         void __iomem *base;
  60         unsigned int nregs;
  61         struct nvmem_config *config;
  62 };
  63
  64 static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags)
  65 {
  66         int count;
  67         u32 c, mask;
  68
  69         mask = IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags;
  70
  71         for (count = 10000; count >= 0; count--) {
  72                 c = readl(base + IMX_OCOTP_ADDR_CTRL);
  73                 if (!(c & mask))
  74                         break;
  75                 cpu_relax();
  76         }
  77
  78         if (count < 0) {
  79                 /* HW_OCOTP_CTRL[ERROR] will be set under the following
  80                  * conditions:
  81                  * - A write is performed to a shadow register during a shadow
  82                  *   reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
  83                  *   set. In addition, the contents of the shadow register shall
  84                  *   not be updated.
  85                  * - A write is performed to a shadow register which has been
  86                  *   locked.
  87                  * - A read is performed to from a shadow register which has
  88                  *   been read locked.
  89                  * - A program is performed to a fuse word which has been locked
  90                  * - A read is performed to from a fuse word which has been read
  91                  *   locked.
  92                  */
  93                 if (c & IMX_OCOTP_BM_CTRL_ERROR)
  94                         return -EPERM;
  95                 return -ETIMEDOUT;
  96         }
  97
  98         return 0;
  99 }
 100
 101 static void imx_ocotp_clr_err_if_set(void __iomem *base)
 102 {
 103         u32 c;
 104
 105         c = readl(base + IMX_OCOTP_ADDR_CTRL);
 106         if (!(c & IMX_OCOTP_BM_CTRL_ERROR))
 107                 return;
 108
 109         writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR);
 110 }
 111
 112 static int imx_ocotp_read(void *context, unsigned int offset,
 113                           void *val, size_t bytes)
 114 {
 115         struct ocotp_priv *priv = context;
 116         unsigned int count;
 117         u32 *buf = val;
 118         int i, ret;
 119         u32 index;
 120
 121         index = offset >> 2;
 122         count = bytes >> 2;
 123
 124         if (count > (priv->nregs - index))
 125                 count = priv->nregs - index;
 126
 127         mutex_lock(&ocotp_mutex);
 128
 129         ret = clk_prepare_enable(priv->clk);
 130         if (ret < 0) {
 131                 mutex_unlock(&ocotp_mutex);
 132                 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
 133                 return ret;
 134         }
 135
 136         ret = imx_ocotp_wait_for_busy(priv->base, 0);
 137         if (ret < 0) {
 138                 dev_err(priv->dev, "timeout during read setup\n");
 139                 goto read_end;
 140         }
 141
 142         for (i = index; i < (index + count); i++) {
 143                 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
 144                                i * IMX_OCOTP_OFFSET_PER_WORD);
 145
 146                 /* 47.3.1.2
 147                  * For "read locked" registers 0xBADABADA will be returned and
 148                  * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
 149                  * software before any new write, read or reload access can be
 150                  * issued
 151                  */
 152                 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
 153                         imx_ocotp_clr_err_if_set(priv->base);
 154         }
 155         ret = 0;
 156
 157 read_end:
 158         clk_disable_unprepare(priv->clk);
 159         mutex_unlock(&ocotp_mutex);
 160         return ret;
 161 }
 162
 163 static int imx_ocotp_write(void *context, unsigned int offset, void *val,
 164                            size_t bytes)
 165 {
 166         struct ocotp_priv *priv = context;
 167         u32 *buf = val;
 168         int ret;
 169
 170         unsigned long clk_rate = 0;
 171         unsigned long strobe_read, relax, strobe_prog;
 172         u32 timing = 0;
 173         u32 ctrl;
 174         u8 waddr;
 175
 176         /* allow only writing one complete OTP word at a time */
 177         if ((bytes != priv->config->word_size) ||
 178             (offset % priv->config->word_size))
 179                 return -EINVAL;
 180
 181         mutex_lock(&ocotp_mutex);
 182
 183         ret = clk_prepare_enable(priv->clk);
 184         if (ret < 0) {
 185                 mutex_unlock(&ocotp_mutex);
 186                 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
 187                 return ret;
 188         }
 189
 190         /* 47.3.1.3.1
 191          * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
 192          * fields with timing values to match the current frequency of the
 193          * ipg_clk. OTP writes will work at maximum bus frequencies as long
 194          * as the HW_OCOTP_TIMING parameters are set correctly.
 195          */
 196         clk_rate = clk_get_rate(priv->clk);
 197
 198         relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
 199         strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
 200         strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
 201
 202         timing = strobe_prog & 0x00000FFF;
 203         timing |= (relax       << 12) & 0x0000F000;
 204         timing |= (strobe_read << 16) & 0x003F0000;
 205
 206         writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
 207
 208         /* 47.3.1.3.2
 209          * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
 210          * Overlapped accesses are not supported by the controller. Any pending
 211          * write or reload must be completed before a write access can be
 212          * requested.
 213          */
 214         ret = imx_ocotp_wait_for_busy(priv->base, 0);
 215         if (ret < 0) {
 216                 dev_err(priv->dev, "timeout during timing setup\n");
 217                 goto write_end;
 218         }
 219
 220         /* 47.3.1.3.3
 221          * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
 222          * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
 223          * for each write access. The lock code is documented in the register
 224          * description. Both the unlock code and address can be written in the
 225          * same operation.
 226          */
 227         /* OTP write/read address specifies one of 128 word address locations */
 228         waddr = offset / 4;
 229
 230         ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
 231         ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR;
 232         ctrl |= waddr & IMX_OCOTP_BM_CTRL_ADDR;
 233         ctrl |= IMX_OCOTP_WR_UNLOCK;
 234
 235         writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
 236
 237         /* 47.3.1.3.4
 238          * Write the data to the HW_OCOTP_DATA register. This will automatically
 239          * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
 240          * protect programming same OTP bit twice, before program OCOTP will
 241          * automatically read fuse value in OTP and use read value to mask
 242          * program data. The controller will use masked program data to program
 243          * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
 244          * fields with 1's will result in that OTP bit being programmed. Bit
 245          * fields with 0's will be ignored. At the same time that the write is
 246          * accepted, the controller makes an internal copy of
 247          * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
 248          * sequence is initiated. This copy guarantees that erroneous writes to
 249          * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
 250          * should also be noted that during the programming HW_OCOTP_DATA will
 251          * shift right (with zero fill). This shifting is required to program
 252          * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
 253          * modified.
 254          */
 255         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA);
 256
 257         /* 47.4.1.4.5
 258          * Once complete, the controller will clear BUSY. A write request to a
 259          * protected or locked region will result in no OTP access and no
 260          * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
 261          * be set. It must be cleared by software before any new write access
 262          * can be issued.
 263          */
 264         ret = imx_ocotp_wait_for_busy(priv->base, 0);
 265         if (ret < 0) {
 266                 if (ret == -EPERM) {
 267                         dev_err(priv->dev, "failed write to locked region");
 268                         imx_ocotp_clr_err_if_set(priv->base);
 269                 } else {
 270                         dev_err(priv->dev, "timeout during data write\n");
 271                 }
 272                 goto write_end;
 273         }
 274
 275         /* 47.3.1.4
 276          * Write Postamble: Due to internal electrical characteristics of the
 277          * OTP during writes, all OTP operations following a write must be
 278          * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
 279          * the write.
 280          */
 281         udelay(2);
 282
 283         /* reload all shadow registers */
 284         writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS,
 285                priv->base + IMX_OCOTP_ADDR_CTRL_SET);
 286         ret = imx_ocotp_wait_for_busy(priv->base,
 287                                       IMX_OCOTP_BM_CTRL_REL_SHADOWS);
 288         if (ret < 0) {
 289                 dev_err(priv->dev, "timeout during shadow register reload\n");
 290                 goto write_end;
 291         }
 292
 293 write_end:
 294         clk_disable_unprepare(priv->clk);
 295         mutex_unlock(&ocotp_mutex);
 296         if (ret < 0)
 297                 return ret;
 298         return bytes;
 299 }
 300
 301 static struct nvmem_config imx_ocotp_nvmem_config = {
 302         .name = "imx-ocotp",
 303         .read_only = false,
 304         .word_size = 4,
 305         .stride = 4,
 306         .owner = THIS_MODULE,
 307         .reg_read = imx_ocotp_read,
 308         .reg_write = imx_ocotp_write,
 309 };
 310
 311 static const struct of_device_id imx_ocotp_dt_ids[] = {
 312         { .compatible = "fsl,imx6q-ocotp",  (void *)128 },
 313         { .compatible = "fsl,imx6sl-ocotp", (void *)64 },
 314         { .compatible = "fsl,imx6sx-ocotp", (void *)128 },
 315         { .compatible = "fsl,imx6ul-ocotp", (void *)128 },
 316         { .compatible = "fsl,imx7d-ocotp", (void *)64 },
 317         { },
 318 };
 319 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
 320
 321 static int imx_ocotp_probe(struct platform_device *pdev)
 322 {
 323         const struct of_device_id *of_id;
 324         struct device *dev = &pdev->dev;
 325         struct resource *res;
 326         struct ocotp_priv *priv;
 327         struct nvmem_device *nvmem;
 328
 329         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 330         if (!priv)
 331                 return -ENOMEM;
 332
 333         priv->dev = dev;
 334
 335         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 336         priv->base = devm_ioremap_resource(dev, res);
 337         if (IS_ERR(priv->base))
 338                 return PTR_ERR(priv->base);
 339
 340         priv->clk = devm_clk_get(dev, NULL);
 341         if (IS_ERR(priv->clk))
 342                 return PTR_ERR(priv->clk);
 343
 344         of_id = of_match_device(imx_ocotp_dt_ids, dev);
 345         priv->nregs = (unsigned long)of_id->data;
 346         imx_ocotp_nvmem_config.size = 4 * priv->nregs;
 347         imx_ocotp_nvmem_config.dev = dev;
 348         imx_ocotp_nvmem_config.priv = priv;
 349         priv->config = &imx_ocotp_nvmem_config;
 350         nvmem = nvmem_register(&imx_ocotp_nvmem_config);
 351
 352         if (IS_ERR(nvmem))
 353                 return PTR_ERR(nvmem);
 354
 355         platform_set_drvdata(pdev, nvmem);
 356
 357         return 0;
 358 }
 359
 360 static int imx_ocotp_remove(struct platform_device *pdev)
 361 {
 362         struct nvmem_device *nvmem = platform_get_drvdata(pdev);
 363
 364         return nvmem_unregister(nvmem);
 365 }
 366
 367 static struct platform_driver imx_ocotp_driver = {
 368         .probe  = imx_ocotp_probe,
 369         .remove = imx_ocotp_remove,
 370         .driver = {
 371                 .name   = "imx_ocotp",
 372                 .of_match_table = imx_ocotp_dt_ids,
 373         },
 374 };
 375 module_platform_driver(imx_ocotp_driver);
 376
 377 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
 378 MODULE_DESCRIPTION("i.MX6 OCOTP fuse box driver");
 379 MODULE_LICENSE("GPL v2");