drivers/nvmem/qfprom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/device.h>
   8 #include <linux/io.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/mod_devicetable.h>
  13 #include <linux/nvmem-provider.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/property.h>
  16 #include <linux/regulator/consumer.h>
  17
  18 /* Blow timer clock frequency in Mhz */
  19 #define QFPROM_BLOW_TIMER_OFFSET 0x03c
  20
  21 /* Amount of time required to hold charge to blow fuse in micro-seconds */
  22 #define QFPROM_FUSE_BLOW_POLL_US        100
  23 #define QFPROM_FUSE_BLOW_TIMEOUT_US     1000
  24
  25 #define QFPROM_BLOW_STATUS_OFFSET       0x048
  26 #define QFPROM_BLOW_STATUS_BUSY         0x1
  27 #define QFPROM_BLOW_STATUS_READY        0x0
  28
  29 #define QFPROM_ACCEL_OFFSET             0x044
  30
  31 #define QFPROM_VERSION_OFFSET           0x0
  32 #define QFPROM_MAJOR_VERSION_SHIFT      28
  33 #define QFPROM_MAJOR_VERSION_MASK       GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
  34 #define QFPROM_MINOR_VERSION_SHIFT      16
  35 #define QFPROM_MINOR_VERSION_MASK       GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)
  36
  37 static bool read_raw_data;
  38 module_param(read_raw_data, bool, 0644);
  39 MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");
  40
  41 /**
  42  * struct qfprom_soc_data - config that varies from SoC to SoC.
  43  *
  44  * @accel_value:             Should contain qfprom accel value.
  45  * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
  46  * @qfprom_blow_set_freq:    The frequency required to set when we start the
  47  *                           fuse blowing.
  48  * @qfprom_blow_uV:          LDO voltage to be set when doing efuse blow
  49  */
  50 struct qfprom_soc_data {
  51         u32 accel_value;
  52         u32 qfprom_blow_timer_value;
  53         u32 qfprom_blow_set_freq;
  54         int qfprom_blow_uV;
  55 };
  56
  57 /**
  58  * struct qfprom_priv - structure holding qfprom attributes
  59  *
  60  * @qfpraw:       iomapped memory space for qfprom-efuse raw address space.
  61  * @qfpconf:      iomapped memory space for qfprom-efuse configuration address
  62  *                space.
  63  * @qfpcorrected: iomapped memory space for qfprom corrected address space.
  64  * @qfpsecurity:  iomapped memory space for qfprom security control space.
  65  * @dev:          qfprom device structure.
  66  * @secclk:       Clock supply.
  67  * @vcc:          Regulator supply.
  68  * @soc_data:     Data that for things that varies from SoC to SoC.
  69  */
  70 struct qfprom_priv {
  71         void __iomem *qfpraw;
  72         void __iomem *qfpconf;
  73         void __iomem *qfpcorrected;
  74         void __iomem *qfpsecurity;
  75         struct device *dev;
  76         struct clk *secclk;
  77         struct regulator *vcc;
  78         const struct qfprom_soc_data *soc_data;
  79 };
  80
  81 /**
  82  * struct qfprom_touched_values - saved values to restore after blowing
  83  *
  84  * @clk_rate: The rate the clock was at before blowing.
  85  * @accel_val: The value of the accel reg before blowing.
  86  * @timer_val: The value of the timer before blowing.
  87  */
  88 struct qfprom_touched_values {
  89         unsigned long clk_rate;
  90         u32 accel_val;
  91         u32 timer_val;
  92 };
  93
  94 /**
  95  * struct qfprom_soc_compatible_data - Data matched against the SoC
  96  * compatible string.
  97  *
  98  * @keepout: Array of keepout regions for this SoC.
  99  * @nkeepout: Number of elements in the keepout array.
 100  */
 101 struct qfprom_soc_compatible_data {
 102         const struct nvmem_keepout *keepout;
 103         unsigned int nkeepout;
 104 };
 105
 106 static const struct nvmem_keepout sc7180_qfprom_keepout[] = {
 107         {.start = 0x128, .end = 0x148},
 108         {.start = 0x220, .end = 0x228}
 109 };
 110
 111 static const struct qfprom_soc_compatible_data sc7180_qfprom = {
 112         .keepout = sc7180_qfprom_keepout,
 113         .nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
 114 };
 115
 116 static const struct nvmem_keepout sc7280_qfprom_keepout[] = {
 117         {.start = 0x128, .end = 0x148},
 118         {.start = 0x238, .end = 0x248}
 119 };
 120
 121 static const struct qfprom_soc_compatible_data sc7280_qfprom = {
 122         .keepout = sc7280_qfprom_keepout,
 123         .nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout)
 124 };
 125
 126 /**
 127  * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
 128  * @priv: Our driver data.
 129  * @old:  The data that was stashed from before fuse blowing.
 130  *
 131  * Resets the value of the blow timer, accel register and the clock
 132  * and voltage settings.
 133  *
 134  * Prints messages if there are errors but doesn't return an error code
 135  * since there's not much we can do upon failure.
 136  */
 137 static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
 138                                         const struct qfprom_touched_values *old)
 139 {
 140         int ret;
 141
 142         /*
 143          * This may be a shared rail and may be able to run at a lower rate
 144          * when we're not blowing fuses.  At the moment, the regulator framework
 145          * applies voltage constraints even on disabled rails, so remove our
 146          * constraints and allow the rail to be adjusted by other users.
 147          */
 148         ret = regulator_set_voltage(priv->vcc, 0, INT_MAX);
 149         if (ret)
 150                 dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n");
 151
 152         ret = regulator_disable(priv->vcc);
 153         if (ret)
 154                 dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");
 155
 156         ret = clk_set_rate(priv->secclk, old->clk_rate);
 157         if (ret)
 158                 dev_warn(priv->dev,
 159                          "Failed to set clock rate for disable (ignoring)\n");
 160
 161         clk_disable_unprepare(priv->secclk);
 162
 163         writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
 164         writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
 165 }
 166
 167 /**
 168  * qfprom_enable_fuse_blowing() - Enable fuse blowing.
 169  * @priv: Our driver data.
 170  * @old:  We'll stash stuff here to use when disabling.
 171  *
 172  * Sets the value of the blow timer, accel register and the clock
 173  * and voltage settings.
 174  *
 175  * Prints messages if there are errors so caller doesn't need to.
 176  *
 177  * Return: 0 or -err.
 178  */
 179 static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
 180                                       struct qfprom_touched_values *old)
 181 {
 182         int ret;
 183         int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV;
 184
 185         ret = clk_prepare_enable(priv->secclk);
 186         if (ret) {
 187                 dev_err(priv->dev, "Failed to enable clock\n");
 188                 return ret;
 189         }
 190
 191         old->clk_rate = clk_get_rate(priv->secclk);
 192         ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
 193         if (ret) {
 194                 dev_err(priv->dev, "Failed to set clock rate for enable\n");
 195                 goto err_clk_prepared;
 196         }
 197
 198         /*
 199          * Hardware requires a minimum voltage for fuse blowing.
 200          * This may be a shared rail so don't specify a maximum.
 201          * Regulator constraints will cap to the actual maximum.
 202          */
 203         ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX);
 204         if (ret) {
 205                 dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV);
 206                 goto err_clk_rate_set;
 207         }
 208
 209         ret = regulator_enable(priv->vcc);
 210         if (ret) {
 211                 dev_err(priv->dev, "Failed to enable regulator\n");
 212                 goto err_clk_rate_set;
 213         }
 214
 215         old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
 216         old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
 217         writel(priv->soc_data->qfprom_blow_timer_value,
 218                priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
 219         writel(priv->soc_data->accel_value,
 220                priv->qfpconf + QFPROM_ACCEL_OFFSET);
 221
 222         return 0;
 223
 224 err_clk_rate_set:
 225         clk_set_rate(priv->secclk, old->clk_rate);
 226 err_clk_prepared:
 227         clk_disable_unprepare(priv->secclk);
 228         return ret;
 229 }
 230
 231 /**
 232  * qfprom_efuse_reg_write() - Write to fuses.
 233  * @context: Our driver data.
 234  * @reg:     The offset to write at.
 235  * @_val:    Pointer to data to write.
 236  * @bytes:   The number of bytes to write.
 237  *
 238  * Writes to fuses.  WARNING: THIS IS PERMANENT.
 239  *
 240  * Return: 0 or -err.
 241  */
 242 static int qfprom_reg_write(void *context, unsigned int reg, void *_val,
 243                             size_t bytes)
 244 {
 245         struct qfprom_priv *priv = context;
 246         struct qfprom_touched_values old;
 247         int words = bytes / 4;
 248         u32 *value = _val;
 249         u32 blow_status;
 250         int ret;
 251         int i;
 252
 253         dev_dbg(priv->dev,
 254                 "Writing to raw qfprom region : %#010x of size: %zu\n",
 255                 reg, bytes);
 256
 257         /*
 258          * The hardware only allows us to write word at a time, but we can
 259          * read byte at a time.  Until the nvmem framework allows a separate
 260          * word_size and stride for reading vs. writing, we'll enforce here.
 261          */
 262         if (bytes % 4) {
 263                 dev_err(priv->dev,
 264                         "%zu is not an integral number of words\n", bytes);
 265                 return -EINVAL;
 266         }
 267         if (reg % 4) {
 268                 dev_err(priv->dev,
 269                         "Invalid offset: %#x.  Must be word aligned\n", reg);
 270                 return -EINVAL;
 271         }
 272
 273         ret = qfprom_enable_fuse_blowing(priv, &old);
 274         if (ret)
 275                 return ret;
 276
 277         ret = readl_relaxed_poll_timeout(
 278                 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
 279                 blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
 280                 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
 281
 282         if (ret) {
 283                 dev_err(priv->dev,
 284                         "Timeout waiting for initial ready; aborting.\n");
 285                 goto exit_enabled_fuse_blowing;
 286         }
 287
 288         for (i = 0; i < words; i++)
 289                 writel(value[i], priv->qfpraw + reg + (i * 4));
 290
 291         ret = readl_relaxed_poll_timeout(
 292                 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
 293                 blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
 294                 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
 295
 296         /* Give an error, but not much we can do in this case */
 297         if (ret)
 298                 dev_err(priv->dev, "Timeout waiting for finish.\n");
 299
 300 exit_enabled_fuse_blowing:
 301         qfprom_disable_fuse_blowing(priv, &old);
 302
 303         return ret;
 304 }
 305
 306 static int qfprom_reg_read(void *context,
 307                         unsigned int reg, void *_val, size_t bytes)
 308 {
 309         struct qfprom_priv *priv = context;
 310         u8 *val = _val;
 311         int i = 0, words = bytes;
 312         void __iomem *base = priv->qfpcorrected;
 313
 314         if (read_raw_data && priv->qfpraw)
 315                 base = priv->qfpraw;
 316
 317         while (words--)
 318                 *val++ = readb(base + reg + i++);
 319
 320         return 0;
 321 }
 322
 323 static const struct qfprom_soc_data qfprom_7_8_data = {
 324         .accel_value = 0xD10,
 325         .qfprom_blow_timer_value = 25,
 326         .qfprom_blow_set_freq = 4800000,
 327         .qfprom_blow_uV = 1800000,
 328 };
 329
 330 static const struct qfprom_soc_data qfprom_7_15_data = {
 331         .accel_value = 0xD08,
 332         .qfprom_blow_timer_value = 24,
 333         .qfprom_blow_set_freq = 4800000,
 334         .qfprom_blow_uV = 1900000,
 335 };
 336
 337 static int qfprom_probe(struct platform_device *pdev)
 338 {
 339         struct nvmem_config econfig = {
 340                 .name = "qfprom",
 341                 .stride = 1,
 342                 .word_size = 1,
 343                 .id = NVMEM_DEVID_AUTO,
 344                 .reg_read = qfprom_reg_read,
 345         };
 346         struct device *dev = &pdev->dev;
 347         struct resource *res;
 348         struct nvmem_device *nvmem;
 349         const struct qfprom_soc_compatible_data *soc_data;
 350         struct qfprom_priv *priv;
 351         int ret;
 352
 353         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 354         if (!priv)
 355                 return -ENOMEM;
 356
 357         /* The corrected section is always provided */
 358         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 359         priv->qfpcorrected = devm_ioremap_resource(dev, res);
 360         if (IS_ERR(priv->qfpcorrected))
 361                 return PTR_ERR(priv->qfpcorrected);
 362
 363         econfig.size = resource_size(res);
 364         econfig.dev = dev;
 365         econfig.priv = priv;
 366
 367         priv->dev = dev;
 368         soc_data = device_get_match_data(dev);
 369         if (soc_data) {
 370                 econfig.keepout = soc_data->keepout;
 371                 econfig.nkeepout = soc_data->nkeepout;
 372         }
 373
 374         /*
 375          * If more than one region is provided then the OS has the ability
 376          * to write.
 377          */
 378         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 379         if (res) {
 380                 u32 version;
 381                 int major_version, minor_version;
 382
 383                 priv->qfpraw = devm_ioremap_resource(dev, res);
 384                 if (IS_ERR(priv->qfpraw))
 385                         return PTR_ERR(priv->qfpraw);
 386                 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 387                 priv->qfpconf = devm_ioremap_resource(dev, res);
 388                 if (IS_ERR(priv->qfpconf))
 389                         return PTR_ERR(priv->qfpconf);
 390                 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
 391                 priv->qfpsecurity = devm_ioremap_resource(dev, res);
 392                 if (IS_ERR(priv->qfpsecurity))
 393                         return PTR_ERR(priv->qfpsecurity);
 394
 395                 version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
 396                 major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
 397                                 QFPROM_MAJOR_VERSION_SHIFT;
 398                 minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
 399                                 QFPROM_MINOR_VERSION_SHIFT;
 400
 401                 if (major_version == 7 && minor_version == 8)
 402                         priv->soc_data = &qfprom_7_8_data;
 403                 else if (major_version == 7 && minor_version == 15)
 404                         priv->soc_data = &qfprom_7_15_data;
 405
 406                 priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
 407                 if (IS_ERR(priv->vcc))
 408                         return PTR_ERR(priv->vcc);
 409
 410                 priv->secclk = devm_clk_get(dev, "core");
 411                 if (IS_ERR(priv->secclk)) {
 412                         ret = PTR_ERR(priv->secclk);
 413                         if (ret != -EPROBE_DEFER)
 414                                 dev_err(dev, "Error getting clock: %d\n", ret);
 415                         return ret;
 416                 }
 417
 418                 /* Only enable writing if we have SoC data. */
 419                 if (priv->soc_data)
 420                         econfig.reg_write = qfprom_reg_write;
 421         }
 422
 423         nvmem = devm_nvmem_register(dev, &econfig);
 424
 425         return PTR_ERR_OR_ZERO(nvmem);
 426 }
 427
 428 static const struct of_device_id qfprom_of_match[] = {
 429         { .compatible = "qcom,qfprom",},
 430         { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom},
 431         { .compatible = "qcom,sc7280-qfprom", .data = &sc7280_qfprom},
 432         {/* sentinel */},
 433 };
 434 MODULE_DEVICE_TABLE(of, qfprom_of_match);
 435
 436 static struct platform_driver qfprom_driver = {
 437         .probe = qfprom_probe,
 438         .driver = {
 439                 .name = "qcom,qfprom",
 440                 .of_match_table = qfprom_of_match,
 441         },
 442 };
 443 module_platform_driver(qfprom_driver);
 444 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
 445 MODULE_DESCRIPTION("Qualcomm QFPROM driver");
 446 MODULE_LICENSE("GPL v2");