1 // SPDX-License-Identifier: GPL-2.0-or-later
5 ** (c) Copyright 1999 Red Hat Software
6 ** (c) Copyright 1999 SuSE GmbH
7 ** (c) Copyright 1999,2000 Hewlett-Packard Company
8 ** (c) Copyright 2000 Grant Grundler
9 ** (c) Copyright 2006 Helge Deller
12 ** This module provides access to Dino PCI bus (config/IOport spaces)
13 ** and helps manage Dino IRQ lines.
15 ** Dino interrupt handling is a bit complicated.
16 ** Dino always writes to the broadcast EIR via irr0 for now.
17 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
18 ** Only one processor interrupt is used for the 11 IRQ line
21 ** The different between Built-in Dino and Card-Mode
22 ** dino is in chip initialization and pci device initialization.
24 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port
25 ** BARs are configured and used by the driver. Programming MMIO address
26 ** requires substantial knowledge of available Host I/O address ranges
27 ** is currently not supported. Port/Config accessor functions are the
28 ** same. "BIOS" differences are handled within the existing routines.
32 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
33 ** - added support for the integrated RS232.
37 ** TODO: create a virtual address for each Dino HPA.
38 ** GSC code might be able to do this since IODC data tells us
39 ** how many pages are used. PCI subsystem could (must?) do this
40 ** for PCI drivers devices which implement/use MMIO registers.
43 #include <linux/delay.h>
44 #include <linux/types.h>
45 #include <linux/kernel.h>
46 #include <linux/pci.h>
47 #include <linux/init.h>
48 #include <linux/ioport.h>
49 #include <linux/slab.h>
50 #include <linux/interrupt.h> /* for struct irqaction */
51 #include <linux/spinlock.h> /* for spinlock_t and prototypes */
56 #include <asm/hardware.h>
64 #define DBG(x...) printk(x)
70 ** Config accessor functions only pass in the 8-bit bus number
71 ** and not the 8-bit "PCI Segment" number. Each Dino will be
72 ** assigned a PCI bus number based on "when" it's discovered.
74 ** The "secondary" bus number is set to this before calling
75 ** pci_scan_bus(). If any PPB's are present, the scan will
76 ** discover them and update the "secondary" and "subordinate"
77 ** fields in Dino's pci_bus structure.
79 ** Changes in the configuration *will* result in a different
80 ** bus number for each dino.
83 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
84 #define is_cujo(id) ((id)->hversion == 0x682)
86 #define DINO_IAR0 0x004
87 #define DINO_IODC_ADDR 0x008
88 #define DINO_IODC_DATA_0 0x008
89 #define DINO_IODC_DATA_1 0x008
90 #define DINO_IRR0 0x00C
91 #define DINO_IAR1 0x010
92 #define DINO_IRR1 0x014
93 #define DINO_IMR 0x018
94 #define DINO_IPR 0x01C
95 #define DINO_TOC_ADDR 0x020
96 #define DINO_ICR 0x024
97 #define DINO_ILR 0x028
98 #define DINO_IO_COMMAND 0x030
99 #define DINO_IO_STATUS 0x034
100 #define DINO_IO_CONTROL 0x038
101 #define DINO_IO_GSC_ERR_RESP 0x040
102 #define DINO_IO_ERR_INFO 0x044
103 #define DINO_IO_PCI_ERR_RESP 0x048
104 #define DINO_IO_FBB_EN 0x05c
105 #define DINO_IO_ADDR_EN 0x060
106 #define DINO_PCI_ADDR 0x064
107 #define DINO_CONFIG_DATA 0x068
108 #define DINO_IO_DATA 0x06c
109 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */
110 #define DINO_GSC2X_CONFIG 0x7b4
111 #define DINO_GMASK 0x800
112 #define DINO_PAMR 0x804
113 #define DINO_PAPR 0x808
114 #define DINO_DAMODE 0x80c
115 #define DINO_PCICMD 0x810
116 #define DINO_PCISTS 0x814
117 #define DINO_MLTIM 0x81c
118 #define DINO_BRDG_FEAT 0x820
119 #define DINO_PCIROR 0x824
120 #define DINO_PCIWOR 0x828
121 #define DINO_TLTIM 0x830
123 #define DINO_IRQS 11 /* bits 0-10 are architected */
124 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
125 #define DINO_LOCAL_IRQS (DINO_IRQS+1)
127 #define DINO_MASK_IRQ(x) (1<<(x))
129 #define PCIINTA 0x001
130 #define PCIINTB 0x002
131 #define PCIINTC 0x004
132 #define PCIINTD 0x008
133 #define PCIINTE 0x010
134 #define PCIINTF 0x020
135 #define GSCEXTINT 0x040
136 /* #define xxx 0x080 - bit 7 is "default" */
137 /* #define xxx 0x100 - bit 8 not used */
138 /* #define xxx 0x200 - bit 9 not used */
139 #define RS232INT 0x400
143 struct pci_hba_data hba
; /* 'C' inheritance - must be first */
144 spinlock_t dinosaur_pen
;
145 unsigned long txn_addr
; /* EIR addr to generate interrupt */
146 u32 txn_data
; /* EIR data assign to each dino */
147 u32 imr
; /* IRQ's which are enabled */
148 int global_irq
[DINO_LOCAL_IRQS
]; /* map IMR bit to global irq */
150 unsigned int dino_irr0
; /* save most recent IRQ line stat */
154 static inline struct dino_device
*DINO_DEV(struct pci_hba_data
*hba
)
156 return container_of(hba
, struct dino_device
, hba
);
160 * Dino Configuration Space Accessor Functions
163 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
166 * keep the current highest bus count to assist in allocating busses. This
167 * tries to keep a global bus count total so that when we discover an
168 * entirely new bus, it can be given a unique bus number.
170 static int dino_current_bus
= 0;
172 static int dino_cfg_read(struct pci_bus
*bus
, unsigned int devfn
, int where
,
175 struct dino_device
*d
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
176 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->busn_res
.start
;
177 u32 v
= DINO_CFG_TOK(local_bus
, devfn
, where
& ~3);
178 void __iomem
*base_addr
= d
->hba
.base_addr
;
181 DBG("%s: %p, %d, %d, %d\n", __func__
, base_addr
, devfn
, where
,
183 spin_lock_irqsave(&d
->dinosaur_pen
, flags
);
185 /* tell HW which CFG address */
186 __raw_writel(v
, base_addr
+ DINO_PCI_ADDR
);
188 /* generate cfg read cycle */
190 *val
= readb(base_addr
+ DINO_CONFIG_DATA
+ (where
& 3));
191 } else if (size
== 2) {
192 *val
= readw(base_addr
+ DINO_CONFIG_DATA
+ (where
& 2));
193 } else if (size
== 4) {
194 *val
= readl(base_addr
+ DINO_CONFIG_DATA
);
197 spin_unlock_irqrestore(&d
->dinosaur_pen
, flags
);
202 * Dino address stepping "feature":
203 * When address stepping, Dino attempts to drive the bus one cycle too soon
204 * even though the type of cycle (config vs. MMIO) might be different.
205 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
207 static int dino_cfg_write(struct pci_bus
*bus
, unsigned int devfn
, int where
,
210 struct dino_device
*d
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
211 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->busn_res
.start
;
212 u32 v
= DINO_CFG_TOK(local_bus
, devfn
, where
& ~3);
213 void __iomem
*base_addr
= d
->hba
.base_addr
;
216 DBG("%s: %p, %d, %d, %d\n", __func__
, base_addr
, devfn
, where
,
218 spin_lock_irqsave(&d
->dinosaur_pen
, flags
);
220 /* avoid address stepping feature */
221 __raw_writel(v
& 0xffffff00, base_addr
+ DINO_PCI_ADDR
);
222 __raw_readl(base_addr
+ DINO_CONFIG_DATA
);
224 /* tell HW which CFG address */
225 __raw_writel(v
, base_addr
+ DINO_PCI_ADDR
);
226 /* generate cfg read cycle */
228 writeb(val
, base_addr
+ DINO_CONFIG_DATA
+ (where
& 3));
229 } else if (size
== 2) {
230 writew(val
, base_addr
+ DINO_CONFIG_DATA
+ (where
& 2));
231 } else if (size
== 4) {
232 writel(val
, base_addr
+ DINO_CONFIG_DATA
);
235 spin_unlock_irqrestore(&d
->dinosaur_pen
, flags
);
239 static struct pci_ops dino_cfg_ops
= {
240 .read
= dino_cfg_read
,
241 .write
= dino_cfg_write
,
246 * Dino "I/O Port" Space Accessor Functions
248 * Many PCI devices don't require use of I/O port space (eg Tulip,
249 * NCR720) since they export the same registers to both MMIO and
250 * I/O port space. Performance is going to stink if drivers use
251 * I/O port instead of MMIO.
254 #define DINO_PORT_IN(type, size, mask) \
255 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
258 unsigned long flags; \
259 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
260 /* tell HW which IO Port address */ \
261 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
262 /* generate I/O PORT read cycle */ \
263 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
264 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
268 DINO_PORT_IN(b
, 8, 3)
269 DINO_PORT_IN(w
, 16, 2)
270 DINO_PORT_IN(l
, 32, 0)
272 #define DINO_PORT_OUT(type, size, mask) \
273 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
275 unsigned long flags; \
276 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
277 /* tell HW which IO port address */ \
278 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
279 /* generate cfg write cycle */ \
280 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
281 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
284 DINO_PORT_OUT(b
, 8, 3)
285 DINO_PORT_OUT(w
, 16, 2)
286 DINO_PORT_OUT(l
, 32, 0)
288 static struct pci_port_ops dino_port_ops
= {
297 static void dino_mask_irq(struct irq_data
*d
)
299 struct dino_device
*dino_dev
= irq_data_get_irq_chip_data(d
);
300 int local_irq
= gsc_find_local_irq(d
->irq
, dino_dev
->global_irq
, DINO_LOCAL_IRQS
);
302 DBG(KERN_WARNING
"%s(0x%px, %d)\n", __func__
, dino_dev
, d
->irq
);
304 /* Clear the matching bit in the IMR register */
305 dino_dev
->imr
&= ~(DINO_MASK_IRQ(local_irq
));
306 __raw_writel(dino_dev
->imr
, dino_dev
->hba
.base_addr
+DINO_IMR
);
309 static void dino_unmask_irq(struct irq_data
*d
)
311 struct dino_device
*dino_dev
= irq_data_get_irq_chip_data(d
);
312 int local_irq
= gsc_find_local_irq(d
->irq
, dino_dev
->global_irq
, DINO_LOCAL_IRQS
);
315 DBG(KERN_WARNING
"%s(0x%px, %d)\n", __func__
, dino_dev
, d
->irq
);
318 ** clear pending IRQ bits
320 ** This does NOT change ILR state!
321 ** See comment below for ILR usage.
323 __raw_readl(dino_dev
->hba
.base_addr
+DINO_IPR
);
325 /* set the matching bit in the IMR register */
326 dino_dev
->imr
|= DINO_MASK_IRQ(local_irq
); /* used in dino_isr() */
327 __raw_writel( dino_dev
->imr
, dino_dev
->hba
.base_addr
+DINO_IMR
);
329 /* Emulate "Level Triggered" Interrupt
330 ** Basically, a driver is blowing it if the IRQ line is asserted
331 ** while the IRQ is disabled. But tulip.c seems to do that....
332 ** Give 'em a kluge award and a nice round of applause!
334 ** The gsc_write will generate an interrupt which invokes dino_isr().
335 ** dino_isr() will read IPR and find nothing. But then catch this
336 ** when it also checks ILR.
338 tmp
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_ILR
);
339 if (tmp
& DINO_MASK_IRQ(local_irq
)) {
340 DBG(KERN_WARNING
"%s(): IRQ asserted! (ILR 0x%x)\n",
342 gsc_writel(dino_dev
->txn_data
, dino_dev
->txn_addr
);
346 static struct irq_chip dino_interrupt_type
= {
348 .irq_unmask
= dino_unmask_irq
,
349 .irq_mask
= dino_mask_irq
,
354 * Handle a Processor interrupt generated by Dino.
356 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
357 * wedging the CPU. Could be removed or made optional at some point.
359 static irqreturn_t
dino_isr(int irq
, void *intr_dev
)
361 struct dino_device
*dino_dev
= intr_dev
;
365 /* read and acknowledge pending interrupts */
367 dino_dev
->dino_irr0
=
369 mask
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_IRR0
) & DINO_IRR_MASK
;
376 int local_irq
= __ffs(mask
);
377 int irq
= dino_dev
->global_irq
[local_irq
];
378 DBG(KERN_DEBUG
"%s(%d, %p) mask 0x%x\n",
379 __func__
, irq
, intr_dev
, mask
);
380 generic_handle_irq(irq
);
381 mask
&= ~DINO_MASK_IRQ(local_irq
);
384 /* Support for level triggered IRQ lines.
386 ** Dropping this support would make this routine *much* faster.
387 ** But since PCI requires level triggered IRQ line to share lines...
388 ** device drivers may assume lines are level triggered (and not
389 ** edge triggered like EISA/ISA can be).
391 mask
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_ILR
) & dino_dev
->imr
;
395 pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n",
396 dino_dev
->hba
.base_addr
, mask
);
401 static void dino_assign_irq(struct dino_device
*dino
, int local_irq
, int *irqp
)
403 int irq
= gsc_assign_irq(&dino_interrupt_type
, dino
);
408 dino
->global_irq
[local_irq
] = irq
;
411 static void dino_choose_irq(struct parisc_device
*dev
, void *ctrl
)
414 struct dino_device
*dino
= ctrl
;
416 switch (dev
->id
.sversion
) {
417 case 0x00084: irq
= 8; break; /* PS/2 */
418 case 0x0008c: irq
= 10; break; /* RS232 */
419 case 0x00096: irq
= 8; break; /* PS/2 */
420 default: return; /* Unknown */
423 dino_assign_irq(dino
, irq
, &dev
->irq
);
428 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
429 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
431 static void quirk_cirrus_cardbus(struct pci_dev
*dev
)
433 u8 new_irq
= dev
->irq
- 1;
434 printk(KERN_INFO
"PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
435 pci_name(dev
), dev
->irq
, new_irq
);
438 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS
, PCI_DEVICE_ID_CIRRUS_6832
, quirk_cirrus_cardbus
);
444 DBG("dino_bios_init\n");
448 * dino_card_setup - Set up the memory space for a Dino in card mode.
449 * @bus: the bus under this dino
451 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
452 * to set up the addresses of the devices on this bus.
454 #define _8MB 0x00800000UL
456 dino_card_setup(struct pci_bus
*bus
, void __iomem
*base_addr
)
459 struct dino_device
*dino_dev
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
460 struct resource
*res
;
464 res
= &dino_dev
->hba
.lmmio_space
;
465 res
->flags
= IORESOURCE_MEM
;
466 size
= scnprintf(name
, sizeof(name
), "Dino LMMIO (%s)",
467 dev_name(bus
->bridge
));
468 res
->name
= kmalloc(size
+1, GFP_KERNEL
);
470 strcpy((char *)res
->name
, name
);
472 res
->name
= dino_dev
->hba
.lmmio_space
.name
;
475 if (ccio_allocate_resource(dino_dev
->hba
.dev
, res
, _8MB
,
476 F_EXTEND(0xf0000000UL
) | _8MB
,
477 F_EXTEND(0xffffffffUL
) &~ _8MB
, _8MB
) < 0) {
478 struct pci_dev
*dev
, *tmp
;
480 printk(KERN_ERR
"Dino: cannot attach bus %s\n",
481 dev_name(bus
->bridge
));
482 /* kill the bus, we can't do anything with it */
483 list_for_each_entry_safe(dev
, tmp
, &bus
->devices
, bus_list
) {
484 list_del(&dev
->bus_list
);
489 bus
->resource
[1] = res
;
490 bus
->resource
[0] = &(dino_dev
->hba
.io_space
);
492 /* Now tell dino what range it has */
493 for (i
= 1; i
< 31; i
++) {
494 if (res
->start
== F_EXTEND(0xf0000000UL
| (i
* _8MB
)))
497 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
498 i
, res
->start
, base_addr
+ DINO_IO_ADDR_EN
);
499 __raw_writel(1 << i
, base_addr
+ DINO_IO_ADDR_EN
);
503 dino_card_fixup(struct pci_dev
*dev
)
508 ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
509 ** Not sure they were ever productized.
510 ** Die here since we'll die later in dino_inb() anyway.
512 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
513 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
517 ** Set Latency Timer to 0xff (not a shared bus)
518 ** Set CACHELINE_SIZE.
520 dino_cfg_write(dev
->bus
, dev
->devfn
,
521 PCI_CACHE_LINE_SIZE
, 2, 0xff00 | L1_CACHE_BYTES
/4);
524 ** Program INT_LINE for card-mode devices.
525 ** The cards are hardwired according to this algorithm.
526 ** And it doesn't matter if PPB's are present or not since
527 ** the IRQ lines bypass the PPB.
529 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
530 ** The additional "-1" adjusts for skewing the IRQ<->slot.
532 dino_cfg_read(dev
->bus
, dev
->devfn
, PCI_INTERRUPT_PIN
, 1, &irq_pin
);
533 dev
->irq
= pci_swizzle_interrupt_pin(dev
, irq_pin
) - 1;
535 /* Shouldn't really need to do this but it's in case someone tries
536 ** to bypass PCI services and look at the card themselves.
538 dino_cfg_write(dev
->bus
, dev
->devfn
, PCI_INTERRUPT_LINE
, 1, dev
->irq
);
541 /* The alignment contraints for PCI bridges under dino */
542 #define DINO_BRIDGE_ALIGN 0x100000
546 dino_fixup_bus(struct pci_bus
*bus
)
549 struct dino_device
*dino_dev
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
551 DBG(KERN_WARNING
"%s(0x%px) bus %d platform_data 0x%px\n",
552 __func__
, bus
, bus
->busn_res
.start
,
553 bus
->bridge
->platform_data
);
555 /* Firmware doesn't set up card-mode dino, so we have to */
556 if (is_card_dino(&dino_dev
->hba
.dev
->id
)) {
557 dino_card_setup(bus
, dino_dev
->hba
.base_addr
);
558 } else if (bus
->parent
) {
561 pci_read_bridge_bases(bus
);
564 for(i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
565 if((bus
->self
->resource
[i
].flags
&
566 (IORESOURCE_IO
| IORESOURCE_MEM
)) == 0)
569 if(bus
->self
->resource
[i
].flags
& IORESOURCE_MEM
) {
570 /* There's a quirk to alignment of
571 * bridge memory resources: the start
572 * is the alignment and start-end is
573 * the size. However, firmware will
574 * have assigned start and end, so we
575 * need to take this into account */
576 bus
->self
->resource
[i
].end
= bus
->self
->resource
[i
].end
- bus
->self
->resource
[i
].start
+ DINO_BRIDGE_ALIGN
;
577 bus
->self
->resource
[i
].start
= DINO_BRIDGE_ALIGN
;
581 DBG("DEBUG %s assigning %d [%pR]\n",
582 dev_name(&bus
->self
->dev
), i
,
583 &bus
->self
->resource
[i
]);
584 WARN_ON(pci_assign_resource(bus
->self
, i
));
585 DBG("DEBUG %s after assign %d [%pR]\n",
586 dev_name(&bus
->self
->dev
), i
,
587 &bus
->self
->resource
[i
]);
592 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
593 if (is_card_dino(&dino_dev
->hba
.dev
->id
))
594 dino_card_fixup(dev
);
597 ** P2PB's only have 2 BARs, no IRQs.
598 ** I'd like to just ignore them for now.
600 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
601 pcibios_init_bridge(dev
);
605 /* null out the ROM resource if there is one (we don't
606 * care about an expansion rom on parisc, since it
607 * usually contains (x86) bios code) */
608 dev
->resource
[PCI_ROM_RESOURCE
].flags
= 0;
610 if(dev
->irq
== 255) {
612 #define DINO_FIX_UNASSIGNED_INTERRUPTS
613 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
615 /* This code tries to assign an unassigned
616 * interrupt. Leave it disabled unless you
617 * *really* know what you're doing since the
618 * pin<->interrupt line mapping varies by bus
623 dino_cfg_read(dev
->bus
, dev
->devfn
,
624 PCI_INTERRUPT_PIN
, 1, &irq_pin
);
625 irq_pin
= pci_swizzle_interrupt_pin(dev
, irq_pin
) - 1;
626 printk(KERN_WARNING
"Device %s has undefined IRQ, "
627 "setting to %d\n", pci_name(dev
), irq_pin
);
628 dino_cfg_write(dev
->bus
, dev
->devfn
,
629 PCI_INTERRUPT_LINE
, 1, irq_pin
);
630 dino_assign_irq(dino_dev
, irq_pin
, &dev
->irq
);
633 printk(KERN_WARNING
"Device %s has unassigned IRQ\n", pci_name(dev
));
636 /* Adjust INT_LINE for that busses region */
637 dino_assign_irq(dino_dev
, dev
->irq
, &dev
->irq
);
643 static struct pci_bios_ops dino_bios_ops
= {
644 .init
= dino_bios_init
,
645 .fixup_bus
= dino_fixup_bus
650 * Initialise a DINO controller chip
653 dino_card_init(struct dino_device
*dino_dev
)
655 u32 brdg_feat
= 0x00784e05;
656 unsigned long status
;
658 status
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_IO_STATUS
);
659 if (status
& 0x0000ff80) {
660 __raw_writel(0x00000005,
661 dino_dev
->hba
.base_addr
+DINO_IO_COMMAND
);
665 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_GMASK
);
666 __raw_writel(0x00000001, dino_dev
->hba
.base_addr
+DINO_IO_FBB_EN
);
667 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_ICR
);
670 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
672 ** PCX-L processors don't support XQL like Dino wants it.
673 ** PCX-L2 ignore XQL signal and it doesn't matter.
675 brdg_feat
&= ~0x4; /* UXQL */
677 __raw_writel( brdg_feat
, dino_dev
->hba
.base_addr
+DINO_BRDG_FEAT
);
680 ** Don't enable address decoding until we know which I/O range
681 ** currently is available from the host. Only affects MMIO
682 ** and not I/O port space.
684 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_IO_ADDR_EN
);
686 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_DAMODE
);
687 __raw_writel(0x00222222, dino_dev
->hba
.base_addr
+DINO_PCIROR
);
688 __raw_writel(0x00222222, dino_dev
->hba
.base_addr
+DINO_PCIWOR
);
690 __raw_writel(0x00000040, dino_dev
->hba
.base_addr
+DINO_MLTIM
);
691 __raw_writel(0x00000080, dino_dev
->hba
.base_addr
+DINO_IO_CONTROL
);
692 __raw_writel(0x0000008c, dino_dev
->hba
.base_addr
+DINO_TLTIM
);
694 /* Disable PAMR before writing PAPR */
695 __raw_writel(0x0000007e, dino_dev
->hba
.base_addr
+DINO_PAMR
);
696 __raw_writel(0x0000007f, dino_dev
->hba
.base_addr
+DINO_PAPR
);
697 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_PAMR
);
700 ** Dino ERS encourages enabling FBB (0x6f).
701 ** We can't until we know *all* devices below us can support it.
702 ** (Something in device configuration header tells us).
704 __raw_writel(0x0000004f, dino_dev
->hba
.base_addr
+DINO_PCICMD
);
706 /* Somewhere, the PCI spec says give devices 1 second
707 ** to recover from the #RESET being de-asserted.
708 ** Experience shows most devices only need 10ms.
709 ** This short-cut speeds up booting significantly.
711 mdelay(pci_post_reset_delay
);
715 dino_bridge_init(struct dino_device
*dino_dev
, const char *name
)
717 unsigned long io_addr
;
718 int result
, i
, count
=0;
719 struct resource
*res
, *prevres
= NULL
;
721 * Decoding IO_ADDR_EN only works for Built-in Dino
722 * since PDC has already initialized this.
725 io_addr
= __raw_readl(dino_dev
->hba
.base_addr
+ DINO_IO_ADDR_EN
);
727 printk(KERN_WARNING
"%s: No PCI devices enabled.\n", name
);
731 res
= &dino_dev
->hba
.lmmio_space
;
732 for (i
= 0; i
< 32; i
++) {
733 unsigned long start
, end
;
735 if((io_addr
& (1 << i
)) == 0)
738 start
= F_EXTEND(0xf0000000UL
) | (i
<< 23);
739 end
= start
+ 8 * 1024 * 1024 - 1;
741 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count
,
744 if(prevres
&& prevres
->end
+ 1 == start
) {
747 if(count
>= DINO_MAX_LMMIO_RESOURCES
) {
748 printk(KERN_ERR
"%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name
, count
, start
, end
);
754 res
->flags
= IORESOURCE_MEM
;
755 res
->name
= kmalloc(64, GFP_KERNEL
);
757 snprintf((char *)res
->name
, 64, "%s LMMIO %d",
764 res
= &dino_dev
->hba
.lmmio_space
;
766 for(i
= 0; i
< DINO_MAX_LMMIO_RESOURCES
; i
++) {
767 if(res
[i
].flags
== 0)
770 result
= ccio_request_resource(dino_dev
->hba
.dev
, &res
[i
]);
772 printk(KERN_ERR
"%s: failed to claim PCI Bus address "
773 "space %d (%pR)!\n", name
, i
, &res
[i
]);
780 static int __init
dino_common_init(struct parisc_device
*dev
,
781 struct dino_device
*dino_dev
, const char *name
)
785 struct gsc_irq gsc_irq
;
786 struct resource
*res
;
788 pcibios_register_hba(&dino_dev
->hba
);
790 pci_bios
= &dino_bios_ops
; /* used by pci_scan_bus() */
791 pci_port
= &dino_port_ops
;
794 ** Note: SMP systems can make use of IRR1/IAR1 registers
795 ** But it won't buy much performance except in very
796 ** specific applications/configurations. Note Dino
797 ** still only has 11 IRQ input lines - just map some of them
798 ** to a different processor.
800 dev
->irq
= gsc_alloc_irq(&gsc_irq
);
801 dino_dev
->txn_addr
= gsc_irq
.txn_addr
;
802 dino_dev
->txn_data
= gsc_irq
.txn_data
;
803 eim
= ((u32
) gsc_irq
.txn_addr
) | gsc_irq
.txn_data
;
806 ** Dino needs a PA "IRQ" to get a processor's attention.
807 ** arch/parisc/kernel/irq.c returns an EIRR bit.
810 printk(KERN_WARNING
"%s: gsc_alloc_irq() failed\n", name
);
814 status
= request_irq(dev
->irq
, dino_isr
, 0, name
, dino_dev
);
816 printk(KERN_WARNING
"%s: request_irq() failed with %d\n",
821 /* Support the serial port which is sometimes attached on built-in
825 gsc_fixup_irqs(dev
, dino_dev
, dino_choose_irq
);
828 ** This enables DINO to generate interrupts when it sees
829 ** any of its inputs *change*. Just asserting an IRQ
830 ** before it's enabled (ie unmasked) isn't good enough.
832 __raw_writel(eim
, dino_dev
->hba
.base_addr
+DINO_IAR0
);
835 ** Some platforms don't clear Dino's IRR0 register at boot time.
836 ** Reading will clear it now.
838 __raw_readl(dino_dev
->hba
.base_addr
+DINO_IRR0
);
840 /* allocate I/O Port resource region */
841 res
= &dino_dev
->hba
.io_space
;
842 if (!is_cujo(&dev
->id
)) {
843 res
->name
= "Dino I/O Port";
845 res
->name
= "Cujo I/O Port";
847 res
->start
= HBA_PORT_BASE(dino_dev
->hba
.hba_num
);
848 res
->end
= res
->start
+ (HBA_PORT_SPACE_SIZE
- 1);
849 res
->flags
= IORESOURCE_IO
; /* do not mark it busy ! */
850 if (request_resource(&ioport_resource
, res
) < 0) {
851 printk(KERN_ERR
"%s: request I/O Port region failed "
852 "0x%lx/%lx (hpa 0x%px)\n",
853 name
, (unsigned long)res
->start
, (unsigned long)res
->end
,
854 dino_dev
->hba
.base_addr
);
861 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL)
862 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL)
863 #define CUJO_RAVEN_BADPAGE 0x01003000UL
864 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL
866 static const char *dino_vers
[] = {
873 static const char *cujo_vers
[] = {
878 void ccio_cujo20_fixup(struct parisc_device
*dev
, u32 iovp
);
881 ** Determine if dino should claim this chip (return 0) or not (return 1).
882 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
883 ** Much of the initialization is common though.
885 static int __init
dino_probe(struct parisc_device
*dev
)
887 struct dino_device
*dino_dev
; // Dino specific control struct
888 const char *version
= "unknown";
891 LIST_HEAD(resources
);
893 unsigned long hpa
= dev
->hpa
.start
;
897 if (is_card_dino(&dev
->id
)) {
898 version
= "3.x (card mode)";
900 if (!is_cujo(&dev
->id
)) {
901 if (dev
->id
.hversion_rev
< 4) {
902 version
= dino_vers
[dev
->id
.hversion_rev
];
907 if (dev
->id
.hversion_rev
< 2) {
908 version
= cujo_vers
[dev
->id
.hversion_rev
];
913 printk("%s version %s found at 0x%lx\n", name
, version
, hpa
);
915 if (!request_mem_region(hpa
, PAGE_SIZE
, name
)) {
916 printk(KERN_ERR
"DINO: Hey! Someone took my MMIO space (0x%lx)!\n",
922 if (is_cujo
&& dev
->id
.hversion_rev
== 1) {
923 #ifdef CONFIG_IOMMU_CCIO
924 printk(KERN_WARNING
"Enabling Cujo 2.0 bug workaround\n");
925 if (hpa
== (unsigned long)CUJO_RAVEN_ADDR
) {
926 ccio_cujo20_fixup(dev
, CUJO_RAVEN_BADPAGE
);
927 } else if (hpa
== (unsigned long)CUJO_FIREHAWK_ADDR
) {
928 ccio_cujo20_fixup(dev
, CUJO_FIREHAWK_BADPAGE
);
930 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa
);
933 } else if (!is_cujo
&& !is_card_dino(&dev
->id
) &&
934 dev
->id
.hversion_rev
< 3) {
936 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
937 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
938 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
939 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
940 dev
->id
.hversion_rev
);
941 /* REVISIT: why are C200/C240 listed in the README table but not
942 ** "Models affected"? Could be an omission in the original literature.
946 dino_dev
= kzalloc(sizeof(struct dino_device
), GFP_KERNEL
);
948 printk("dino_init_chip - couldn't alloc dino_device\n");
952 dino_dev
->hba
.dev
= dev
;
953 dino_dev
->hba
.base_addr
= ioremap_nocache(hpa
, 4096);
954 dino_dev
->hba
.lmmio_space_offset
= PCI_F_EXTEND
;
955 spin_lock_init(&dino_dev
->dinosaur_pen
);
956 dino_dev
->hba
.iommu
= ccio_get_iommu(dev
);
958 if (is_card_dino(&dev
->id
)) {
959 dino_card_init(dino_dev
);
961 dino_bridge_init(dino_dev
, name
);
964 if (dino_common_init(dev
, dino_dev
, name
))
967 dev
->dev
.platform_data
= dino_dev
;
969 pci_add_resource_offset(&resources
, &dino_dev
->hba
.io_space
,
970 HBA_PORT_BASE(dino_dev
->hba
.hba_num
));
971 if (dino_dev
->hba
.lmmio_space
.flags
)
972 pci_add_resource_offset(&resources
, &dino_dev
->hba
.lmmio_space
,
973 dino_dev
->hba
.lmmio_space_offset
);
974 if (dino_dev
->hba
.elmmio_space
.flags
)
975 pci_add_resource_offset(&resources
, &dino_dev
->hba
.elmmio_space
,
976 dino_dev
->hba
.lmmio_space_offset
);
977 if (dino_dev
->hba
.gmmio_space
.flags
)
978 pci_add_resource(&resources
, &dino_dev
->hba
.gmmio_space
);
980 dino_dev
->hba
.bus_num
.start
= dino_current_bus
;
981 dino_dev
->hba
.bus_num
.end
= 255;
982 dino_dev
->hba
.bus_num
.flags
= IORESOURCE_BUS
;
983 pci_add_resource(&resources
, &dino_dev
->hba
.bus_num
);
985 ** It's not used to avoid chicken/egg problems
986 ** with configuration accessor functions.
988 dino_dev
->hba
.hba_bus
= bus
= pci_create_root_bus(&dev
->dev
,
989 dino_current_bus
, &dino_cfg_ops
, NULL
, &resources
);
991 printk(KERN_ERR
"ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
992 dev_name(&dev
->dev
), dino_current_bus
);
993 pci_free_resource_list(&resources
);
994 /* increment the bus number in case of duplicates */
999 max
= pci_scan_child_bus(bus
);
1000 pci_bus_update_busn_res_end(bus
, max
);
1002 /* This code *depends* on scanning being single threaded
1003 * if it isn't, this global bus number count will fail
1005 dino_current_bus
= max
+ 1;
1006 pci_bus_assign_resources(bus
);
1007 pci_bus_add_devices(bus
);
1012 * Normally, we would just test sversion. But the Elroy PCI adapter has
1013 * the same sversion as Dino, so we have to check hversion as well.
1014 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1015 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1016 * For card-mode Dino, most machines report an sversion of 9D. But 715
1017 * and 725 firmware misreport it as 0x08080 for no adequately explained
1020 static const struct parisc_device_id dino_tbl
[] __initconst
= {
1021 { HPHW_A_DMA
, HVERSION_REV_ANY_ID
, 0x004, 0x0009D },/* Card-mode Dino */
1022 { HPHW_A_DMA
, HVERSION_REV_ANY_ID
, HVERSION_ANY_ID
, 0x08080 }, /* XXX */
1023 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, 0x680, 0xa }, /* Bridge-mode Dino */
1024 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, 0x682, 0xa }, /* Bridge-mode Cujo */
1025 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, 0x05d, 0xa }, /* Dino in a J2240 */
1029 static struct parisc_driver dino_driver __refdata
= {
1031 .id_table
= dino_tbl
,
1032 .probe
= dino_probe
,
1036 * One time initialization to let the world know Dino is here.
1037 * This is the only routine which is NOT static.
1038 * Must be called exactly once before pci_init().
1040 int __init
dino_init(void)
1042 register_parisc_driver(&dino_driver
);