2 ** System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6 ** (c) Copyright 2000-2004 Hewlett-Packard Company
8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17 ** J5000/J7000/N-class/L-class machines and their successors.
19 ** FIXME: add DMA hint support programming in both sba and lba modules.
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
29 #include <linux/string.h>
30 #include <linux/pci.h>
31 #include <linux/scatterlist.h>
32 #include <linux/iommu-helper.h>
34 #include <asm/byteorder.h>
36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
40 #include <linux/proc_fs.h>
41 #include <linux/seq_file.h>
42 #include <linux/module.h>
44 #include <asm/ropes.h>
45 #include <asm/mckinley.h> /* for proc_mckinley_root */
46 #include <asm/runway.h> /* for proc_runway_root */
47 #include <asm/page.h> /* for PAGE0 */
48 #include <asm/pdc.h> /* for PDC_MODEL_* */
49 #include <asm/pdcpat.h> /* for is_pdc_pat() */
50 #include <asm/parisc-device.h>
52 #define MODULE_NAME "SBA"
55 ** The number of debug flags is a clue - this code is fragile.
56 ** Don't even think about messing with it unless you have
57 ** plenty of 710's to sacrifice to the computer gods. :^)
61 #undef DEBUG_SBA_RUN_SG
62 #undef DEBUG_SBA_RESOURCE
63 #undef ASSERT_PDIR_SANITY
64 #undef DEBUG_LARGE_SG_ENTRIES
68 #define DBG_INIT(x...) printk(x)
70 #define DBG_INIT(x...)
74 #define DBG_RUN(x...) printk(x)
79 #ifdef DEBUG_SBA_RUN_SG
80 #define DBG_RUN_SG(x...) printk(x)
82 #define DBG_RUN_SG(x...)
86 #ifdef DEBUG_SBA_RESOURCE
87 #define DBG_RES(x...) printk(x)
92 #define SBA_INLINE __inline__
94 #define DEFAULT_DMA_HINT_REG 0
96 struct sba_device
*sba_list
;
97 EXPORT_SYMBOL_GPL(sba_list
);
99 static unsigned long ioc_needs_fdc
= 0;
101 /* global count of IOMMUs in the system */
102 static unsigned int global_ioc_cnt
= 0;
104 /* PA8700 (Piranha 2.2) bug workaround */
105 static unsigned long piranha_bad_128k
= 0;
107 /* Looks nice and keeps the compiler happy */
108 #define SBA_DEV(d) ((struct sba_device *) (d))
110 #ifdef CONFIG_AGP_PARISC
111 #define SBA_AGP_SUPPORT
112 #endif /*CONFIG_AGP_PARISC*/
114 #ifdef SBA_AGP_SUPPORT
115 static int sba_reserve_agpgart
= 1;
116 module_param(sba_reserve_agpgart
, int, 0444);
117 MODULE_PARM_DESC(sba_reserve_agpgart
, "Reserve half of IO pdir as AGPGART");
121 /************************************
122 ** SBA register read and write support
124 ** BE WARNED: register writes are posted.
125 ** (ie follow writes which must reach HW with a read)
127 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
129 #define READ_REG32(addr) readl(addr)
130 #define READ_REG64(addr) readq(addr)
131 #define WRITE_REG32(val, addr) writel((val), (addr))
132 #define WRITE_REG64(val, addr) writeq((val), (addr))
135 #define READ_REG(addr) READ_REG64(addr)
136 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
138 #define READ_REG(addr) READ_REG32(addr)
139 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
142 #ifdef DEBUG_SBA_INIT
144 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
147 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
148 * @hpa: base address of the sba
150 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
151 * IO Adapter (aka Bus Converter).
154 sba_dump_ranges(void __iomem
*hpa
)
156 DBG_INIT("SBA at 0x%p\n", hpa
);
157 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa
+IOS_DIST_BASE
));
158 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa
+IOS_DIST_MASK
));
159 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa
+IOS_DIST_ROUTE
));
161 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa
+IOS_DIRECT_BASE
));
162 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa
+IOS_DIRECT_MASK
));
163 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa
+IOS_DIRECT_ROUTE
));
167 * sba_dump_tlb - debugging only - print IOMMU operating parameters
168 * @hpa: base address of the IOMMU
170 * Print the size/location of the IO MMU PDIR.
172 static void sba_dump_tlb(void __iomem
*hpa
)
174 DBG_INIT("IO TLB at 0x%p\n", hpa
);
175 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa
+IOC_IBASE
));
176 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa
+IOC_IMASK
));
177 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa
+IOC_TCNFG
));
178 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa
+IOC_PDIR_BASE
));
182 #define sba_dump_ranges(x)
183 #define sba_dump_tlb(x)
184 #endif /* DEBUG_SBA_INIT */
187 #ifdef ASSERT_PDIR_SANITY
190 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
191 * @ioc: IO MMU structure which owns the pdir we are interested in.
192 * @msg: text to print ont the output line.
195 * Print one entry of the IO MMU PDIR in human readable form.
198 sba_dump_pdir_entry(struct ioc
*ioc
, char *msg
, uint pide
)
200 /* start printing from lowest pde in rval */
201 u64
*ptr
= &(ioc
->pdir_base
[pide
& (~0U * BITS_PER_LONG
)]);
202 unsigned long *rptr
= (unsigned long *) &(ioc
->res_map
[(pide
>>3) & ~(sizeof(unsigned long) - 1)]);
205 printk(KERN_DEBUG
"SBA: %s rp %p bit %d rval 0x%lx\n",
207 rptr
, pide
& (BITS_PER_LONG
- 1), *rptr
);
210 while (rcnt
< BITS_PER_LONG
) {
211 printk(KERN_DEBUG
"%s %2d %p %016Lx\n",
212 (rcnt
== (pide
& (BITS_PER_LONG
- 1)))
218 printk(KERN_DEBUG
"%s", msg
);
223 * sba_check_pdir - debugging only - consistency checker
224 * @ioc: IO MMU structure which owns the pdir we are interested in.
225 * @msg: text to print ont the output line.
227 * Verify the resource map and pdir state is consistent
230 sba_check_pdir(struct ioc
*ioc
, char *msg
)
232 u32
*rptr_end
= (u32
*) &(ioc
->res_map
[ioc
->res_size
]);
233 u32
*rptr
= (u32
*) ioc
->res_map
; /* resource map ptr */
234 u64
*pptr
= ioc
->pdir_base
; /* pdir ptr */
237 while (rptr
< rptr_end
) {
239 int rcnt
= 32; /* number of bits we might check */
242 /* Get last byte and highest bit from that */
243 u32 pde
= ((u32
) (((char *)pptr
)[7])) << 24;
244 if ((rval
^ pde
) & 0x80000000)
247 ** BUMMER! -- res_map != pdir --
248 ** Dump rval and matching pdir entries
250 sba_dump_pdir_entry(ioc
, msg
, pide
);
254 rval
<<= 1; /* try the next bit */
258 rptr
++; /* look at next word of res_map */
260 /* It'd be nice if we always got here :^) */
266 * sba_dump_sg - debugging only - print Scatter-Gather list
267 * @ioc: IO MMU structure which owns the pdir we are interested in.
268 * @startsg: head of the SG list
269 * @nents: number of entries in SG list
271 * print the SG list so we can verify it's correct by hand.
274 sba_dump_sg( struct ioc
*ioc
, struct scatterlist
*startsg
, int nents
)
276 while (nents
-- > 0) {
277 printk(KERN_DEBUG
" %d : %08lx/%05x %p/%05x\n",
279 (unsigned long) sg_dma_address(startsg
),
281 sg_virt(startsg
), startsg
->length
);
286 #endif /* ASSERT_PDIR_SANITY */
291 /**************************************************************
293 * I/O Pdir Resource Management
295 * Bits set in the resource map are in use.
296 * Each bit can represent a number of pages.
297 * LSbs represent lower addresses (IOVA's).
299 ***************************************************************/
300 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
302 /* Convert from IOVP to IOVA and vice versa. */
305 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
306 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
307 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
309 /* only support Astro and ancestors. Saves a few cycles in key places */
310 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
311 #define SBA_IOVP(ioc,iova) (iova)
314 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
316 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
317 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
319 static unsigned long ptr_to_pide(struct ioc
*ioc
, unsigned long *res_ptr
,
320 unsigned int bitshiftcnt
)
322 return (((unsigned long)res_ptr
- (unsigned long)ioc
->res_map
) << 3)
327 * sba_search_bitmap - find free space in IO PDIR resource bitmap
328 * @ioc: IO MMU structure which owns the pdir we are interested in.
329 * @bits_wanted: number of entries we need.
331 * Find consecutive free bits in resource bitmap.
332 * Each bit represents one entry in the IO Pdir.
333 * Cool perf optimization: search for log2(size) bits at a time.
335 static SBA_INLINE
unsigned long
336 sba_search_bitmap(struct ioc
*ioc
, struct device
*dev
,
337 unsigned long bits_wanted
)
339 unsigned long *res_ptr
= ioc
->res_hint
;
340 unsigned long *res_end
= (unsigned long *) &(ioc
->res_map
[ioc
->res_size
]);
341 unsigned long pide
= ~0UL, tpide
;
342 unsigned long boundary_size
;
346 boundary_size
= ALIGN((unsigned long long)dma_get_seg_boundary(dev
) + 1,
347 1ULL << IOVP_SHIFT
) >> IOVP_SHIFT
;
349 #if defined(ZX1_SUPPORT)
350 BUG_ON(ioc
->ibase
& ~IOVP_MASK
);
351 shift
= ioc
->ibase
>> IOVP_SHIFT
;
356 if (bits_wanted
> (BITS_PER_LONG
/2)) {
357 /* Search word at a time - no mask needed */
358 for(; res_ptr
< res_end
; ++res_ptr
) {
359 tpide
= ptr_to_pide(ioc
, res_ptr
, 0);
360 ret
= iommu_is_span_boundary(tpide
, bits_wanted
,
363 if ((*res_ptr
== 0) && !ret
) {
364 *res_ptr
= RESMAP_MASK(bits_wanted
);
369 /* point to the next word on next pass */
371 ioc
->res_bitshift
= 0;
374 ** Search the resource bit map on well-aligned values.
375 ** "o" is the alignment.
376 ** We need the alignment to invalidate I/O TLB using
377 ** SBA HW features in the unmap path.
379 unsigned long o
= 1 << get_order(bits_wanted
<< PAGE_SHIFT
);
380 uint bitshiftcnt
= ALIGN(ioc
->res_bitshift
, o
);
383 if (bitshiftcnt
>= BITS_PER_LONG
) {
387 mask
= RESMAP_MASK(bits_wanted
) >> bitshiftcnt
;
389 DBG_RES("%s() o %ld %p", __func__
, o
, res_ptr
);
390 while(res_ptr
< res_end
)
392 DBG_RES(" %p %lx %lx\n", res_ptr
, mask
, *res_ptr
);
394 tpide
= ptr_to_pide(ioc
, res_ptr
, bitshiftcnt
);
395 ret
= iommu_is_span_boundary(tpide
, bits_wanted
,
398 if ((((*res_ptr
) & mask
) == 0) && !ret
) {
399 *res_ptr
|= mask
; /* mark resources busy! */
406 mask
= RESMAP_MASK(bits_wanted
);
411 /* look in the same word on the next pass */
412 ioc
->res_bitshift
= bitshiftcnt
+ bits_wanted
;
416 if (res_end
<= res_ptr
) {
417 ioc
->res_hint
= (unsigned long *) ioc
->res_map
;
418 ioc
->res_bitshift
= 0;
420 ioc
->res_hint
= res_ptr
;
427 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
428 * @ioc: IO MMU structure which owns the pdir we are interested in.
429 * @size: number of bytes to create a mapping for
431 * Given a size, find consecutive unmarked and then mark those bits in the
435 sba_alloc_range(struct ioc
*ioc
, struct device
*dev
, size_t size
)
437 unsigned int pages_needed
= size
>> IOVP_SHIFT
;
438 #ifdef SBA_COLLECT_STATS
439 unsigned long cr_start
= mfctl(16);
443 pide
= sba_search_bitmap(ioc
, dev
, pages_needed
);
444 if (pide
>= (ioc
->res_size
<< 3)) {
445 pide
= sba_search_bitmap(ioc
, dev
, pages_needed
);
446 if (pide
>= (ioc
->res_size
<< 3))
447 panic("%s: I/O MMU @ %p is out of mapping resources\n",
448 __FILE__
, ioc
->ioc_hpa
);
451 #ifdef ASSERT_PDIR_SANITY
452 /* verify the first enable bit is clear */
453 if(0x00 != ((u8
*) ioc
->pdir_base
)[pide
*sizeof(u64
) + 7]) {
454 sba_dump_pdir_entry(ioc
, "sba_search_bitmap() botched it?", pide
);
458 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
459 __func__
, size
, pages_needed
, pide
,
460 (uint
) ((unsigned long) ioc
->res_hint
- (unsigned long) ioc
->res_map
),
463 #ifdef SBA_COLLECT_STATS
465 unsigned long cr_end
= mfctl(16);
466 unsigned long tmp
= cr_end
- cr_start
;
467 /* check for roll over */
468 cr_start
= (cr_end
< cr_start
) ? -(tmp
) : (tmp
);
470 ioc
->avg_search
[ioc
->avg_idx
++] = cr_start
;
471 ioc
->avg_idx
&= SBA_SEARCH_SAMPLE
- 1;
473 ioc
->used_pages
+= pages_needed
;
481 * sba_free_range - unmark bits in IO PDIR resource bitmap
482 * @ioc: IO MMU structure which owns the pdir we are interested in.
483 * @iova: IO virtual address which was previously allocated.
484 * @size: number of bytes to create a mapping for
486 * clear bits in the ioc's resource map
488 static SBA_INLINE
void
489 sba_free_range(struct ioc
*ioc
, dma_addr_t iova
, size_t size
)
491 unsigned long iovp
= SBA_IOVP(ioc
, iova
);
492 unsigned int pide
= PDIR_INDEX(iovp
);
493 unsigned int ridx
= pide
>> 3; /* convert bit to byte address */
494 unsigned long *res_ptr
= (unsigned long *) &((ioc
)->res_map
[ridx
& ~RESMAP_IDX_MASK
]);
496 int bits_not_wanted
= size
>> IOVP_SHIFT
;
498 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
499 unsigned long m
= RESMAP_MASK(bits_not_wanted
) >> (pide
& (BITS_PER_LONG
- 1));
501 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
502 __func__
, (uint
) iova
, size
,
503 bits_not_wanted
, m
, pide
, res_ptr
, *res_ptr
);
505 #ifdef SBA_COLLECT_STATS
506 ioc
->used_pages
-= bits_not_wanted
;
513 /**************************************************************
515 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
517 ***************************************************************/
519 #ifdef SBA_HINT_SUPPORT
520 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
523 typedef unsigned long space_t
;
524 #define KERNEL_SPACE 0
527 * sba_io_pdir_entry - fill in one IO PDIR entry
528 * @pdir_ptr: pointer to IO PDIR entry
529 * @sid: process Space ID - currently only support KERNEL_SPACE
530 * @vba: Virtual CPU address of buffer to map
531 * @hint: DMA hint set to use for this mapping
533 * SBA Mapping Routine
535 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
536 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
538 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
539 * for Astro/Ike looks like:
543 * +-+---------------------+----------------------------------+----+--------+
544 * |V| U | PPN[43:12] | U | VI |
545 * +-+---------------------+----------------------------------+----+--------+
547 * Pluto is basically identical, supports fewer physical address bits:
550 * +-+------------------------+-------------------------------+----+--------+
551 * |V| U | PPN[39:12] | U | VI |
552 * +-+------------------------+-------------------------------+----+--------+
554 * V == Valid Bit (Most Significant Bit is bit 0)
556 * PPN == Physical Page Number
557 * VI == Virtual Index (aka Coherent Index)
559 * LPA instruction output is put into PPN field.
560 * LCI (Load Coherence Index) instruction provides the "VI" bits.
562 * We pre-swap the bytes since PCX-W is Big Endian and the
563 * IOMMU uses little endian for the pdir.
566 static void SBA_INLINE
567 sba_io_pdir_entry(u64
*pdir_ptr
, space_t sid
, unsigned long vba
,
570 u64 pa
; /* physical address */
571 register unsigned ci
; /* coherent index */
573 pa
= virt_to_phys(vba
);
577 asm("lci 0(%%sr1, %1), %0" : "=r" (ci
) : "r" (vba
));
578 pa
|= (ci
>> PAGE_SHIFT
) & 0xff; /* move CI (8 bits) into lowest byte */
580 pa
|= SBA_PDIR_VALID_BIT
; /* set "valid" bit */
581 *pdir_ptr
= cpu_to_le64(pa
); /* swap and store into I/O Pdir */
584 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
585 * (bit #61, big endian), we have to flush and sync every time
586 * IO-PDIR is changed in Ike/Astro.
588 asm_io_fdc(pdir_ptr
);
593 * sba_mark_invalid - invalidate one or more IO PDIR entries
594 * @ioc: IO MMU structure which owns the pdir we are interested in.
595 * @iova: IO Virtual Address mapped earlier
596 * @byte_cnt: number of bytes this mapping covers.
598 * Marking the IO PDIR entry(ies) as Invalid and invalidate
599 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
600 * is to purge stale entries in the IO TLB when unmapping entries.
602 * The PCOM register supports purging of multiple pages, with a minium
603 * of 1 page and a maximum of 2GB. Hardware requires the address be
604 * aligned to the size of the range being purged. The size of the range
605 * must be a power of 2. The "Cool perf optimization" in the
606 * allocation routine helps keep that true.
608 static SBA_INLINE
void
609 sba_mark_invalid(struct ioc
*ioc
, dma_addr_t iova
, size_t byte_cnt
)
611 u32 iovp
= (u32
) SBA_IOVP(ioc
,iova
);
612 u64
*pdir_ptr
= &ioc
->pdir_base
[PDIR_INDEX(iovp
)];
614 #ifdef ASSERT_PDIR_SANITY
615 /* Assert first pdir entry is set.
617 ** Even though this is a big-endian machine, the entries
618 ** in the iopdir are little endian. That's why we look at
619 ** the byte at +7 instead of at +0.
621 if (0x80 != (((u8
*) pdir_ptr
)[7])) {
622 sba_dump_pdir_entry(ioc
,"sba_mark_invalid()", PDIR_INDEX(iovp
));
626 if (byte_cnt
> IOVP_SIZE
)
629 unsigned long entries_per_cacheline
= ioc_needs_fdc
?
630 L1_CACHE_ALIGN(((unsigned long) pdir_ptr
))
631 - (unsigned long) pdir_ptr
;
635 /* set "size" field for PCOM */
636 iovp
|= get_order(byte_cnt
) + PAGE_SHIFT
;
639 /* clear I/O Pdir entry "valid" bit first */
640 ((u8
*) pdir_ptr
)[7] = 0;
641 asm_io_fdc(pdir_ptr
);
644 entries_per_cacheline
= L1_CACHE_SHIFT
- 3;
648 byte_cnt
-= IOVP_SIZE
;
649 } while (byte_cnt
> IOVP_SIZE
);
651 iovp
|= IOVP_SHIFT
; /* set "size" field for PCOM */
654 ** clear I/O PDIR entry "valid" bit.
655 ** We have to R/M/W the cacheline regardless how much of the
656 ** pdir entry that we clobber.
657 ** The rest of the entry would be useful for debugging if we
658 ** could dump core on HPMC.
660 ((u8
*) pdir_ptr
)[7] = 0;
661 asm_io_fdc(pdir_ptr
);
663 WRITE_REG( SBA_IOVA(ioc
, iovp
, 0, 0), ioc
->ioc_hpa
+IOC_PCOM
);
667 * sba_dma_supported - PCI driver can query DMA support
668 * @dev: instance of PCI owned by the driver that's asking
669 * @mask: number of address bits this PCI device can handle
671 * See Documentation/DMA-API-HOWTO.txt
673 static int sba_dma_supported( struct device
*dev
, u64 mask
)
678 printk(KERN_ERR MODULE_NAME
": EISA/ISA/et al not supported\n");
683 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit
684 * first, then fall back to 32-bit if that fails.
685 * We are just "encouraging" 32-bit DMA masks here since we can
686 * never allow IOMMU bypass unless we add special support for ZX1.
696 * check if mask is >= than the current max IO Virt Address
697 * The max IO Virt address will *always* < 30 bits.
699 return((int)(mask
>= (ioc
->ibase
- 1 +
700 (ioc
->pdir_size
/ sizeof(u64
) * IOVP_SIZE
) )));
705 * sba_map_single - map one buffer and return IOVA for DMA
706 * @dev: instance of PCI owned by the driver that's asking.
707 * @addr: driver buffer to map.
708 * @size: number of bytes to map in driver buffer.
709 * @direction: R/W or both.
711 * See Documentation/DMA-API-HOWTO.txt
714 sba_map_single(struct device
*dev
, void *addr
, size_t size
,
715 enum dma_data_direction direction
)
726 return DMA_MAPPING_ERROR
;
728 /* save offset bits */
729 offset
= ((dma_addr_t
) (long) addr
) & ~IOVP_MASK
;
731 /* round up to nearest IOVP_SIZE */
732 size
= (size
+ offset
+ ~IOVP_MASK
) & IOVP_MASK
;
734 spin_lock_irqsave(&ioc
->res_lock
, flags
);
735 #ifdef ASSERT_PDIR_SANITY
736 sba_check_pdir(ioc
,"Check before sba_map_single()");
739 #ifdef SBA_COLLECT_STATS
740 ioc
->msingle_calls
++;
741 ioc
->msingle_pages
+= size
>> IOVP_SHIFT
;
743 pide
= sba_alloc_range(ioc
, dev
, size
);
744 iovp
= (dma_addr_t
) pide
<< IOVP_SHIFT
;
746 DBG_RUN("%s() 0x%p -> 0x%lx\n",
747 __func__
, addr
, (long) iovp
| offset
);
749 pdir_start
= &(ioc
->pdir_base
[pide
]);
752 sba_io_pdir_entry(pdir_start
, KERNEL_SPACE
, (unsigned long) addr
, 0);
754 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
756 (u8
) (((u8
*) pdir_start
)[7]),
757 (u8
) (((u8
*) pdir_start
)[6]),
758 (u8
) (((u8
*) pdir_start
)[5]),
759 (u8
) (((u8
*) pdir_start
)[4]),
760 (u8
) (((u8
*) pdir_start
)[3]),
761 (u8
) (((u8
*) pdir_start
)[2]),
762 (u8
) (((u8
*) pdir_start
)[1]),
763 (u8
) (((u8
*) pdir_start
)[0])
771 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
774 #ifdef ASSERT_PDIR_SANITY
775 sba_check_pdir(ioc
,"Check after sba_map_single()");
777 spin_unlock_irqrestore(&ioc
->res_lock
, flags
);
779 /* form complete address */
780 return SBA_IOVA(ioc
, iovp
, offset
, DEFAULT_DMA_HINT_REG
);
785 sba_map_page(struct device
*dev
, struct page
*page
, unsigned long offset
,
786 size_t size
, enum dma_data_direction direction
,
789 return sba_map_single(dev
, page_address(page
) + offset
, size
,
795 * sba_unmap_page - unmap one IOVA and free resources
796 * @dev: instance of PCI owned by the driver that's asking.
797 * @iova: IOVA of driver buffer previously mapped.
798 * @size: number of bytes mapped in driver buffer.
799 * @direction: R/W or both.
801 * See Documentation/DMA-API-HOWTO.txt
804 sba_unmap_page(struct device
*dev
, dma_addr_t iova
, size_t size
,
805 enum dma_data_direction direction
, unsigned long attrs
)
808 #if DELAYED_RESOURCE_CNT > 0
809 struct sba_dma_pair
*d
;
814 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__
, (long) iova
, size
);
821 offset
= iova
& ~IOVP_MASK
;
822 iova
^= offset
; /* clear offset bits */
824 size
= ALIGN(size
, IOVP_SIZE
);
826 spin_lock_irqsave(&ioc
->res_lock
, flags
);
828 #ifdef SBA_COLLECT_STATS
829 ioc
->usingle_calls
++;
830 ioc
->usingle_pages
+= size
>> IOVP_SHIFT
;
833 sba_mark_invalid(ioc
, iova
, size
);
835 #if DELAYED_RESOURCE_CNT > 0
836 /* Delaying when we re-use a IO Pdir entry reduces the number
837 * of MMIO reads needed to flush writes to the PCOM register.
839 d
= &(ioc
->saved
[ioc
->saved_cnt
]);
842 if (++(ioc
->saved_cnt
) >= DELAYED_RESOURCE_CNT
) {
843 int cnt
= ioc
->saved_cnt
;
845 sba_free_range(ioc
, d
->iova
, d
->size
);
850 READ_REG(ioc
->ioc_hpa
+IOC_PCOM
); /* flush purges */
852 #else /* DELAYED_RESOURCE_CNT == 0 */
853 sba_free_range(ioc
, iova
, size
);
855 /* If fdc's were issued, force fdc's to be visible now */
858 READ_REG(ioc
->ioc_hpa
+IOC_PCOM
); /* flush purges */
859 #endif /* DELAYED_RESOURCE_CNT == 0 */
861 spin_unlock_irqrestore(&ioc
->res_lock
, flags
);
863 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
864 ** For Astro based systems this isn't a big deal WRT performance.
865 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
866 ** we don't need the syncdma. The issue here is I/O MMU cachelines
867 ** are *not* coherent in all cases. May be hwrev dependent.
868 ** Need to investigate more.
869 asm volatile("syncdma");
875 * sba_alloc - allocate/map shared mem for DMA
876 * @hwdev: instance of PCI owned by the driver that's asking.
877 * @size: number of bytes mapped in driver buffer.
878 * @dma_handle: IOVA of new buffer.
880 * See Documentation/DMA-API-HOWTO.txt
882 static void *sba_alloc(struct device
*hwdev
, size_t size
, dma_addr_t
*dma_handle
,
883 gfp_t gfp
, unsigned long attrs
)
888 /* only support PCI */
893 ret
= (void *) __get_free_pages(gfp
, get_order(size
));
896 memset(ret
, 0, size
);
897 *dma_handle
= sba_map_single(hwdev
, ret
, size
, 0);
905 * sba_free - free/unmap shared mem for DMA
906 * @hwdev: instance of PCI owned by the driver that's asking.
907 * @size: number of bytes mapped in driver buffer.
908 * @vaddr: virtual address IOVA of "consistent" buffer.
909 * @dma_handler: IO virtual address of "consistent" buffer.
911 * See Documentation/DMA-API-HOWTO.txt
914 sba_free(struct device
*hwdev
, size_t size
, void *vaddr
,
915 dma_addr_t dma_handle
, unsigned long attrs
)
917 sba_unmap_page(hwdev
, dma_handle
, size
, 0, 0);
918 free_pages((unsigned long) vaddr
, get_order(size
));
923 ** Since 0 is a valid pdir_base index value, can't use that
924 ** to determine if a value is valid or not. Use a flag to indicate
925 ** the SG list entry contains a valid pdir index.
927 #define PIDE_FLAG 0x80000000UL
929 #ifdef SBA_COLLECT_STATS
930 #define IOMMU_MAP_STATS
932 #include "iommu-helpers.h"
934 #ifdef DEBUG_LARGE_SG_ENTRIES
940 * sba_map_sg - map Scatter/Gather list
941 * @dev: instance of PCI owned by the driver that's asking.
942 * @sglist: array of buffer/length pairs
943 * @nents: number of entries in list
944 * @direction: R/W or both.
946 * See Documentation/DMA-API-HOWTO.txt
949 sba_map_sg(struct device
*dev
, struct scatterlist
*sglist
, int nents
,
950 enum dma_data_direction direction
, unsigned long attrs
)
953 int coalesced
, filled
= 0;
956 DBG_RUN_SG("%s() START %d entries\n", __func__
, nents
);
962 /* Fast path single entry scatterlists. */
964 sg_dma_address(sglist
) = sba_map_single(dev
, sg_virt(sglist
),
965 sglist
->length
, direction
);
966 sg_dma_len(sglist
) = sglist
->length
;
970 spin_lock_irqsave(&ioc
->res_lock
, flags
);
972 #ifdef ASSERT_PDIR_SANITY
973 if (sba_check_pdir(ioc
,"Check before sba_map_sg()"))
975 sba_dump_sg(ioc
, sglist
, nents
);
976 panic("Check before sba_map_sg()");
980 #ifdef SBA_COLLECT_STATS
985 ** First coalesce the chunks and allocate I/O pdir space
987 ** If this is one DMA stream, we can properly map using the
988 ** correct virtual address associated with each DMA page.
989 ** w/o this association, we wouldn't have coherent DMA!
990 ** Access to the virtual address is what forces a two pass algorithm.
992 coalesced
= iommu_coalesce_chunks(ioc
, dev
, sglist
, nents
, sba_alloc_range
);
995 ** Program the I/O Pdir
997 ** map the virtual addresses to the I/O Pdir
998 ** o dma_address will contain the pdir index
999 ** o dma_len will contain the number of bytes to map
1000 ** o address contains the virtual address.
1002 filled
= iommu_fill_pdir(ioc
, sglist
, nents
, 0, sba_io_pdir_entry
);
1004 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1007 #ifdef ASSERT_PDIR_SANITY
1008 if (sba_check_pdir(ioc
,"Check after sba_map_sg()"))
1010 sba_dump_sg(ioc
, sglist
, nents
);
1011 panic("Check after sba_map_sg()\n");
1015 spin_unlock_irqrestore(&ioc
->res_lock
, flags
);
1017 DBG_RUN_SG("%s() DONE %d mappings\n", __func__
, filled
);
1024 * sba_unmap_sg - unmap Scatter/Gather list
1025 * @dev: instance of PCI owned by the driver that's asking.
1026 * @sglist: array of buffer/length pairs
1027 * @nents: number of entries in list
1028 * @direction: R/W or both.
1030 * See Documentation/DMA-API-HOWTO.txt
1033 sba_unmap_sg(struct device
*dev
, struct scatterlist
*sglist
, int nents
,
1034 enum dma_data_direction direction
, unsigned long attrs
)
1037 #ifdef ASSERT_PDIR_SANITY
1038 unsigned long flags
;
1041 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1042 __func__
, nents
, sg_virt(sglist
), sglist
->length
);
1050 #ifdef SBA_COLLECT_STATS
1054 #ifdef ASSERT_PDIR_SANITY
1055 spin_lock_irqsave(&ioc
->res_lock
, flags
);
1056 sba_check_pdir(ioc
,"Check before sba_unmap_sg()");
1057 spin_unlock_irqrestore(&ioc
->res_lock
, flags
);
1060 while (sg_dma_len(sglist
) && nents
--) {
1062 sba_unmap_page(dev
, sg_dma_address(sglist
), sg_dma_len(sglist
),
1064 #ifdef SBA_COLLECT_STATS
1065 ioc
->usg_pages
+= ((sg_dma_address(sglist
) & ~IOVP_MASK
) + sg_dma_len(sglist
) + IOVP_SIZE
- 1) >> PAGE_SHIFT
;
1066 ioc
->usingle_calls
--; /* kluge since call is unmap_sg() */
1071 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__
, nents
);
1073 #ifdef ASSERT_PDIR_SANITY
1074 spin_lock_irqsave(&ioc
->res_lock
, flags
);
1075 sba_check_pdir(ioc
,"Check after sba_unmap_sg()");
1076 spin_unlock_irqrestore(&ioc
->res_lock
, flags
);
1081 static const struct dma_map_ops sba_ops
= {
1082 .dma_supported
= sba_dma_supported
,
1085 .map_page
= sba_map_page
,
1086 .unmap_page
= sba_unmap_page
,
1087 .map_sg
= sba_map_sg
,
1088 .unmap_sg
= sba_unmap_sg
,
1092 /**************************************************************************
1094 ** SBA PAT PDC support
1096 ** o call pdc_pat_cell_module()
1097 ** o store ranges in PCI "resource" structures
1099 **************************************************************************/
1102 sba_get_pat_resources(struct sba_device
*sba_dev
)
1106 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1107 ** PAT PDC to program the SBA/LBA directed range registers...this
1108 ** burden may fall on the LBA code since it directly supports the
1109 ** PCI subsystem. It's not clear yet. - ggg
1111 PAT_MOD(mod
)->mod_info
.mod_pages
= PAT_GET_MOD_PAGES(temp
);
1113 PAT_MOD(mod
)->mod_info
.dvi
= PAT_GET_DVI(temp
);
1114 Tells where the dvi bits are located in the address
.
1115 PAT_MOD(mod
)->mod_info
.ioc
= PAT_GET_IOC(temp
);
1121 /**************************************************************
1123 * Initialization and claim
1125 ***************************************************************/
1126 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1127 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1129 sba_alloc_pdir(unsigned int pdir_size
)
1131 unsigned long pdir_base
;
1132 unsigned long pdir_order
= get_order(pdir_size
);
1134 pdir_base
= __get_free_pages(GFP_KERNEL
, pdir_order
);
1135 if (NULL
== (void *) pdir_base
) {
1136 panic("%s() could not allocate I/O Page Table\n",
1140 /* If this is not PA8700 (PCX-W2)
1141 ** OR newer than ver 2.2
1142 ** OR in a system that doesn't need VINDEX bits from SBA,
1144 ** then we aren't exposed to the HW bug.
1146 if ( ((boot_cpu_data
.pdc
.cpuid
>> 5) & 0x7f) != 0x13
1147 || (boot_cpu_data
.pdc
.versions
> 0x202)
1148 || (boot_cpu_data
.pdc
.capabilities
& 0x08L
) )
1149 return (void *) pdir_base
;
1152 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1154 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1155 * Ike/Astro can cause silent data corruption. This is only
1156 * a problem if the I/O PDIR is located in memory such that
1157 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1159 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1160 * right physical address, we can either avoid (IOPDIR <= 1MB)
1161 * or minimize (2MB IO Pdir) the problem if we restrict the
1162 * IO Pdir to a maximum size of 2MB-128K (1902K).
1164 * Because we always allocate 2^N sized IO pdirs, either of the
1165 * "bad" regions will be the last 128K if at all. That's easy
1169 if (pdir_order
<= (19-12)) {
1170 if (((virt_to_phys(pdir_base
)+pdir_size
-1) & PIRANHA_ADDR_MASK
) == PIRANHA_ADDR_VAL
) {
1171 /* allocate a new one on 512k alignment */
1172 unsigned long new_pdir
= __get_free_pages(GFP_KERNEL
, (19-12));
1173 /* release original */
1174 free_pages(pdir_base
, pdir_order
);
1176 pdir_base
= new_pdir
;
1178 /* release excess */
1179 while (pdir_order
< (19-12)) {
1180 new_pdir
+= pdir_size
;
1181 free_pages(new_pdir
, pdir_order
);
1189 ** Needs to be aligned on an "odd" 1MB boundary.
1191 unsigned long new_pdir
= __get_free_pages(GFP_KERNEL
, pdir_order
+1); /* 2 or 4MB */
1193 /* release original */
1194 free_pages( pdir_base
, pdir_order
);
1196 /* release first 1MB */
1197 free_pages(new_pdir
, 20-12);
1199 pdir_base
= new_pdir
+ 1024*1024;
1201 if (pdir_order
> (20-12)) {
1205 ** Flag tells init_bitmap() to mark bad 128k as used
1206 ** and to reduce the size by 128k.
1208 piranha_bad_128k
= 1;
1210 new_pdir
+= 3*1024*1024;
1211 /* release last 1MB */
1212 free_pages(new_pdir
, 20-12);
1214 /* release unusable 128KB */
1215 free_pages(new_pdir
- 128*1024 , 17-12);
1217 pdir_size
-= 128*1024;
1221 memset((void *) pdir_base
, 0, pdir_size
);
1222 return (void *) pdir_base
;
1225 struct ibase_data_struct
{
1230 static int setup_ibase_imask_callback(struct device
*dev
, void *data
)
1232 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1233 extern void lba_set_iregs(struct parisc_device
*, u32
, u32
);
1234 struct parisc_device
*lba
= to_parisc_device(dev
);
1235 struct ibase_data_struct
*ibd
= data
;
1236 int rope_num
= (lba
->hpa
.start
>> 13) & 0xf;
1237 if (rope_num
>> 3 == ibd
->ioc_num
)
1238 lba_set_iregs(lba
, ibd
->ioc
->ibase
, ibd
->ioc
->imask
);
1242 /* setup Mercury or Elroy IBASE/IMASK registers. */
1244 setup_ibase_imask(struct parisc_device
*sba
, struct ioc
*ioc
, int ioc_num
)
1246 struct ibase_data_struct ibase_data
= {
1251 device_for_each_child(&sba
->dev
, &ibase_data
,
1252 setup_ibase_imask_callback
);
1255 #ifdef SBA_AGP_SUPPORT
1257 sba_ioc_find_quicksilver(struct device
*dev
, void *data
)
1259 int *agp_found
= data
;
1260 struct parisc_device
*lba
= to_parisc_device(dev
);
1262 if (IS_QUICKSILVER(lba
))
1269 sba_ioc_init_pluto(struct parisc_device
*sba
, struct ioc
*ioc
, int ioc_num
)
1271 u32 iova_space_mask
;
1272 u32 iova_space_size
;
1273 int iov_order
, tcnfg
;
1274 #ifdef SBA_AGP_SUPPORT
1278 ** Firmware programs the base and size of a "safe IOVA space"
1279 ** (one that doesn't overlap memory or LMMIO space) in the
1280 ** IBASE and IMASK registers.
1282 ioc
->ibase
= READ_REG(ioc
->ioc_hpa
+ IOC_IBASE
);
1283 iova_space_size
= ~(READ_REG(ioc
->ioc_hpa
+ IOC_IMASK
) & 0xFFFFFFFFUL
) + 1;
1285 if ((ioc
->ibase
< 0xfed00000UL
) && ((ioc
->ibase
+ iova_space_size
) > 0xfee00000UL
)) {
1286 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1287 iova_space_size
/= 2;
1291 ** iov_order is always based on a 1GB IOVA space since we want to
1292 ** turn on the other half for AGP GART.
1294 iov_order
= get_order(iova_space_size
>> (IOVP_SHIFT
- PAGE_SHIFT
));
1295 ioc
->pdir_size
= (iova_space_size
/ IOVP_SIZE
) * sizeof(u64
);
1297 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1298 __func__
, ioc
->ioc_hpa
, iova_space_size
>> 20,
1299 iov_order
+ PAGE_SHIFT
);
1301 ioc
->pdir_base
= (void *) __get_free_pages(GFP_KERNEL
,
1302 get_order(ioc
->pdir_size
));
1303 if (!ioc
->pdir_base
)
1304 panic("Couldn't allocate I/O Page Table\n");
1306 memset(ioc
->pdir_base
, 0, ioc
->pdir_size
);
1308 DBG_INIT("%s() pdir %p size %x\n",
1309 __func__
, ioc
->pdir_base
, ioc
->pdir_size
);
1311 #ifdef SBA_HINT_SUPPORT
1312 ioc
->hint_shift_pdir
= iov_order
+ PAGE_SHIFT
;
1313 ioc
->hint_mask_pdir
= ~(0x3 << (iov_order
+ PAGE_SHIFT
));
1315 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1316 ioc
->hint_shift_pdir
, ioc
->hint_mask_pdir
);
1319 WARN_ON((((unsigned long) ioc
->pdir_base
) & PAGE_MASK
) != (unsigned long) ioc
->pdir_base
);
1320 WRITE_REG(virt_to_phys(ioc
->pdir_base
), ioc
->ioc_hpa
+ IOC_PDIR_BASE
);
1322 /* build IMASK for IOC and Elroy */
1323 iova_space_mask
= 0xffffffff;
1324 iova_space_mask
<<= (iov_order
+ PAGE_SHIFT
);
1325 ioc
->imask
= iova_space_mask
;
1327 ioc
->iovp_mask
= ~(iova_space_mask
+ PAGE_SIZE
- 1);
1329 sba_dump_tlb(ioc
->ioc_hpa
);
1331 setup_ibase_imask(sba
, ioc
, ioc_num
);
1333 WRITE_REG(ioc
->imask
, ioc
->ioc_hpa
+ IOC_IMASK
);
1337 ** Setting the upper bits makes checking for bypass addresses
1338 ** a little faster later on.
1340 ioc
->imask
|= 0xFFFFFFFF00000000UL
;
1343 /* Set I/O PDIR Page size to system page size */
1344 switch (PAGE_SHIFT
) {
1345 case 12: tcnfg
= 0; break; /* 4K */
1346 case 13: tcnfg
= 1; break; /* 8K */
1347 case 14: tcnfg
= 2; break; /* 16K */
1348 case 16: tcnfg
= 3; break; /* 64K */
1350 panic(__FILE__
"Unsupported system page size %d",
1354 WRITE_REG(tcnfg
, ioc
->ioc_hpa
+ IOC_TCNFG
);
1357 ** Program the IOC's ibase and enable IOVA translation
1358 ** Bit zero == enable bit.
1360 WRITE_REG(ioc
->ibase
| 1, ioc
->ioc_hpa
+ IOC_IBASE
);
1363 ** Clear I/O TLB of any possible entries.
1364 ** (Yes. This is a bit paranoid...but so what)
1366 WRITE_REG(ioc
->ibase
| 31, ioc
->ioc_hpa
+ IOC_PCOM
);
1368 #ifdef SBA_AGP_SUPPORT
1371 ** If an AGP device is present, only use half of the IOV space
1372 ** for PCI DMA. Unfortunately we can't know ahead of time
1373 ** whether GART support will actually be used, for now we
1374 ** can just key on any AGP device found in the system.
1375 ** We program the next pdir index after we stop w/ a key for
1376 ** the GART code to handshake on.
1378 device_for_each_child(&sba
->dev
, &agp_found
, sba_ioc_find_quicksilver
);
1380 if (agp_found
&& sba_reserve_agpgart
) {
1381 printk(KERN_INFO
"%s: reserving %dMb of IOVA space for agpgart\n",
1382 __func__
, (iova_space_size
/2) >> 20);
1383 ioc
->pdir_size
/= 2;
1384 ioc
->pdir_base
[PDIR_INDEX(iova_space_size
/2)] = SBA_AGPGART_COOKIE
;
1386 #endif /*SBA_AGP_SUPPORT*/
1390 sba_ioc_init(struct parisc_device
*sba
, struct ioc
*ioc
, int ioc_num
)
1392 u32 iova_space_size
, iova_space_mask
;
1393 unsigned int pdir_size
, iov_order
, tcnfg
;
1396 ** Determine IOVA Space size from memory size.
1398 ** Ideally, PCI drivers would register the maximum number
1399 ** of DMA they can have outstanding for each device they
1400 ** own. Next best thing would be to guess how much DMA
1401 ** can be outstanding based on PCI Class/sub-class. Both
1402 ** methods still require some "extra" to support PCI
1403 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1405 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1406 ** for DMA hints - ergo only 30 bits max.
1409 iova_space_size
= (u32
) (totalram_pages
/global_ioc_cnt
);
1411 /* limit IOVA space size to 1MB-1GB */
1412 if (iova_space_size
< (1 << (20 - PAGE_SHIFT
))) {
1413 iova_space_size
= 1 << (20 - PAGE_SHIFT
);
1415 else if (iova_space_size
> (1 << (30 - PAGE_SHIFT
))) {
1416 iova_space_size
= 1 << (30 - PAGE_SHIFT
);
1420 ** iova space must be log2() in size.
1421 ** thus, pdir/res_map will also be log2().
1422 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1424 iov_order
= get_order(iova_space_size
<< PAGE_SHIFT
);
1426 /* iova_space_size is now bytes, not pages */
1427 iova_space_size
= 1 << (iov_order
+ PAGE_SHIFT
);
1429 ioc
->pdir_size
= pdir_size
= (iova_space_size
/IOVP_SIZE
) * sizeof(u64
);
1431 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1434 (unsigned long) totalram_pages
>> (20 - PAGE_SHIFT
),
1435 iova_space_size
>>20,
1436 iov_order
+ PAGE_SHIFT
);
1438 ioc
->pdir_base
= sba_alloc_pdir(pdir_size
);
1440 DBG_INIT("%s() pdir %p size %x\n",
1441 __func__
, ioc
->pdir_base
, pdir_size
);
1443 #ifdef SBA_HINT_SUPPORT
1444 /* FIXME : DMA HINTs not used */
1445 ioc
->hint_shift_pdir
= iov_order
+ PAGE_SHIFT
;
1446 ioc
->hint_mask_pdir
= ~(0x3 << (iov_order
+ PAGE_SHIFT
));
1448 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1449 ioc
->hint_shift_pdir
, ioc
->hint_mask_pdir
);
1452 WRITE_REG64(virt_to_phys(ioc
->pdir_base
), ioc
->ioc_hpa
+ IOC_PDIR_BASE
);
1454 /* build IMASK for IOC and Elroy */
1455 iova_space_mask
= 0xffffffff;
1456 iova_space_mask
<<= (iov_order
+ PAGE_SHIFT
);
1459 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1460 ** ibase=0, imask=0xFE000000, size=0x2000000.
1463 ioc
->imask
= iova_space_mask
; /* save it */
1465 ioc
->iovp_mask
= ~(iova_space_mask
+ PAGE_SIZE
- 1);
1468 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1469 __func__
, ioc
->ibase
, ioc
->imask
);
1472 ** FIXME: Hint registers are programmed with default hint
1473 ** values during boot, so hints should be sane even if we
1474 ** can't reprogram them the way drivers want.
1477 setup_ibase_imask(sba
, ioc
, ioc_num
);
1480 ** Program the IOC's ibase and enable IOVA translation
1482 WRITE_REG(ioc
->ibase
| 1, ioc
->ioc_hpa
+IOC_IBASE
);
1483 WRITE_REG(ioc
->imask
, ioc
->ioc_hpa
+IOC_IMASK
);
1485 /* Set I/O PDIR Page size to system page size */
1486 switch (PAGE_SHIFT
) {
1487 case 12: tcnfg
= 0; break; /* 4K */
1488 case 13: tcnfg
= 1; break; /* 8K */
1489 case 14: tcnfg
= 2; break; /* 16K */
1490 case 16: tcnfg
= 3; break; /* 64K */
1492 panic(__FILE__
"Unsupported system page size %d",
1496 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
1497 WRITE_REG(tcnfg
, ioc
->ioc_hpa
+IOC_TCNFG
);
1500 ** Clear I/O TLB of any possible entries.
1501 ** (Yes. This is a bit paranoid...but so what)
1503 WRITE_REG(0 | 31, ioc
->ioc_hpa
+IOC_PCOM
);
1505 ioc
->ibase
= 0; /* used by SBA_IOVA and related macros */
1507 DBG_INIT("%s() DONE\n", __func__
);
1512 /**************************************************************************
1514 ** SBA initialization code (HW and SW)
1516 ** o identify SBA chip itself
1517 ** o initialize SBA chip modes (HardFail)
1518 ** o initialize SBA chip modes (HardFail)
1519 ** o FIXME: initialize DMA hints for reasonable defaults
1521 **************************************************************************/
1523 static void __iomem
*ioc_remap(struct sba_device
*sba_dev
, unsigned int offset
)
1525 return ioremap_nocache(sba_dev
->dev
->hpa
.start
+ offset
, SBA_FUNC_SIZE
);
1528 static void sba_hw_init(struct sba_device
*sba_dev
)
1534 if (!is_pdc_pat()) {
1535 /* Shutdown the USB controller on Astro-based workstations.
1536 ** Once we reprogram the IOMMU, the next DMA performed by
1537 ** USB will HPMC the box. USB is only enabled if a
1538 ** keyboard is present and found.
1540 ** With serial console, j6k v5.0 firmware says:
1541 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1543 ** FIXME: Using GFX+USB console at power up but direct
1544 ** linux to serial console is still broken.
1545 ** USB could generate DMA so we must reset USB.
1546 ** The proper sequence would be:
1547 ** o block console output
1548 ** o reset USB device
1549 ** o reprogram serial port
1550 ** o unblock console output
1552 if (PAGE0
->mem_kbd
.cl_class
== CL_KEYBD
) {
1553 pdc_io_reset_devices();
1560 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0
->mem_boot
.hpa
,
1561 PAGE0
->mem_boot
.spa
, PAGE0
->mem_boot
.pad
, PAGE0
->mem_boot
.cl_class
);
1564 ** Need to deal with DMA from LAN.
1565 ** Maybe use page zero boot device as a handle to talk
1566 ** to PDC about which device to shutdown.
1568 ** Netbooting, j6k v5.0 firmware says:
1569 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1570 ** ARGH! invalid class.
1572 if ((PAGE0
->mem_boot
.cl_class
!= CL_RANDOM
)
1573 && (PAGE0
->mem_boot
.cl_class
!= CL_SEQU
)) {
1578 if (!IS_PLUTO(sba_dev
->dev
)) {
1579 ioc_ctl
= READ_REG(sba_dev
->sba_hpa
+IOC_CTRL
);
1580 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1581 __func__
, sba_dev
->sba_hpa
, ioc_ctl
);
1582 ioc_ctl
&= ~(IOC_CTRL_RM
| IOC_CTRL_NC
| IOC_CTRL_CE
);
1583 ioc_ctl
|= IOC_CTRL_DD
| IOC_CTRL_D4
| IOC_CTRL_TC
;
1584 /* j6700 v1.6 firmware sets 0x294f */
1585 /* A500 firmware sets 0x4d */
1587 WRITE_REG(ioc_ctl
, sba_dev
->sba_hpa
+IOC_CTRL
);
1589 #ifdef DEBUG_SBA_INIT
1590 ioc_ctl
= READ_REG64(sba_dev
->sba_hpa
+IOC_CTRL
);
1591 DBG_INIT(" 0x%Lx\n", ioc_ctl
);
1595 if (IS_ASTRO(sba_dev
->dev
)) {
1597 sba_dev
->ioc
[0].ioc_hpa
= ioc_remap(sba_dev
, ASTRO_IOC_OFFSET
);
1600 sba_dev
->chip_resv
.name
= "Astro Intr Ack";
1601 sba_dev
->chip_resv
.start
= PCI_F_EXTEND
| 0xfef00000UL
;
1602 sba_dev
->chip_resv
.end
= PCI_F_EXTEND
| (0xff000000UL
- 1) ;
1603 err
= request_resource(&iomem_resource
, &(sba_dev
->chip_resv
));
1606 } else if (IS_PLUTO(sba_dev
->dev
)) {
1609 sba_dev
->ioc
[0].ioc_hpa
= ioc_remap(sba_dev
, PLUTO_IOC_OFFSET
);
1612 sba_dev
->chip_resv
.name
= "Pluto Intr/PIOP/VGA";
1613 sba_dev
->chip_resv
.start
= PCI_F_EXTEND
| 0xfee00000UL
;
1614 sba_dev
->chip_resv
.end
= PCI_F_EXTEND
| (0xff200000UL
- 1);
1615 err
= request_resource(&iomem_resource
, &(sba_dev
->chip_resv
));
1618 sba_dev
->iommu_resv
.name
= "IOVA Space";
1619 sba_dev
->iommu_resv
.start
= 0x40000000UL
;
1620 sba_dev
->iommu_resv
.end
= 0x50000000UL
- 1;
1621 err
= request_resource(&iomem_resource
, &(sba_dev
->iommu_resv
));
1625 sba_dev
->ioc
[0].ioc_hpa
= ioc_remap(sba_dev
, IKE_IOC_OFFSET(0));
1626 sba_dev
->ioc
[1].ioc_hpa
= ioc_remap(sba_dev
, IKE_IOC_OFFSET(1));
1629 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1631 /* XXX: What about Reo Grande? */
1633 sba_dev
->num_ioc
= num_ioc
;
1634 for (i
= 0; i
< num_ioc
; i
++) {
1635 void __iomem
*ioc_hpa
= sba_dev
->ioc
[i
].ioc_hpa
;
1638 for (j
=0; j
< sizeof(u64
) * ROPES_PER_IOC
; j
+=sizeof(u64
)) {
1641 * Clear ROPE(N)_CONFIG AO bit.
1642 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1643 * Overrides bit 1 in DMA Hint Sets.
1644 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1646 if (IS_PLUTO(sba_dev
->dev
)) {
1647 void __iomem
*rope_cfg
;
1648 unsigned long cfg_val
;
1650 rope_cfg
= ioc_hpa
+ IOC_ROPE0_CFG
+ j
;
1651 cfg_val
= READ_REG(rope_cfg
);
1652 cfg_val
&= ~IOC_ROPE_AO
;
1653 WRITE_REG(cfg_val
, rope_cfg
);
1657 ** Make sure the box crashes on rope errors.
1659 WRITE_REG(HF_ENABLE
, ioc_hpa
+ ROPE0_CTL
+ j
);
1662 /* flush out the last writes */
1663 READ_REG(sba_dev
->ioc
[i
].ioc_hpa
+ ROPE7_CTL
);
1665 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1667 READ_REG(sba_dev
->ioc
[i
].ioc_hpa
+ 0x40),
1668 READ_REG(sba_dev
->ioc
[i
].ioc_hpa
+ 0x50)
1670 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1671 READ_REG(sba_dev
->ioc
[i
].ioc_hpa
+ 0x108),
1672 READ_REG(sba_dev
->ioc
[i
].ioc_hpa
+ 0x400)
1675 if (IS_PLUTO(sba_dev
->dev
)) {
1676 sba_ioc_init_pluto(sba_dev
->dev
, &(sba_dev
->ioc
[i
]), i
);
1678 sba_ioc_init(sba_dev
->dev
, &(sba_dev
->ioc
[i
]), i
);
1684 sba_common_init(struct sba_device
*sba_dev
)
1688 /* add this one to the head of the list (order doesn't matter)
1689 ** This will be useful for debugging - especially if we get coredumps
1691 sba_dev
->next
= sba_list
;
1694 for(i
=0; i
< sba_dev
->num_ioc
; i
++) {
1696 #ifdef DEBUG_DMB_TRAP
1697 extern void iterate_pages(unsigned long , unsigned long ,
1698 void (*)(pte_t
* , unsigned long),
1700 void set_data_memory_break(pte_t
* , unsigned long);
1702 /* resource map size dictated by pdir_size */
1703 res_size
= sba_dev
->ioc
[i
].pdir_size
/sizeof(u64
); /* entries */
1705 /* Second part of PIRANHA BUG */
1706 if (piranha_bad_128k
) {
1707 res_size
-= (128*1024)/sizeof(u64
);
1710 res_size
>>= 3; /* convert bit count to byte count */
1711 DBG_INIT("%s() res_size 0x%x\n",
1712 __func__
, res_size
);
1714 sba_dev
->ioc
[i
].res_size
= res_size
;
1715 sba_dev
->ioc
[i
].res_map
= (char *) __get_free_pages(GFP_KERNEL
, get_order(res_size
));
1717 #ifdef DEBUG_DMB_TRAP
1718 iterate_pages( sba_dev
->ioc
[i
].res_map
, res_size
,
1719 set_data_memory_break
, 0);
1722 if (NULL
== sba_dev
->ioc
[i
].res_map
)
1724 panic("%s:%s() could not allocate resource map\n",
1725 __FILE__
, __func__
);
1728 memset(sba_dev
->ioc
[i
].res_map
, 0, res_size
);
1729 /* next available IOVP - circular search */
1730 sba_dev
->ioc
[i
].res_hint
= (unsigned long *)
1731 &(sba_dev
->ioc
[i
].res_map
[L1_CACHE_BYTES
]);
1733 #ifdef ASSERT_PDIR_SANITY
1734 /* Mark first bit busy - ie no IOVA 0 */
1735 sba_dev
->ioc
[i
].res_map
[0] = 0x80;
1736 sba_dev
->ioc
[i
].pdir_base
[0] = 0xeeffc0addbba0080ULL
;
1739 /* Third (and last) part of PIRANHA BUG */
1740 if (piranha_bad_128k
) {
1741 /* region from +1408K to +1536 is un-usable. */
1743 int idx_start
= (1408*1024/sizeof(u64
)) >> 3;
1744 int idx_end
= (1536*1024/sizeof(u64
)) >> 3;
1745 long *p_start
= (long *) &(sba_dev
->ioc
[i
].res_map
[idx_start
]);
1746 long *p_end
= (long *) &(sba_dev
->ioc
[i
].res_map
[idx_end
]);
1748 /* mark that part of the io pdir busy */
1749 while (p_start
< p_end
)
1754 #ifdef DEBUG_DMB_TRAP
1755 iterate_pages( sba_dev
->ioc
[i
].res_map
, res_size
,
1756 set_data_memory_break
, 0);
1757 iterate_pages( sba_dev
->ioc
[i
].pdir_base
, sba_dev
->ioc
[i
].pdir_size
,
1758 set_data_memory_break
, 0);
1761 DBG_INIT("%s() %d res_map %x %p\n",
1762 __func__
, i
, res_size
, sba_dev
->ioc
[i
].res_map
);
1765 spin_lock_init(&sba_dev
->sba_lock
);
1766 ioc_needs_fdc
= boot_cpu_data
.pdc
.capabilities
& PDC_MODEL_IOPDIR_FDC
;
1768 #ifdef DEBUG_SBA_INIT
1770 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1771 * (bit #61, big endian), we have to flush and sync every time
1772 * IO-PDIR is changed in Ike/Astro.
1774 if (ioc_needs_fdc
) {
1775 printk(KERN_INFO MODULE_NAME
" FDC/SYNC required.\n");
1777 printk(KERN_INFO MODULE_NAME
" IOC has cache coherent PDIR.\n");
1782 #ifdef CONFIG_PROC_FS
1783 static int sba_proc_info(struct seq_file
*m
, void *p
)
1785 struct sba_device
*sba_dev
= sba_list
;
1786 struct ioc
*ioc
= &sba_dev
->ioc
[0]; /* FIXME: Multi-IOC support! */
1787 int total_pages
= (int) (ioc
->res_size
<< 3); /* 8 bits per byte */
1788 #ifdef SBA_COLLECT_STATS
1789 unsigned long avg
= 0, min
, max
;
1793 seq_printf(m
, "%s rev %d.%d\n",
1795 (sba_dev
->hw_rev
& 0x7) + 1,
1796 (sba_dev
->hw_rev
& 0x18) >> 3);
1797 seq_printf(m
, "IO PDIR size : %d bytes (%d entries)\n",
1798 (int)((ioc
->res_size
<< 3) * sizeof(u64
)), /* 8 bits/byte */
1801 seq_printf(m
, "Resource bitmap : %d bytes (%d pages)\n",
1802 ioc
->res_size
, ioc
->res_size
<< 3); /* 8 bits per byte */
1804 seq_printf(m
, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1805 READ_REG32(sba_dev
->sba_hpa
+ LMMIO_DIST_BASE
),
1806 READ_REG32(sba_dev
->sba_hpa
+ LMMIO_DIST_MASK
),
1807 READ_REG32(sba_dev
->sba_hpa
+ LMMIO_DIST_ROUTE
));
1810 seq_printf(m
, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
1812 READ_REG32(sba_dev
->sba_hpa
+ LMMIO_DIRECT0_BASE
+ i
*0x18),
1813 READ_REG32(sba_dev
->sba_hpa
+ LMMIO_DIRECT0_MASK
+ i
*0x18),
1814 READ_REG32(sba_dev
->sba_hpa
+ LMMIO_DIRECT0_ROUTE
+ i
*0x18));
1816 #ifdef SBA_COLLECT_STATS
1817 seq_printf(m
, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1818 total_pages
- ioc
->used_pages
, ioc
->used_pages
,
1819 (int)(ioc
->used_pages
* 100 / total_pages
));
1821 min
= max
= ioc
->avg_search
[0];
1822 for (i
= 0; i
< SBA_SEARCH_SAMPLE
; i
++) {
1823 avg
+= ioc
->avg_search
[i
];
1824 if (ioc
->avg_search
[i
] > max
) max
= ioc
->avg_search
[i
];
1825 if (ioc
->avg_search
[i
] < min
) min
= ioc
->avg_search
[i
];
1827 avg
/= SBA_SEARCH_SAMPLE
;
1828 seq_printf(m
, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1831 seq_printf(m
, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1832 ioc
->msingle_calls
, ioc
->msingle_pages
,
1833 (int)((ioc
->msingle_pages
* 1000)/ioc
->msingle_calls
));
1835 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1836 min
= ioc
->usingle_calls
;
1837 max
= ioc
->usingle_pages
- ioc
->usg_pages
;
1838 seq_printf(m
, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1839 min
, max
, (int)((max
* 1000)/min
));
1841 seq_printf(m
, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1842 ioc
->msg_calls
, ioc
->msg_pages
,
1843 (int)((ioc
->msg_pages
* 1000)/ioc
->msg_calls
));
1845 seq_printf(m
, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1846 ioc
->usg_calls
, ioc
->usg_pages
,
1847 (int)((ioc
->usg_pages
* 1000)/ioc
->usg_calls
));
1854 sba_proc_bitmap_info(struct seq_file
*m
, void *p
)
1856 struct sba_device
*sba_dev
= sba_list
;
1857 struct ioc
*ioc
= &sba_dev
->ioc
[0]; /* FIXME: Multi-IOC support! */
1859 seq_hex_dump(m
, " ", DUMP_PREFIX_NONE
, 32, 4, ioc
->res_map
,
1860 ioc
->res_size
, false);
1865 #endif /* CONFIG_PROC_FS */
1867 static const struct parisc_device_id sba_tbl
[] __initconst
= {
1868 { HPHW_IOA
, HVERSION_REV_ANY_ID
, ASTRO_RUNWAY_PORT
, 0xb },
1869 { HPHW_BCPORT
, HVERSION_REV_ANY_ID
, IKE_MERCED_PORT
, 0xc },
1870 { HPHW_BCPORT
, HVERSION_REV_ANY_ID
, REO_MERCED_PORT
, 0xc },
1871 { HPHW_BCPORT
, HVERSION_REV_ANY_ID
, REOG_MERCED_PORT
, 0xc },
1872 { HPHW_IOA
, HVERSION_REV_ANY_ID
, PLUTO_MCKINLEY_PORT
, 0xc },
1876 static int sba_driver_callback(struct parisc_device
*);
1878 static struct parisc_driver sba_driver __refdata
= {
1879 .name
= MODULE_NAME
,
1880 .id_table
= sba_tbl
,
1881 .probe
= sba_driver_callback
,
1885 ** Determine if sba should claim this chip (return 0) or not (return 1).
1886 ** If so, initialize the chip and tell other partners in crime they
1889 static int __init
sba_driver_callback(struct parisc_device
*dev
)
1891 struct sba_device
*sba_dev
;
1895 void __iomem
*sba_addr
= ioremap_nocache(dev
->hpa
.start
, SBA_FUNC_SIZE
);
1896 #ifdef CONFIG_PROC_FS
1897 struct proc_dir_entry
*root
;
1900 sba_dump_ranges(sba_addr
);
1902 /* Read HW Rev First */
1903 func_class
= READ_REG(sba_addr
+ SBA_FCLASS
);
1905 if (IS_ASTRO(dev
)) {
1906 unsigned long fclass
;
1907 static char astro_rev
[]="Astro ?.?";
1909 /* Astro is broken...Read HW Rev First */
1910 fclass
= READ_REG(sba_addr
);
1912 astro_rev
[6] = '1' + (char) (fclass
& 0x7);
1913 astro_rev
[8] = '0' + (char) ((fclass
& 0x18) >> 3);
1914 version
= astro_rev
;
1916 } else if (IS_IKE(dev
)) {
1917 static char ike_rev
[] = "Ike rev ?";
1918 ike_rev
[8] = '0' + (char) (func_class
& 0xff);
1920 } else if (IS_PLUTO(dev
)) {
1921 static char pluto_rev
[]="Pluto ?.?";
1922 pluto_rev
[6] = '0' + (char) ((func_class
& 0xf0) >> 4);
1923 pluto_rev
[8] = '0' + (char) (func_class
& 0x0f);
1924 version
= pluto_rev
;
1926 static char reo_rev
[] = "REO rev ?";
1927 reo_rev
[8] = '0' + (char) (func_class
& 0xff);
1931 if (!global_ioc_cnt
) {
1932 global_ioc_cnt
= count_parisc_driver(&sba_driver
);
1934 /* Astro and Pluto have one IOC per SBA */
1935 if ((!IS_ASTRO(dev
)) || (!IS_PLUTO(dev
)))
1936 global_ioc_cnt
*= 2;
1939 printk(KERN_INFO
"%s found %s at 0x%llx\n",
1940 MODULE_NAME
, version
, (unsigned long long)dev
->hpa
.start
);
1942 sba_dev
= kzalloc(sizeof(struct sba_device
), GFP_KERNEL
);
1944 printk(KERN_ERR MODULE_NAME
" - couldn't alloc sba_device\n");
1948 parisc_set_drvdata(dev
, sba_dev
);
1950 for(i
=0; i
<MAX_IOC
; i
++)
1951 spin_lock_init(&(sba_dev
->ioc
[i
].res_lock
));
1954 sba_dev
->hw_rev
= func_class
;
1955 sba_dev
->name
= dev
->name
;
1956 sba_dev
->sba_hpa
= sba_addr
;
1958 sba_get_pat_resources(sba_dev
);
1959 sba_hw_init(sba_dev
);
1960 sba_common_init(sba_dev
);
1962 hppa_dma_ops
= &sba_ops
;
1964 #ifdef CONFIG_PROC_FS
1965 switch (dev
->id
.hversion
) {
1966 case PLUTO_MCKINLEY_PORT
:
1967 root
= proc_mckinley_root
;
1969 case ASTRO_RUNWAY_PORT
:
1970 case IKE_MERCED_PORT
:
1972 root
= proc_runway_root
;
1976 proc_create_single("sba_iommu", 0, root
, sba_proc_info
);
1977 proc_create_single("sba_iommu-bitmap", 0, root
, sba_proc_bitmap_info
);
1983 ** One time initialization to let the world know the SBA was found.
1984 ** This is the only routine which is NOT static.
1985 ** Must be called exactly once before pci_init().
1987 void __init
sba_init(void)
1989 register_parisc_driver(&sba_driver
);
1994 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
1995 * @dev: The parisc device.
1997 * Returns the appropriate IOMMU data for the given parisc PCI controller.
1998 * This is cached and used later for PCI DMA Mapping.
2000 void * sba_get_iommu(struct parisc_device
*pci_hba
)
2002 struct parisc_device
*sba_dev
= parisc_parent(pci_hba
);
2003 struct sba_device
*sba
= dev_get_drvdata(&sba_dev
->dev
);
2004 char t
= sba_dev
->id
.hw_type
;
2005 int iocnum
= (pci_hba
->hw_path
>> 3); /* rope # */
2007 WARN_ON((t
!= HPHW_IOA
) && (t
!= HPHW_BCPORT
));
2009 return &(sba
->ioc
[iocnum
]);
2014 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2015 * @pa_dev: The parisc device.
2016 * @r: resource PCI host controller wants start/end fields assigned.
2018 * For the given parisc PCI controller, determine if any direct ranges
2019 * are routed down the corresponding rope.
2021 void sba_directed_lmmio(struct parisc_device
*pci_hba
, struct resource
*r
)
2023 struct parisc_device
*sba_dev
= parisc_parent(pci_hba
);
2024 struct sba_device
*sba
= dev_get_drvdata(&sba_dev
->dev
);
2025 char t
= sba_dev
->id
.hw_type
;
2027 int rope
= (pci_hba
->hw_path
& (ROPES_PER_IOC
-1)); /* rope # */
2029 BUG_ON((t
!=HPHW_IOA
) && (t
!=HPHW_BCPORT
));
2031 r
->start
= r
->end
= 0;
2033 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2034 for (i
=0; i
<4; i
++) {
2036 void __iomem
*reg
= sba
->sba_hpa
+ i
*0x18;
2038 base
= READ_REG32(reg
+ LMMIO_DIRECT0_BASE
);
2039 if ((base
& 1) == 0)
2040 continue; /* not enabled */
2042 size
= READ_REG32(reg
+ LMMIO_DIRECT0_ROUTE
);
2044 if ((size
& (ROPES_PER_IOC
-1)) != rope
)
2045 continue; /* directed down different rope */
2047 r
->start
= (base
& ~1UL) | PCI_F_EXTEND
;
2048 size
= ~ READ_REG32(reg
+ LMMIO_DIRECT0_MASK
);
2049 r
->end
= r
->start
+ size
;
2050 r
->flags
= IORESOURCE_MEM
;
2056 * sba_distributed_lmmio - return portion of distributed LMMIO range
2057 * @pa_dev: The parisc device.
2058 * @r: resource PCI host controller wants start/end fields assigned.
2060 * For the given parisc PCI controller, return portion of distributed LMMIO
2061 * range. The distributed LMMIO is always present and it's just a question
2062 * of the base address and size of the range.
2064 void sba_distributed_lmmio(struct parisc_device
*pci_hba
, struct resource
*r
)
2066 struct parisc_device
*sba_dev
= parisc_parent(pci_hba
);
2067 struct sba_device
*sba
= dev_get_drvdata(&sba_dev
->dev
);
2068 char t
= sba_dev
->id
.hw_type
;
2070 int rope
= (pci_hba
->hw_path
& (ROPES_PER_IOC
-1)); /* rope # */
2072 BUG_ON((t
!=HPHW_IOA
) && (t
!=HPHW_BCPORT
));
2074 r
->start
= r
->end
= 0;
2076 base
= READ_REG32(sba
->sba_hpa
+ LMMIO_DIST_BASE
);
2077 if ((base
& 1) == 0) {
2078 BUG(); /* Gah! Distr Range wasn't enabled! */
2082 r
->start
= (base
& ~1UL) | PCI_F_EXTEND
;
2084 size
= (~READ_REG32(sba
->sba_hpa
+ LMMIO_DIST_MASK
)) / ROPES_PER_IOC
;
2085 r
->start
+= rope
* (size
+ 1); /* adjust base for this rope */
2086 r
->end
= r
->start
+ size
;
2087 r
->flags
= IORESOURCE_MEM
;