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1 /*
2 * drivers/pci/ats.c
3 *
4 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
5 * Copyright (C) 2011 Advanced Micro Devices,
6 *
7 * PCI Express I/O Virtualization (IOV) support.
8 * Address Translation Service 1.0
9 * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
10 * PASID support added by Joerg Roedel <joerg.roedel@amd.com>
11 */
12
13 #include <linux/export.h>
14 #include <linux/pci-ats.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
17
18 #include "pci.h"
19
20 void pci_ats_init(struct pci_dev *dev)
21 {
22 int pos;
23
24 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
25 if (!pos)
26 return;
27
28 dev->ats_cap = pos;
29 }
30
31 /**
32 * pci_enable_ats - enable the ATS capability
33 * @dev: the PCI device
34 * @ps: the IOMMU page shift
35 *
36 * Returns 0 on success, or negative on failure.
37 */
38 int pci_enable_ats(struct pci_dev *dev, int ps)
39 {
40 u16 ctrl;
41 struct pci_dev *pdev;
42
43 if (!dev->ats_cap)
44 return -EINVAL;
45
46 if (WARN_ON(dev->ats_enabled))
47 return -EBUSY;
48
49 if (ps < PCI_ATS_MIN_STU)
50 return -EINVAL;
51
52 /*
53 * Note that enabling ATS on a VF fails unless it's already enabled
54 * with the same STU on the PF.
55 */
56 ctrl = PCI_ATS_CTRL_ENABLE;
57 if (dev->is_virtfn) {
58 pdev = pci_physfn(dev);
59 if (pdev->ats_stu != ps)
60 return -EINVAL;
61
62 atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */
63 } else {
64 dev->ats_stu = ps;
65 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
66 }
67 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
68
69 dev->ats_enabled = 1;
70 return 0;
71 }
72 EXPORT_SYMBOL_GPL(pci_enable_ats);
73
74 /**
75 * pci_disable_ats - disable the ATS capability
76 * @dev: the PCI device
77 */
78 void pci_disable_ats(struct pci_dev *dev)
79 {
80 struct pci_dev *pdev;
81 u16 ctrl;
82
83 if (WARN_ON(!dev->ats_enabled))
84 return;
85
86 if (atomic_read(&dev->ats_ref_cnt))
87 return; /* VFs still enabled */
88
89 if (dev->is_virtfn) {
90 pdev = pci_physfn(dev);
91 atomic_dec(&pdev->ats_ref_cnt);
92 }
93
94 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
95 ctrl &= ~PCI_ATS_CTRL_ENABLE;
96 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
97
98 dev->ats_enabled = 0;
99 }
100 EXPORT_SYMBOL_GPL(pci_disable_ats);
101
102 void pci_restore_ats_state(struct pci_dev *dev)
103 {
104 u16 ctrl;
105
106 if (!dev->ats_enabled)
107 return;
108
109 ctrl = PCI_ATS_CTRL_ENABLE;
110 if (!dev->is_virtfn)
111 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
112 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
113 }
114 EXPORT_SYMBOL_GPL(pci_restore_ats_state);
115
116 /**
117 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
118 * @dev: the PCI device
119 *
120 * Returns the queue depth on success, or negative on failure.
121 *
122 * The ATS spec uses 0 in the Invalidate Queue Depth field to
123 * indicate that the function can accept 32 Invalidate Request.
124 * But here we use the `real' values (i.e. 1~32) for the Queue
125 * Depth; and 0 indicates the function shares the Queue with
126 * other functions (doesn't exclusively own a Queue).
127 */
128 int pci_ats_queue_depth(struct pci_dev *dev)
129 {
130 u16 cap;
131
132 if (!dev->ats_cap)
133 return -EINVAL;
134
135 if (dev->is_virtfn)
136 return 0;
137
138 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
139 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
140 }
141 EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
142
143 #ifdef CONFIG_PCI_PRI
144 /**
145 * pci_enable_pri - Enable PRI capability
146 * @ pdev: PCI device structure
147 *
148 * Returns 0 on success, negative value on error
149 */
150 int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
151 {
152 u16 control, status;
153 u32 max_requests;
154 int pos;
155
156 if (WARN_ON(pdev->pri_enabled))
157 return -EBUSY;
158
159 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
160 if (!pos)
161 return -EINVAL;
162
163 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
164 if (!(status & PCI_PRI_STATUS_STOPPED))
165 return -EBUSY;
166
167 pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
168 reqs = min(max_requests, reqs);
169 pdev->pri_reqs_alloc = reqs;
170 pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
171
172 control = PCI_PRI_CTRL_ENABLE;
173 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
174
175 pdev->pri_enabled = 1;
176
177 return 0;
178 }
179 EXPORT_SYMBOL_GPL(pci_enable_pri);
180
181 /**
182 * pci_disable_pri - Disable PRI capability
183 * @pdev: PCI device structure
184 *
185 * Only clears the enabled-bit, regardless of its former value
186 */
187 void pci_disable_pri(struct pci_dev *pdev)
188 {
189 u16 control;
190 int pos;
191
192 if (WARN_ON(!pdev->pri_enabled))
193 return;
194
195 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
196 if (!pos)
197 return;
198
199 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
200 control &= ~PCI_PRI_CTRL_ENABLE;
201 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
202
203 pdev->pri_enabled = 0;
204 }
205 EXPORT_SYMBOL_GPL(pci_disable_pri);
206
207 /**
208 * pci_restore_pri_state - Restore PRI
209 * @pdev: PCI device structure
210 */
211 void pci_restore_pri_state(struct pci_dev *pdev)
212 {
213 u16 control = PCI_PRI_CTRL_ENABLE;
214 u32 reqs = pdev->pri_reqs_alloc;
215 int pos;
216
217 if (!pdev->pri_enabled)
218 return;
219
220 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
221 if (!pos)
222 return;
223
224 pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
225 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
226 }
227 EXPORT_SYMBOL_GPL(pci_restore_pri_state);
228
229 /**
230 * pci_reset_pri - Resets device's PRI state
231 * @pdev: PCI device structure
232 *
233 * The PRI capability must be disabled before this function is called.
234 * Returns 0 on success, negative value on error.
235 */
236 int pci_reset_pri(struct pci_dev *pdev)
237 {
238 u16 control;
239 int pos;
240
241 if (WARN_ON(pdev->pri_enabled))
242 return -EBUSY;
243
244 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
245 if (!pos)
246 return -EINVAL;
247
248 control = PCI_PRI_CTRL_RESET;
249 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
250
251 return 0;
252 }
253 EXPORT_SYMBOL_GPL(pci_reset_pri);
254 #endif /* CONFIG_PCI_PRI */
255
256 #ifdef CONFIG_PCI_PASID
257 /**
258 * pci_enable_pasid - Enable the PASID capability
259 * @pdev: PCI device structure
260 * @features: Features to enable
261 *
262 * Returns 0 on success, negative value on error. This function checks
263 * whether the features are actually supported by the device and returns
264 * an error if not.
265 */
266 int pci_enable_pasid(struct pci_dev *pdev, int features)
267 {
268 u16 control, supported;
269 int pos;
270
271 if (WARN_ON(pdev->pasid_enabled))
272 return -EBUSY;
273
274 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
275 if (!pos)
276 return -EINVAL;
277
278 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
279 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
280
281 /* User wants to enable anything unsupported? */
282 if ((supported & features) != features)
283 return -EINVAL;
284
285 control = PCI_PASID_CTRL_ENABLE | features;
286 pdev->pasid_features = features;
287
288 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
289
290 pdev->pasid_enabled = 1;
291
292 return 0;
293 }
294 EXPORT_SYMBOL_GPL(pci_enable_pasid);
295
296 /**
297 * pci_disable_pasid - Disable the PASID capability
298 * @pdev: PCI device structure
299 */
300 void pci_disable_pasid(struct pci_dev *pdev)
301 {
302 u16 control = 0;
303 int pos;
304
305 if (WARN_ON(!pdev->pasid_enabled))
306 return;
307
308 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
309 if (!pos)
310 return;
311
312 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
313
314 pdev->pasid_enabled = 0;
315 }
316 EXPORT_SYMBOL_GPL(pci_disable_pasid);
317
318 /**
319 * pci_restore_pasid_state - Restore PASID capabilities
320 * @pdev: PCI device structure
321 */
322 void pci_restore_pasid_state(struct pci_dev *pdev)
323 {
324 u16 control;
325 int pos;
326
327 if (!pdev->pasid_enabled)
328 return;
329
330 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
331 if (!pos)
332 return;
333
334 control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
335 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
336 }
337 EXPORT_SYMBOL_GPL(pci_restore_pasid_state);
338
339 /**
340 * pci_pasid_features - Check which PASID features are supported
341 * @pdev: PCI device structure
342 *
343 * Returns a negative value when no PASI capability is present.
344 * Otherwise is returns a bitmask with supported features. Current
345 * features reported are:
346 * PCI_PASID_CAP_EXEC - Execute permission supported
347 * PCI_PASID_CAP_PRIV - Privileged mode supported
348 */
349 int pci_pasid_features(struct pci_dev *pdev)
350 {
351 u16 supported;
352 int pos;
353
354 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
355 if (!pos)
356 return -EINVAL;
357
358 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
359
360 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
361
362 return supported;
363 }
364 EXPORT_SYMBOL_GPL(pci_pasid_features);
365
366 #define PASID_NUMBER_SHIFT 8
367 #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
368 /**
369 * pci_max_pasid - Get maximum number of PASIDs supported by device
370 * @pdev: PCI device structure
371 *
372 * Returns negative value when PASID capability is not present.
373 * Otherwise it returns the numer of supported PASIDs.
374 */
375 int pci_max_pasids(struct pci_dev *pdev)
376 {
377 u16 supported;
378 int pos;
379
380 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
381 if (!pos)
382 return -EINVAL;
383
384 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
385
386 supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
387
388 return (1 << supported);
389 }
390 EXPORT_SYMBOL_GPL(pci_max_pasids);
391 #endif /* CONFIG_PCI_PASID */