1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
7 * Copyright (C) 2016 Marvell Technology Group Ltd.
9 * Author: Yehuda Yitshak <yehuday@marvell.com>
10 * Author: Shadi Ammouri <shadi@marvell.com>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/of_pci.h>
24 #include <linux/of_irq.h>
25 #include <linux/gpio/consumer.h>
27 #include "pcie-designware.h"
29 struct armada8k_pcie
{
33 struct gpio_desc
*reset_gpio
;
36 #define PCIE_VENDOR_REGS_OFFSET 0x8000
38 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
39 #define PCIE_APP_LTSSM_EN BIT(2)
40 #define PCIE_DEVICE_TYPE_SHIFT 4
41 #define PCIE_DEVICE_TYPE_MASK 0xF
42 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
44 #define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
45 #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1)
46 #define PCIE_GLB_STS_PHY_LINK_UP BIT(9)
48 #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
49 #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
50 #define PCIE_INT_A_ASSERT_MASK BIT(9)
51 #define PCIE_INT_B_ASSERT_MASK BIT(10)
52 #define PCIE_INT_C_ASSERT_MASK BIT(11)
53 #define PCIE_INT_D_ASSERT_MASK BIT(12)
55 #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
56 #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
57 #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
58 #define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60)
60 * AR/AW Cache defauls: Normal memory, Write-Back, Read / Write
63 #define ARCACHE_DEFAULT_VALUE 0x3511
64 #define AWCACHE_DEFAULT_VALUE 0x5311
66 #define DOMAIN_OUTER_SHAREABLE 0x2
67 #define AX_USER_DOMAIN_MASK 0x3
68 #define AX_USER_DOMAIN_SHIFT 4
70 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
72 static int armada8k_pcie_link_up(struct dw_pcie
*pci
)
75 u32 mask
= PCIE_GLB_STS_RDLH_LINK_UP
| PCIE_GLB_STS_PHY_LINK_UP
;
77 reg
= dw_pcie_readl_dbi(pci
, PCIE_GLOBAL_STATUS_REG
);
79 if ((reg
& mask
) == mask
)
82 dev_dbg(pci
->dev
, "No link detected (Global-Status: 0x%08x).\n", reg
);
86 static void armada8k_pcie_establish_link(struct armada8k_pcie
*pcie
)
88 struct dw_pcie
*pci
= pcie
->pci
;
91 if (!dw_pcie_link_up(pci
)) {
92 /* Disable LTSSM state machine to enable configuration */
93 reg
= dw_pcie_readl_dbi(pci
, PCIE_GLOBAL_CONTROL_REG
);
94 reg
&= ~(PCIE_APP_LTSSM_EN
);
95 dw_pcie_writel_dbi(pci
, PCIE_GLOBAL_CONTROL_REG
, reg
);
98 /* Set the device to root complex mode */
99 reg
= dw_pcie_readl_dbi(pci
, PCIE_GLOBAL_CONTROL_REG
);
100 reg
&= ~(PCIE_DEVICE_TYPE_MASK
<< PCIE_DEVICE_TYPE_SHIFT
);
101 reg
|= PCIE_DEVICE_TYPE_RC
<< PCIE_DEVICE_TYPE_SHIFT
;
102 dw_pcie_writel_dbi(pci
, PCIE_GLOBAL_CONTROL_REG
, reg
);
104 /* Set the PCIe master AxCache attributes */
105 dw_pcie_writel_dbi(pci
, PCIE_ARCACHE_TRC_REG
, ARCACHE_DEFAULT_VALUE
);
106 dw_pcie_writel_dbi(pci
, PCIE_AWCACHE_TRC_REG
, AWCACHE_DEFAULT_VALUE
);
108 /* Set the PCIe master AxDomain attributes */
109 reg
= dw_pcie_readl_dbi(pci
, PCIE_ARUSER_REG
);
110 reg
&= ~(AX_USER_DOMAIN_MASK
<< AX_USER_DOMAIN_SHIFT
);
111 reg
|= DOMAIN_OUTER_SHAREABLE
<< AX_USER_DOMAIN_SHIFT
;
112 dw_pcie_writel_dbi(pci
, PCIE_ARUSER_REG
, reg
);
114 reg
= dw_pcie_readl_dbi(pci
, PCIE_AWUSER_REG
);
115 reg
&= ~(AX_USER_DOMAIN_MASK
<< AX_USER_DOMAIN_SHIFT
);
116 reg
|= DOMAIN_OUTER_SHAREABLE
<< AX_USER_DOMAIN_SHIFT
;
117 dw_pcie_writel_dbi(pci
, PCIE_AWUSER_REG
, reg
);
119 /* Enable INT A-D interrupts */
120 reg
= dw_pcie_readl_dbi(pci
, PCIE_GLOBAL_INT_MASK1_REG
);
121 reg
|= PCIE_INT_A_ASSERT_MASK
| PCIE_INT_B_ASSERT_MASK
|
122 PCIE_INT_C_ASSERT_MASK
| PCIE_INT_D_ASSERT_MASK
;
123 dw_pcie_writel_dbi(pci
, PCIE_GLOBAL_INT_MASK1_REG
, reg
);
125 if (!dw_pcie_link_up(pci
)) {
126 /* Configuration done. Start LTSSM */
127 reg
= dw_pcie_readl_dbi(pci
, PCIE_GLOBAL_CONTROL_REG
);
128 reg
|= PCIE_APP_LTSSM_EN
;
129 dw_pcie_writel_dbi(pci
, PCIE_GLOBAL_CONTROL_REG
, reg
);
132 /* Wait until the link becomes active again */
133 if (dw_pcie_wait_for_link(pci
))
134 dev_err(pci
->dev
, "Link not up after reconfiguration\n");
137 static int armada8k_pcie_host_init(struct pcie_port
*pp
)
139 struct dw_pcie
*pci
= to_dw_pcie_from_pp(pp
);
140 struct armada8k_pcie
*pcie
= to_armada8k_pcie(pci
);
142 if (pcie
->reset_gpio
) {
143 /* assert and then deassert the reset signal */
144 gpiod_set_value_cansleep(pcie
->reset_gpio
, 1);
146 gpiod_set_value_cansleep(pcie
->reset_gpio
, 0);
148 dw_pcie_setup_rc(pp
);
149 armada8k_pcie_establish_link(pcie
);
154 static irqreturn_t
armada8k_pcie_irq_handler(int irq
, void *arg
)
156 struct armada8k_pcie
*pcie
= arg
;
157 struct dw_pcie
*pci
= pcie
->pci
;
161 * Interrupts are directly handled by the device driver of the
162 * PCI device. However, they are also latched into the PCIe
163 * controller, so we simply discard them.
165 val
= dw_pcie_readl_dbi(pci
, PCIE_GLOBAL_INT_CAUSE1_REG
);
166 dw_pcie_writel_dbi(pci
, PCIE_GLOBAL_INT_CAUSE1_REG
, val
);
171 static const struct dw_pcie_host_ops armada8k_pcie_host_ops
= {
172 .host_init
= armada8k_pcie_host_init
,
175 static int armada8k_add_pcie_port(struct armada8k_pcie
*pcie
,
176 struct platform_device
*pdev
)
178 struct dw_pcie
*pci
= pcie
->pci
;
179 struct pcie_port
*pp
= &pci
->pp
;
180 struct device
*dev
= &pdev
->dev
;
183 pp
->ops
= &armada8k_pcie_host_ops
;
185 pp
->irq
= platform_get_irq(pdev
, 0);
187 dev_err(dev
, "failed to get irq for port\n");
191 ret
= devm_request_irq(dev
, pp
->irq
, armada8k_pcie_irq_handler
,
192 IRQF_SHARED
, "armada8k-pcie", pcie
);
194 dev_err(dev
, "failed to request irq %d\n", pp
->irq
);
198 ret
= dw_pcie_host_init(pp
);
200 dev_err(dev
, "failed to initialize host: %d\n", ret
);
207 static const struct dw_pcie_ops dw_pcie_ops
= {
208 .link_up
= armada8k_pcie_link_up
,
211 static int armada8k_pcie_probe(struct platform_device
*pdev
)
214 struct armada8k_pcie
*pcie
;
215 struct device
*dev
= &pdev
->dev
;
216 struct resource
*base
;
219 pcie
= devm_kzalloc(dev
, sizeof(*pcie
), GFP_KERNEL
);
223 pci
= devm_kzalloc(dev
, sizeof(*pci
), GFP_KERNEL
);
228 pci
->ops
= &dw_pcie_ops
;
232 pcie
->clk
= devm_clk_get(dev
, NULL
);
233 if (IS_ERR(pcie
->clk
))
234 return PTR_ERR(pcie
->clk
);
236 ret
= clk_prepare_enable(pcie
->clk
);
240 pcie
->clk_reg
= devm_clk_get(dev
, "reg");
241 if (pcie
->clk_reg
== ERR_PTR(-EPROBE_DEFER
)) {
245 if (!IS_ERR(pcie
->clk_reg
)) {
246 ret
= clk_prepare_enable(pcie
->clk_reg
);
251 /* Get the dw-pcie unit configuration/control registers base. */
252 base
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "ctrl");
253 pci
->dbi_base
= devm_pci_remap_cfg_resource(dev
, base
);
254 if (IS_ERR(pci
->dbi_base
)) {
255 dev_err(dev
, "couldn't remap regs base %p\n", base
);
256 ret
= PTR_ERR(pci
->dbi_base
);
260 /* Get reset gpio signal and hold asserted (logically high) */
261 pcie
->reset_gpio
= devm_gpiod_get_optional(dev
, "reset",
263 if (IS_ERR(pcie
->reset_gpio
)) {
264 ret
= PTR_ERR(pcie
->reset_gpio
);
268 platform_set_drvdata(pdev
, pcie
);
270 ret
= armada8k_add_pcie_port(pcie
, pdev
);
277 clk_disable_unprepare(pcie
->clk_reg
);
279 clk_disable_unprepare(pcie
->clk
);
284 static const struct of_device_id armada8k_pcie_of_match
[] = {
285 { .compatible
= "marvell,armada8k-pcie", },
289 static struct platform_driver armada8k_pcie_driver
= {
290 .probe
= armada8k_pcie_probe
,
292 .name
= "armada8k-pcie",
293 .of_match_table
= of_match_ptr(armada8k_pcie_of_match
),
294 .suppress_bind_attrs
= true,
297 builtin_platform_driver(armada8k_pcie_driver
);