1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
5 * Copyright (c) 2014 Applied Micro Circuits Corporation.
7 * Author: Tanmay Inamdar <tinamdar@apm.com>.
10 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/memblock.h>
14 #include <linux/init.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_pci.h>
19 #include <linux/pci.h>
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
27 #define PCIECORE_CTLANDSTATUS 0x50
35 #define OMR1BARL 0x100
36 #define OMR2BARL 0x118
37 #define OMR3BARL 0x130
42 #define BRIDGE_CFG_0 0x2000
43 #define BRIDGE_CFG_4 0x2010
44 #define BRIDGE_STATUS_0 0x2600
46 #define LINK_UP_MASK 0x00000100
47 #define AXI_EP_CFG_ACCESS 0x10000
48 #define EN_COHERENCY 0xF0000000
49 #define EN_REG 0x00000001
50 #define OB_LO_IO 0x00000002
51 #define XGENE_PCIE_VENDORID 0x10E8
52 #define XGENE_PCIE_DEVICEID 0xE004
53 #define SZ_1T (SZ_1G*1024ULL)
54 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
56 #define XGENE_V1_PCI_EXP_CAP 0x40
59 #define XGENE_PCIE_IP_VER_UNKN 0
60 #define XGENE_PCIE_IP_VER_1 1
61 #define XGENE_PCIE_IP_VER_2 2
63 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
64 struct xgene_pcie_port
{
65 struct device_node
*node
;
68 void __iomem
*csr_base
;
69 void __iomem
*cfg_base
;
70 unsigned long cfg_addr
;
75 static u32
xgene_pcie_readl(struct xgene_pcie_port
*port
, u32 reg
)
77 return readl(port
->csr_base
+ reg
);
80 static void xgene_pcie_writel(struct xgene_pcie_port
*port
, u32 reg
, u32 val
)
82 writel(val
, port
->csr_base
+ reg
);
85 static inline u32
pcie_bar_low_val(u32 addr
, u32 flags
)
87 return (addr
& PCI_BASE_ADDRESS_MEM_MASK
) | flags
;
90 static inline struct xgene_pcie_port
*pcie_bus_to_port(struct pci_bus
*bus
)
92 struct pci_config_window
*cfg
;
95 return (struct xgene_pcie_port
*)(bus
->sysdata
);
98 return (struct xgene_pcie_port
*)(cfg
->priv
);
102 * When the address bit [17:16] is 2'b01, the Configuration access will be
103 * treated as Type 1 and it will be forwarded to external PCIe device.
105 static void __iomem
*xgene_pcie_get_cfg_base(struct pci_bus
*bus
)
107 struct xgene_pcie_port
*port
= pcie_bus_to_port(bus
);
109 if (bus
->number
>= (bus
->primary
+ 1))
110 return port
->cfg_base
+ AXI_EP_CFG_ACCESS
;
112 return port
->cfg_base
;
116 * For Configuration request, RTDID register is used as Bus Number,
117 * Device Number and Function number of the header fields.
119 static void xgene_pcie_set_rtdid_reg(struct pci_bus
*bus
, uint devfn
)
121 struct xgene_pcie_port
*port
= pcie_bus_to_port(bus
);
122 unsigned int b
, d
, f
;
129 if (!pci_is_root_bus(bus
))
130 rtdid_val
= (b
<< 8) | (d
<< 3) | f
;
132 xgene_pcie_writel(port
, RTDID
, rtdid_val
);
133 /* read the register back to ensure flush */
134 xgene_pcie_readl(port
, RTDID
);
138 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
139 * the translation from PCI bus to native BUS. Entire DDR region
140 * is mapped into PCIe space using these registers, so it can be
141 * reached by DMA from EP devices. The BAR0/1 of bridge should be
142 * hidden during enumeration to avoid the sizing and resource allocation
145 static bool xgene_pcie_hide_rc_bars(struct pci_bus
*bus
, int offset
)
147 if (pci_is_root_bus(bus
) && ((offset
== PCI_BASE_ADDRESS_0
) ||
148 (offset
== PCI_BASE_ADDRESS_1
)))
154 static void __iomem
*xgene_pcie_map_bus(struct pci_bus
*bus
, unsigned int devfn
,
157 if ((pci_is_root_bus(bus
) && devfn
!= 0) ||
158 xgene_pcie_hide_rc_bars(bus
, offset
))
161 xgene_pcie_set_rtdid_reg(bus
, devfn
);
162 return xgene_pcie_get_cfg_base(bus
) + offset
;
165 static int xgene_pcie_config_read32(struct pci_bus
*bus
, unsigned int devfn
,
166 int where
, int size
, u32
*val
)
168 struct xgene_pcie_port
*port
= pcie_bus_to_port(bus
);
170 if (pci_generic_config_read32(bus
, devfn
, where
& ~0x3, 4, val
) !=
172 return PCIBIOS_DEVICE_NOT_FOUND
;
175 * The v1 controller has a bug in its Configuration Request
176 * Retry Status (CRS) logic: when CRS Software Visibility is
177 * enabled and we read the Vendor and Device ID of a non-existent
178 * device, the controller fabricates return data of 0xFFFF0001
179 * ("device exists but is not ready") instead of 0xFFFFFFFF
180 * ("device does not exist"). This causes the PCI core to retry
181 * the read until it times out. Avoid this by not claiming to
184 if (pci_is_root_bus(bus
) && (port
->version
== XGENE_PCIE_IP_VER_1
) &&
185 ((where
& ~0x3) == XGENE_V1_PCI_EXP_CAP
+ PCI_EXP_RTCTL
))
186 *val
&= ~(PCI_EXP_RTCAP_CRSVIS
<< 16);
189 *val
= (*val
>> (8 * (where
& 3))) & ((1 << (size
* 8)) - 1);
191 return PCIBIOS_SUCCESSFUL
;
195 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
196 static int xgene_get_csr_resource(struct acpi_device
*adev
,
197 struct resource
*res
)
199 struct device
*dev
= &adev
->dev
;
200 struct resource_entry
*entry
;
201 struct list_head list
;
205 INIT_LIST_HEAD(&list
);
206 flags
= IORESOURCE_MEM
;
207 ret
= acpi_dev_get_resources(adev
, &list
,
208 acpi_dev_filter_resource_type_cb
,
211 dev_err(dev
, "failed to parse _CRS method, error code %d\n",
217 dev_err(dev
, "no IO and memory resources present in _CRS\n");
221 entry
= list_first_entry(&list
, struct resource_entry
, node
);
223 acpi_dev_free_resource_list(&list
);
227 static int xgene_pcie_ecam_init(struct pci_config_window
*cfg
, u32 ipversion
)
229 struct device
*dev
= cfg
->parent
;
230 struct acpi_device
*adev
= to_acpi_device(dev
);
231 struct xgene_pcie_port
*port
;
235 port
= devm_kzalloc(dev
, sizeof(*port
), GFP_KERNEL
);
239 ret
= xgene_get_csr_resource(adev
, &csr
);
241 dev_err(dev
, "can't get CSR resource\n");
244 port
->csr_base
= devm_pci_remap_cfg_resource(dev
, &csr
);
245 if (IS_ERR(port
->csr_base
))
246 return PTR_ERR(port
->csr_base
);
248 port
->cfg_base
= cfg
->win
;
249 port
->version
= ipversion
;
255 static int xgene_v1_pcie_ecam_init(struct pci_config_window
*cfg
)
257 return xgene_pcie_ecam_init(cfg
, XGENE_PCIE_IP_VER_1
);
260 const struct pci_ecam_ops xgene_v1_pcie_ecam_ops
= {
261 .init
= xgene_v1_pcie_ecam_init
,
263 .map_bus
= xgene_pcie_map_bus
,
264 .read
= xgene_pcie_config_read32
,
265 .write
= pci_generic_config_write
,
269 static int xgene_v2_pcie_ecam_init(struct pci_config_window
*cfg
)
271 return xgene_pcie_ecam_init(cfg
, XGENE_PCIE_IP_VER_2
);
274 const struct pci_ecam_ops xgene_v2_pcie_ecam_ops
= {
275 .init
= xgene_v2_pcie_ecam_init
,
277 .map_bus
= xgene_pcie_map_bus
,
278 .read
= xgene_pcie_config_read32
,
279 .write
= pci_generic_config_write
,
284 #if defined(CONFIG_PCI_XGENE)
285 static u64
xgene_pcie_set_ib_mask(struct xgene_pcie_port
*port
, u32 addr
,
288 u64 mask
= (~(size
- 1) & PCI_BASE_ADDRESS_MEM_MASK
) | flags
;
292 val32
= xgene_pcie_readl(port
, addr
);
293 val
= (val32
& 0x0000ffff) | (lower_32_bits(mask
) << 16);
294 xgene_pcie_writel(port
, addr
, val
);
296 val32
= xgene_pcie_readl(port
, addr
+ 0x04);
297 val
= (val32
& 0xffff0000) | (lower_32_bits(mask
) >> 16);
298 xgene_pcie_writel(port
, addr
+ 0x04, val
);
300 val32
= xgene_pcie_readl(port
, addr
+ 0x04);
301 val
= (val32
& 0x0000ffff) | (upper_32_bits(mask
) << 16);
302 xgene_pcie_writel(port
, addr
+ 0x04, val
);
304 val32
= xgene_pcie_readl(port
, addr
+ 0x08);
305 val
= (val32
& 0xffff0000) | (upper_32_bits(mask
) >> 16);
306 xgene_pcie_writel(port
, addr
+ 0x08, val
);
311 static void xgene_pcie_linkup(struct xgene_pcie_port
*port
,
312 u32
*lanes
, u32
*speed
)
316 port
->link_up
= false;
317 val32
= xgene_pcie_readl(port
, PCIECORE_CTLANDSTATUS
);
318 if (val32
& LINK_UP_MASK
) {
319 port
->link_up
= true;
320 *speed
= PIPE_PHY_RATE_RD(val32
);
321 val32
= xgene_pcie_readl(port
, BRIDGE_STATUS_0
);
322 *lanes
= val32
>> 26;
326 static int xgene_pcie_init_port(struct xgene_pcie_port
*port
)
328 struct device
*dev
= port
->dev
;
331 port
->clk
= clk_get(dev
, NULL
);
332 if (IS_ERR(port
->clk
)) {
333 dev_err(dev
, "clock not available\n");
337 rc
= clk_prepare_enable(port
->clk
);
339 dev_err(dev
, "clock enable failed\n");
346 static int xgene_pcie_map_reg(struct xgene_pcie_port
*port
,
347 struct platform_device
*pdev
)
349 struct device
*dev
= port
->dev
;
350 struct resource
*res
;
352 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "csr");
353 port
->csr_base
= devm_pci_remap_cfg_resource(dev
, res
);
354 if (IS_ERR(port
->csr_base
))
355 return PTR_ERR(port
->csr_base
);
357 port
->cfg_base
= devm_platform_ioremap_resource_byname(pdev
, "cfg");
358 if (IS_ERR(port
->cfg_base
))
359 return PTR_ERR(port
->cfg_base
);
360 port
->cfg_addr
= res
->start
;
365 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port
*port
,
366 struct resource
*res
, u32 offset
,
367 u64 cpu_addr
, u64 pci_addr
)
369 struct device
*dev
= port
->dev
;
370 resource_size_t size
= resource_size(res
);
371 u64 restype
= resource_type(res
);
376 if (restype
== IORESOURCE_MEM
) {
383 if (size
>= min_size
)
384 mask
= ~(size
- 1) | flag
;
386 dev_warn(dev
, "res size 0x%llx less than minimum 0x%x\n",
387 (u64
)size
, min_size
);
389 xgene_pcie_writel(port
, offset
, lower_32_bits(cpu_addr
));
390 xgene_pcie_writel(port
, offset
+ 0x04, upper_32_bits(cpu_addr
));
391 xgene_pcie_writel(port
, offset
+ 0x08, lower_32_bits(mask
));
392 xgene_pcie_writel(port
, offset
+ 0x0c, upper_32_bits(mask
));
393 xgene_pcie_writel(port
, offset
+ 0x10, lower_32_bits(pci_addr
));
394 xgene_pcie_writel(port
, offset
+ 0x14, upper_32_bits(pci_addr
));
397 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port
*port
)
399 u64 addr
= port
->cfg_addr
;
401 xgene_pcie_writel(port
, CFGBARL
, lower_32_bits(addr
));
402 xgene_pcie_writel(port
, CFGBARH
, upper_32_bits(addr
));
403 xgene_pcie_writel(port
, CFGCTL
, EN_REG
);
406 static int xgene_pcie_map_ranges(struct xgene_pcie_port
*port
)
408 struct pci_host_bridge
*bridge
= pci_host_bridge_from_priv(port
);
409 struct resource_entry
*window
;
410 struct device
*dev
= port
->dev
;
412 resource_list_for_each_entry(window
, &bridge
->windows
) {
413 struct resource
*res
= window
->res
;
414 u64 restype
= resource_type(res
);
416 dev_dbg(dev
, "%pR\n", res
);
420 xgene_pcie_setup_ob_reg(port
, res
, OMR3BARL
,
421 pci_pio_to_address(res
->start
),
422 res
->start
- window
->offset
);
425 if (res
->flags
& IORESOURCE_PREFETCH
)
426 xgene_pcie_setup_ob_reg(port
, res
, OMR2BARL
,
431 xgene_pcie_setup_ob_reg(port
, res
, OMR1BARL
,
439 dev_err(dev
, "invalid resource %pR\n", res
);
443 xgene_pcie_setup_cfg_reg(port
);
447 static void xgene_pcie_setup_pims(struct xgene_pcie_port
*port
, u32 pim_reg
,
450 xgene_pcie_writel(port
, pim_reg
, lower_32_bits(pim
));
451 xgene_pcie_writel(port
, pim_reg
+ 0x04,
452 upper_32_bits(pim
) | EN_COHERENCY
);
453 xgene_pcie_writel(port
, pim_reg
+ 0x10, lower_32_bits(size
));
454 xgene_pcie_writel(port
, pim_reg
+ 0x14, upper_32_bits(size
));
458 * X-Gene PCIe support maximum 3 inbound memory regions
459 * This function helps to select a region based on size of region
461 static int xgene_pcie_select_ib_reg(u8
*ib_reg_mask
, u64 size
)
463 if ((size
> 4) && (size
< SZ_16M
) && !(*ib_reg_mask
& (1 << 1))) {
464 *ib_reg_mask
|= (1 << 1);
468 if ((size
> SZ_1K
) && (size
< SZ_1T
) && !(*ib_reg_mask
& (1 << 0))) {
469 *ib_reg_mask
|= (1 << 0);
473 if ((size
> SZ_1M
) && (size
< SZ_1T
) && !(*ib_reg_mask
& (1 << 2))) {
474 *ib_reg_mask
|= (1 << 2);
481 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port
*port
,
482 struct resource_entry
*entry
,
485 void __iomem
*cfg_base
= port
->cfg_base
;
486 struct device
*dev
= port
->dev
;
489 u64 cpu_addr
= entry
->res
->start
;
490 u64 pci_addr
= cpu_addr
- entry
->offset
;
491 u64 size
= resource_size(entry
->res
);
492 u64 mask
= ~(size
- 1) | EN_REG
;
493 u32 flags
= PCI_BASE_ADDRESS_MEM_TYPE_64
;
497 region
= xgene_pcie_select_ib_reg(ib_reg_mask
, size
);
499 dev_warn(dev
, "invalid pcie dma-range config\n");
503 if (entry
->res
->flags
& IORESOURCE_PREFETCH
)
504 flags
|= PCI_BASE_ADDRESS_MEM_PREFETCH
;
506 bar_low
= pcie_bar_low_val((u32
)cpu_addr
, flags
);
509 xgene_pcie_set_ib_mask(port
, BRIDGE_CFG_4
, flags
, size
);
510 bar_addr
= cfg_base
+ PCI_BASE_ADDRESS_0
;
511 writel(bar_low
, bar_addr
);
512 writel(upper_32_bits(cpu_addr
), bar_addr
+ 0x4);
516 xgene_pcie_writel(port
, IBAR2
, bar_low
);
517 xgene_pcie_writel(port
, IR2MSK
, lower_32_bits(mask
));
521 xgene_pcie_writel(port
, IBAR3L
, bar_low
);
522 xgene_pcie_writel(port
, IBAR3L
+ 0x4, upper_32_bits(cpu_addr
));
523 xgene_pcie_writel(port
, IR3MSKL
, lower_32_bits(mask
));
524 xgene_pcie_writel(port
, IR3MSKL
+ 0x4, upper_32_bits(mask
));
529 xgene_pcie_setup_pims(port
, pim_reg
, pci_addr
, ~(size
- 1));
532 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port
*port
)
534 struct pci_host_bridge
*bridge
= pci_host_bridge_from_priv(port
);
535 struct resource_entry
*entry
;
538 resource_list_for_each_entry(entry
, &bridge
->dma_ranges
)
539 xgene_pcie_setup_ib_reg(port
, entry
, &ib_reg_mask
);
544 /* clear BAR configuration which was done by firmware */
545 static void xgene_pcie_clear_config(struct xgene_pcie_port
*port
)
549 for (i
= PIM1_1L
; i
<= CFGCTL
; i
+= 4)
550 xgene_pcie_writel(port
, i
, 0);
553 static int xgene_pcie_setup(struct xgene_pcie_port
*port
)
555 struct device
*dev
= port
->dev
;
556 u32 val
, lanes
= 0, speed
= 0;
559 xgene_pcie_clear_config(port
);
561 /* setup the vendor and device IDs correctly */
562 val
= (XGENE_PCIE_DEVICEID
<< 16) | XGENE_PCIE_VENDORID
;
563 xgene_pcie_writel(port
, BRIDGE_CFG_0
, val
);
565 ret
= xgene_pcie_map_ranges(port
);
569 ret
= xgene_pcie_parse_map_dma_ranges(port
);
573 xgene_pcie_linkup(port
, &lanes
, &speed
);
575 dev_info(dev
, "(rc) link down\n");
577 dev_info(dev
, "(rc) x%d gen-%d link up\n", lanes
, speed
+ 1);
581 static struct pci_ops xgene_pcie_ops
= {
582 .map_bus
= xgene_pcie_map_bus
,
583 .read
= xgene_pcie_config_read32
,
584 .write
= pci_generic_config_write32
,
587 static int xgene_pcie_probe(struct platform_device
*pdev
)
589 struct device
*dev
= &pdev
->dev
;
590 struct device_node
*dn
= dev
->of_node
;
591 struct xgene_pcie_port
*port
;
592 struct pci_host_bridge
*bridge
;
595 bridge
= devm_pci_alloc_host_bridge(dev
, sizeof(*port
));
599 port
= pci_host_bridge_priv(bridge
);
601 port
->node
= of_node_get(dn
);
604 port
->version
= XGENE_PCIE_IP_VER_UNKN
;
605 if (of_device_is_compatible(port
->node
, "apm,xgene-pcie"))
606 port
->version
= XGENE_PCIE_IP_VER_1
;
608 ret
= xgene_pcie_map_reg(port
, pdev
);
612 ret
= xgene_pcie_init_port(port
);
616 ret
= xgene_pcie_setup(port
);
620 bridge
->sysdata
= port
;
621 bridge
->ops
= &xgene_pcie_ops
;
623 return pci_host_probe(bridge
);
626 static const struct of_device_id xgene_pcie_match_table
[] = {
627 {.compatible
= "apm,xgene-pcie",},
631 static struct platform_driver xgene_pcie_driver
= {
633 .name
= "xgene-pcie",
634 .of_match_table
= of_match_ptr(xgene_pcie_match_table
),
635 .suppress_bind_attrs
= true,
637 .probe
= xgene_pcie_probe
,
639 builtin_platform_driver(xgene_pcie_driver
);